Vector inner product operation method and device and electronic equipment

Abstract

The invention discloses a vector inner product operation method and device and electronic equipment, and belongs to the technical field of computers. The method comprises the following steps: acquiring an input first vector; comparing each first feature value in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first feature value; obtaining a first bit stream corresponding to each second bit stream according to the position of a second feature value corresponding to a plurality of pre-stored second bit streams in a second vector, and performing bitwise AND operation on the obtained first bit stream and the corresponding second bit stream to obtain a third bit stream corresponding to each second feature value; and determining an inner product operation result of the first vector and the second vector according to the number of preset bit values in the third bit stream corresponding to each second feature value. In this way, the probability of bit flipping can be reduced, and the accuracy of vector inner product operation can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a vector inner product operation method, device, and electronic device. Background Art

[0002] AI chips, also known as AI accelerators or computing cards, are integrated circuits specifically designed to perform artificial intelligence computing tasks. They are used in a variety of AI scenarios, including speech recognition, image recognition, natural language processing, intelligent driving, and the intelligent Internet of Things. The vector inner product operation within AI chips is a key computational operation in deep learning and neural network models.

[0003] However, when using AI chips to perform vector inner product operations, bit flips are prone to occur due to factors such as insufficient device power supply, power supply interference, and transmission interference. That is, during the data transmission or processing process, the value of one or more binary bits changes, affecting the accuracy of the vector inner product operation. Summary of the Invention

[0004] Embodiments of the present application provide a vector inner product operation method, device, and electronic device to at least solve the problem of low accuracy when performing vector inner product operations on general-purpose processors.

[0005] In a first aspect, an embodiment of the present application provides a vector inner product operation method, including: obtaining an input first vector; comparing each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue; obtaining a first bit stream corresponding to each second bit stream according to the position of the second eigenvalue corresponding to a plurality of pre-stored second bit streams in the second vector, performing a bitwise AND operation on the obtained first bit stream and the corresponding second bit stream to obtain a third bit stream corresponding to each second eigenvalue; and determining the inner product operation result of the first vector and the second vector according to the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue.

[0006] In the second aspect, an embodiment of the present application provides a vector inner product operation device, including: a vector input module for obtaining an input first vector; a random encoding module for comparing each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue; an in-memory operation module for obtaining the first bit stream corresponding to each second bit stream according to the position of the second eigenvalue corresponding to a plurality of pre-stored second bit streams in the second vector, and performing a bitwise AND operation on the obtained first bit stream and the corresponding second bit stream to obtain a third bit stream corresponding to each second eigenvalue; an inner product operation module for determining the inner product operation result of the first vector and the second vector according to the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue.

[0007] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method described in the first aspect above are implemented.

[0008] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect above are implemented.

[0009] In an embodiment of the present application, a first input vector is obtained; each first eigenvalue in the first vector is compared with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue; based on the position of the second eigenvalue corresponding to multiple pre-stored second bit streams in the second vector, the first bit stream corresponding to each second bit stream is obtained, and the obtained first bit stream is bitwise ANDed with the corresponding second bit stream to obtain a third bit stream corresponding to each second eigenvalue; based on the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue, the result of the inner product operation of the first vector and the second vector is determined. In this way, by introducing randomness to each eigenvalue in the vector and converting it into a bit stream, and performing a vector inner product operation based on the bit stream, the probability of bit flipping can be reduced and the accuracy of the vector inner product operation can be improved.

[0010] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0012] Figure 1A schematic diagram of a process flow of a vector inner product calculation method provided in an embodiment of the present application is shown;

[0013] Figure 2 One of the structural schematic diagrams of the vector inner product operation device provided in an embodiment of the present application is shown;

[0014] Figure 3 The second structural diagram of the vector inner product operation device provided in an embodiment of the present application is shown;

[0015] Figure 4 The third structural diagram of the vector inner product operation device provided in an embodiment of the present application is shown;

[0016] Figure 5 A schematic diagram of the structure of the in-memory computing unit Cell provided in an embodiment of the present application is shown;

[0017] Figure 6 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0019] In mathematics and computer science, a vector is a quantity with both magnitude and direction. In the fields of machine learning and deep learning, vectors are typically represented as one-dimensional arrays, where each element represents the value of a feature or attribute. For example, in image recognition tasks, vectors can be used to represent the pixel values ​​of an image; in natural language processing tasks, vectors can be used to represent the word embeddings (word vectors) of words. The inner product operation is often used to calculate the similarity or correlation between two vectors and plays an important role in various machine learning tasks. For example, in image processing or recommendation systems, the inner product can be used to calculate the similarity between feature vectors to determine whether they are related or close. In the forward propagation process of a neural network, the inner product is used to combine the input feature vector with the weights to calculate the output of the network layer. In algorithms such as support vector machines (SVM), the inner product can be used to calculate the relationship between samples in a nonlinear feature space, thereby implementing classification or regression tasks, etc.

[0020] In the process of using a general-purpose processor to perform the above-mentioned vector inner product operation, the general-purpose processor is prone to bit flips due to factors such as insufficient device power supply, power supply interference, and transmission interference, resulting in low vector operation accuracy. In this regard, an embodiment of the present application provides a vector inner product operation method. By introducing randomness to each number in the vector, the probability of bit flips can be reduced and the accuracy of the vector inner product operation can be improved.

[0021] See also Figure 1 , Figure 1 The flowchart of the vector inner product operation method provided in the embodiment of the present application is shown. The execution subject of the method can be an AI chip or a general-purpose processor, which can be used as a row and column multiplication and addition unit of the GEMM (General Matrix Multiply) module. In the embodiment of the present application, the execution subject is a processor as an example. As shown in the figure, the vector inner product operation method 100 may include the following steps:

[0022] Step S101: Obtain the first input vector.

[0023] The first vector can be used to represent the feature vector representation of the data. These feature vectors can be one-dimensional arrays, where each element represents the value of a feature. In image processing, the first vector can be used to represent the vector representation of image features. Each first eigenvalue can represent the pixel value of the image or a value used to represent deep features such as the structure, texture, and shape of the image. In natural language processing, the first vector can be used to represent the word vector representation of text. Each first eigenvalue can represent a value used to represent semantics or features, such as different semantics or feature information in word embeddings.

[0024] In an embodiment of the present application, a first vector is input into a processor, which obtains the input first vector and performs an inner product operation with a pre-stored second vector to obtain an inner product operation result. Here, in image processing, the inner product between two vectors can be used to measure the similarity between image features, and the inner product operation result can be used to indicate the degree of matching between image features; in natural language processing, the inner product between word vectors can be used to measure the semantic similarity between them, and the inner product operation result can be used to indicate the association between words, etc.

[0025] Step S102: Compare each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue.

[0026] The first eigenvalue in the first vector may be a pixel value of an image, a value used to represent deep features such as image structure, texture, shape, or a value used to represent semantics or features.

[0027] In an embodiment of the present application, a random number generator can be used to generate a random number sequence. For each first eigenvalue in the first vector, a comparator can be used to compare the first eigenvalue with a pre-generated random number sequence to obtain a first bit stream corresponding to the first eigenvalue. In this way, randomness can be introduced into each first eigenvalue in the first vector, and then, in a subsequent vector inner product operation, a vector inner product operation can be performed based on the bit stream to reduce the probability of bit flips.

[0028] Step S103: According to the positions of the second eigenvalues ​​corresponding to the plurality of pre-stored second bit streams in the second vector, obtain the first bit stream corresponding to each of the second bit streams, perform a bitwise AND operation on the obtained first bit stream and the corresponding second bit stream to obtain a third bit stream corresponding to each of the second eigenvalues.

[0029] The second eigenvalue in the second vector can be a pixel value of the image, a value used to represent deep features such as image structure, texture, shape, or a value used to represent semantics or features. The second eigenvalue in the second vector represents the same type of feature as the first eigenvalue in the first vector. For example, if the first vector is used to represent the word vector representation of text, the second vector will also be used to represent the word vector representation of text; if the first vector is used to represent the vector representation of image features, the second vector will also be used to represent the vector representation of image features.

[0030] In an embodiment of the present application, a plurality of pre-stored second bit streams are obtained, and the first bit stream corresponding to each second bit stream is obtained based on the position of the second eigenvalues ​​corresponding to the plurality of second bit streams in the second vector. For example, the second vector is [x1 x2 x3], and the input first vector is [y1 y2 y3]. Based on the position of the second eigenvalue x1 corresponding to the second bit stream in the second vector, the first bit stream y1 corresponding to the second bit stream is obtained. Then, the obtained first bit stream y1 is bitwise ANDed with the second bit stream x1 to obtain the third bit stream corresponding to x1*y1. Similarly, the third bit streams corresponding to x2*y2 and x3*y3 can be obtained in this way.

[0031] Step S104: determining an inner product operation result of the first vector and the second vector according to the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue.

[0032] In the embodiment of the present application, the predetermined bit value may be 1 or 0. According to the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue, the inner product operation result of the pre-stored second vector [x1 x2x3] and the input first vector [y1y2 y3] is determined.

[0033] In this way, by introducing randomness into each eigenvalue in the vector and converting it into a bit stream, and performing vector inner product operation based on the bit stream, the probability of bit flipping can be reduced and the accuracy of vector inner product operation can be improved.

[0034] In a possible implementation, in step S102, comparing each first eigenvalue in the input first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue includes:

[0035] For each first eigenvalue in the first vector, compare the binary number corresponding to the first eigenvalue with a pre-generated random number sequence; if the binary number corresponding to the first eigenvalue is greater than or equal to the random number sequence, the comparison result is 1; if the binary number corresponding to the first eigenvalue is less than the random number sequence, the comparison result is 0; determine the first bit stream corresponding to the first eigenvalue based on the comparison result; and obtain the first bit stream corresponding to each first eigenvalue in the first vector.

[0036] In an embodiment of the present application, for each first eigenvalue in the first vector, the first eigenvalue is converted into a binary number. Taking A4'b1010 as an example, A=4'b1010 indicates that A is a 4-bit binary number. The binary number is compared with a pre-generated random number sequence. When the binary number A is greater than or equal to the random number sequence, the comparison result is 1; when the binary number A is less than the random number sequence, the comparison result is 0. The first bit stream corresponding to the first eigenvalue is determined based on the comparison result. For example, if the pre-generated random number sequence is 1011 and the comparison result is 0, the first bit stream corresponding to the first eigenvalue is 0. Similarly, after multiple comparisons, the first bit stream corresponding to each first eigenvalue in the first vector is obtained.

[0037] In specific applications, the length of the random number sequence can be determined according to the number of bits in the binary number. Taking A4'b1010 as an example, the length of the random number sequence can be 2 4 = 16. When performing comparison, the binary number is converted from 4 bits to a 16-bit bit stream after 16 comparisons.

[0038] In a possible implementation, before the step S101 of obtaining the first input vector, the following steps are further included:

[0039] Compare each second eigenvalue in the second vector with a pre-generated random number sequence to obtain a second bit stream corresponding to each second eigenvalue in the second vector; and store the second bit stream corresponding to each second eigenvalue in the second vector in the first storage unit.

[0040] In an embodiment of the present application, before obtaining the input first vector, a second bit stream can be pre-stored in a preset first storage unit. Specifically, each second eigenvalue in the second vector can be compared with a pre-generated random number sequence to obtain a second bit stream corresponding to each second eigenvalue in the second vector; and each second bit stream is stored in the first storage unit.

[0041] The first storage unit includes a plurality of storage units; storing the second bit stream corresponding to each second eigenvalue in the second vector into the first storage unit includes:

[0042] The second bit stream corresponding to each second eigenvalue in the second vector is stored in the corresponding first storage unit according to a preconfigured storage rule.

[0043] In the embodiment of the present application, the plurality of second bit streams may be stored in the corresponding first storage units respectively according to the pre-configured storage rule, for example, [x1 x2 x3]*[y1 y2 y3] T Convert x1, x2, and x3 into second bit streams, respectively. Store the multiple second bit streams in columns in multiple first storage units, with x1 in the first column, x2 in the second column, and x3 in the third column. Transfer y1, y2, and y3 data to the corresponding first storage units for multiplication. In this way, within the same operation cycle, the second bit stream in each first storage unit can be bitwise ANDed with the corresponding first bit stream to obtain a third bit stream, improving the efficiency of the inner product operation.

[0044] In a possible implementation, in step S102, after comparing each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue in the first vector, the method further includes:

[0045] Storing a first bit stream corresponding to each first eigenvalue in the first vector in a second storage unit;

[0046] In the above step S103, obtaining the first bit stream corresponding to each of the plurality of pre-stored second bit streams according to the position of the second eigenvalues ​​corresponding to the second bit streams in the second vector includes:

[0047] Obtaining, according to positions of the second eigenvalues ​​corresponding to the plurality of pre-stored second bit streams in the second vector, a strobe address of the first bit stream corresponding to each of the second bit streams in the second storage unit;

[0048] A corresponding first bit stream is obtained from the second storage unit according to the selection address.

[0049] In this way, by storing the first bit stream corresponding to each first eigenvalue in the first vector into the second storage unit, and obtaining the first bit stream corresponding to each second bit stream in the second storage unit according to the selection address, the corresponding first bit stream can be accurately obtained, thereby improving the accuracy of the inner product operation.

[0050] In a possible implementation, in step S104, determining the result of the inner product operation of the first vector and the second vector according to the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue includes:

[0051] Determine the number of predetermined bit values ​​in each third bit stream; accumulate the numbers determined for each third bit stream to obtain an inner product operation result of the first vector and the second vector.

[0052] Continuing with the above example, let's take the pre-stored second vector as [x1 x2 x3] and the input first vector as [y1y2 y3]. Assuming the binary number corresponding to y1 is A4'b1010 and the binary number corresponding to x2 is B4'b1100, the corresponding converted bit streams are shown in the following table:

[0053] A 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 1 10 B 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 12 C 1 1 1 0 1 0 0 1 0 0 0 0 0 1 1 1 8

[0054] Perform a bitwise AND operation on A and B to obtain a third bit stream C. Determine that the number of bits with a value of 1 in the third bit stream C is 8, and thus obtain the value of x1*y1 as 8. Similarly, the number of bits with a value of 1 in the third bit stream corresponding to x2*y2 and x3*y3 can be obtained, and accumulated to obtain the inner product of the first and second vectors.

[0055] The embodiment of the present application provides a vector inner product operation method, which obtains an input first vector; compares each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue; obtains a first bit stream corresponding to each second bit stream based on the position of the second eigenvalue corresponding to multiple pre-stored second bit streams in the second vector, performs a bitwise AND operation on the obtained first bit stream and the corresponding second bit stream to obtain a third bit stream corresponding to each second eigenvalue; and determines the inner product operation result of the first vector and the second vector based on the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue. In this way, by introducing randomness to each eigenvalue in the vector and converting it into a bit stream, and performing a vector inner product operation based on the bit stream, the probability of bit flipping can be reduced and the accuracy of the vector inner product operation can be improved.

[0056] Figure 2 FIG. 1 shows one of the structural diagrams of the vector inner product operation device provided in an embodiment of the present application. The vector inner product operation device can implement the following Figure 1In the embodiment shown, all or part of the content, the vector inner product operation device 200 includes:

[0057] A vector input module 210 is configured to obtain a first input vector;

[0058] a random encoding module 220, configured to compare each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue;

[0059] an in-memory operation module 230 for obtaining, based on positions of second eigenvalues ​​corresponding to a plurality of pre-stored second bit streams in the second vector, first bit streams corresponding to each second bit stream, and performing a bitwise AND operation on the obtained first bit stream and the corresponding second bit stream to obtain a third bit stream corresponding to each second eigenvalue;

[0060] The inner product operation module 240 is configured to determine an inner product operation result of the first vector and the second vector according to the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue.

[0061] In specific implementation, Figure 3 As shown, a random number generator 221 is used to generate a random number sequence. For each first eigenvalue in the first vector, a comparator 222 is used to compare the first eigenvalue with the pre-generated random number sequence to obtain a first bit stream corresponding to the first eigenvalue. In this way, randomness can be introduced into each first eigenvalue in the first vector, and then in the subsequent vector inner product operation process, a vector inner product operation is performed based on the bit stream to reduce the probability of bit flipping.

[0062] In one possible implementation, the random encoding module 220, when used to compare each first eigenvalue in the input first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue in the first vector, is specifically configured to:

[0063] For each first eigenvalue in the first vector, compare the binary number corresponding to the first eigenvalue with a pre-generated random number sequence, where if the binary number corresponding to the first eigenvalue is greater than or equal to the random number sequence, the comparison result is 1; if the binary number corresponding to the first eigenvalue is less than the random number sequence, the comparison result is 0; and determine a first bit stream corresponding to the first eigenvalue based on the comparison result;

[0064] Obtain a first bit stream corresponding to each first eigenvalue in the first vector.

[0065] In one possible implementation, Figure 4 and Figure 5As shown in , the random encoding module 220 is further used to compare each second eigenvalue in the second vector with a pre-generated random number sequence to obtain a second bit stream corresponding to each second eigenvalue in the second vector; and store the second bit stream corresponding to each second eigenvalue in the second vector in the first storage unit 2321.

[0066] In a possible implementation, the vector inner product operation device 200 further includes:

[0067] A second storage unit 250 is configured to store a first bit stream corresponding to each first eigenvalue in the first vector;

[0068] The in-memory operation module 230, when used to obtain the first bit stream corresponding to each of the plurality of pre-stored second bit streams based on the position of the second eigenvalues ​​corresponding to the second bit streams in the second vector, is specifically used to:

[0069] According to the positions of the second eigenvalues ​​corresponding to the plurality of pre-stored second bit streams in the second vector, the gating addresses of the first bit streams corresponding to the respective second bit streams in the second storage unit are obtained; and the corresponding first bit streams are obtained in the second storage unit according to the gating addresses.

[0070] The in-memory operation module 230 includes a controller 231 and a plurality of in-memory operation units Cell; each in-memory operation unit Cell includes a first storage unit 2321 and an AND gate 2322;

[0071] The controller 231 is configured to obtain, based on the position of the second eigenvalue corresponding to the second bit stream pre-stored in the first storage unit 2321 in the second vector, a strobe address of the first bit stream corresponding to each second bit stream in the second storage unit 250; and obtain the corresponding first bit stream in the second storage unit 250 according to the strobe address;

[0072] A first storage unit 2321 is configured to store a second bit stream a;

[0073] The AND gate 2322 is configured to obtain the pre-stored second bit stream b in the first storage unit 2321 and perform an AND operation on the pre-stored second bit stream b and the first bit stream c to obtain a third bit stream d.

[0074] In one possible implementation, the inner product calculation module 240 includes:

[0075] a counter unit for determining the number of predetermined bit values ​​in each third bit stream;

[0076] An adder unit is configured to accumulate the quantities determined by the respective third bit streams to obtain an inner product operation result of the first vector and the second vector.

[0077] The embodiment of the present application provides a vector inner product operation device, including a vector input module, a random encoding module, an in-memory operation module and an inner product operation module; the vector input module obtains an input first vector; the random encoding module compares each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue; the in-memory operation module obtains the first bit stream corresponding to each second bit stream according to the position of the second eigenvalue corresponding to a plurality of pre-stored second bit streams in the second vector, performs a bitwise AND operation on the obtained first bit stream and the corresponding second bit stream to obtain a third bit stream corresponding to each second eigenvalue; the inner product operation module determines the inner product operation result of the first vector and the second vector according to the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue. In this way, by introducing randomness to each eigenvalue in the vector and converting it into a bit stream, and performing a vector inner product operation based on the bit stream, the probability of bit flipping can be reduced and the accuracy of the vector inner product operation can be improved.

[0078] Moreover, within the same operation cycle, the second bit stream in each first storage unit can be bitwise ANDed with the corresponding first bit stream to obtain a third bit stream. Multiple in-memory operation units Cell can realize parallel operation of bit streams, which can improve the efficiency of inner product operation.

[0079] Figure 6 A schematic diagram of the hardware structure of an electronic device that implements an embodiment of the present application is shown. Referring to the figure, at the hardware level, the electronic device 600 includes a processor 610, and optionally, an internal bus 620, a network interface 630, and a memory 640. Among them, the memory 640 may include a memory 641, such as a high-speed random access memory (RAM), and may also include a non-volatile memory 642 (non-volatile memory), such as at least one disk storage device. Of course, the electronic device may also include hardware required for other services.

[0080] The processor 610, the network interface 630, and the memory can be interconnected via an internal bus 620. The internal bus 620 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Such buses can be classified as address buses, data buses, control buses, and the like. For ease of illustration, only one bidirectional arrow is used in this figure, but this does not imply that there is only one bus or only one type of bus.

[0081] The memory 640 stores programs. Specifically, the programs may include program codes, which include computer operating instructions. The memory 640 may include a memory 641 and a non-volatile memory 642, and provides instructions and data to the processor 610.

[0082] The processor 610 reads the corresponding computer program from the non-volatile memory 642 into the memory and then runs it, forming a device for locating the target user at the logical level. The processor 610 executes the program stored in the memory and specifically performs the following: Figure 1 The methods disclosed in the illustrated embodiments implement the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be described in detail here.

[0083] The above application Figure 1The methods disclosed in the illustrated embodiments can be applied to or implemented by processor 610. Processor 610 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits or software instructions in processor 610. The above-mentioned processor 610 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in conjunction with the embodiments of this application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0084] The computer device can also execute the methods described in the above method embodiments and realize the functions and beneficial effects of the methods described in the above method embodiments, which will not be repeated here.

[0085] Of course, in addition to software implementation, the electronic device of this application does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0086] The embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, which, when executed by an electronic device including multiple application programs, enables the electronic device to execute Figure 1 The methods disclosed in the illustrated embodiments implement the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be described in detail here.

[0087] The computer-readable storage medium includes a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0088] Furthermore, an embodiment of the present application provides a computer program product, comprising a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program comprises program instructions. When the program instructions are executed by a computer, the following process is implemented: Figure 1 The methods disclosed in the illustrated embodiments implement the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be described in detail here.

[0089] The embodiments of the present application can be applied to various electronic device collaboration or interconnection scenarios, including: collaboration and interconnection between mobile phones and laptops / tablets; collaboration and interconnection between mobile terminals and smart TVs / displays; collaboration and interconnection between mobile phones or tablets and in-car entertainment systems; collaboration and interconnection between mobile terminals and smart conference systems, etc., thereby meeting the diverse needs of users in scenarios such as smart homes, smart offices, and smart travel.

[0090] In short, the above description is only a preferred embodiment of the present application and does not limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

[0091] The systems, devices, modules, or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0092] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0093] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0094] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

Claims

1. A vector inner product calculation method, characterized in that: include: Get the first vector of input; Comparing each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue; Obtaining, based on positions of second eigenvalues ​​corresponding to a plurality of pre-stored second bit streams in the second vector, first bit streams corresponding to the respective second bit streams, and performing a bitwise AND operation on the obtained first bit streams and the corresponding second bit streams to obtain third bit streams corresponding to the respective second eigenvalues; An inner product operation result of the first vector and the second vector is determined according to the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue.

2. The method according to claim 1, characterized in that The step of comparing each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue includes: For each first eigenvalue in the first vector, compare the binary number corresponding to the first eigenvalue with a pre-generated random number sequence, where if the binary number corresponding to the first eigenvalue is greater than or equal to the random number sequence, the comparison result is 1; if the binary number corresponding to the first eigenvalue is less than the random number sequence, the comparison result is 0; and determine a first bit stream corresponding to the first eigenvalue based on the comparison result; Obtain a first bit stream corresponding to each first eigenvalue in the first vector.

3. The method according to claim 1, characterized in that Before obtaining the first input vector, the method further includes: Comparing each second eigenvalue in the second vector with a pre-generated random number sequence to obtain a second bit stream corresponding to each second eigenvalue in the second vector; The second bit stream corresponding to each second eigenvalue in the second vector is stored in the first storage unit.

4. The method according to claim 3, characterized in that The first storage unit includes a plurality of units; and the storing the second bit stream corresponding to each second eigenvalue in the second vector into the first storage unit includes: The second bit stream corresponding to each second eigenvalue in the second vector is stored in the corresponding first storage unit according to a preconfigured storage rule.

5. The method according to claim 1, wherein After comparing each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue, the method further includes: Storing a first bit stream corresponding to each first eigenvalue in the first vector in a second storage unit; The obtaining, according to positions of second eigenvalues ​​corresponding to the plurality of pre-stored second bit streams in the second vector, a first bit stream corresponding to each second bit stream includes: Obtaining, according to positions of the second eigenvalues ​​corresponding to the plurality of pre-stored second bit streams in the second vector, a strobe address of the first bit stream corresponding to each of the second bit streams in the second storage unit; A corresponding first bit stream is obtained from the second storage unit according to the selection address.

6. The method according to claim 1, characterized in that The determining, based on the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue, a result of an inner product operation between the first vector and the second vector includes: determining a number of predetermined bit values ​​in each third bit stream; The quantities determined by the respective third bit streams are accumulated to obtain an inner product operation result of the first vector and the second vector.

7. A vector inner product operation device, characterized in that: include: A vector input module, used to obtain a first input vector; a random encoding module, configured to compare each first eigenvalue in the first vector with a pre-generated random number sequence to obtain a first bit stream corresponding to each first eigenvalue; an in-memory operation module, configured to obtain, based on positions of second eigenvalues ​​corresponding to a plurality of pre-stored second bit streams in the second vector, a first bit stream corresponding to each of the second bit streams, and perform a bitwise AND operation on the obtained first bit stream and the corresponding second bit stream to obtain a third bit stream corresponding to each of the second eigenvalues; The inner product operation module is used to determine the inner product operation result of the first vector and the second vector according to the number of predetermined bit values ​​in the third bit stream corresponding to each second eigenvalue.

8. The device according to claim 7, characterized in that Also includes: a second storage unit, configured to store a first bit stream corresponding to each first eigenvalue in the first vector; The in-memory operation module, when used to obtain the first bit stream corresponding to each of the plurality of pre-stored second bit streams based on the position of the second eigenvalues ​​corresponding to the second bit streams in the second vector, is specifically used to: According to the positions of the second eigenvalues ​​corresponding to the plurality of pre-stored second bit streams in the second vector, the gating addresses of the first bit streams corresponding to the respective second bit streams in the second storage unit are obtained; and the corresponding first bit streams are obtained in the second storage unit according to the gating addresses.

9. The device according to claim 7, characterized in that The inner product operation module includes: a counter unit for determining the number of predetermined bit values ​​in each third bit stream; An adder unit is configured to accumulate the quantities determined by the respective third bit streams to obtain an inner product operation result of the first vector and the second vector.

10. An electronic device, characterized in that: The electronic device includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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