Logic comprehensive optimization operator acceleration method

Abstract

The invention belongs to the field of electronic design automation (EDA), and particularly provides a logic comprehensive optimization operator acceleration method, which introduces a screening strategy of a sub-circuit diagram, and improves the optimization efficiency of an operator on the premise of ensuring the optimization quality of the operator. According to the method, the sub-circuit diagrams are classified by using the graph neural network, and the sub-diagrams suitable for operator execution are screened out, so that all the sub-diagrams are prevented from being traversed, and the operator execution speed is increased; in the sub-graph screening, a screening range is set according to the execution sequence of operators, a relatively large screening range is set for the operators executed firstly so as to obtain a better optimization effect, and a relatively small screening range is set for the operators executed later so as to obtain a higher execution speed; in conclusion, the characteristic that the logic comprehensive optimization operator is continuously executed in a sequence mode is utilized, and the operator optimization efficiency is improved on the premise that the operator optimization quality is guaranteed.

Description

Technical Field

[0001] The present invention belongs to the field of Electronic Design Automation (EDA), and specifically provides a logic synthesis optimization operator acceleration method. Background Art

[0002] In integrated circuit design, the function of logic synthesis is to convert the register transfer level (RTL) hardware description language into a gate-level netlist. A core step of logic synthesis is to optimize parameters such as circuit structure, timing, area, and power consumption through optimization operators to generate a physical implementation solution that meets the design constraints.

[0003] Logic synthesis optimization operators are the basic operational units of logic synthesis optimization. Common optimization operators include logic rewrite, logic refactor, and logic replacement. Based on the scope of the operator, logic synthesis optimization operators can be divided into two categories: local optimization operators and global optimization operators. Local optimization operators act on a local subcircuit, optimizing the entire circuit by optimizing each subcircuit one by one. Global optimization operators act directly on the entire circuit, optimizing the entire circuit at once. Logic synthesis optimization of a circuit typically requires the use of multiple operators, including local and global optimization operators. These operators form an operator sequence. During the optimization process, the operators in the operator sequence are executed sequentially to continuously optimize the circuit.

[0004] Traditional logic synthesis operator optimization methods use a traversal strategy to apply local optimization operators, traversing all subgraphs in the circuit and executing local operators on each subgraph. This approach can exhaustively optimize all subgraphs, but it incurs significant computational overhead and may introduce computational redundancy, as executing optimization operators on some subgraphs may not lead to circuit optimization. Therefore, how to screen subgraphs to improve optimization efficiency while ensuring optimization quality has become a worthy research question. In recent years, neural networks have demonstrated superior modeling capabilities in circuit optimization tasks and have been applied to subgraph classification and screening. However, existing logic synthesis optimization operator acceleration methods primarily consider the acceleration of individual operators in isolation, ignoring the fact that operators are executed sequentially and that the optimization effect of an operator is affected by its predecessors in the sequence. Summary of the Invention

[0005] The purpose of the present invention is to provide a logic synthesis optimization operator acceleration method to address the above-mentioned deficiencies in the prior art, introduce a sub-circuit diagram screening strategy, and improve the optimization efficiency of the operator while ensuring the quality of the operator optimization.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] A logic synthesis optimization operator acceleration method, characterized by comprising the following steps:

[0008] A1. Build and train the operator effectiveness model:

[0009] A1-1. Forming a set of local optimization operators: Define logic synthesis optimization operators that optimize each subgraph of a circuit diagram as a local optimization operator. Filter out the local optimization operators and form a set of local optimization operators T.

[0010] A1-2. Construct training samples for each operator t in the local optimization operator set T and train the operator effectiveness model;

[0011] A2. Take the operator: Assume that the length of the input optimization operator sequence is N, and take the nth operator z from the optimization operator sequence. n , where the initial value of n is 1;

[0012] A3. Determine the local optimization operator: Determine operator z n Is it a local optimization operator? If not, go to step A4; if yes, go to step A5;

[0013] A4. Execute operator: Execute operator z on the entire input test circuit n ;

[0014] A5. Execute the operator:

[0015] A5-1. Prediction operator effectiveness: Divide the input test circuit diagram into non-overlapping subgraphs and use operator z n The corresponding operator effectiveness model predicts the operator effectiveness of each subgraph and obtains the predicted value of its operator effectiveness;

[0016] A5-2. Sort all subgraphs by operator validity prediction value from large to small, and select the top K n subgraphs, and execute operators z on them in turn n ;

[0017] A6. Determine whether the optimization operator sequence has been traversed: Update n to n+1 and make a judgment. If n≤N, go to step A2 and continue the optimization. Otherwise, end the optimization and output the optimized circuit.

[0018] Furthermore, the specific process of step A1-2 is as follows:

[0019] A1-2-1. Construct training samples: Divide the training circuit diagram into several subgraphs, set a valid or invalid label for each subgraph, and group the subgraph and its label into a training sample pair;

[0020] A1-2-2. Build an operator effectiveness model, including graph convolutional layers and perceptron layers.

[0021] The graph convolution layer contains nodes and edges of the graph network. Its construction process is as follows: for each logic gate in the input subgraph, a logic gate node is created, the logic gate node corresponding to the subgraph root node is recorded as the root node, and the initial value of the feature vector of each logic gate node is set; for each pair of logic gates in the subgraph, an edge is created from the input logic gate node to the output logic gate node;

[0022] The perceptron layer includes an input layer, a hidden layer, and an output layer. The number of neurons in the input layer is the same as the dimension of the feature vector of the logic gate node of the graph convolution layer. The input layer receives the feature vector of the root node and transmits it to the hidden layer. The output layer contains one neuron, and its output data corresponds to the operator validity prediction value of the input subgraph.

[0023] A1-2-3. Train the operator effectiveness model: Set the loss function and use the backpropagation algorithm to complete the model training to obtain the operator effectiveness prediction model.

[0024] Furthermore, the label setting process of step A1-2-1 is: execute operator t on each subgraph, and determine whether the number of circuit logic gates decreases after the operator is executed compared to before execution. If it decreases, set the label of the current subgraph to valid execution; otherwise, set the label of the current subgraph to invalid execution.

[0025] Furthermore, the loss function in step A1-2-3 is:

[0026]

[0027] in, and y are the predicted value and ideal value of operator effectiveness output by the model output layer, respectively. y is a binary variable with a value of 0 or 1, indicating that the label in the current training sample pair is invalid or valid.

[0028] Furthermore, in step A5-2, K n Specifically:

[0029]

[0030] Among them, U0 is the number of logic gates of the input circuit, U n-1 with U n-2 They represent the number of logic gates of the circuit after executing the n-1th and n-2th operators respectively, and α is a preset proportional parameter.

[0031] Based on the above technical solution, the beneficial effects of the present invention are:

[0032] The present invention provides a logic synthesis optimization operator acceleration method, which uses a graph neural network to classify sub-circuit diagrams and screen out sub-graphs suitable for operator execution, thereby avoiding traversal of all sub-graphs and speeding up the operator execution speed; in the sub-graph screening, the screening range is set according to the order of operator execution, a larger screening range is set for the operator executed first to obtain a better optimization effect, and a smaller screening range is set for the operator executed later to obtain a faster execution speed; in summary, the present invention utilizes the characteristic of the logic synthesis optimization operator being executed continuously in a serial manner, thereby improving the operator optimization efficiency while ensuring the operator optimization quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the flow of the logic synthesis optimization operator acceleration method in the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0035] This embodiment provides a logic synthesis optimization operator acceleration method, the process of which is as follows: Figure 1 The specific steps are as follows:

[0036] A1. Build and train the operator effectiveness model:

[0037] A1-1. Forming a set of local optimization operators: Define logic synthesis optimization operators that optimize each subgraph of a circuit diagram as a local optimization operator. Filter out the local optimization operators and form a set of local optimization operators T.

[0038] Filter out local optimization operators from common logic synthesis optimization operators. In this embodiment, the local optimization operators selected are: rewrite, refactor, and resub. These operators are combined into a local optimization operator set T, that is, T = {rewrite, refactor, resub};

[0039] A1-2. Construct training samples for each operator t in the local optimization operator set T and train the operator effectiveness model:

[0040] In this embodiment, taking the local optimization operator resub in the set T as an example, training samples are constructed for the operator resub and the operator effectiveness model is trained.

[0041] A1-2-1. Constructing training samples: Divide the training circuit diagram into several subgraphs and assign a valid or invalid label to each subgraph. The process is as follows: Execute operator t on each subgraph and determine whether the number of logic gates in the circuit decreases after the operator is executed. If so, set the label of the current subgraph to valid; otherwise, set the label of the current subgraph to invalid. Group the subgraph and its label as a training sample pair.

[0042] In this embodiment, the operator resub is executed on each divided subgraph g. After the execution, the number of logic gates in the circuit is counted. If the number of logic gates decreases compared to before the operator execution, the label of the current subgraph is set to execution valid, forming a training sample pair: (g, execution valid); otherwise, the training sample pair: (g, execution invalid) is formed.

[0043] A1-2-2. Build an operator effectiveness model, including graph convolutional layers and perceptron layers.

[0044] The graph convolution layer contains nodes and edges of the graph network. Its construction process is as follows: for each logic gate in the input subgraph, a logic gate node is created, the logic gate node corresponding to the subgraph root node is recorded as the root node, and the initial value of the feature vector of each logic gate node is set; for each pair of logic gates in the subgraph, an edge is created from the input logic gate node to the output logic gate node;

[0045] In this embodiment, for the operator resub, the initial value of the feature vector of each logic gate node is set to be a 20-dimensional vector, which includes 8-dimensional root node feature data and two 6-dimensional root node input node feature data, wherein the root node feature data includes the node number (1 dimension), the number of fan-outs (1 dimension), the number of positive logic layers (1 dimension), the number of reverse logic layers (1 dimension), whether the first input edge is inverted (1 dimension), whether the second input edge is inverted (1 dimension), the number of leaves (1 dimension) and the number of cut sets (1 dimension), etc. The input node feature data of the root node includes the node number (1 dimension), the number of fan-outs (1 dimension), the number of positive logic layers (1 dimension), the number of reverse logic layers (1 dimension), whether input edge 0 is inverted (1 dimension), whether input edge 1 is inverted (1 dimension), etc.;

[0046] The perceptron layer includes an input layer, a hidden layer, and an output layer. The number of neurons in the input layer is the same as the dimension of the feature vector of the logic gate node of the graph convolution layer. The input layer receives the feature vector of the root node and transmits it to the hidden layer. The output layer contains one neuron, and its output data corresponds to the operator validity prediction value of the input subgraph.

[0047] In this embodiment, the number of neurons in the input layer of the perceptron is 20;

[0048] A1-2-3. Train the operator effectiveness model: Set the loss function and use the backpropagation algorithm to complete the model training to obtain the operator effectiveness prediction model;

[0049] In this embodiment, the loss function is:

[0050]

[0051] in, and y are the predicted value and ideal value of operator effectiveness output by the model output layer, respectively. y is a binary variable with a value of 0 or 1, indicating that the label in the current training sample pair is invalid or valid.

[0052] A2. Take the operator: Assume that the length of the input optimization operator sequence is N, and take the nth operator z from the optimization operator sequence. n , where the initial value of n is 1;

[0053] In this embodiment, the input optimization operator sequence is: balance → resub → rewrite → resub → refactor → resub → balance → resub → rewrite → resub → rewrite → resub → balance → resub → refactor → resub → rewrite → balance. The length of the operator sequence is 18, that is, N = 18. Taking n = 1 as an example, the first operator z1 = balance is taken from the optimization operator sequence;

[0054] A3. Determine the local optimization operator: Determine operator z n Is it a local optimization operator? If not, go to step A4; if yes, go to step A5;

[0055] In this embodiment, taking n=1 as an example, the operator z1 is not a local optimization operator, and the process goes to step A4; taking n=2 as an example, the operator z2=resub is a local optimization operator, and the process goes to step A5;

[0056] A4. Execute operator: Execute operator z on the entire input test circuit n ;

[0057] In this embodiment, taking n=1 as an example, since the operator z1=balance is not a local optimization operator, the operator balance is executed on the entire input test circuit;

[0058] A5. Execute the operator:

[0059] A5-1. Prediction operator effectiveness: Divide the input test circuit diagram into non-overlapping subgraphs and use operator z nThe corresponding operator effectiveness model predicts the operator effectiveness of each subgraph and obtains the predicted value of its operator effectiveness;

[0060] In this embodiment, taking n=2 as an example, since the operator z2=resub is a local optimization operator, the operator effectiveness model corresponding to the operator z2 is used to predict the operator effectiveness of each subgraph of the test circuit diagram to obtain the predicted value of the operator effectiveness of each subgraph;

[0061] A5-2. Sort all subgraphs by operator validity prediction value from large to small, and select the top K n subgraphs, and execute operators z on them in turn n , where K n The calculation formula is as follows:

[0062]

[0063] Among them, U0 is the number of logic gates of the input circuit, U n-1 with U n-2 They represent the number of logic gates of the circuit after executing the n-1th and n-2th operators, respectively, and α is a preset scaling parameter;

[0064] In this embodiment, the formula is used to calculate The range of the scale parameter α is 1≤α≤5. In this embodiment, the value is 5. The number of logic gates in the input circuit is U0=32060. After executing the first operator, the number of logic gates in the circuit is U1=30357. Therefore, K2=15652 is calculated. Therefore, the first 15652 subgraphs with the largest operator validity prediction values ​​are taken and the operator resub is executed on them in sequence.

[0065] A6. Determine whether the optimization operator sequence has been traversed: Update n to n+1 and make a judgment. If n≤N, go to step A2 and continue optimization. Otherwise, end the optimization and output the optimized circuit.

[0066] In this embodiment, each operator in the optimization operator sequence is traversed. When n=N=18, the traversal is completed, and the entire process ends, and the optimized circuit is output.

[0067] To evaluate the performance of the method of the present invention, the method of the present invention is compared with the traditional method, using two indicators: running time and the number of AND gates reduced. The input circuit and the optimized operator sequence of the embodiment are used as input. The experimental results are shown in Table 1.

[0068] Table 1

[0069] method Runtime AND gates reduce the number Traditional methods 126.31s 2872 Method of the present invention 85.07s 2863

[0070] It can be seen that after acceleration by the method of the present invention, the running time is greatly reduced, while the number of AND gates is only slightly reduced, indicating that the method of the present invention can improve the efficiency of operator optimization while ensuring the quality of operator optimization.

[0071] The above description is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes; all disclosed features, or all steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A logic synthesis optimization operator acceleration method, characterized in that: The following steps are involved: A1. Build and train the operator effectiveness model: A1-1. Forming a set of local optimization operators: Define logic synthesis optimization operators that optimize each subgraph of a circuit diagram as a local optimization operator. Filter out the local optimization operators and form a set of local optimization operators T. A1-2. Construct training samples for each operator t in the local optimization operator set T and train the operator effectiveness model; A2. Take the operator: Assume that the length of the input optimization operator sequence is N, and take the nth operator z from the optimization operator sequence. n , where the initial value of n is 1; A3. Determine the local optimization operator: Determine operator z n Is it a local optimization operator? If not, go to step A4; if yes, go to step A5; A4. Execute operator: Execute operator z on the entire input test circuit n ; A5. Execute the operator: A5-1. Prediction operator effectiveness: Divide the input test circuit diagram into non-overlapping subgraphs and use operator z n The corresponding operator effectiveness model predicts the operator effectiveness of each subgraph and obtains the predicted value of its operator effectiveness; A5-2. Sort all subgraphs by operator validity prediction value from large to small, and select the top K n subgraphs, and execute operators z on them in turn n ; A6. Determine whether the optimization operator sequence has been traversed: Update n to n+1 and make a judgment. If n≤N, go to step A2 and continue the optimization. Otherwise, end the optimization and output the optimized circuit.

2. The logic synthesis optimization operator acceleration method according to claim 1, characterized in that: The specific process of step A1-2 is as follows: A1-2-1. Construct training samples: Divide the training circuit diagram into several subgraphs, set a valid or invalid label for each subgraph, and group the subgraph and its label into a training sample pair; A1-2-2. Build an operator effectiveness model, including graph convolutional layers and perceptron layers. The graph convolution layer contains nodes and edges of the graph network. Its construction process is as follows: for each logic gate in the input subgraph, a logic gate node is created, the logic gate node corresponding to the subgraph root node is recorded as the root node, and the initial value of the feature vector of each logic gate node is set; for each pair of logic gates in the subgraph, an edge is created from the input logic gate node to the output logic gate node; The perceptron layer includes an input layer, a hidden layer, and an output layer. The number of neurons in the input layer is the same as the dimension of the feature vector of the logic gate node of the graph convolution layer. The input layer receives the feature vector of the root node and transmits it to the hidden layer. The output layer contains one neuron, and its output data corresponds to the operator validity prediction value of the input subgraph. A1-2-3. Train the operator effectiveness model: Set the loss function and use the backpropagation algorithm to complete the model training to obtain the operator effectiveness prediction model.

3. The logic synthesis optimization operator acceleration method according to claim 2, characterized in that: The label setting process of step A1-2-1 is: execute operator t for each subgraph, and determine whether the number of circuit logic gates decreases after the operator is executed compared to before execution. If it decreases, set the label of the current subgraph to execution valid; otherwise, set the label of the current subgraph to execution invalid.

4. The logic synthesis optimization operator acceleration method according to claim 2, characterized in that: The loss function in step A1-2-3 is: in, and y are the predicted value and ideal value of operator effectiveness output by the model output layer, respectively. y is a binary variable with a value of 0 or 1, indicating that the label in the current training sample pair is invalid or valid.

5. The logic synthesis optimization operator acceleration method according to claim 1, characterized in that: K in step A5-2 n Specifically: Among them, U0 is the number of logic gates of the input circuit, U n-1 with U n-2 They represent the number of logic gates of the circuit after executing the n-1th and n-2th operators respectively, and α is a preset proportional parameter.

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