An automated synthesis system for asynchronous pipelines to asynchronous circuits

Abstract

The application discloses an automatic synthesis system of an asynchronous pipeline to an asynchronous circuit, adopts a modular architecture, takes a high-level structure description file in a JSON / XML format as input, gradually maps to generate a gate-level netlist and a standard delay format file, and is connected to a commercial back-end design process.The application can automatically map asynchronous design based on an asynchronous structure to an asynchronous circuit, the automatic mapping process can seamlessly process multi-level design representation, the mapping result is stable and cooperatively operated, and timing detection and delay matching of the asynchronous circuit are automatically completed, so that the design efficiency is greatly improved, the automatic delay matching mechanism makes the circuit have good data ready detection and handshaking mechanism, low power consumption, high throughput and no global clock drift sensitivity are realized; in addition, while guaranteeing design readability, level consistency and timing controllability, structure abstraction, delay modeling, testability insertion and other key links of asynchronous design are realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of asynchronous circuit design, and particularly relates to an automatic synthesis system of asynchronous pipeline to asynchronous circuit. BACKGROUND

[0002] The working mechanism of an asynchronous circuit is realized by events generated by the logic of the circuit, and is independent of the clock generated by the crystal oscillator. The asynchronous circuit divides a specific task into an event stream (sequence), and the event stream drives the asynchronous chip to execute the task. The events and data can be uniformly coded or separately processed, and finally form a circuit subsystem with a specific function. The circuit subsystem and the circuit system are driven by events to perform their functions.

[0003] Although asynchronous circuits have many advantages in theory, they still face many challenges in practical engineering applications. At present, the asynchronous circuit system has not been fully established and is still in the development stage. The mainstream electronic design automation (EDA) tools mainly face synchronous circuit design, and there is no commercial EDA platform for asynchronous circuit design. Only a few open-source tools from research teams exist, and many asynchronous circuit development environments are also manually built internal tools. In addition, the design and verification methods of asynchronous circuits have not formed a unified standard. Compared with the widespread use of Verilog / VHDL and other hardware description languages for synchronous circuits, the description languages and design specifications of asynchronous circuits are not yet unified, which leads to poor compatibility between tools and limits the promotion and application of asynchronous circuits.

[0004] Overall, the existing asynchronous circuit design tools have the following defects:

[0005] 1. Low automation degree of asynchronous circuit mapping

[0006] A large amount of manual intervention and manual configuration is required in the mapping process. Designers need to make tedious adjustments and configurations according to circuit requirements, and manual operations are prone to errors, resulting in low design efficiency. This not only increases the design time and cost, but also cannot ensure the consistency and repeatability of the design process, reducing the overall design quality.

[0007] 2. Low efficiency in processing complex designs

[0008] When dealing with large-scale and complex designs, efficiency bottlenecks are often encountered, especially when facing multi-level asynchronous pipeline structures. There is often computational redundancy, and the mapping relationship of each layer cannot be effectively optimized, resulting in a time-consuming mapping process and excessive consumption of computing resources.

[0009] 3. Difficulty in preserving the advantages of asynchronous characteristics in the mapping process

[0010] Generally rely on the design idea of synchronous circuit, lack of depth understanding and optimization of asynchronous circuit characteristics. In the mapping process of asynchronous pipeline to asynchronous circuit, the timing flexibility, low power consumption characteristics and the advantages of clockless design of asynchronous circuit are often not fully considered, resulting in that the mapped circuit cannot fully exert the advantages of asynchronous circuit, but may introduce additional complexity and performance bottleneck, so that the mapping process is not only inefficient, but also may cause performance loss;

[0011] 4. Poor scalability

[0012] When processing large-scale or complex circuits, the scalability is poor, and it is often unable to adapt to the design requirements of larger scale integrated circuits. When mapping complex circuits, calculation bottlenecks or memory limitations are often encountered, resulting in that the design process cannot be completed efficiently. In addition, the modular design capability is weak, and it cannot flexibly cope with the circuit requirements of different scales and different complexities, limiting the scalability and adaptability of the design. SUMMARY

[0013] In order to solve the problems in the above background art, the present application provides an automatic synthesis system of asynchronous pipeline to asynchronous circuit, which realizes the full-process automation of automatic parsing, structure mapping, logic generation and delay matching of high-level structure description in JSON / XML format by constructing a tool chain based on C language.

[0014] In order to achieve the above purpose, the present application adopts the following technical scheme:

[0015] An automatic synthesis system of asynchronous pipeline to asynchronous circuit, which is a front-end EDA tool chain for asynchronous circuit design, adopts a modular architecture, takes a high-level structure description file in JSON / XML format as input, gradually maps to generate a gate-level netlist and a standard delay format file, and connects to a commercial back-end design process.

[0016] The automatic synthesis system comprises:

[0017] FlowParse module: used for syntax parsing and semantic extraction of high-level structure description file in JSON / XML format, and constructing flow structure FlowSt; the output of FlowParse module is FlowStTop data structure or gate-level netlist file, which is used as the input of next stage Flow2Micro module; wherein, FlowStTop data structure is the top summary of FlowSt, and FlowParse module retains the annotation information in the gate-level netlist file to FlowStTop structure for module debugging and visualization;

[0018] Flow2Micro module: used to map the asynchronous control logic (such as waiting, converging, arbitrating, etc.) described in the FlowSt into combinable asynchronous structure sub-instances, and to build a microstructure MicroSt, wherein the asynchronous structure sub is a data flow-based asynchronous micro-pipeline unit developed based on a "sender-relay-receiver" structure; the output of the Flow2Micro module is a MicroStTop data structure or a gate-level netlist file of the asynchronous structure sub level, and the MicroStTop data structure is a top-level summary of the MicroSt; the Flow2Micro module has semantic verification capability, detects problems such as incomplete semantic coverage of the asynchronous structure sub, port direction conflict, signal floating, and prompts through annotation or structure marking;

[0019] Micro2Meso module: used to convert each asynchronous structure sub-instance of the MicroSt into an asynchronous control path composed of a "sender-relay-receiver" structure in combination with a mesoscopic model library (a specific mesoscopic model built using the SystemVerilog language and callable / usable in processor code design), and to generate a mesoscopic structure MesoSt; the output of the Micro2Meso module is a MesoSt containing a "sender-relay-receiver" structure or a gate-level netlist file at the mesoscopic level, which can be used for mesoscopic modeling model verification and subsequent delay analysis;

[0020] DFTInsert module: based on the MesoSt containing a "sender-relay-receiver" structure, according to a preset insertion strategy file, the DFTInsert module automatically identifies the asynchronous control links and combinational logic links in the MesoSt and inserts DFT structure units, and inserts instance statements in the gate-level netlist file at the mesoscopic level; the DFTInsert module generates test control paths such as test clock, scan enable, link reset, etc., to ensure that the final gate-level netlist has good scannability and verifiability;

[0021] Meso2Logic module: used to identify and expand the relay instances in the MesoSt in which the DFT structure units are inserted, and to replace the corresponding behavior model with basic logic combination and flip-flop units; at the same time, the Meso2Logic module performs stripping and standardization processing on data lines and control lines, and expands multi-dimensional linear variables into one-dimensional standard logic bus signals, which facilitates subsequent synthesis tool identification; the output of the Meso2Logic module is a logic structure LogicSt and a gate-level netlist file;

[0022] Synthesis module: by loading the process library file, the logic gate (such as AND, MUX, DFF) abstracted in the LogicSt is mapped to the specific standard cell instance (such as AND2_X1, MUX2_X1, DFF_X2, etc.), and the parameters, clock edge attributes, gate signal and other information are automatically completed. The output of the Synthesis module is the gate-level netlist file of the bound process unit, and the cell type field of all logic units in the LogicSt is updated to provide structural basis for subsequent delay modeling, and the gate-level LogicSt is output;

[0023] DelayInsert module: used for inserting delay elements in the gate-level LogicSt to meet the timing alignment, path balance and asynchronous protocol precision requirements of the asynchronous control chain and combinational logic, complete path delay analysis and compensation, and generate an accurate standard delay format file;

[0024] Assemble module: used for integrating the gate-level netlist files and delay information output by all modules, completing instance path renaming, signal remapping and lint-level semantic verification, generating global netlist and standard delay format file as the standard input for backend physical design, simulation verification and formal verification.

[0025] Further, the FlowSt is used to store data flow described in JSON / XML; the MicroSt is used to store processor design code using asynchronous structure sub according to customized design specifications, to realize the translation between high-level behavior and asynchronous structure sub; the MesoSt is used to store processor design code using mesoscopic model according to customized design specifications; and the LogicSt is used to store gate-level netlist-level design code, to record all logic units, connections, signal relationships and topological structures.

[0026] Further, the "sender-relay-receiver" structure includes a sender (Sender), a relay (Relay) and a receiver (Receiver), wherein:

[0027] Sender: including a flip-flop, an inverter and a delay module, when receiving a driving pulse signal i_drive, the Sender flips the output level signal, and the input pulse signal i_free is output as o_free after being delayed by the delay module;

[0028] Relay: composed of XOR gate, XNOR gate, AND gate, D flip-flop, inverter and delay module, realized based on Click asynchronous controller;

[0029] Receiver: including a flip-flop, when receiving a lower pulse signal i_freeNext, the flip-flop is activated.

[0030] Further, the asynchronous structure sub includes Source, ArbMerge, WaitMerge, MutexMerge, Trap, Splitter and Selector, wherein:

[0031] The Source includes an inverter, a delay unit, and a phase difference pulse event signal generator;

[0032] The ArbMerge includes a cFifo, a cPmtFifo, a Contap, an AND gate, an OR gate, an inverter and a flip-flop; the cFifo includes a Sender, a Relay, a Receiver, receives an input event pulse signal, generates a timing control signal, and outputs a next stage event pulse signal; the cPmtFifo includes a Sender, a Relay with an enable mechanism, a Receiver, a delay unit, receives an input event pulse signal, generates a timing control signal when the enable signal is high, and outputs a next stage event pulse signal; the Contap uses a Sender without generating a free signal, and the Contap includes a flip-flop and an inverter, and is used for converting a pulse signal to a level signal;

[0033] The WaitMerge includes a Contap, an AND gate and an OR gate; the Contap uses a Sender without generating a free signal, and the Contap includes a flip-flop and an inverter, and is used for converting a pulse signal to a level signal;

[0034] The MutexMerge includes a Contap, an AND gate, an OR gate and a multiplexer; the Contap uses a Sender without generating a free signal, and the Contap includes a flip-flop and an inverter, and is used for converting a pulse signal to a level signal;

[0035] The Trap includes a delay unit, and outputs an input pulse after delay; the Splitter includes a Contap, an AND gate, an OR gate and an NOR gate; the Contap uses a Sender without generating a free signal, and the Contap includes a flip-flop and an inverter, and is used for converting a pulse signal to a level signal;

[0036] The Selector includes a Sender, a Relay, a Receiver, an AND gate and an inverter.

[0037] Further, the Flow2Micro module generates the corresponding structure description by automatically calling the asynchronous structure sub-library, and parses the gate-level netlist file of the asynchronous structure sub-library to generate MicroSt, the asynchronous structure sub-library is composed of the gate-level netlist template of the asynchronous structure sub; the Flow2Micro module translates each abstract node into an asynchronous structure sub-call statement, and automatically connects the ports, remaps the module names, and manages multiple instances based on the internal topology and data flow of the Flow2Micro module.

[0038] Further, in the Micro2Meso module, Sender, Relay, and Receiver are injected into the mesoscopic model as black box behavior units, the output end of Sender is connected to the input end of Relay, the output end of Relay is connected to the input end of Receiver, and the output end of Receiver is connected to the input end of Relay; the pulse signal generated in Relay is connected to the pulse signal output end of Sender and the driving pulse signal output end of Receiver after passing through the delay unit; at the same time, the Micro2Meso module performs timing analysis on the combined logic encapsulated in the asynchronous structure sub, divides the combined logic block according to the timing relationship in the logic, and generates a corresponding number of relay units in the control path to match the timing logic.

[0039] Further, in the DelayInsert module, the method of inserting delay elements in the gate-level LogicSt is as follows:

[0040] First, a complete timing path graph is constructed for the gate-level LogicSt, each propagation path from input to output is analyzed, the cumulative propagation delay of each propagation path is evaluated, and the delay difference between the shortest and longest paths is identified;

[0041] Second, the DelayInsert module determines the propagation path that needs to insert the delay element according to the configuration strategy, and calculates the size and insertion position of the required delay unit;

[0042] Finally, insert the delay element, the insertion process synchronously modifies the LogicSt, and updates the modification to the standard delay format file, which is used to record the IOPATH, INTERCONNECT, and three-value delay (min:typ:max) of each logic unit, and generate the TIMINGCHECK item (SETUP, HOLD, WIDTH) to meet the verification requirements of simulation and STA tools.

[0043] Further, in the timing path diagram, the nodes are logical gate output signals, and the edges are connection relationships.

[0044] Further, the method for generating a global netlist and a standard delay format file by the Assemble module is as follows:

[0045] First, the Assemble module reads the gate-level netlist files generated by each module, constructs a module dependency graph, identifies the top module, automatically parses the instance relationship and renames the instances and signals according to the naming strategy (prefix, suffix, UUID), solves the cross-module signal conflict and naming coverage problem;

[0046] Secondly, the gate-level netlist files output by all modules are spliced or flattened and combined to construct the final top-level gate-level netlist with consistent structure; the corresponding multiple standard delay format files will be path-completed and combined according to the instance path mapping rule, support flat path (U1_U2_n3) or hierarchical path (top / U1 / U2 / n3) format output, and generate TIMESCALE, SDFVERSION, CELL level delay and other contents uniformly;

[0047] Finally, the Assemble module outputs the global netlist and the standard delay format file which can be directly used by the ASIC back-end EDA process, and provides full-process closed-loop support for the asynchronous design process from abstract behavioral modeling to process-level simulation verification.

[0048] Further, the lint-level semantic verification in the Assemble module is implemented by a structure checker, and the lint-level semantic verification includes detection of floating signals, double-driven signals, repeated declarations, unconnected ports and IO mismatching; the structure checker generates a structure checking report and netlist statistical information, and supports users to quickly locate potential design errors.

[0049] Compared with the disadvantages and deficiencies of the prior art, the present application has the following beneficial effects:

[0050] 1. By constructing a tool chain based on C language, the full-process automation of automatic parsing, structure mapping, logic generation and delay matching of XML / JSON asynchronous structure sub-description is realized. This automatic mapping process can seamlessly process multi-level design representations (such as asynchronous structure sub, micro-pipeline, mesoscopic model), effectively reduces the dependence on manual coding, greatly improves the design efficiency, and reduces the design defects and verification costs caused by manual operation;

[0051] 2. Abstractly based on asynchronous structure sub, retaining the essential characteristics of asynchronous behavior, through data flow driven hierarchical mapping and timing modeling based on "send-relay-receive" structure, ensuring stable collaborative operation of mapping results. The automatic delay matching mechanism makes the circuit have good data ready detection and handshaking mechanism, thereby realizing the characteristics of low power consumption, high throughput and no global clock drift sensitivity;

[0052] 3. The architecture of "asynchronous structure sub → mesoscopic model → circuit netlist" is adopted, each layer defines clear input and output interfaces and intermediate state format, and the standardized data structure (XML / JSON) and unified gate-level netlist output are used as a bridge, so that the system has good module reuse and system expansion capability when facing more complex design scale. At the same time, the key tool chain modules can be replaced or extended to adapt to different design scenarios and target platforms (such as ASIC / FPGA);

[0053] 4. A set of clear asynchronous design rules (asynchronous structure sub naming, semantics, module boundary definition, etc.) and supporting tool chain are constructed, so that each link from input to output can be structured, parsed and verified, ensuring stable process and uniform format. At the same time, the final output is seamlessly connected with mainstream commercial tools such as Synopsys Design Compiler / VCS, realizing design closed loop. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 is the expression diagram of the asynchronous structure sub provided by the embodiment of the present application;

[0055] Figure 2 is the circuit schematic diagram of the mesoscopic model provided by the embodiment of the present application;

[0056] Figure 3 is the logic conversion diagram of the automatic synthesis system from asynchronous pipeline to asynchronous circuit provided by the embodiment of the present application;

[0057] Figure 4 is the overall architecture of the automatic synthesis system from asynchronous pipeline to asynchronous circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0059] This invention proposes an automated integrated system from asynchronous pipeline to asynchronous circuit based on an asynchronous structure. The asynchronous structure is a data-flow-based asynchronous micropipeline unit developed based on a "Sender-Relay-Receiver" structure. The "Sender-Relay-Receiver" structure includes a sender, a relay, and a receiver. The sender includes a flip-flop, an inverter, and a delay module. When it receives the drive pulse signal i_drive, the sender toggles the output level signal. The input pulse signal i_free is delayed by the delay module and outputs o_free. The relay consists of XOR gates, XNOR gates, AND gates, D flip-flops, inverters, and a delay module, implemented based on the Click asynchronous controller. The receiver includes a flip-flop, which is activated when it receives the next-level pulse signal i_freeNext.

[0060] The representation diagram of asynchronous structure is as follows Figure 1 As shown, it includes: Source, ArbMerge, WaitMerge, MutexMerge, Trap, Splitter, and Selector. Depending on different design requirements, one or more asynchronous structures can be selected and combined to implement specific functions. Among them:

[0061] The source includes an inverter and a delay unit, which use the phase difference to generate a pulse event signal;

[0062] ArbMerge includes: cFifo, cPmtFifo, ConTap, AND gates, OR gates, inverters, and flip-flops; cFifo includes a sender, a relay, and a receiver, which receives input event pulse signals, generates timing control signals, and outputs the next-stage event pulse signal; cPmtFifo includes a sender, a relay with an enable mechanism, a receiver, and a delay unit, which receives input event pulse signals, generates timing control signals when the enable signal is high, and outputs the next-stage event pulse signal; Contap uses a sender that does not generate a free signal, and includes a flip-flop and an inverter to convert pulse signals to level signals;

[0063] WaitMerge includes: Contap, AND gate, and OR gate; Contap uses a sender that does not generate a free signal. Contap includes a flip-flop and an inverter to convert pulse signals to level signals.

[0064] MutexMerge includes: Contap, AND gate, OR gate, and multiplexer; Contap uses a sender that does not generate a free signal, and includes a flip-flop and an inverter to convert pulse signals to level signals;

[0065] The Trap includes a delay unit that outputs the input pulse after a delay.

[0066] Splitter includes: Contap, AND gate, OR gate, NOR gate; Contap uses a sender that does not generate a free signal. Contap includes a flip-flop and an inverter to convert pulse signals to level signals.

[0067] Selectors include: Sender, Relay, Receiver, AND gate, and NOT gate.

[0068] The automated synthesis system for asynchronous pipelines to asynchronous circuits proposed in this invention is a front-end EDA toolchain for asynchronous circuit design. Based on this toolchain, open-source asynchronous EDA software is developed, which can automatically map asynchronous designs based on asynchronous structures to asynchronous circuits and automatically perform timing checks and delay matching. This automated synthesis system adopts a modular architecture, taking a high-level structure description file in JSON / XML format as input and progressively mapping to generate gate-level netlists and standard delay format files (.sdf) for integration with commercial back-end design flows.

[0069] The automated integrated system is divided into eight modules: (1) FlowParse module, which parses input data into a flow structure; (2) Flow2Micro module, which realizes the conversion between high-level behavior and asynchronous structs; (3) Micro2Meso module, which expands asynchronous structs into a mesoscopic model; the circuit principle of the mesoscopic model is as follows. Figure 2As shown, it consists of a Sender, a Relay, and a Receiver. When the drive pulse signal i_drive is received, the value of the flip-flop D in the Sender is output to the Q terminal, and the Q terminal is connected to the D terminal via a delay unit and an inverter. The output terminal outR of the Sender is connected to the input terminal inR of the Relay. The Relay is built based on a Click controller. After the signal level of the input terminal inR flips, it sequentially drives the pulse fire, the output terminal outR, and the output terminal inA to flip, and then pulls the pulse fire low, so that the pulse fire appears in pulse form. The output terminal outR of the Relay is connected to the input terminal inR of the Receiver. When the pulse signal i_free is received, the value of the flip-flop D in the Receiver is output to the Q terminal, and the value of the Q terminal is output from the output terminal inA to the input terminal outA of the Relay. In addition, the pulse fire generated in the Relay is connected to the output terminal of the pulse signal o_free of the Sender and the output terminal of the drive pulse signal o_drive of the Receiver after a delay unit. rst is the reset signal of the module, which returns the module to its initial state. LogicSt: LogicStruct stores gate-level netlist-level design code, recording all logic units, connections, signal relationships, and topology. (4) DFTInsert module automatically inserts testability links; (5) Meso2Logic module expands to basic logic gate-level structures; (6) Synthesis module implements standard unit synthesis; (7) DelayInsert module completes path delay analysis and compensation, and generates accurate standard delay format files; (8) Assemble module integrates the logic netlists and delay information output by all modules, completes instance path renaming, signal remapping, and lint-level semantic verification, and finally generates a unified global netlist and standard delay format files, providing standard interfaces for backend placement and routing, timing simulation, and formal verification. This automated synthesis system, while ensuring design readability, hierarchical consistency, and timing controllability, automates key asynchronous design steps such as structural abstraction, delay modeling, and testability insertion.

[0070] Each of the eight modules is an independent software package with a unified command-line interface, and they are logically linked through intermediate data structures (such as FlowSt, MicroSt, MesoSt, and LogicSt). The logical transformations during the synthesis process are as follows: Figure 3As shown. Among them, FlowSt: Flow Struct, stores the data flow described in JSON / XML, GramTest0 is used to check if the structure conforms to the specification; MicroSt: Microscopic Struct, stores the processor design code using asynchronous structures according to the customized design specification, GramTest1 is used to check if the structure conforms to the specification; MesoSt: Mesoscopic Struct, stores the processor design code using a mesoscopic model according to the customized design specification, GramTest2 is used to check if the structure conforms to the specification; LogicS: LogicStruct, stores the gate-level netlist-level design code, GramTest3 is used to check if the structure conforms to the specification. Virtual Circuit Library (.sv): This is a virtual circuit library written in SystemVerilog, built with reference to actual physical technology libraries, and contains the electrical properties of circuit components.

[0071] The following is combined with Figure 4 The overall architecture diagram of the automated integrated system from asynchronous pipeline to asynchronous circuit (named PinTu) shows a detailed description of the eight major modules.

[0072] The FlowParse module performs syntax parsing and semantic extraction on high-level structural description files in JSON / XML format, and constructs FlowSt, which serves as the foundation for subsequent modeling and transformation stages. This module processes multiple input files in batches, parsing module names, asynchronous sub-calls, port connections, control paths, data flows, and other content. The output of the FlowParse module is either a FlowStTop data structure or a gate-level netlist SystemVerilog file, which serves as the input for the next-level Flow2Micro module. The FlowStTop data structure is the top-level summary of FlowSt. The FlowParse module retains the comment information from the gate-level netlist SystemVerilog file in the FlowStTop data structure for module debugging and visualization.

[0073] The Flow2Micro module maps the asynchronous control logic described in FlowSt (such as wait, convergence, arbitration, etc.) to composable asynchronous structure sub-instances and constructs the microstructure MicroSt, completing the translation process from high-level behavior to asynchronous structures. In the processing flow, the Flow2Micro module automatically calls the asynchronous structure sub-library (composed of SystemVerilog templates of asynchronous structure gate-level netlists) to generate the corresponding structure description and supports parsing SystemVerilog files of asynchronous structure sub-level gate-level netlists to generate MicroSt. This module translates each abstract node into asynchronous structure sub-call statements, such as WaitMerge, ArbMerge, NatSplit, etc., and, combined with the internal topology and data flow of the Flow2Micro module, performs automatic port wiring, module naming remapping, and multi-instance management. The Flow2Micro module also has certain semantic verification capabilities, detecting issues such as incomplete semantic coverage of asynchronous structures, port direction conflicts, and signal floating, and providing hints through comments or structure tags. The output of the Flow2Micro module is the MicroStTop data structure, which is the top-level summary of MicroSt, providing a foundation for subsequent mesoscopic behavior modeling.

[0074] The Micro2Meso module receives the MicroSt generated by the Flow2Micro module and, in conjunction with the mesoscopic model library (a concrete mesoscopic model built using SystemVerilog that can be called / used in processor code design), converts each asynchronous structure instance into an asynchronous control path composed of a "send-relay-receive" structure. The core of this stage is deconstructing the abstract asynchronous structure into a timing model based on relay behavior. Relay behavior refers to the behavior of building a timing model using a send-relay-receive format. Relay units (implemented encapsulation, called in specific code, and the encapsulated send, relay, and receive modules) are retained as black boxes at this stage, while the send and receive modules can be optionally expanded into control combinational logic depending on the context. The Micro2Meso module supports parameter binding, hierarchical path expansion, and control signal insertion for relay templates, and generates a complete MesoSt. It also outputs a MesoSt containing the "send-relay-receive" structure or a SystemVerilog file containing a gate-level netlist of the mesoscopic hierarchy, which can be used for mesoscopic model modeling, model verification, and subsequent delay analysis. In the Micro2Meso module, Sender, Relay, and Receiver are injected into the mesoscopic model as black-box behavioral units. At the same time, the combinational logic encapsulated in the asynchronous structure is subjected to timing analysis. The combinational logic is divided into blocks according to the timing relationship in the logic, and the corresponding number of relay units are generated in the control path to match the timing logic.

[0075] The DFTInsert module, based on MesoSt containing a "transmit-relay-receive" structure, automatically identifies asynchronous control links and combinational logic links in MesoSt according to a preset insertion strategy file. Based on their characteristics and test requirements, it custom-embeds DFT structural units such as scan registers, pulse generators, and bypass muxes. This module controls the insertion granularity and coverage area of ​​test units through a strategy algorithm and has capabilities such as fan-out control, insertion redundancy optimization, and link de-annotation. All inserted DFT structural units are synchronously updated in the MesoSt containing the "transmit-relay-receive" structure, and instance statements are inserted into the SystemVerilog file at the mesoscopic level gate-level netlist. The DFTInsert module also maintains a testability signal netlist, generating test control paths such as test clocks, scan enable, and link reset, ensuring the final netlist has good scanability and verifiability. Implanting testability links in asynchronous circuits is difficult, complex, highly customized, and prone to errors. The module's automated support greatly simplifies the implementation process of the test loop and ensures the consistency of the insertion logic in functionality and testing.

[0076] The Meso2Logic module takes as input on inserted DFT structural units containing a "transmit-relay-receive" structure (MesoSt) or a corresponding gate-level netlist SystemVerilog file. It identifies and expands all relay instances (instantiated transmit, relay, and receive units in the code), replacing their corresponding behavioral models with basic logic combinational and trigger units. Simultaneously, the Meso2Logic module strips and standardizes data and control lines, expanding multidimensional linear variables into one-dimensional standard logic bus signals for easier identification by subsequent synthesis tools. The Meso2Logic module outputs a unified logic structure (LogicSt) and a gate-level netlist SystemVerilog file. LogicSt stores the gate-level netlist design code, recording all logic units, connections, signal relationships, and topology, and supports converting and outputting data structures as gate-level SystemVerilog code.

[0077] The Synthesis module maps logic structures to specific process cells. By loading process library files, it maps abstract logic gates (such as AND, MUX, DFF) in LogicSt to specific standard cell instances (such as AND2_X1, MUX2_X1, DFF_X2, etc.), and automatically completes their parameters, clock edge attributes, gating signals, and other information. The Synthesis module selects target cells based on weights such as drive strength, fan-out capability, area, and power consumption, while performing necessary logic rewriting and optimization, such as merging common subexpressions, folding redundant flip-flops, and balancing combinational paths. In this automated synthesis system, the Synthesis module can be integrated with existing commercial synthesis tools (such as Yosys, DC) or its built-in synthesis logic can perform offline mapping; the specific implementation is configurable. The output of the Synthesis module is a SystemVerilog file containing a gate-level netlist bound to process cells, and it updates the cell type field of all logic cells in LogicSt, providing a structural basis for subsequent delay modeling and outputting the updated gate-level LogicSt.

[0078] The DelayInsert module inserts delay elements into the gate-level LogicSt to meet the timing alignment, path balancing, and asynchronous protocol accuracy requirements of asynchronous control chains and combinational logic. It performs path delay analysis and compensation, and generates a precise standard delay format file. The method by which this module inserts delay elements into the gate-level LogicSt is as follows:

[0079] First, a complete timing path diagram is constructed for the gate-level LogicSt. In the timing path diagram, nodes represent the output signals of logic gates, and edges represent the connection relationships. The delay of each logic gate and connection is accumulated on the timing path diagram, and the timing of each path is dynamically evaluated. By loading a standard delay format file (such as .lib), the delay of each logic unit and wire is automatically labeled. Each propagation path from input to output is analyzed, the cumulative propagation delay of each propagation path is evaluated, and the delay difference between the shortest and longest paths is identified.

[0080] Secondly, the DelayInsert module determines the propagation path for inserting delay elements based on the configuration strategy, and calculates the required delay unit size and insertion position.

[0081] Finally, delay elements are inserted. The insertion process includes inserting new logic cells into LogicSt, updating signal connections, and automatically generating instance names, signal names, and constraint tags. In addition to the logic structure, the insertion process simultaneously modifies LogicSt and updates the changes to the standard delay format file. It records the IOPATH, INTERCONNECT, and three-valued delays (min:typ:max) of each logic cell, generating TIMINGCHECK items (SETUP, HOLD, WIDTH) to meet the verification requirements of simulation and STA tools. This module also supports patch mode updates to existing standard delay format files, preserving timing information for unchanged paths and only incrementally updating modified parts.

[0082] The Assemble module integrates the gate-level netlist SystemVerilog files and delay information output by all modules, performs instance path renaming, signal remapping, and lint-level semantic verification, and generates a global netlist (.sv) and standard delay format files. First, the Assemble module reads the gate-level netlist SystemVerilog files generated by each module, constructs a module dependency graph, identifies the top-level module, automatically parses instance relationships, and renames instances and signals according to naming strategies (prefix, suffix, UUID), resolving cross-module signal conflicts and naming overriding issues. Second, it concatenates or flattens the gate-level netlist SystemVerilog files output by all modules to construct a final, consistent top-level gate-level netlist. The corresponding multiple standard delay format files are completed and merged according to instance path mapping rules, supporting flat path (U1_U2_n3) or hierarchical path (top / U1 / U2 / n3) format output, and uniformly generates TIMESCALE, SDFVERSION, CELL-level delay, and other content. In the Assemble module, lint-level semantic verification is implemented through a structure checker. Lint-level semantic verification includes detection of floating signals, dual-drive signals, duplicate declarations, unconnected ports, and I / O mismatches. The structure checker generates a structure check report and netlist statistics, enabling users to quickly locate potential design errors. Finally, the Assemble module outputs a global netlist (.sv) and standard delay format files that can be directly used in the ASIC backend EDA process. It seamlessly integrates with mainstream commercial tools such as Synopsys VCS / P&R, providing a closed-loop support for asynchronous design processes from abstract behavioral modeling to process-level simulation verification.

[0083] The overall architecture of the automated integrated system from asynchronous pipeline to asynchronous circuit proposed in this invention is as follows: Figure 4As shown, an architecture of "asynchronous struct → mesoscopic model → circuit netlist" is adopted, with each layer defining clearly defined input / output interfaces and intermediate state formats. Standardized data structures (XML / JSON) and unified gate-level netlist SystemVerilog file output serve as bridges, enabling the system to possess excellent module reuse and system scalability when facing more complex design scales. Simultaneously, key modules can be replaced or extended to adapt to different design scenarios and target platforms (such as ASIC / FPGA). Through modular design, it supports asynchronous circuit designs of different scales and complexities, ensuring the tool has strong scalability and can adapt to increasingly complex and diverse design needs in the future. The entire process of automatic parsing, structure mapping, logic generation, and delay matching of XML / JSON asynchronous struct descriptions is automated.

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An automated integrated system for asynchronous pipelines to asynchronous circuits, characterized in that, include: The FlowParse module is used to perform syntax parsing and semantic extraction on high-level structure description files in JSON / XML format, and to build a flow structure FlowSt. FlowSt is used to store data streams described in JSON / XML, and the FlowParse module outputs a top-level summary or gate-level netlist file of FlowSt. Flow2Micro module: used to map the asynchronous control logic described in FlowSt into composable asynchronous structure instances and construct the microstructure MicroSt. MicroSt is used to store processor design code using asynchronous structures; the asynchronous structure is an asynchronous micropipeline unit based on a "transmit-relay-receive" structure. The Flow2Micro module outputs the gate-level netlist file of the top-level summary or asynchronous sub-structure of MicroSt; The Micro2Meso module is used to convert each asynchronous structure sub-instance of the MicroSt into an asynchronous control path consisting of a "transmit-relay-receive" structure, and generate a mesoscopic structure MesoSt. MesoSt is used to store processor design code using the mesoscopic model. The Micro2Meso module outputs a gate-level netlist file containing the "transmit-relay-receive" structure MesoSt or the mesoscopic hierarchy. The DFTInsert module automatically identifies asynchronous control links and combinational logic links in MesoSt containing "transmit-relay-receive" structures and inserts them into DFT structure units, inserting instance statements into the gate-level netlist file at the mesoscopic level. The Meso2Logic module identifies and expands relay instances in the MesoSt inserted DFT structural units, replacing the behavioral model corresponding to the relay instances with basic logic combination and flip-flop units. Simultaneously, the Meso2Logic module strips and standardizes data and control lines, expanding multidimensional linear variables into one-dimensional standard logic bus signals. The Meso2Logic module outputs the logic structure LogicSt and a gate-level netlist file; LogicSt stores the logic structure of the gate-level netlist-level design code. Synthesis module: By loading the technology library file, it maps the abstract logic gates in the LogicSt to specific standard cell instances, and automatically completes the parameters, clock edge attributes, and gate control signals; Synthesis module outputs the gate-level LogicSt and the gate-level netlist files of the bound technology cells; The DelayInsert module is used to insert delay elements in the gate-level LogicSt and generate a precise standard delay format file. The Assemble module is used to integrate the gate-level netlist files and delay information output by all modules to generate a global netlist and a standard delay format file.

2. The automated integrated system for asynchronous pipelines to asynchronous circuits as described in claim 1, characterized in that, The "send-relay-receive" structure includes Sender, Relay, and Receiver, where: Sender: Includes a flip-flop, an inverter, and a delay module. When it receives the drive pulse signal i_drive, Sender flips the output level signal. The input pulse signal i_free is delayed by the delay module and outputs as o_free. Relay: Composed of XOR gates, XNOR gates, AND gates, D flip-flops, inverters, and delay modules, it is implemented based on the Click asynchronous controller; Receiver: Includes a trigger that is activated when the next-level pulse signal i_freeNext is received.

3. The automated integrated system for asynchronous pipelines to asynchronous circuits as described in claim 2, characterized in that, The asynchronous structure includes Source, ArbMerge, WaitMerge, MutexMerge, Trap, Splitter, and Selector, where: The source includes an inverter and a delay unit, which use the phase difference to generate a pulse event signal; ArbMerge includes: cFifo, cPmtFifo, ConTap, AND gates, OR gates, inverters, and flip-flops; cFifo includes a sender, relay, and receiver, which receives input event pulse signals, generates timing control signals, and outputs the next stage's event pulse signal; cPmtFifo includes a sender, a relay with an enable mechanism, a receiver, and a delay unit, which receives input event pulse signals, generates timing control signals when the enable signal is high, and outputs the next stage's event pulse signal; Contap uses a sender that does not generate a free signal, and includes flip-flops and inverters to convert pulse signals to level signals; WaitMerge includes: Contap, AND gate, and OR gate; Contap uses a sender that does not generate a free signal. Contap includes a flip-flop and an inverter to convert pulse signals to level signals. MutexMerge includes: Contap, AND gate, OR gate, and multiplexer; Contap uses a sender that does not generate a free signal, and includes a flip-flop and an inverter to convert pulse signals to level signals; The Trap includes a delay unit that outputs the input pulse after a delay; the Splitter includes a Contap, an AND gate, an OR gate, and a NOR gate; the Contap uses a Sender that does not generate a free signal, and the Contap includes a flip-flop and an inverter to convert the pulse signal into a level signal; Selectors include: Sender, Relay, Receiver, AND gate, and NOT gate.

4. The automated integrated system from asynchronous pipeline to asynchronous circuit as described in claim 3, characterized in that, The Flow2Micro module generates corresponding structure descriptions by automatically calling the asynchronous structure sub-library and parses the gate-level netlist file of the asynchronous structure sub-level to generate MicroSt. The asynchronous structure sub-library is composed of gate-level netlist templates of asynchronous structures. The Flow2Micro module translates each abstract node into an asynchronous structure sub-call statement and, combined with the internal topology and data flow of the Flow2Micro module, performs automatic port connection, module naming remapping, and multi-instance management.

5. The automated integrated system for asynchronous pipelines to asynchronous circuits as described in claim 2, characterized in that, In the Micro2Meso module, Sender, Relay, and Receiver are injected into the mesoscopic model as black-box behavioral units. The output of Sender is connected to the input of Relay, the output of Relay is connected to the input of Receiver, and the output of Receiver is connected to the input of Relay. The pulse signal generated in Relay is connected to the pulse signal output of Sender and the drive pulse signal output of Receiver after passing through a delay unit. At the same time, the Micro2Meso module performs timing analysis on the combinational logic encapsulated in the asynchronous structure, divides the combinational logic into blocks according to the timing relationship in the logic, and generates the required number of relay units in the control path to match the timing logic.

6. The automated integrated system for asynchronous pipelines to asynchronous circuits as described in claim 1, characterized in that, In the DelayInsert module, the method for inserting delay elements in the gate-level LogicSt is as follows: First, a complete timing path diagram is constructed for the gate-level LogicSt, each propagation path from input to output is analyzed, the cumulative propagation delay of each propagation path is evaluated, and the delay difference between the shortest and longest paths is identified. Secondly, the DelayInsert module determines the propagation path for inserting delay elements based on the configuration strategy, and calculates the required delay unit size and insertion position. Finally, insert the delay element, modifying LogicSt synchronously during the insertion process and updating the modifications to the standard delay format file.

7. The automated integrated system for asynchronous pipelines to asynchronous circuits as described in claim 6, characterized in that, In the timing path diagram, nodes represent logic gate output signals, and edges represent connection relationships. The delay of each logic gate and connection is accumulated on the timing path diagram to dynamically evaluate the timing of each path. By loading a standard delay format file, delay annotations are automatically applied to each logic unit and wire.

8. The automated integrated system for asynchronous pipelines to asynchronous circuits as described in claim 1, characterized in that, The method by which the Assemble module generates the global netlist and standard delay format file is as follows: First, the Assemble module reads the gate-level netlist files generated by each module, constructs the module dependency graph, identifies the top-level module, automatically resolves instance relationships, and renames instances and signals according to the naming strategy to resolve cross-module signal conflicts and naming overwrite issues. Secondly, the gate-level netlist files output by all modules are concatenated or flattened and merged to construct a top-level gate-level netlist with a consistent final structure; the corresponding multiple standard delay format files will be completed and merged according to the instance path mapping rules, supporting flat path or hierarchical path format output, and uniformly generating TIMESCALE, SDFVERSION, and CELL level delay content. Finally, the Assemble module outputs a global netlist and a standard delay format file.

9. The automated integrated system for asynchronous pipelines to asynchronous circuits as described in claim 1, characterized in that, The Assemble module implements lint-level semantic verification through a structure checker. Lint-level semantic verification includes the detection of floating signals, dual-drive signals, duplicate declarations, unconnected ports, and I / O mismatches. The structure checker generates a structure check report and netlist statistics, enabling users to quickly locate potential design errors.

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