Method and system for verifying transpose operation of chip register transfer level model and computing equipment

Abstract

The invention provides a method and a system for verifying transposition operation of a chip register transfer level model and computing equipment. The method comprises the following steps: generating a multi-dimensional array in a coordinate point form; obtaining a data format required by a first node in front of the calculation module by using the data shape after overall transposition according to the requirement of the calculation module after the transposition is completed, and obtaining a first data point coordinate of data required by the calculation module for calculation each time; performing overall transposition operation on the first data point coordinates according to dimensions of transposition requirements to obtain second data point coordinates corresponding to the original data; according to the second data point coordinates, obtaining first reference data of the corresponding coordinates in the original data; obtaining first simulation data output by the register transfer level model at the first node; and comparing the first reference data with the first simulation data so as to verify the correctness of the transposition result. According to the technical scheme of the invention, real-time comparison of the transposed data can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of chip development, and in particular to a method and system for verifying a transposition operation of a chip register transfer level model, and a computing device. Background Art

[0002] Artificial intelligence chips (AI chips) have become more important driven by large models and large language models (LLMs). The basis of data calculations involved in various AI chips is tensor operations. Figure 1 Data transposition is a common problem faced by AI computing chips. An m*n matrix needs to be transposed to an n*m matrix for storage or calculation. Using software to perform data transposition consumes a large amount of resources, and DMA (direct memory access) transfer is time-consuming and inefficient. Using hardware to perform the transposition operation is difficult due to hardware limitations and can only be performed in blocks.

[0003] Conventional verification methods perform a comparison at the end of data calculation. If a transposition error occurs midway, the location efficiency is low. For example, if matrix multiplication or convolution is performed after matrix transposition, it is difficult to quickly find the problem by comparing the final result. Therefore, it is expected that the comparison can be performed at a smaller granularity, such as comparing each block of data, to facilitate rapid location. Usually, data comparison is performed in an address + data manner. However, if it is not implemented in an RTL (register transfer level) manner, the output of each data block may be different, and comparison by data block cannot be performed. If the reference model and RTL binding are made consistent, the errors may be the same, and the RTL function cannot be effectively verified. Because the data may be high-dimensional (greater than 2 dimensions), the address after transposition is complex, making analysis and location more difficult.

[0004] To this end, a technical solution is needed that can achieve real-time comparison of transposed data, improve verification efficiency, increase coverage of internal functions, and adapt to different verification needs. Summary of the Invention

[0005] The present invention aims to provide a method, system and computing device for verifying the transposition operation of a chip register transfer level model, which can realize real-time comparison of transposed data, improve verification efficiency, increase coverage of internal functions, and adapt to different verification requirements.

[0006] According to one aspect of the present invention, a method for verifying a transposition operation of a chip register transfer level model is provided, the method comprising:

[0007] Generate a multidimensional array in the form of coordinate points for storing data used by the reference model, wherein the dimension of the multidimensional array is consistent with the dimension of the data, and the coordinates of the coordinate points correspond to the indexes of the multidimensional array;

[0008] According to the requirements of the calculation module after the transposition is completed, the data format required by the first node before the calculation module is obtained using the overall transposed data shape, and the first data point coordinates of the data required for each calculation by the calculation module are obtained;

[0009] Performing an overall transposition operation on the first data point coordinates according to the required transposition dimension to obtain the second data point coordinates corresponding to the original data;

[0010] According to the coordinates of the second data point, obtaining first reference data corresponding to the coordinates in the original data;

[0011] Acquire first simulation data output by the register transfer level model at the first node;

[0012] The first reference data is compared with the first simulation data to verify the correctness of the transposition result.

[0013] According to some embodiments, the original data is rearranged based on the multidimensional array to obtain rearranged data;

[0014] Performing an inverse transposition of the register transfer level model block transposition on the first data point coordinate to obtain a third data point coordinate of the second node before the block transposition;

[0015] According to the coordinates of the third data point, obtaining second rearranged data corresponding to the coordinates in the rearranged data;

[0016] Acquire second simulation data output by the register transfer level model at the second node;

[0017] The second rearranged data is compared with the second simulation data to verify the correctness of the transposition intermediate process.

[0018] According to some embodiments, the transpose operation and the overall transpose operation are two-dimensional or higher-dimensional.

[0019] According to some embodiments, based on the multidimensional array, the coordinates of the coordinate points of the original data are rearranged to obtain the coordinates of the fourth data points;

[0020] Performing an inverse transposition of the RTL model block transposition on the first data point coordinate to obtain a third data point coordinate of the second node before the block transposition;

[0021] The third coordinate point is compared with the fourth coordinate point to verify the correctness of the transposition intermediate process.

[0022] According to some embodiments, the output results of the reference model are compared with the output results of the calculation module of the register transfer level model, thereby achieving an end-to-end comparison.

[0023] According to another aspect of the present invention, a system for verifying a transposition operation of a chip register transfer level model is provided, the system comprising:

[0024] An array module generates a multidimensional array in the form of coordinate points for storing data used by the reference model, wherein the dimension of the multidimensional array is consistent with the dimension of the data, and the coordinates of the coordinate points correspond to the indexes of the multidimensional array;

[0025] A first coordinate module, based on the requirements of the calculation module after the transposition, uses the overall transposed data shape to obtain the data format required by the first node before the calculation module, and obtains the first data point coordinates of the data required for each calculation by the calculation module;

[0026] A second coordinate module performs an overall transposition operation on the first data point coordinates according to a required transposition dimension to obtain the second data point coordinates corresponding to the original data;

[0027] A first data module, which obtains first reference data corresponding to the coordinates in the original data according to the coordinates of the second data point;

[0028] a simulation data acquisition module, configured to acquire first simulation data output by the register transfer level model at the first node;

[0029] The comparison module compares the first reference data with the first simulation data to verify the correctness of the transposition result.

[0030] According to some embodiments, a first rearrangement module rearranges the original data based on the multidimensional array to obtain rearranged data;

[0031] A third coordinate module, which performs an inverse transposition of the RTL model block transposition on the first data point coordinate to obtain a third data point coordinate of the second node before the block transposition device;

[0032] A second data module, according to the coordinates of the third data point, obtains second rearranged data corresponding to the coordinates in the rearranged data;

[0033] in,

[0034] The simulation data acquisition module is further configured to acquire second simulation data output by the register transfer level model at the second node;

[0035] The comparison module is further configured to compare the second rearranged data with the second simulation data, thereby verifying the correctness of the transposition intermediate process.

[0036] According to some embodiments, a second rearrangement module rearranges the coordinates of the original data points based on the multidimensional array to obtain coordinates of fourth data points;

[0037] a fourth coordinate module, performing an inverse transposition of the RTL model block transposition on the first data point coordinate to obtain a third data point coordinate of the second node before the block transposition;

[0038] in,

[0039] The comparison module is further configured to compare the third coordinate point with the fourth coordinate point, thereby verifying the correctness of the transposition intermediate process.

[0040] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the method as described above is implemented.

[0041] According to another aspect of the present invention, there is provided a computing device comprising:

[0042] processor;

[0043] A memory stores a computer program, and when the computer program is executed by the processor, implements any of the methods described above.

[0044] According to an embodiment of the present invention, the data obtained through the transposition operation are compared, the calculation results and the original data are compared, and the rearranged data and the process data are compared to verify the correctness of the model calculation, thereby realizing real-time comparison of the transposed data and improving the verification efficiency.

[0045] According to an embodiment of the present invention, the data obtained through the transposition operation are compared, and the data obtained in the rearranged data and the simulation data generated by the calculation process are compared to verify the correctness of the model calculation process, increase the coverage of internal functions, and adapt to different verification requirements.

[0046] According to some embodiments, the present invention realizes real-time comparison of transposed data by combining reverse and forward reasoning. By adding two comparison points in the module calculation process to compare with the original data and the calculation results, compared with only comparing the final calculation result data points in the entire process, the verification efficiency is improved, and the coverage of internal functions is increased to prevent over-coupling and missed detection.

[0047] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments.

[0049] Figure 1 Diagram illustrating the concept of data transposition.

[0050] Figure 2 A schematic diagram showing the process of data transposition.

[0051] Figure 3 A flow chart of a method for verifying a transposition operation of a chip RTL model according to an example embodiment is shown.

[0052] Figure 4 A schematic diagram illustrating a process of verifying a transposition operation of a chip RTL model according to an example embodiment.

[0053] Figure 5 A schematic diagram illustrating a system for verifying a transposition operation of a chip RTL model according to an example embodiment is shown.

[0054] Figure 6 A block diagram of a computing device is shown according to an exemplary embodiment. DETAILED DESCRIPTION

[0055] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repeated description thereof will be omitted.

[0056] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, it will be appreciated by those skilled in the art that the technical solutions of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0057] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0058] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0059] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Thus, the first component discussed below could be referred to as the second component without departing from the teachings of the present inventive concept. As used herein, the term "and / or" includes any one and all combinations of one or more of the associated listed items.

[0060] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0061] Those skilled in the art will understand that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present invention, and therefore cannot be used to limit the scope of protection of the present invention.

[0062] Data transposition is a common problem faced by AI computing chips. Using software to perform data transposition consumes a large amount of resources, and DMA (direct memory access) transfers are time-consuming and inefficient. Using hardware to perform the transposition operation is difficult due to hardware limitations and can only be performed in blocks.

[0063] Conventional verification methods perform a comparison at the end of data calculation. If a transposition error occurs midway, the location efficiency is low. For example, if matrix multiplication or convolution is performed after matrix transposition, it is difficult to quickly find the problem by comparing the final result. Therefore, it is expected that the comparison can be performed at a smaller granularity, such as comparing each block of data, to facilitate rapid location. Usually, data comparison is performed in an address + data manner. However, if it is not implemented in an RTL (register transfer level) manner, the output of each data block may be different, and comparison by data block cannot be performed. If the reference model and RTL binding are made consistent, the errors may be the same, and the RTL function cannot be effectively verified. Because the data may be high-dimensional (greater than 2 dimensions), the address after transposition is complex, making analysis and location more difficult.

[0064] If the data is transposed as a whole, it can be decoupled from the RTL implementation, but due to the inconsistent output order, it is impossible to accurately compare each data. For example, see Figure 2 , when comparing the data at point A and the data at point D, the intermediate function span is large, and it is impossible to distinguish which position A, B, C, or D has an error. When comparing the transposed data one by one, that is, Figure 2 Compare the data at point C in the middle. If traditional address and data modeling is used, due to RTL implementation restrictions and the use of block processing, the storage method obtained from the original data after passing through A is different. Assuming that the data output at point C is 4*4 points, in different modes, it may be four 2*2 transposed and spliced ​​points, or it may be a single 4*4 transposed point.

[0065] Therefore, the original data needs to be rearranged differently. Therefore, the reference model (RM) must use the same partitioning and processing principles as the RTL. Data at point B must be acquired in the same manner as the RTL, and then transposed to obtain data at point C. Otherwise, data mismatches will occur. However, this approach complicates modeling and is too tightly coupled with the RTL, potentially leading to missed tests. For example, the path from point A to point B and from point B to point C may both be incorrect, but the path from point A to point C may be correct in some scenarios. If this approach is fully coupled, or only end-to-end verification is performed, the problem may not be discovered.

[0066] Address modeling becomes complex if the data is high-dimensional. For example, for common two-dimensional data (x, y), M = 32, N = 64, and INT8 data type, address 0x80 may represent the point (2, 0). For four-dimensional or higher-dimensional data, address 0x540 represents an address. Calculations may require reading multiple segments of data, making it even more difficult to compare with RTL using address access. Furthermore, high-dimensional data may not only convert between two dimensions (X and Y), but may also convert between X and Z or Y and Z, resulting in more implementation options. Accessing data by address and performing calculations based on the format is even more complex.

[0067] To this end, the present invention proposes a method for verifying the transposition operation of the chip register transfer level model, which can realize real-time comparison of transposed data, improve verification efficiency, increase coverage of internal functions, prevent over-coupling and missed detection, and adapt to different verification requirements.

[0068] Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.

[0069] Figure 3 A flow chart of a method for verifying a transposition operation of a chip RTL model according to an example embodiment is shown.

[0070] See also Figure 3 ,In S301, a multidimensional array is generated in the form of coordinate points for storing data used by the reference model.

[0071] According to some embodiments, the dimension of the multidimensional array is consistent with the dimension of the data, and the coordinates of the coordinate points correspond to the indices of the multidimensional array.

[0072] According to some embodiments, the original data is rearranged based on the multidimensional array to obtain rearranged data. The original data is rearranged according to chip design requirements, and the tail position of any original data in the original data is rearranged to the head position of the original data.

[0073] According to some embodiments, a multidimensional array is generated in the form of coordinate points to store data used by the reference model, for example, data data_a is in the original data format, and rearranged data data_b is obtained according to rearrangement requirements.

[0074] According to some embodiments, the input data is rearranged according to the chip design. For example, in mode 1, the data is rearranged in 4 small blocks, and in mode 2, the data is rearranged in one large block. The head and tail of the arrow represent two pieces of data. The data is rearranged from the position of the tail of the arrow to the position of the head of the arrow. The data at the same tail of the arrow in two blocks of different sizes will be rearranged to different positions (see Figure 4The rearranged data, data_b, is used for transposition in subsequent steps. The data must be rearranged according to the transposition module's functionality to achieve the desired data shape after transposition. The original data must be rearranged into data_b before it can be used as data at point A in the subsequent transposition module.

[0075] According to some embodiments, operations on the coordinates of the data points are implemented using a Python library. Operations on the coordinates can be implemented using a Python library, such as numpy, to simplify the coding of the reference model.

[0076] In S303, according to the requirements of the calculation module after the transposition is completed, the data shape after the overall transposition is used to obtain the data format required by the first node before the calculation module, and obtain the first data point coordinates of the data required for each calculation by the calculation module.

[0077] According to some embodiments, the transpose operation and the overall transpose operation are two-dimensional or higher-dimensional.

[0078] According to some embodiments, the first node (e.g., Figure 4 The data format required by the calculation result is to obtain the data point coordinate idx_c required for each calculation of the point C position data.

[0079] According to the calculation module's requirements after the transposition is completed, the data format required for the position before the calculation result is obtained, for example, the INT8 data type is 16*16. In this way, the coordinate points of the data required for each calculation are obtained, from (0, 0) to (15, 15).

[0080] In S305 , the first data point coordinates are subjected to an overall transposition operation according to the required transposition dimension to obtain second data point coordinates corresponding to the original data.

[0081] According to some embodiments, the first data point coordinates obtained in S303 are transposed according to a data format required for chip design calculations to obtain second data point coordinates.

[0082] For example, the data point coordinate idx_c of the data at the position of point C is transposed according to the dimension required for transposition to obtain the second data point coordinate idx_a (see Figure 4The transposed format here refers to the format of the data block at point C. For example, the 16*16 here is transposed as a whole, without considering the RTL block behavior. For example, in a two-dimensional transposition, (0, 15) is transformed into (15, 0). If it is other data formats, the transposed results can be various, such as three-dimensional (0, 1, 2) -> (1, 0, 2), or (0, 1, 2) -> (2, 1, 0), or (0, 1, 2) -> (0, 2, 1). Multi-dimensional transposition can be regarded as the superposition of two-dimensional transposition.

[0083] In S307 , according to the coordinates of the second data point, first reference data of corresponding coordinates are obtained from the original data.

[0084] According to some embodiments, the transposed coordinates of the first data point idx_a are returned to the original data to retrieve the first reference data c1 corresponding to the coordinate point.

[0085] At S309 , first simulation data output by the register transfer level model at the first node is obtained.

[0086] According to some embodiments, first simulation data c0 outputted at point C of the RTL model is obtained.

[0087] In S311 , the first reference data is compared with the first simulation data to verify the correctness of the transposition result.

[0088] According to some embodiments, by comparing first reference data c1 of a reference model at point C with first simulation data c0 of point C output by actual RTL, real-time comparison of point C position data is achieved.

[0089] According to some embodiments, the method for verifying the transposition operation of the chip RTL model also includes: performing the reverse transposition of the first data point coordinates through the block transposition of the register transfer level model to obtain the third data point coordinates of the second node before the block transposition; according to the third data point coordinates, obtaining the second rearranged data of the corresponding coordinates in the rearranged data; obtaining the second simulation data output by the register transfer level model at the second node; and comparing the second rearranged data with the second simulation data to verify the correctness of the transposition intermediate process.

[0090] According to some embodiments, the coordinates of the first data point idx_c before transposition are reverse transposed by the RTL block transposition to obtain the coordinates of the third data point idx_b1. For example, if the RTL is (a,b)->(b,a), then the reverse transposition is (b,a)->(a,b). The data is retrieved from the rearranged data data_b by the third data point coordinate idx_b1 to obtain the data rearranged data b1. The rearranged data b1 is forward transposed by the RTL to obtain the process data b0 output at point B. The rearranged data b1 is compared with the process data b0 output by the RTL at point B to verify the correctness of the actual random access memory (RAM) address operation and the consistency of the rearrangement and blocking functions.

[0091] According to some embodiments, based on the multidimensional array, the coordinates of the original data points are rearranged to obtain the coordinates of a fourth data point; the coordinates of the first data point are subjected to the reverse transposition of the RTL model block transposition to obtain the coordinates of a third data point of the second node before the block transposition; the third coordinate point is compared with the fourth coordinate point to verify the correctness of the transposition process. idx_b2 is obtained by rearranging idx_a, and idx_b1 and idx_b2 are compared to verify the functional consistency of the rearrangement process and the block transposition process.

[0092] According to some embodiments, in the solution of the present invention, each data at positions such as point C and point B can be compared during the entire calculation process, and the data of each clock cycle can be compared, instead of having to wait until the final calculation is completed before comparing at point D. This realizes real-time comparison of transposed data, improves verification efficiency, increases coverage of internal functions, prevents over-coupling missed tests, and adapts to different verification requirements.

[0093] Figure 4 A schematic diagram illustrating a process of verifying a transposition operation of a chip RTL model according to an example embodiment.

[0094] See also Figure 4 The present invention implements transposition and data retrieval in three steps. First, coordinate points are used as the data retrieval method of the reference model RM. For example, the point (2,1) is the element of the array data[2][1]. This decouples the data from the address and simplifies the difficulty of address conversion.

[0095] Secondly, for the reference model RM, directly use the full data transposition specifications for data acquisition. This is because the input data format is fixed for the tensor module used in chip calculations. Therefore, once the calculation module specifications are determined, regardless of the implementation method used for the modules from point A to point B and from point B to point C, the data format requirement at point C can be assumed to be fixed.

[0096] Finally, the patented process uses the transposed data shape N*M to obtain the coordinate point set idx_q of the c data block according to the data format requirements of point C, but does not transpose the actual data, that is, the reference model RM still uses the data stored in M*N.

[0097] According to some embodiments, a transposition operation is performed on each coordinate point of the acquired coordinate set, which may be two-dimensional or higher-dimensional. The transposed data acquisition coordinate idx is returned to the pre-transposed stored data M*N to obtain the data block c. This allows the process of moving from point A to point B and from point B to point C to be skipped. The data c1 at point C of the reference model is obtained through the "C(idx)-original data-C" method and compared with the simulation data c0 output from point C of the RTL.

[0098] Rearrange the coordinates of C(idx) according to the data pattern at point A to obtain data b1 at point B. Reverse the conversion process from point B to point C to obtain data b2 at point C. Compare b1 and b2 with the RTL data b0 at point B to achieve data comparison at point B.

[0099] According to some embodiments, the output of the reference model is compared with the output of the calculation module of the register transfer level model to achieve an end-to-end comparison. For point D, full data transposition and calculation are used to achieve an end-to-end high-level comparison.

[0100] According to some embodiments, a possible implementation is that, for two-dimensional data calculation, the transposed data block size required for point C is 16*16. Due to implementation limitations, RTL implements a 4*4 transposition module, which is implemented by taking four different data transpositions and then splicing them together. Figure 4 As shown in Mode 1.

[0101] For the first 16*16 computation block, the coordinates of point C are the 16*16 data point. Directly transpose the coordinates to obtain idx_a, for example, (0, 15) becomes (15, 0). Use idx_a to retrieve the corresponding data c1 from the original data data_a and compare it with the data c0 output by the RTL at point C. If the comparison is consistent, the computation block hierarchy is functioning correctly.

[0102] Take the coordinate idx_c and reverse-transpose it to get idx_b1. For example, if (0, 15) is divided into four blocks, the coordinate after block transposition is (3, 12). This coordinate is retrieved from the rearranged data data_b to get b1. Compare b1 with the RTL output b0 at point B to complete the data comparison at point B.

[0103] According to some embodiments, a possible embodiment is to not rearrange the data data_a, but to use idx_a through the rearrangement process to obtain idx_b2, and compare idx_b1 and idx_b2 to determine the consistency of the point B position algorithm.

[0104] According to some embodiments, one possible embodiment is that for Figure 4 In the case of consistent blocks such as Mode 2, the position comparison of point B is not performed, and only the position comparison function of point C is retained.

[0105] In summary, using the coordinates of point C as a basis for data extraction and comparison of the simulation data output at point C decouples the RTL data rearrangement and transposition process, enabling algorithm-level sub-data block calculation and comparison. The coordinates inferred from the data at point C then serve as a golden reference to calculate b1 and b2, verifying the correctness of the two sub-processes and enabling comparison of point B.

[0106] Figure 5 A schematic diagram illustrating a system for verifying a transposition operation of a chip RTL model according to an example embodiment is shown.

[0107] See also Figure 5 The RTL model transposition verification system includes an array module, a simulation data acquisition module, a comparison module, a first coordinate module, a second coordinate module, a third coordinate module, a fourth coordinate module, a first data module, a second data module, a first rearrangement module and a second rearrangement module.

[0108] According to an exemplary embodiment of the present invention, the first reference data is compared with the first simulation data to verify the correctness of the transposition result through the array module, the first coordinate module, the second coordinate module, the first data module, the simulation data acquisition module and the comparison module.

[0109] According to some embodiments, the array module generates a multidimensional array in the form of coordinate points for storing data used by the reference model, the dimension of the multidimensional array is consistent with the dimension of the data, and the coordinates of the coordinate points correspond to the index of the multidimensional array.

[0110] According to some embodiments, the first coordinate module uses the overall transposed data shape according to the needs of the calculation module after the transposition is completed to obtain the data format required by the first node before the calculation module, and obtains the first data point coordinates of the data required by the calculation module for each calculation.

[0111] According to some embodiments, the second coordinate module performs an overall transposition operation on the first data point coordinates according to a required transposition dimension to obtain the second data point coordinates corresponding to the original data.

[0112] According to some embodiments, the first data module obtains first reference data corresponding to the coordinates in the original data based on the coordinates of the second data point.

[0113] According to some embodiments, the simulation data acquisition module acquires first simulation data output by the register transfer level model at the first node, and the comparison module compares the first reference data with the first simulation data to verify the correctness of the transposition result.

[0114] According to an exemplary embodiment of the present invention, the second rearranged data is compared with the second simulation data through the first rearrangement module, the third coordinate module, the second data module, the simulation data acquisition module and the comparison module to verify the correctness of the transposition intermediate process.

[0115] According to some embodiments, the first rearrangement module rearranges the original data based on the multidimensional array to obtain rearranged data.

[0116] According to some embodiments, the third coordinate module performs an inverse transposition of the RTL model block transposition on the first data point coordinate to obtain a third data point coordinate of the second node before the block transposition device;

[0117] According to some embodiments, the second data module obtains second rearranged data corresponding to the coordinates in the rearranged data based on the coordinates of the third data point.

[0118] The simulation data acquisition module is further configured to acquire second simulation data output by the register transfer level model at the second node; the comparison module is further configured to compare the second rearranged data with the second simulation data to verify the correctness of the transposition intermediate process.

[0119] According to an exemplary embodiment of the present invention, the correctness of the transposition intermediate process is also verified by the second rearrangement module, the fourth coordinate module and the comparison module.

[0120] According to some embodiments, the second rearrangement module rearranges the coordinates of the original data points based on the multidimensional array to obtain the coordinates of the fourth data points.

[0121] According to some embodiments, the fourth coordinate module performs an inverse transposition of the RTL model block transposition on the first data point coordinate to obtain the third data point coordinate of the second node before the block transposition.

[0122] The comparison module is further configured to compare the third coordinate point with the fourth coordinate point, thereby verifying the correctness of the transposition intermediate process.

[0123] The system provided by the present invention realizes real-time comparison of transposed data by combining reverse and forward deduction, which can improve verification efficiency, increase coverage of internal functions, and prevent missed detection due to over-coupling.

[0124] The system of the present invention adds two comparison points, B and C, in the verification process. Compared with the whole process where only point D is compared, the positioning interface is added, which improves the positioning efficiency (see Figure 4 ). Depending on the actual chip situation, you can also add or delete comparison points to adapt to different verification requirements.

[0125] For the full-process comparison, although RTL and the reference model use relatively similar specific calculation processes, the input source of the reference model RM is obtained by reverse deduction through the expected output, while the input of RTL is the original data start and loop address. In the process from point A to point B, both RM and RTL use the forward deduction method. However, in the process from point B to point C, RTL is forward deduction and RM is reverse deduction. Therefore, for example, in certain scenarios, when the calculation from point A to point B and from point B to point C is wrong, but the result from point A to point D is correct, the verification process of the present invention can solve the problem of over-coupling between RTL and RM and discover possible potential problems.

[0126] Figure 6 A block diagram of a computing device is shown according to an exemplary embodiment.

[0127] like Figure 6 As shown, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include bus 22, network interface 16, and I / O interface 18. Processor 12, memory 14, network interface 16, and I / O interface 18 may communicate with each other via bus 22.

[0128] The processor 12 may include one or more general-purpose CPUs (Central Processing Units), microprocessors, or application-specific integrated circuits, etc., for executing relevant program instructions. According to some embodiments, the computing device 30 may also include a high-performance graphics card (GPU) 20 for accelerating the processor 12.

[0129] The memory 14 may include machine-readable media in the form of volatile memory, such as random access memory (RAM), read-only memory (ROM), and / or cache memory. The memory 14 is used to store one or more programs including instructions and data. The processor 12 may read the instructions stored in the memory 14 to execute the method according to the embodiment of the present invention described above.

[0130] The computing device 30 may also communicate with one or more networks through the network interface 16. The network interface 16 may be a wireless network interface.

[0131] The bus 22 may include an address bus, a data bus, a control bus, etc. The bus 22 provides a path for exchanging information between various components.

[0132] It should be noted that, in the specific implementation process, the computing device 30 may also include other components necessary for normal operation. In addition, those skilled in the art will understand that the above-mentioned device may also only include components necessary to implement the embodiments of this specification, and does not necessarily include all components shown in the figure.

[0133] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above method. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a microdrive and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic or optical card, a nanosystem (including a molecular memory IC), a network storage device, a cloud storage device, or any type of medium or device suitable for storing instructions and / or data.

[0134] An embodiment of the present invention further provides a computer program product, which includes a computer program. The computer program is operable to enable a computer to execute part or all of the steps of any one of the methods described in the above method embodiments.

[0135] Those skilled in the art will readily appreciate that the technical solutions of the present invention can be implemented using software and / or hardware. "Unit" and "module" in this specification refer to software and / or hardware that can independently perform specific functions or work in conjunction with other components. Examples of hardware include field programmable gate arrays and integrated circuits.

[0136] It should be noted that for the aforementioned method embodiments, for simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the order of the actions described, because according to the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0137] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0138] In the several embodiments provided herein, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, other division methods may be used. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented. In addition, the coupling or direct coupling or communication connection shown or discussed may be through some service interface. The indirect coupling or communication connection of devices or units may be electrical or other forms.

[0139] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0140] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0141] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. This computer software product is stored in a memory and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the method of the present invention.

[0142] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0143] The exemplary embodiments of the present invention are specifically shown and described above. It should be understood that the present invention is not limited to the detailed structure, configuration or implementation described herein; on the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended clauses.

Claims

1. A method for verifying a transposition operation of a chip register transfer level model, the method comprising: Generate a multidimensional array in the form of coordinate points for storing data used by the reference model, wherein the dimension of the multidimensional array is consistent with the dimension of the data, and the coordinates of the coordinate points correspond to the indexes of the multidimensional array; According to the requirements of the calculation module after the transposition is completed, the data format required by the first node before the calculation module is obtained using the overall transposed data shape, and the first data point coordinates of the data required for each calculation by the calculation module are obtained; Performing an overall transposition operation on the first data point coordinates according to the required transposition dimension to obtain the second data point coordinates corresponding to the original data; According to the coordinates of the second data point, obtaining first reference data corresponding to the coordinates in the original data; Acquire first simulation data output by the register transfer level model at the first node; The first reference data is compared with the first simulation data to verify the correctness of the transposition result.

2. The method according to claim 1, characterized in that Also includes: Based on the multidimensional array, the original data is rearranged to obtain rearranged data; Performing an inverse transposition of the register transfer level model block transposition on the first data point coordinate to obtain a third data point coordinate of the second node before the block transposition; According to the coordinates of the third data point, obtaining second rearranged data corresponding to the coordinates in the rearranged data; Acquire second simulation data output by the register transfer level model at the second node; The second rearranged data is compared with the second simulation data to verify the correctness of the transposition intermediate process.

3. The method according to claim 1, characterized in that The transpose operation and the overall transpose operation are two-dimensional or higher-dimensional.

4. The method according to claim 1, wherein Also includes: Based on the multidimensional array, rearrange the coordinates of the original data points to obtain the coordinates of the fourth data points; Performing an inverse transposition of the RTL model block transposition on the first data point coordinate to obtain a third data point coordinate of the second node before the block transposition; The third coordinate point is compared with the fourth coordinate point to verify the correctness of the transposition intermediate process.

5. The method according to claim 1, wherein Also includes: The output result of the reference model is compared with the output result of the calculation module of the register transfer level model, thereby achieving end-to-end comparison.

6. A system for verifying a transposition operation of a chip register transfer level model, the system comprising: An array module generates a multidimensional array in the form of coordinate points for storing data used by the reference model, wherein the dimension of the multidimensional array is consistent with the dimension of the data, and the coordinates of the coordinate points correspond to the indexes of the multidimensional array; A first coordinate module, based on the requirements of the calculation module after the transposition, uses the overall transposed data shape to obtain the data format required by the first node before the calculation module, and obtains the first data point coordinates of the data required for each calculation by the calculation module; A second coordinate module performs an overall transposition operation on the first data point coordinates according to a required transposition dimension to obtain the second data point coordinates corresponding to the original data; A first data module, which obtains first reference data corresponding to the coordinates in the original data according to the coordinates of the second data point; a simulation data acquisition module, configured to acquire first simulation data output by the register transfer level model at the first node; The comparison module compares the first reference data with the first simulation data to verify the correctness of the transposition result.

7. The system according to claim 6, characterized in that Also includes: A first rearrangement module, based on the multidimensional array, rearranges the original data to obtain rearranged data; A third coordinate module, which performs an inverse transposition of the RTL model block transposition on the first data point coordinate to obtain a third data point coordinate of the second node before the block transposition device; A second data module, according to the coordinates of the third data point, obtains second rearranged data corresponding to the coordinates in the rearranged data; in, The simulation data acquisition module is further configured to acquire second simulation data output by the register transfer level model at the second node; The comparison module is further configured to compare the second rearranged data with the second simulation data, thereby verifying the correctness of the transposition intermediate process.

8. The system according to claim 6, wherein: Also includes: A second rearrangement module, based on the multidimensional array, rearranges the coordinates of the original data points to obtain the coordinates of the fourth data points; a fourth coordinate module, performing an inverse transposition of the RTL model block transposition on the first data point coordinate to obtain a third data point coordinate of the second node before the block transposition; in, The comparison module is further configured to compare the third coordinate point with the fourth coordinate point, thereby verifying the correctness of the transposition intermediate process.

9. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 5 when the computer program is executed by a processor.

10. A computing device, characterized in that include: processor; A memory storing a computer program, wherein when the computer program is executed by the processor, the method according to any one of claims 1 to 5 is implemented.

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