Multi-source chip compatible method and system, vehicle and storage medium

Abstract

The invention provides a multi-source chip compatible method and system, a vehicle and a storage medium. The method comprises the steps that function analysis is conducted on an original chip, an analysis result is obtained, the original chip is a main chip in a multi-source chip cluster, and the analysis result is used for determining multiple functions of the original chip and the mutual relation among the multiple functions; an alternative chip matched with the original chip is selected according to the analysis result, and the alternative chip is a slave chip to be integrated into the multi-source chip cluster; and adapting the hardware environment of the target equipment based on the attribute information of the alternative chip. According to the invention, the technical problems of low compatibility and high cost of a chip replacement method provided in the related art are solved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a multi-source chip compatibility method, system, vehicle, and storage medium. Background Art

[0002] Amidst a global chip shortage and technological blockade, access to high-end chips has become a bottleneck hindering the development of industries such as automotive and electronics. Traditionally, highly integrated single-chip solutions can meet high-performance demands, but they come with high R&D costs and significant supply chain risks. Furthermore, any chip supply constraints directly impact product production and upgrades. To address this, the industry has begun exploring the use of multiple, mature, and stable chips, clustering them to emulate the functionality of high-end chips, as a way to alleviate the supply-demand imbalance. Currently, some multi-chip solutions exist on the market, attempting to coordinate the operation of multiple chips through software. However, these approaches face numerous practical challenges. Firstly, inter-chip compatibility is poor, making functional matching and parameter coordination difficult, resulting in overall system performance far below expectations and low stability. Secondly, high hardware adaptation costs and lengthy chip replacement evaluation cycles make these solutions uneconomical. In particular, when the primary chip fails, the lack of a rapid and effective replacement mechanism results in long system recovery cycles and high maintenance costs.

[0003] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0004] The embodiments of the present disclosure provide a multi-source chip compatibility method, system, vehicle, and storage medium to at least solve the technical problems of low compatibility and high cost of chip replacement methods provided in related technologies.

[0005] According to one aspect of an embodiment of the present disclosure, a multi-source chip compatibility method is provided, comprising: performing a functional analysis on an original chip to obtain an analysis result, wherein the original chip is a master chip in a multi-source chip cluster, and the analysis result is used to determine multiple functions possessed by the original chip and the relationship between the multiple functions; selecting a replacement chip that matches the original chip based on the analysis result, wherein the replacement chip is a slave chip to be integrated into the multi-source chip cluster; and adapting the hardware environment of a target device based on attribute information of the replacement chip.

[0006] Optionally, selecting a replacement chip that matches the original chip based on the analysis results includes: performing multi-dimensional verification on multiple candidate chips based on the analysis results to obtain verification results, wherein the verification results are used to evaluate whether there is a replacement chip that matches the original chip among the multiple candidate chips; and selecting the replacement chip based on the verification results.

[0007] Optionally, multi-dimensional verification is performed on multiple candidate chips based on the analysis results, and the verification results obtained include: performing functional testing on multiple candidate chips based on the analysis results to obtain a first test result, wherein the first test result is used to record the test results of the functions of the multiple candidate chips; performing performance testing on multiple candidate chips based on the analysis results to obtain a second test result, wherein the second test result is used to record the performance indicator test results of the multiple candidate chips; performing compatibility testing on multiple candidate chips based on the analysis results to obtain a third test result, wherein the third test result is used to record the compatibility between the multiple candidate chips and the hardware modules configured in the hardware environment; and determining the verification result based on the first test result, the second test result and the third test result.

[0008] Optionally, selecting a replacement chip based on the verification result includes: selecting a chip that has passed multi-dimensional verification among the plurality of candidate chips as the replacement chip based on the verification result.

[0009] Optionally, the multi-source chip compatibility method in the embodiment of the present disclosure also includes: communicating and interacting between the original chip and the peripheral device associated with the target device through a functional interface encapsulation layer, wherein the functional interface encapsulation layer is used to encapsulate the functional interface corresponding to the original chip into a communication interface that complies with a preset communication standard protocol, and the communication interface is used to communicate with the peripheral device.

[0010] Optionally, the multi-source chip compatibility method in the embodiment of the present disclosure also includes: performing an operating status detection on the original chip to obtain a status detection result; in response to determining that the original chip is in a normal operating state based on the status detection result, generating a target task to be executed based on an external request received from a peripheral device; allocating the target task to the replacement chip through the original chip, so that the replacement chip executes the target task and feeds back the execution result; using the original chip to post-process the execution result to obtain a target processing result; and feeding back the target processing result to the peripheral device via the functional interface encapsulation layer.

[0011] Optionally, allocating the target task to the replacement chip through the original chip includes: obtaining the chip model of the replacement chip; loading the adaptation layer corresponding to the replacement chip based on the chip model, wherein the adaptation layer is encapsulated using a hardware abstraction layer, and the hardware abstraction layer is used to drive the replacement chip into a normal working state after the replacement chip is powered on; allocating the target task issued by the original chip to the replacement chip through the adaptation layer.

[0012] Optionally, the multi-source chip compatibility method in the embodiment of the present disclosure also includes: performing an operating status detection on the original chip to obtain a status detection result; in response to determining that the original chip is in an abnormal operating state based on the status detection result, obtaining a priority sorting result of a replacement chip, wherein different replacement chips have different priorities; based on the priority sorting result, selecting a target chip from the replacement chips, and switching the target chip to a main chip, wherein the main chip has the highest priority.

[0013] Optionally, the multi-source chip compatibility method in the embodiment of the present disclosure also includes: sending a heartbeat packet after any chip among the original chip and the replacement chip is powered on, wherein the heartbeat packet is used to notify the remaining chips of the message that the powered-on chip is in normal operating status; and prioritizing the multiple powered-on chips among the original chip and the replacement chip based on the heartbeat packet to obtain a priority sorting result.

[0014] Optionally, the multi-source chip compatibility method in the embodiment of the present disclosure also includes: performing workload detection on the original chip to obtain a load detection result; in response to determining that the current workload of the original chip has exceeded a preset load threshold based on the load detection result, obtaining a priority sorting result of an alternative chip; based on the priority sorting result, selecting a target chip from the alternative chips, and switching the target chip to the main chip.

[0015] According to another aspect of the embodiment of the present disclosure, a multi-source chip compatibility system is also provided, including: a chip function analysis module, used to perform functional analysis on the original chip to obtain analysis results, wherein the original chip is the main chip in the multi-source chip cluster, and the analysis results are used to determine the multiple functions of the original chip and the relationship between the multiple functions; a replacement chip screening module, used to select a replacement chip that matches the original chip based on the analysis results, wherein the replacement chip is a slave chip to be integrated into the multi-source chip cluster; a hardware adaptation module, used to adapt the hardware environment of the target device based on the attribute information of the replacement chip.

[0016] Optionally, the alternative chip screening module is further used to: perform multi-dimensional verification on multiple candidate chips based on the analysis results to obtain verification results, wherein the verification results are used to evaluate whether there are alternative chips that match the original chips among the multiple candidate chips; and select the alternative chip based on the verification results.

[0017] Optionally, the alternative chip screening module is also used to: perform functional testing on multiple candidate chips based on the analysis results to obtain a first test result, wherein the first test result is used to record the test results of the functions of the multiple candidate chips; perform performance testing on multiple candidate chips based on the analysis results to obtain a second test result, wherein the second test result is used to record the performance indicator test results of the multiple candidate chips; perform compatibility testing on multiple candidate chips based on the analysis results to obtain a third test result, wherein the third test result is used to record the compatibility between the multiple candidate chips and the hardware modules configured in the hardware environment; and determine the verification result based on the first test result, the second test result and the third test result.

[0018] Optionally, the replacement chip screening module is further configured to: based on the verification result, select a chip that has passed the multi-dimensional verification from the plurality of candidate chips as a replacement chip.

[0019] Optionally, the multi-source chip compatible system in the embodiment of the present disclosure also includes: a communication module, which is used to communicate and interact between the original chip and the peripheral device associated with the target device through a functional interface encapsulation layer, wherein the functional interface encapsulation layer is used to encapsulate the functional interface corresponding to the original chip into a communication interface that complies with a preset communication standard protocol, and the communication interface is used to communicate with the peripheral device.

[0020] Optionally, the communication module is also used to: perform an operating status detection on the original chip to obtain a status detection result; in response to determining that the original chip is in a normal operating state based on the status detection result, generate a target task to be executed based on an external request received from a peripheral device; allocate the target task to the replacement chip through the original chip, so that the replacement chip executes the target task and feeds back the execution result; use the original chip to post-process the execution result to obtain a target processing result; and feed back the target processing result to the peripheral device via the functional interface encapsulation layer.

[0021] Optionally, the communication module is also used to: obtain the chip model of the replacement chip; load the adaptation layer corresponding to the replacement chip based on the chip model, wherein the adaptation layer is encapsulated using a hardware abstraction layer, and the hardware abstraction layer is used to drive the replacement chip into a normal working state after the replacement chip is powered on; and allocate the target task issued by the original chip to the replacement chip through the adaptation layer.

[0022] Optionally, the communication module is also used to: perform an operating status detection on the original chip to obtain a status detection result; in response to determining that the original chip is in an abnormal operating state based on the status detection result, obtain a priority sorting result of the replacement chip, wherein different replacement chips have different priorities; based on the priority sorting result, select a target chip from the replacement chips, and switch the target chip to the main chip, wherein the main chip has the highest priority.

[0023] Optionally, the communication module is also used to: send a heartbeat packet after any chip among the original chip and the replacement chip is powered on, wherein the heartbeat packet is used to notify the remaining chips of the message that the powered-on chip is in normal operating status; and prioritize multiple powered-on chips among the original chip and the replacement chip based on the heartbeat packet to obtain a priority sorting result.

[0024] Optionally, the multi-source chip compatible system in the embodiment of the present disclosure also includes: a detection module, which is used to perform workload detection on the original chip and obtain a load detection result; an acquisition module, which is used to respond to the load detection result, in which it is determined that the current workload of the original chip has exceeded a preset load threshold, and obtain a priority sorting result of the replacement chip; and a selection module, which is used to select a target chip from the replacement chips based on the priority sorting result, and switch the target chip to the main chip.

[0025] According to another aspect of an embodiment of the present disclosure, a vehicle is further provided, including: a memory storing an executable program; and a processor for running the program, wherein the multi-source chip compatibility method in the embodiment of the present disclosure is executed when the program is run.

[0026] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is further provided. The computer-readable storage medium includes a stored executable program, wherein when the executable program runs, the device where the storage medium is located is controlled to execute the multi-source chip compatibility method in the embodiment of the present disclosure.

[0027] According to another aspect of the embodiments of the present disclosure, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the multi-source chip compatibility method in the embodiments of the present disclosure is implemented.

[0028] In the embodiment of the present disclosure, by performing functional analysis on the original chip, and then selecting a replacement chip that matches the original chip based on the analysis results, and finally adapting the hardware environment of the target device based on the attribute information of the replacement chip, the purpose of rapid response and flexible chip replacement is achieved when the chip supply is limited or the cost is high, thereby achieving the technical effect of improving the chip compatibility of the multi-source chip compatible system and reducing the chip replacement cost, and thus solving the technical problems of low compatibility and high cost of the chip replacement method provided in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0030] Figure 1 is a flow chart of a multi-source chip compatibility method according to one embodiment of the present disclosure;

[0031] Figure 2 is a schematic diagram of a multi-source chip compatible system according to one embodiment of the present disclosure;

[0032] Figure 3 is a schematic diagram of a multi-dimensional verification method according to one embodiment of the present disclosure;

[0033] Figure 4 is a schematic diagram of a multi-source chip compatibility method according to one embodiment of the present disclosure;

[0034] Figure 5 is a schematic diagram of a hardware abstraction layer according to one embodiment of the present disclosure;

[0035] Figure 6 is a schematic diagram of another multi-source chip compatibility method according to one embodiment of the present disclosure;

[0036] Figure 7 is a schematic diagram of another multi-source chip compatibility method according to one embodiment of the present disclosure;

[0037] Figure 8 It is a structural block diagram of a multi-source chip compatible system according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0040] According to an embodiment of the present disclosure, a method embodiment of a multi-source chip compatibility method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0041] The method embodiment can be executed in an electronic device or similar computing device including a memory and a processor. Taking running on a computer terminal as an example, the computer terminal may include one or more processors (processors may include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processing (DSP) chip, a microcontroller unit (MCU), a programmable logic device (Field Programmable Gate Array, FPGA), a neural network processor (NPU), a tensor processing unit (TPU), an artificial intelligence (AI) type processor, etc.) and a memory for storing data. Optionally, the above-mentioned computer terminal may also include a transmission device, an input and output device, and a display device for communication functions. It will be understood by those skilled in the art that the above-mentioned structural description is only illustrative and does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include more or fewer components than the above-mentioned structural description, or have a configuration different from the above-mentioned structural description.

[0042] The memory can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the source chip compatible method in the embodiment of the present disclosure. The processor executes various functional applications and data processing by running the computer program stored in the memory, that is, realizing the above-mentioned source chip compatible method. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely located relative to the processor, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0043] The transmission device is used to receive or send data via a network. Specific examples of the aforementioned network may include a wireless network provided by the mobile terminal's communications provider. In one embodiment, the transmission device includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In one embodiment, the transmission device may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0044] The display device can be, for example, a touch-screen liquid crystal display (LCD) and a touch display (also referred to as a "touch screen" or "touch display screen"). The liquid crystal display can enable the user to interact with the user interface of the mobile terminal. In some embodiments, the mobile terminal has a graphical user interface (GUI), and the user can interact with the GUI by finger contacts and / or gestures on the touch-sensitive surface. The human-computer interaction functions here optionally include the following interactions: creating web pages, drawing, word processing, making electronic documents, games, video conferencing, instant messaging, sending and receiving emails, call interfaces, playing digital videos, playing digital music and / or web browsing, etc. The executable instructions for performing the above-mentioned human-computer interaction functions are configured / stored in a computer program product or readable storage medium executable by one or more processors.

[0045] Figure 1 is a flow chart of a multi-source chip compatibility method according to one embodiment of the present disclosure. Figure 1 As shown, the method includes the following steps:

[0046] Step S11, performing functional analysis on the original chip to obtain analysis results, wherein the original chip is the main chip in the multi-source chip cluster, and the analysis results are used to determine multiple functions of the original chip and the relationships between the multiple functions;

[0047] The above-mentioned original chip is the main chip located in the host unit in the multi-source chip cluster, and is used to realize the core computing, data processing, system control and interface management of the multi-source chip cluster.

[0048] For example, the original chip can be any high-performance, highly integrated processor or microcontroller, such as Xilinx Zynq UltraScale+ MPSoC, NVIDIA Jetson Xavier NX, Intel Atom x6000E, Qualcomm Snapdragon 865, etc. Among the above original chips, Xilinx Zynq UltraScale+ MPSoC combines an ARM processor and a field-programmable gate array (FPGA), with powerful computing power and programmable logic resources, suitable for complex data processing and system control scenarios; NVIDIA Jetson Xavier NX is a high-performance chip designed for AI and machine learning applications, integrating GPU, CPU, deep learning accelerator, etc., and can provide efficient parallel computing and deep learning processing capabilities; Intel Atom x6000E is a low-power, high-performance processor suitable for edge computing, Internet of Things, and embedded systems; Qualcomm Snapdragon 865 is a high-end mobile processing chip with a high-performance CPU, GPU, and AI engine, suitable for the high-performance requirements of smartphones, tablets, smart cars and other fields.

[0049] It should be noted that the original chip in the embodiment of the present disclosure is not limited to the above-mentioned specific models, and the original chip can be flexibly selected according to actual conditions.

[0050] Figure 2 FIG. 1 is a schematic diagram of a multi-source chip compatible system according to one embodiment of the present disclosure. Figure 2 As shown, the system includes: a master unit and multiple slave units, each unit is equipped with a master-slave unit scheduling and management module, a system module and a functional interface. Figure 2 In the system, the host unit is connected to the slave units 1 to n via an internal communication bus; the host unit is connected to the peripheral devices via a functional interface.

[0051] The master unit is responsible for controlling and managing the entire multi-source chip cluster, scheduling tasks, and communicating with the outside world. Specifically, it receives and interprets external requests, distributes tasks to slave units, and collects feedback from slave units, organizing it and providing services to the outside world.

[0052] The slave units are responsible for executing specific tasks assigned to them according to the scheduling of the master unit. In the disclosed embodiment, the number of master units can be flexibly adjusted according to system requirements and chip availability.

[0053] The master-slave unit scheduling and management module is used to dynamically allocate tasks to different slave units in the multi-source chip system according to the real-time needs of the system and the performance status of each slave unit, while monitoring and managing the operating status of the entire system.

[0054] The above system modules include various functional modules embedded in the chip, such as memory management, communication protocol stack, etc.

[0055] The above functional interfaces are various interfaces provided by the multi-source chip compatible system to the outside world and are used to interact with peripheral devices.

[0056] For example, the chip function analysis module can conduct a comprehensive and in-depth analysis of the original chip's functionality, accurately identifying the chip's key functional points and the relationships between them. This detailed analysis of chip functionality provides an accurate basis for subsequent selection of replacement chips, ensuring that the replacement chips closely match the original chip's functionality, thereby safeguarding the normal operation of a multi-source chip compatibility system.

[0057] For example, a preset test framework can be used to perform benchmark tests on various functions of the original chip, including but not limited to processor performance tests, GPU rendering capability tests, direct memory access (DMA) bandwidth measurements, communication interface transmission rate and stability tests, etc., and measurement tools and software can be used to collect actual operating data of the original chip, including key indicators such as power consumption, latency, and throughput under different loads. Furthermore, the original chip is analyzed and processed based on the above data, and a database based on the functional characteristics and mutual relationships of the original chip is constructed based on the analysis results, recording the static specifications of each functional module of the original chip and the details of the dynamic interactions between the functional modules. For example, when the CPU performs intensive operations, how does DMA effectively transfer data from external memory to the GPU for parallel processing, and how does the bandwidth utilization of the functional interface change in this scenario?

[0058] Step S12, selecting a replacement chip that matches the original chip based on the analysis result, wherein the replacement chip is a slave chip to be integrated into the multi-source chip cluster;

[0059] The above-mentioned replacement chip is a slave chip selected from multiple slave units based on the functional characteristics and performance requirements of the original chip.

[0060] For example, if the primary chip is a high-performance computing chip, the replacement chip can be a slave chip with similar computing power and interfaces, such as Intel's Atom series processors, ARM's Cortex-A series chips, or AMD's embedded Ryzen processors. These replacement chips can achieve similar levels of performance as the primary chip in key functions and have good compatibility with the primary chip, making them suitable replacement chips for the original chip.

[0061] Step S13: adapting the hardware environment of the target device based on the attribute information of the replacement chip.

[0062] The attribute information of the above-mentioned replacement chips includes but is not limited to the chip's architecture type, number of cores, main frequency, power consumption characteristics, memory interface type and bandwidth, supported communication protocols and interfaces, peripheral support, temperature range, and chip package size and pin definition.

[0063] Specifically, the architecture type and core count of the replacement chip can be used to estimate its computing power and parallel processing potential in different scenarios. Power consumption characteristics can be used to consider the impact on battery life or thermal management when designing power management systems. Memory interface type and bandwidth can be used to assess the replacement chip's data processing efficiency and storage expansion capabilities. Communication protocols and interfaces directly impact its compatibility with peripheral devices and communication efficiency. Furthermore, the replacement chip's peripheral support helps determine whether additional hardware components or drivers are required to support specific functions. Temperature range and package size information are used to assess the replacement chip's stability in different environments and its ability to fit within the target device's physical space constraints. By carefully analyzing and adjusting these attributes, the hardware adaptation module intelligently configures hardware parameters such as voltage and current, optimizes circuit design, and adjusts thermal management to accommodate the replacement chip's characteristics. This ensures functional continuity in a multi-source chip-compatible system when using the replacement chip, while mitigating the additional costs and risks associated with chip replacement. Therefore, adapting the target device's hardware environment based on the replacement chip's attribute information ensures high performance, stability, and compatibility within a multi-source chip cluster, even in the event of supply issues with the primary chip.

[0064] Based on the above steps S11 to S13, by performing functional analysis on the original chip, a replacement chip that matches the original chip is selected based on the analysis results, and finally, based on the attribute information of the replacement chip, the hardware environment of the target device is adapted, thereby achieving the purpose of rapid response and flexible chip replacement when chip supply is limited or cost is high, thereby achieving the technical effect of improving the chip compatibility of the multi-source chip compatible system and reducing the chip replacement cost, and thus solving the technical problems of low compatibility and high cost of the multi-source chip compatibility method provided in the related art.

[0065] Optionally, in step S12, selecting a replacement chip that matches the original chip according to the analysis result includes:

[0066] Step S121 , performing multi-dimensional verification on the plurality of candidate chips according to the analysis results to obtain verification results, wherein the verification results are used to evaluate whether there is an alternative chip that matches the original chip among the plurality of candidate chips;

[0067] Step S122: selecting a replacement chip based on the verification result.

[0068] The candidate chips mentioned above are from different manufacturers and have different functional characteristics. Specifically, the candidate chips include but are not limited to high-performance computing chips, embedded microcontrollers, dedicated signal processors, FPGAs, low-power chips, AI-specific chips, automotive-grade chips, industrial-grade chips, and security chips.

[0069] For example, multiple candidate chips can be subject to multi-dimensional verification based on factors such as functional compatibility, performance, power consumption, compatibility, cost-effectiveness, and supply chain risk. Based on the verification results, the candidate chips can be evaluated for potential replacement chips that match the original chip. Once the multi-dimensional verification of the candidate chips is complete, the suitability of each chip can be comprehensively evaluated using a weighted average method or a rule-based decision tree, based on the scores of various indicators in the verification results. This allows the selection of replacement chips that match the original chip.

[0070] Based on the above steps S121 to S122, multiple candidate chips are multi-dimensionally verified according to the analysis results, and replacement chips are selected based on the verification results. This can ensure that when chip supply is limited, compatible replacement chips can be selected quickly and accurately to maintain system functional stability, optimize costs, and enhance supply chain flexibility.

[0071] Optionally, in step S121, multiple candidate chips are respectively subjected to multi-dimensional verification based on the analysis results, and the obtained verification results include:

[0072] Step S1211: Perform functional tests on the multiple candidate chips according to the analysis results to obtain first test results, wherein the first test results are used to record test results of the functions of the multiple candidate chips;

[0073] Step S1212: Perform performance tests on the multiple candidate chips according to the analysis results to obtain second test results, where the second test results are used to record performance indicator test results of the multiple candidate chips;

[0074] Step S1213: performing compatibility tests on the multiple candidate chips based on the analysis results to obtain third test results, where the third test results are used to record the compatibility between the multiple candidate chips and the hardware modules configured in the hardware environment;

[0075] Step S1214: Determine a verification result based on the first test result, the second test result, and the third test result.

[0076] Figure 3 is a schematic diagram of a multi-dimensional verification method according to one embodiment of the present disclosure, such as Figure 3 As shown, in the process of multi-dimensional verification of multiple candidate chips, it is first necessary to determine the chip model and load the dynamic hardware abstraction layer configuration (DHAL configuration) based on the chip model. Furthermore, multi-dimensional verification is performed based on hardware initialization, namely functional testing, performance testing, and compatibility testing, and whether the multi-dimensional verification has passed is determined based on the above multi-dimensional verification results. Finally, if the multi-dimensional verification passes, the current verification process ends. Otherwise, debugging and repair are performed, and re-determination is made as to whether the multi-dimensional verification has passed.

[0077] These functional tests include, but are not limited to, GPIO read and write tests, SPI communication tests, clock management tests, interrupt handling tests, image processing tests, and data encryption tests. GPIO read and write operations involve data input and output operations through the General Purpose Input / Output (GPIO) interface, reading pin status or outputting signals to pins. SPI communication is a synchronous serial data communication protocol commonly used for high-speed data exchange between microcontrollers and peripheral devices (such as sensors and memory chips).

[0078] The above performance tests include but are not limited to processing speed tests, power consumption tests, memory bandwidth tests, calculation accuracy tests, response time tests, data throughput tests, etc.

[0079] The above compatibility tests include but are not limited to system bus compatibility tests, peripheral interface compatibility tests, software driver compatibility tests, operating voltage range tests, operating temperature range tests, and electromagnetic compatibility tests.

[0080] For example, the above-mentioned functional test, performance test and compatibility test can be performed on multiple candidate chips respectively according to the analysis results, thereby obtaining multiple test results, and then determining whether the multiple candidate chips pass the multi-dimensional verification based on the multiple test results.

[0081] For example, assume the target device is an intelligent industrial robot. Due to supply chain disruptions, a replacement chip matching the main chip needs to be selected from multiple candidate chips. Based on this scenario, multiple candidate chips require multi-dimensional verification. Specifically, using GPIO read / write testing and SPI communication testing as examples, the functional testing process for multiple candidate chips is as follows: When performing GPIO read / write testing on multiple candidate chips, a simulated motor control circuit can be connected to the candidate chip's GPIO pins. By controlling the GPIO output state, the motor's start, stop, and direction control can be simulated. Feedback from the GPIO input pins is simultaneously monitored to verify signal correctness, thereby testing whether the candidate chips can effectively control and read input / output signals. When performing SPI communication testing on multiple candidate chips, a standard SPI read / write module, such as an SPI flash memory or SPI sensor, can be used to establish an SPI communication connection with the candidate chip. By sending a series of SPI read / write commands, the chip is tested to ensure that it can correctly exchange data with the SPI device, including data reading, writing, and synchronization timing control.

[0082] For example, taking processing speed testing and power consumption testing as examples, the performance testing process for multiple candidate chips is as follows: When testing the processing speed of multiple candidate chips, a benchmark program containing complex industrial control algorithms (such as motion planning and visual recognition) can be constructed. By running the above benchmark program on multiple candidate chips, the time required for multiple candidate chips to complete the program is measured to test their processing speed. When testing the power consumption of multiple candidate chips, a power consumption analyzer can be used to monitor the power consumption changes of the candidate chips in real time during the execution of the benchmark program, record their average power consumption and peak power consumption, and evaluate the energy efficiency level of the chips.

[0083] For example, taking the peripheral interface compatibility test and software driver compatibility test as examples, the test process for compatibility testing of multiple candidate chips is as follows: When testing the compatibility of multiple candidate chips with peripheral interfaces, you can connect a variety of common industrial peripherals, such as sensors, actuators (such as motors, valves, etc.), and communication modules to different interfaces of the candidate chips, and test whether the candidate chips can correctly identify and respond to the above control instructions by sending control instructions, thereby testing the compatibility of multiple candidate chips with peripheral interfaces. For software driver compatibility testing, you can install software stacks and operating systems commonly used by intelligent industrial robots, such as Linux or RTOS, on the candidate chips. Then, load a series of standard device drivers covering all peripheral types and observe whether the drivers can successfully initialize and control the corresponding hardware devices. In addition, you can run some applications to see if there will be driver conflicts, system crashes or abnormal behaviors, so as to evaluate the compatibility and stability of the candidate chips at the software level.

[0084] Based on the above steps S1211 to S1214, multiple candidate chips are multi-dimensionally verified according to the analysis results, and then the verification results are determined based on the test results. This can screen out the replacement chip that is closest to and most compatible with the original chip, ensuring that the replacement chip can meet the requirements of the multi-source chip compatible system in various dimensions, reducing system integration risks, and improving system stability and reliability.

[0085] Optionally, in step S13 , selecting a replacement chip based on the verification result includes: selecting a chip that has passed multi-dimensional verification among the plurality of candidate chips as the replacement chip based on the verification result.

[0086] For example, the first, second, and third test results can be compared against preset standards or thresholds to select a chip that meets the required functionality, performance, and compatibility as a replacement chip. If multiple chips pass multi-dimensional verification, the advantages and disadvantages of these chips are further compared on key metrics, such as performance, cost, and availability, to determine the optimal choice. Ultimately, the chip with the best overall performance among the multi-dimensionally verified chips is selected as a replacement chip. Furthermore, all key parameters and test results of the selected replacement chip can be recorded for reference during subsequent design and verification.

[0087] Based on the above optional embodiments, a chip that has passed multi-dimensional verification among multiple candidate chips is selected as a replacement chip, which can ensure that the selected chip meets the original design requirements in many aspects such as function, performance and compatibility, and effectively reduce system instability and compatibility issues caused by chip replacement.

[0088] Optionally, the multi-source chip compatibility method in the embodiment of the present disclosure also includes: communicating and interacting between the original chip and the peripheral device associated with the target device through a functional interface encapsulation layer, wherein the functional interface encapsulation layer is used to encapsulate the functional interface corresponding to the original chip into a communication interface that complies with a preset communication standard protocol, and the communication interface is used to communicate with the peripheral device.

[0089] The functional interface encapsulation layer is used to encapsulate the functional interfaces provided by the host unit into standard communication interfaces, such as the Peripheral Component Interconnect Express (PCIe) interface, Ethernet interface, Controller Area Network (CAN) interface, Universal Asynchronous Receiver / Transmitter (UART) interface, bidirectional two-wire serial bus (I2C) interface, and Serial Peripheral Interface (SPI). Among these communication interfaces, the PCIe interface is used for high-speed data transmission and is suitable for high-performance computing and storage devices; the Ethernet interface is used for network communication and is suitable for network devices and remote control; the CAN interface is used in automotive and industrial control and is suitable for real-time control and communication; the UART interface is used for serial communication and is suitable for low-speed devices and debugging; the I2C interface is used for low-speed device communication and is suitable for sensors and small devices; and the SPI interface is used for high-speed device communication and is suitable for storage and sensors.

[0090] The above-mentioned peripheral devices are various devices that interact with multi-source chip compatible systems, including but not limited to storage devices, network devices, sensors, actuators, displays, input devices, power management devices, industrial control equipment, audio and video equipment, wireless communication equipment and navigation and positioning equipment.

[0091] Figure 4 is a schematic diagram of a multi-source chip compatibility method according to one embodiment of the present disclosure, such as Figure 4 As shown, in this method, the chip cluster product provides the required functional interfaces to the outside world, encapsulating them into standard communication interfaces (such as PCIe, Ethernet, CAN, UART, I2C, SPI, and other common interfaces), connecting and communicating with peripheral devices, making them universally applicable to other hardware platforms or other products. When the system is operating, a master unit and slave units are defined. The master unit is responsible for the external functional interface device and is responsible for scheduling and managing the task allocation of the slave units. The slave units are responsible for executing the tasks assigned by the master unit through their functional modules and feeding back the data obtained after execution to the master unit.

[0092] For example, suppose the original chip has a native data transmission interface whose communication protocol and data format are incompatible with the peripheral devices on the target device. In this case, the functional interface encapsulation layer can be used to encapsulate and convert the data transmission interface of the original chip into an interface that complies with the communication standard of the target device's peripheral devices, such as a PCIe interface. After the encapsulation conversion, the original chip and the peripheral devices can communicate using the PCIe protocol, eliminating the need for the peripheral devices to adapt to the original chip's specific communication protocol, thereby improving the compatibility and flexibility of the system.

[0093] Based on the above optional embodiment, communication interaction is performed between the original chip and the peripheral device associated with the target device through the functional interface encapsulation layer, which can improve the compatibility and communication efficiency between the original chip and the peripheral device.

[0094] Optionally, the multi-source chip compatibility method in the embodiment of the present disclosure further includes:

[0095] Step S21, performing a running status test on the original chip to obtain a status test result;

[0096] Step S22 , in response to determining that the original chip is in a normal operating state according to the status detection result, generating a target task to be executed based on an external request received from the peripheral device;

[0097] Step S23, allocating the target task to the replacement chip through the original chip, so that the replacement chip executes the target task and feeds back the execution result;

[0098] Step S24, post-processing the execution result using the original chip to obtain the target processing result;

[0099] Step S25 : Feedback the target processing result to the peripheral device via the functional interface encapsulation layer.

[0100] The above status detection results are indicators of the current operating status of the original chip, including but not limited to chip temperature, voltage stability, CPU utilization, memory utilization, system error logs, etc., which are used to determine whether the original chip is in a safe and stable working state.

[0101] The above-mentioned target tasks are specific operation instructions or data processing tasks parsed by the original chip based on external requests, such as data packet processing tasks received from the network, sensor data collection and analysis tasks, image recognition tasks, audio encoding or decoding tasks, etc.

[0102] Post-processing is a series of supplementary operations performed by the original chip after the replacement chip completes the target task and returns the execution results. It is used to ensure data integrity and security, and to ensure the connection with subsequent tasks. Specifically, post-processing includes but is not limited to data verification, encryption and decryption, format conversion, error handling, result integration, system logging, etc., to ensure that the processing results meet the expected system requirements and, if necessary, optimize or adjust the results to facilitate understanding and processing by peripheral devices or higher-level applications.

[0103] For example, if the target task is an image recognition task, the target processing result can be image data with an identification tag, which has been encrypted or formatted for display or storage operations; if the target task is a data packet processing task, the target processing result can be a data packet that has been verified, reassembled or error-corrected for receipt and forwarding by a network layer device.

[0104] For example, during the operation of a multi-source chip compatibility system, the original chip first initiates a self-test program to monitor its own chip temperature, power supply voltage stability, CPU usage, memory utilization, and error records in the system log, generating detailed status detection results. Furthermore, based on the status detection results, after confirming that the original chip is operating normally, the original chip begins receiving data requests from peripheral devices, parses the request content, and generates target tasks to be executed. These generated target tasks are then appropriately assigned to the replacement chips based on the performance of each replacement chip and the current task requirements. Upon receiving the target tasks, the replacement chips initiate the corresponding processing routines, execute the target tasks, generate execution results, and feed the results back to the original chip. Upon receiving the execution results, the original chip immediately initiates a post-processing routine to perform verification, format conversion, and necessary encryption on the execution results to ensure their integrity and security, generating the target processing results. Finally, the target processing results are converted into data packets in a standard communication protocol format, such as PCIe, Ethernet, or CAN, through the functional interface encapsulation layer, and transmitted to the peripheral devices.

[0105] Based on the above steps S21 to S25, through the dynamic task allocation and execution result post-processing mechanism of the multi-source chip compatible system, efficient utilization of chip resources and safe optimization of data processing can be achieved, ensuring that even in a complex and changing operating environment, the multi-source chip compatible system can continue to provide services to peripheral devices in a stable manner, thereby improving the adaptability and reliability of the system.

[0106] Optionally, in step S23, allocating the target task to the replacement chip through the original chip includes:

[0107] Step S231, obtaining the chip model of the replacement chip;

[0108] Step S232: Loading an adaptation layer corresponding to the replacement chip based on the chip model, wherein the adaptation layer is encapsulated by a hardware abstraction layer, and the hardware abstraction layer is used to drive the replacement chip into a normal working state after the replacement chip is powered on;

[0109] Step S233: Allocate the target task issued by the original chip to the replacement chip through the adaptation layer.

[0110] The above chip model is a unique identifier for the replacement chip, which contains important information such as manufacturer, product series, version number, etc., and is used to accurately identify the type and specifications of each replacement chip.

[0111] The adaptation layer is a software module whose function is to provide hardware drivers and interface call layers that match the replacement chip's model and characteristics. The adaptation layer is designed to bridge the hardware differences between the original chip and the replacement chip. By loading the adaptation layer corresponding to the chip model, the replacement chip can function properly in a multi-source chip-compatible system, effectively replacing the original chip's functionality. It also handles inter-chip communication protocol conversion, hardware resource management, and task scheduling, ensuring that the replacement chip can execute its assigned target tasks within the system while maintaining overall system stability and compatibility.

[0112] The hardware abstraction layer (HAL) is the foundational software layer in a multi-chip compatible system. Its purpose is to establish a unified interface between the operating system or upper-layer software and the specific hardware. The HAL hides the hardware details of different chips and provides a standardized set of functions and data structures, allowing upper-layer software to access and control various hardware resources in a consistent manner, regardless of hardware differences.

[0113] Figure 5 is a schematic diagram of a hardware abstraction layer according to one embodiment of the present disclosure, such as Figure 5 As shown, the process is as follows: the application layer calls the unified application programming interface (API) through the dynamic hardware abstraction layer (DHAL) interface, and forwards the API to the corresponding adaptation layer in the hardware abstraction layer.

[0114] For example, at system startup, the chip ID register or other hardware detection mechanism is used to determine the currently used chip model. Furthermore, based on the detected chip model, the corresponding adaptation layer is dynamically loaded. For example, if chip A is detected, the chip A adaptation layer is loaded; if chip B is detected, the chip B adaptation layer is loaded. Finally, the adaptation layer performs the corresponding hardware operations based on the specific chip hardware characteristics and returns the results to the application layer.

[0115] For example, after determining the adaptation layer corresponding to the replacement chip, the target task issued by the original chip can be assigned to the replacement chip based on the interface corresponding to the replacement chip. For example, the target task corresponding to chip A issued by the original chip can be assigned to chip A through chip A's hardware interface; the target task corresponding to chip B issued by the original chip can be assigned to chip B through chip B's hardware interface.

[0116] Based on the above steps S231 to S233, through the synergy between the dynamic hardware abstraction layer (DHAL) and the adaptation layer, the model of the replacement chip can be automatically identified, and the corresponding driver and interface call layer can be loaded, thereby improving the adaptability of the multi-source chip compatible system.

[0117] Optionally, the multi-source chip compatibility method in the embodiment of the present disclosure further includes:

[0118] Step S31, performing a running status test on the original chip to obtain a status test result;

[0119] Step S32, in response to determining that the original chip is in an abnormal operating state according to the status detection result, obtaining a priority ranking result of a replacement chip, wherein different replacement chips have different priorities;

[0120] Step S33 : Based on the priority sorting result, a target chip is selected from the alternative chips, and the target chip is switched to the main chip, wherein the main chip has the highest priority.

[0121] The above abnormal operating conditions include but are not limited to abnormal operation, abnormal temperature, system crash, abnormal power supply, communication failure, memory overflow, etc.

[0122] For example, if the status detection result determines that the original chip is in an abnormal operating state, the priority ranking of the replacement chips is as follows: replacement chip 1 > replacement chip 2 > replacement chip 3 > ... > replacement chip n. Because replacement chip 1 has the highest priority in the priority ranking, replacement chip 1 can be selected as the target chip and switched to the primary chip.

[0123] Figure 6 is a schematic diagram of another multi-source chip compatibility method according to one embodiment of the present disclosure, such as Figure 6 As shown in the figure, the master unit is responsible for monitoring its own operating status and performing task control and data transmission with the slave units. The slave units are used to feed back task execution data to the master unit via an internal communication bus. If an anomaly occurs in the master unit, a secondary slave unit can be configured to operate in master mode through an anomaly detection and switching mechanism, reasserting control of external interfaces and ensuring that external communication functions continue to function properly.

[0124] For example, after the optional replacement chip is determined, it can be integrated into the chip cluster. The chips can be interconnected, hybrid-connected, or star-connected, and accessed in a one-master-multiple-slave mode.

[0125] Based on the above steps S31 to S33, by selecting the target chip from the alternative chips according to the priority sorting results of the alternative chips when the original chip is in an abnormal operating state, the system can be quickly recovered and its functions can be continued. This ensures that even if the main chip fails, the system can quickly mobilize backup resources and promote the alternative chip that best meets current needs and is the most stable to the main chip, thereby avoiding the risk of system shutdown or service interruption, improving the continuity of external communications and services, and at the same time, there is no need to replace the new original chip, thereby reducing hardware costs.

[0126] Figure 7 is a schematic diagram of another multi-source chip compatibility method according to one embodiment of the present disclosure, such as Figure 7 As shown, when the multi-source chip compatible system starts, the host unit and all slave units are initialized first, and the status of the original chip in the host unit is detected. Subsequently, based on the status detection result, it is determined whether the original chip in the host unit is in a normal operating state. Then, when the original chip is in a normal operating state, a target task to be executed is generated based on an external request received from a peripheral device, and the target task is assigned to a replacement chip in the slave unit. Furthermore, the replacement chip feeds back the execution result generated after executing the target task to the original chip. After receiving the execution result, the original chip post-processes the execution result to obtain the target processing result, and finally feeds back the target processing result to the peripheral device via the functional interface encapsulation layer. On the contrary, when the original chip is in an abnormal operating state, the sub-priority replacement chip is switched to the original chip, that is, the sub-priority slave unit is switched to the host unit, and the operating state of the original chip in the current host unit is re-judged to be normal.

[0127] Optionally, the multi-source chip compatibility method in the embodiment of the present disclosure further includes:

[0128] Step S41: After any one of the original chip and the replacement chip is powered on, a heartbeat packet is sent, wherein the heartbeat packet is used to notify the other chips that the powered-on chip is in a normal operating state;

[0129] Step S42 : Prioritizing multiple powered-on chips among the original chip and the replacement chip based on the heartbeat packet to obtain a priority ranking result.

[0130] The heartbeat packet is a small data packet sent periodically, and is mainly used to monitor whether each node in the network or the chip in the system is in an active state.

[0131] For example, when any chip is powered on, it will periodically send heartbeat packets to other chips in the system. The receiving chip can determine whether the sending chip is in normal operation based on the received heartbeat packet information, and then update the priority ranking between the chips.

[0132] For example, in a multi-source chip compatible system, if a high-priority original chip detects an abnormal operation, the system initiates the exception handling process. At this point, a lower-priority replacement chip, upon detecting a heartbeat packet interruption or abnormal status report from the abnormal chip, immediately notifies the master's power control unit to reset the original chip. This involves cutting off and re-supplying power, restoring normal operation through a hardware-level reset. After the reset is complete, the original chip will resend a heartbeat packet when powered on again, indicating that it has re-entered normal operation. Upon receiving the heartbeat packet, the system re-evaluates and re-orders the operating priorities of all powered-on chips based on their actual operating status and pre-set priority rules. If the original chip returns to normal after the reset, it will re-assume system control and external communication tasks. However, if the abnormal state of the original chip cannot be resolved through a reset, the replacement chip with the highest priority will be selected as the primary chip.

[0133] Based on the above steps S41 to S42, through the combined application of the heartbeat packet mechanism and dynamic priority sorting, real-time monitoring and efficient management of the operating status of the chips in the system can be achieved, ensuring that the system has the ability to respond quickly and self-repair when facing chip anomalies, maintaining the continuity of external communications and services, and optimizing chip resource allocation, thereby improving the overall system stability and operating efficiency.

[0134] Optionally, the multi-source chip compatibility method in the embodiment of the present disclosure further includes:

[0135] Step S51, performing workload detection on the original chip to obtain a load detection result;

[0136] Step S52 , in response to determining that the current workload of the original chip has exceeded a preset workload threshold according to the load detection result, obtaining a priority ranking result of a replacement chip;

[0137] Step S53 : Based on the priority sorting result, a target chip is selected from the alternative chips, and the target chip is switched to the main chip.

[0138] For example, in a multi-source chip compatibility system, if a chip with the highest priority is detected to be operating at a high load, the system will automatically adjust the priority of that chip to the second priority. The system will then re-evaluate and prioritize the chips based on the CPU load of all current alternative chips, identify the alternative chip with the lowest CPU load, and configure it in master mode to share the workload, ensuring the smooth operation of the entire chip cluster and maintaining communication with the outside world.

[0139] For example, in a multi-chip compatible in-vehicle electronic control system, the primary chip is responsible for processing large amounts of real-time data, including vehicle sensor information, navigation data, and data processing for driver assistance functions. Due to the various complex road conditions and driving behaviors during vehicle operation, the primary chip may face sudden high load pressures. For example, when performing complex path planning and real-time obstacle detection in busy urban traffic, CPU utilization can surge, memory usage increases, and system interrupt requests become frequent, causing the primary chip's workload to quickly exceed its preset safety threshold. When the system recognizes that the primary chip's load has exceeded the preset load threshold, it immediately obtains the priority ranking results of alternative chips and, based on the ranking results, selects a target chip from the alternative chips, switching the target chip to the primary chip. Simultaneously, the original primary chip is downgraded to a slave chip, which can suspend some non-critical tasks and perform necessary cooling or other maintenance operations to reduce its load and restore its health.

[0140] Based on the above steps S51 to S53, by dynamically adjusting the priority and intelligently switching the master and slave chips, the workload of the multi-source chip compatible system can be effectively balanced, ensuring stable operation of the system while maintaining efficient communication with the outside world.

[0141] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present disclosure.

[0142] In the embodiments of the present disclosure, a multi-source chip compatible system is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments. The details that have been described will not be repeated here. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation by hardware, or a combination of software and hardware, is also possible and contemplated.

[0143] Figure 8 is a structural block diagram of a multi-source chip compatible system according to one embodiment of the present disclosure, such as Figure 8 As shown, the system includes:

[0144] The chip function analysis module 801 is used to perform function analysis on the original chip to obtain analysis results, wherein the original chip is the main chip in the multi-source chip cluster. The analysis results are used to determine multiple functions of the original chip and the relationships between the multiple functions;

[0145] The replacement chip screening module 802 is used to select a replacement chip that matches the original chip based on the analysis result, wherein the replacement chip is a slave chip to be integrated into the multi-source chip cluster;

[0146] The hardware adaptation module 803 is used to adapt the hardware environment of the target device based on the attribute information of the replacement chip.

[0147] Optionally, the replacement chip screening module 802 is further used to: perform multi-dimensional verification on multiple candidate chips according to the analysis results to obtain verification results, wherein the verification results are used to evaluate whether there are replacement chips that match the original chips among the multiple candidate chips; and select the replacement chip based on the verification results.

[0148] Optionally, the alternative chip screening module 802 is also used to: perform functional testing on multiple candidate chips based on the analysis results to obtain a first test result, wherein the first test result is used to record the test results of the functions of the multiple candidate chips; perform performance testing on multiple candidate chips based on the analysis results to obtain a second test result, wherein the second test result is used to record the performance indicator test results of the multiple candidate chips; perform compatibility testing on multiple candidate chips based on the analysis results to obtain a third test result, wherein the third test result is used to record the compatibility between the multiple candidate chips and the hardware modules configured in the hardware environment; and determine the verification result based on the first test result, the second test result and the third test result.

[0149] Optionally, the replacement chip screening module 802 is further configured to: based on the verification result, select a chip that has passed the multi-dimensional verification from the plurality of candidate chips as a replacement chip.

[0150] Optionally, the multi-source chip compatible system in the embodiment of the present disclosure also includes: a communication module 804, which is used to communicate and interact between the original chip and the peripheral device associated with the target device through a functional interface encapsulation layer, wherein the functional interface encapsulation layer is used to encapsulate the functional interface corresponding to the original chip into a communication interface that complies with a preset communication standard protocol, and the communication interface is used to communicate with the peripheral device.

[0151] Optionally, the communication module 804 is also used to: perform an operating status detection on the original chip to obtain a status detection result; in response to determining that the original chip is in a normal operating state based on the status detection result, generate a target task to be executed based on an external request received from a peripheral device; allocate the target task to the replacement chip through the original chip, so that the replacement chip executes the target task and feeds back the execution result; use the original chip to post-process the execution result to obtain a target processing result; and feed back the target processing result to the peripheral device via the functional interface encapsulation layer.

[0152] Optionally, the communication module 804 is also used to: obtain the chip model of the replacement chip; load the adaptation layer corresponding to the replacement chip based on the chip model, wherein the adaptation layer is encapsulated using a hardware abstraction layer, and the hardware abstraction layer is used to drive the replacement chip into a normal working state after the replacement chip is powered on; and allocate the target task issued by the original chip to the replacement chip through the adaptation layer.

[0153] Optionally, the communication module 804 is also used to: perform an operating status detection on the original chip to obtain a status detection result; in response to determining that the original chip is in an abnormal operating state based on the status detection result, obtain a priority sorting result of the replacement chip, wherein different replacement chips have different priorities; based on the priority sorting result, select a target chip from the replacement chips, and switch the target chip to the main chip, wherein the main chip has the highest priority.

[0154] Optionally, the communication module 804 is also used to: send a heartbeat packet after any chip among the original chip and the replacement chip is powered on, wherein the heartbeat packet is used to notify the remaining chips of the message that the powered-on chip is in normal operating status; and prioritize the multiple chips that have been powered on among the original chip and the replacement chip based on the heartbeat packet to obtain a priority sorting result.

[0155] Optionally, the multi-source chip compatible system in the embodiment of the present disclosure also includes: a detection module 805, which is used to perform workload detection on the original chip and obtain a load detection result; an acquisition module 806, which is used to obtain a priority sorting result of the replacement chip in response to determining that the current workload of the original chip has exceeded a preset load threshold based on the load detection result; and a selection module, which is used to select a target chip from the replacement chips based on the priority sorting result and switch the target chip to the main chip.

[0156] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0157] According to another aspect of an embodiment of the present disclosure, a vehicle is further provided, including: a memory storing an executable program; and a processor for running the program, wherein the multi-source chip compatibility method in the embodiment of the present disclosure is executed when the program is run.

[0158] Optionally, in this embodiment, the processor may be configured to execute the following steps through a computer program:

[0159] S1, performing functional analysis on an original chip to obtain analysis results, wherein the original chip is a master chip in a multi-source chip cluster, and the analysis results are used to determine multiple functions possessed by the original chip and relationships between the multiple functions;

[0160] S2, selecting a replacement chip that matches the original chip based on the analysis results, wherein the replacement chip is a slave chip to be integrated into the multi-source chip cluster;

[0161] S3, based on the attribute information of the replacement chip, adapt the hardware environment of the target device.

[0162] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is further provided. The computer-readable storage medium includes a stored executable program, wherein when the executable program runs, the device where the storage medium is located is controlled to execute the multi-source chip compatibility method in the embodiment of the present disclosure.

[0163] Optionally, in this embodiment, the storage medium may be configured to store a computer program for performing the following steps:

[0164] S1, performing functional analysis on an original chip to obtain analysis results, wherein the original chip is a master chip in a multi-source chip cluster, and the analysis results are used to determine multiple functions possessed by the original chip and relationships between the multiple functions;

[0165] S2, selecting a replacement chip that matches the original chip based on the analysis results, wherein the replacement chip is a slave chip to be integrated into the multi-source chip cluster;

[0166] S3, based on the attribute information of the replacement chip, adapt the hardware environment of the target device.

[0167] Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0168] According to another aspect of the embodiments of the present disclosure, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the multi-source chip compatibility method in the embodiments of the present disclosure is implemented.

[0169] Optionally, in this embodiment, the computer program product may be configured as a computer program for executing the following steps:

[0170] S1, performing functional analysis on an original chip to obtain analysis results, wherein the original chip is a master chip in a multi-source chip cluster, and the analysis results are used to determine multiple functions possessed by the original chip and relationships between the multiple functions;

[0171] S2, selecting a replacement chip that matches the original chip based on the analysis results, wherein the replacement chip is a slave chip to be integrated into the multi-source chip cluster;

[0172] S3, based on the attribute information of the replacement chip, adapt the hardware environment of the target device.

[0173] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0174] In the above embodiments of the present disclosure, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0175] In the several embodiments provided in the present disclosure, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of the units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0176] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0177] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0178] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0179] The above is only a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A multi-source chip compatibility method, characterized in that: include: Performing functional analysis on an original chip to obtain an analysis result, wherein the original chip is a master chip in a multi-source chip cluster, and the analysis result is used to determine multiple functions of the original chip and relationships between the multiple functions; selecting a replacement chip that matches the original chip according to the analysis result, wherein the replacement chip is a slave chip to be integrated into the multi-source chip cluster; Based on the attribute information of the replacement chip, the hardware environment of the target device is adapted.

2. The multi-source chip compatibility method according to claim 1, characterized in that: Selecting the replacement chip that matches the original chip based on the analysis result includes: Performing multi-dimensional verification on a plurality of candidate chips according to the analysis results to obtain verification results, wherein the verification results are used to evaluate whether there is a replacement chip matching the original chip among the plurality of candidate chips; The replacement chip is selected based on the verification result.

3. The multi-source chip compatibility method according to claim 2, characterized in that: Performing multi-dimensional verification on the plurality of candidate chips according to the analysis results, and obtaining the verification results includes: Performing functional tests on the multiple candidate chips respectively according to the analysis results to obtain first test results, wherein the first test results are used to record test results of the functions possessed by the multiple candidate chips; Performing performance tests on the multiple candidate chips respectively according to the analysis results to obtain second test results, wherein the second test results are used to record performance indicator test results of the multiple candidate chips; Performing compatibility tests on the multiple candidate chips respectively according to the analysis results to obtain third test results, wherein the third test results are used to record the compatibility between the multiple candidate chips and the hardware modules configured in the hardware environment; The verification result is determined based on the first test result, the second test result, and the third test result.

4. The multi-source chip compatibility method according to claim 2, characterized in that: Selecting the replacement chip based on the verification result includes: Based on the verification result, a chip that passes the multi-dimensional verification among the plurality of candidate chips is selected as the replacement chip.

5. The multi-source chip compatibility method according to claim 1, characterized in that: The multi-source chip compatibility method further includes: Communication interaction is carried out between the original chip and the peripheral device associated with the target device through a functional interface encapsulation layer, wherein the functional interface encapsulation layer is used to encapsulate the functional interface corresponding to the original chip into a communication interface that complies with a preset communication standard protocol, and the communication interface is used to communicate with the peripheral device.

6. The multi-source chip compatibility method according to claim 5, characterized in that: The multi-source chip compatibility method further includes: Performing an operating status detection on the original chip to obtain a status detection result; In response to determining that the original chip is in a normal operating state according to the status detection result, generating a target task to be executed based on an external request received from the peripheral device; Allocating the target task to the replacement chip through the original chip, so that the replacement chip executes the target task and feeds back the execution result; Post-processing the execution result using the original chip to obtain a target processing result; The target processing result is fed back to the peripheral device via the functional interface encapsulation layer.

7. The multi-source chip compatibility method according to claim 6, characterized in that: Allocating the target task to the replacement chip through the original chip includes: Obtaining the chip model of the replacement chip; Loading an adaptation layer corresponding to the replacement chip based on the chip model, wherein the adaptation layer is encapsulated by a hardware abstraction layer, and the hardware abstraction layer is used to drive the replacement chip into a normal working state after the replacement chip is powered on; The target task issued by the original chip is allocated to the replacement chip through the adaptation layer.

8. The multi-source chip compatibility method according to claim 5, characterized in that: The multi-source chip compatibility method further includes: Performing an operating status detection on the original chip to obtain a status detection result; In response to determining that the original chip is in an abnormal operating state according to the status detection result, obtaining a priority ranking result of the replacement chips, wherein different replacement chips have different priorities; Based on the priority ranking result, a target chip is selected from the alternative chips, and the target chip is switched to the main chip, wherein the main chip has the highest priority.

9. The multi-source chip compatibility method according to claim 8, characterized in that: The multi-source chip compatibility method further includes: After any one of the original chip and the replacement chip is powered on, a heartbeat packet is sent, wherein the heartbeat packet is used to notify the other chips that the powered-on chip is in a normal operating state; Prioritizing the original chip and multiple powered-on chips among the replacement chips based on the heartbeat packet to obtain the priority sorting result.

10. The multi-source chip compatibility method according to claim 1, characterized in that: The multi-source chip compatibility method further includes: Performing a workload test on the original chip to obtain a load test result; In response to determining, based on the load detection result, that the current workload of the original chip has exceeded a preset load threshold, obtaining a priority ranking result of the replacement chip; Based on the priority sorting result, a target chip is selected from the alternative chips, and the target chip is switched to the main chip.

11. A multi-source chip compatible system, characterized in that: include: a chip function analysis module, configured to perform function analysis on an original chip, where the original chip is a master chip in a multi-source chip cluster, and obtain analysis results, wherein the analysis results are used to determine multiple functions possessed by the original chip and the relationships between the multiple functions; a replacement chip screening module, configured to select a replacement chip that matches the original chip based on the analysis result, wherein the replacement chip is a slave chip to be integrated into the multi-source chip cluster; The hardware adaptation module is used to adapt the hardware environment of the target device based on the attribute information of the replacement chip.

12. A vehicle, characterized in that: include: a memory storing an executable program; A processor is configured to run the program, wherein the program, when running, executes the multi-source chip compatibility method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored executable program, wherein when the executable program is run, the device where the storage medium is located is controlled to execute the multi-source chip compatibility method according to any one of claims 1 to 10.

14. A computer program product, characterized in that The invention comprises a computer program, which implements the multi-source chip compatibility method according to any one of claims 1 to 10 when being executed by a processor.

Images