Method, electronic device and medium for automatically generating register verification models

Abstract

The present application relates to the technical field of chip verification, and particularly relates to a method for automatically generating a register verification model, an electronic device and a medium, comprising the following steps: S1, obtaining a register definition file; S2, based on a preset script, analyzing the register definition file, obtaining attribute information corresponding to a register module and attribute information corresponding to each register contained in the register module, and storing the attribute information in a scope of UVM; S3, constructing a corresponding UVM class type declaration by using a preset script; S4, constructing the corresponding UVM class type declaration by using a preset script, and instantiating each register in the UVM class type declaration corresponding to the register module; and S5, generating a register verification model based on the UVM class type declaration corresponding to the register module. The present application improves the efficiency and accuracy of automatically generating a register verification model.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, and particularly relates to a method for automatically generating a register verification model, an electronic device and a medium. BACKGROUND

[0002] In the process of chip verification, the verification of registers is an important part. When verifying registers, the prior art needs to use a universal verification methodology (UVM) to generate a UVM RAL (Register Abstraction Layer) register model in a verification environment by using a UVM RAL library, and to verify the registers in a design under test (DUT) of a chip by using the UVM RAL register model. In the prior art, a vcsralgen tool or a Cadence reg_verifier tool is usually used to automatically generate the UVM RAL register model, but the input of the vcsralgen tool and the Cadence reg_verifier tool must be an Extensible Markup Language (XML) file. Therefore, if the original input file is not an XML file, the original input file needs to be converted into an XML file. In addition, the vcsralgen tool also needs to convert the XML file into a ralf file, and then convert the ralf file into a uvm_ral file. With the continuous increase in the size of a chip, the number of registers in the design under test also increases. Therefore, the vcsralgen tool or the Cadence reg_verifier tool needs to perform a large number of file conversion operations to automatically generate the UVM RAL register model, and the efficiency of automatically generating the register verification model is low and prone to errors. Therefore, how to improve the efficiency and accuracy of automatically generating the register verification model becomes a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a method for automatically generating a register verification model, an electronic device and a medium, which improves the efficiency and accuracy of automatically generating the register verification model.

[0004] According to a first aspect of the present application, a method for automatically generating a register verification model is provided, comprising:

[0005] In step S1, a register definition file is obtained, the register definition file is a json format file, and the register definition file includes attribute information corresponding to a register module and attribute information corresponding to each register contained in the register module.

[0006] In step S2, the register definition file is parsed based on a preset script to obtain attribute information of the register module and attribute information of each register included in the register module, and the attribute information is stored in a scope of UVM.

[0007] In step S3, a corresponding UVM class type declaration is constructed based on the attribute information of each register included in the register module by using a preset script.

[0008] In step S4, a corresponding UVM class type declaration is constructed based on the attribute information of the register module by using a preset script, and each register is instantiated in the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to each register included in the register module.

[0009] In step S5, a register verification model is generated based on the UVM class type declaration corresponding to the register module.

[0010] According to a second aspect of the present application, an electronic device is provided, comprising at least one processor, and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method according to the first aspect of the present application.

[0011] According to a third aspect of the present application, a computer readable storage medium is provided, which stores computer executable instructions, and the computer executable instructions are configured to execute the method according to the first aspect of the present application.

[0012] Compared with the prior art, the method, the electronic device and the medium for automatically generating a register verification model provided by the present application have obvious advantages and beneficial effects. The method, the electronic device and the medium for automatically generating a register verification model provided by the present application can achieve considerable technical progress and practicability, and have wide industrial utilization value. At least the following beneficial effects are achieved:

[0013] The preset script is used to process the register definition file in json format, and the register verification model can be generated without other file type conversion in the middle, so that the file conversion operation in the generation process of the register verification model is reduced, and the efficiency of automatically generating the register verification model is improved. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without creative labor.

[0015] Figure 1 The method flow chart for automatically generating a register verification model provided by the embodiments of the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0017] The embodiments of the present application provide a method for automatically generating a register verification model, as shown in Figure 1 , which comprises the following steps.

[0018] Step S1, a register definition file is obtained, the register definition file is a file in json format, and the register definition file includes attribute information corresponding to a register module and attribute information corresponding to each register contained in the register module.

[0019] The register module includes at least one register.

[0020] Step S2, based on a preset script, the register definition file is parsed to obtain the attribute information corresponding to the register module and the attribute information corresponding to each register contained in the register module and store them in the scope of UVM.

[0021] It should be noted that in step S2, the attribute information corresponding to the register module can be obtained first, and then the attribute information corresponding to each register contained in the register module is obtained for X times, respectively, and X is the number of registers contained in the register module.

[0022] The preset script can be a perl script, a python script, or the like. Preferably, the preset script is a python script, because the python script has a parse json module that can be directly called to parse the register definition file. The attribute information of the register module and the attribute information of each register included in the register module are stored in the scope of UVM, so as to facilitate the generation of the register verification model and the acquisition of information required in the verification process.

[0023] As an embodiment, the attribute information of the register module and the attribute information of each register included in the register module can be stored in the preset cache area in the form of an associative array.

[0024] Step S3: A preset script is used to construct a corresponding UVM class type declaration based on the attribute information of each register included in the register module.

[0025] It should be noted that, in step S3, a general UVM code architecture corresponding to the register verification model can be constructed in advance, the attribute information of the register is set as a to-be-filled field, the preset script is used to read the attribute information of each register included in the register module from the scope of UVM, and the attribute information is filled into the general UVM code architecture corresponding to the register verification model, so as to generate the UVM class type declaration corresponding to each register included in the register module. Step S3 needs to be executed X times in a loop to establish the UVM class type declaration corresponding to each register included in the register module.

[0026] Step S4: A preset script is used to construct a corresponding UVM class type declaration based on the attribute information of the register module, and each register is instantiated in the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to each register included in the register module.

[0027] It should be noted that, in step S4, a general UVM code architecture corresponding to the register module can be constructed in advance, the attribute information of the register module is set as a to-be-filled field, the preset script is used to read the attribute information of the register module from the scope of UVM, and the attribute information is filled into the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to each register included in the register module, so as to instantiate each register in the UVM class type declaration corresponding to the register module.

[0028] Step S5: A register verification model is generated based on the UVM class type declaration corresponding to the register module.

[0029] It should be noted that the register verification model is generated based on the UVM class type declaration corresponding to the register module, and the register verification model includes all registers in the register module. The embodiment of the present application can directly generate the register verification model based on the json format file, without conversion to the XML file, and without conversion of other file types, thereby improving the generation efficiency and accuracy of the register verification model.

[0030] As an embodiment, the step S1 comprises:

[0031] Step S11, extracting register module attribute information and register attribute information from design text information corresponding to the design under test.

[0032] Step S12, storing the register module attribute information and the register attribute information in the json to generate the register definition file, and the register module in the register definition file contains the register attribute information nested in the register module attribute information.

[0033] As an embodiment, the attribute information corresponding to the register module includes path information, constraint information, and function coverage information, and the attribute information corresponding to the register includes path information, constraint information, function coverage information, register group type, and register group depth. If the register does not have a corresponding register group, the register group type and the register group depth are set to empty.

[0034] The constraint information corresponding to the register is used to generate a random test stimulus of the register, and the constraint information corresponding to the register module is used to generate a random test stimulus of the register based on the constraint relationship between different registers included in the register module. The function coverage information corresponding to the register is used to set the function coverage point and the cross function coverage point information corresponding to the register, and the function coverage information corresponding to the register module is used to set the function coverage point and the cross function coverage point information between different registers included in the register module.

[0035] As an embodiment, the attribute information corresponding to the register module further includes the register module name corresponding to the register module, address mapping information, reset information, address width, data width, access attribute, etc. The attribute information corresponding to the register further includes register description information corresponding to the register, address mapping information, access attribute, data width, address offset, reset information, etc. The above attribute information can be extracted from the design text information corresponding to the design under test, and the fields in the register definition file can be added or deleted according to specific application requirements.

[0036] As an embodiment, the step S3 comprises:

[0037] Step S31, whether to enable backdoor access is configured for each register through the command line parameter configured in the preset script, if the register is configured to enable backdoor access, step S32 is executed.

[0038] Step S33, the path information corresponding to the register module and the path information corresponding to the register are spliced to generate the backdoor access path corresponding to the register.

[0039] Step S34, the backdoor access declaration is set in the UVM class type declaration corresponding to the register based on the backdoor access path corresponding to the register.

[0040] It should be noted that the backdoor access is used in the simulation verification process. In the prior art, if the backdoor access is involved, the verification engineer needs to manually write the path corresponding to each backdoor access, which is low in efficiency, easy to make mistakes and high in maintenance cost. In the embodiment of the present application, after the register definition file is set, the design and verification are executed based on the register definition file, that is, the design and verification are based on the same source information, so the hierarchy and name of the same register corresponding to the design and verification are consistent. The present application sets the corresponding path information in the attribute information of the register module and each register, and automatically splices the path information corresponding to the register module and the path information corresponding to the register through the preset script, so that the backdoor access path corresponding to each register can be obtained without manual writing by the verification engineer, which is high in efficiency and not easy to make mistakes.

[0041] As an embodiment, the step S3 comprises:

[0042] Step C31, whether the register module supports factory override is configured through the command line parameter configured in the preset script, if it supports, the factory registration is executed in the UVM class type declaration corresponding to each register contained in the register module, if it does not support, the factory registration does not need to be executed in the UVM class type declaration corresponding to each register contained in the register module.

[0043] It should be noted that the register verification does not need factory override function in many cases, whether the register module supports factory override is flexibly configured through the command line parameter configured in the preset script, the factory override function can be closed, so that the system performance and the construction speed of the register verification model can be greatly improved.

[0044] Step C32, the constraint information corresponding to the register is set in the UVM class type declaration corresponding to the register.

[0045] Step C33, set the register corresponding function coverage information in the register corresponding UVM class type declaration.

[0046] It should be noted that in the prior art, the constrained random verification of the register and the acquisition of the function coverage are set based on the understanding of the design intention of the design architecture by the verification engineer, but the understanding of the verification engineer is not necessarily accurate, there may be information barriers, and the workload is very large. The embodiments of the present application directly set the constraint information and the function coverage information corresponding to the register in the register definition file, and then set the constraint information and the function coverage information in the register corresponding UVM class type declaration, and then set the constraint information and the function coverage information in the register verification model in the process of generating the register verification model.

[0047] As an embodiment, the step S4 comprises:

[0048] Step S41, adding the attribute information corresponding to the register module in the UVM class type declaration corresponding to the register module by using a preset script.

[0049] It should be noted that the constraint information, the function coverage point and the cross function coverage point information between different registers included in the register module are also added to the UVM class type declaration corresponding to the register module as attribute information in step S41.

[0050] Step S42, if the register does not exist corresponding register group, adding the corresponding register instance in the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to the register.

[0051] Step S43, if the register exists corresponding register group, adding the corresponding register array instance in the UVM class type declaration corresponding to the register module based on the register group type, the register group depth and the UVM class type declaration corresponding to the register.

[0052] As an embodiment, after the step S5 generates the register verification model, if it is required to perform the random verification with constraints on a register, it is first judged whether the constraint information corresponding to the register exists in the register module, if yes, it is indicated that the register is associated with other registers when the random test excitation with constraints is generated, therefore, the random test excitation corresponding to the register is generated based on the constraint information corresponding to the register in the register module and the constraint information corresponding to the register in the register to realize the random verification with constraints on the register. If the constraint information corresponding to the register does not exist in the register module, the random test excitation corresponding to the register is generated based on only the constraint information corresponding to the register in the register to realize the random verification with constraints on the register.

[0053] As an embodiment, after the step S5 generates the register verification model, if it is required to obtain the function coverage of a register, it is first judged whether the function coverage information corresponding to the register exists in the register module, if yes, it is indicated that the register is associated with other registers when the function coverage is obtained, therefore, the function coverage corresponding to the register is obtained based on the function coverage information corresponding to the register in the register module and the function coverage information corresponding to the register in the register. If the function coverage information corresponding to the register does not exist in the register module, the function coverage corresponding to the register is obtained based on only the function coverage information corresponding to the register in the register.

[0054] It is noted that some example embodiments are described as processes or methods depicted as flow diagrams. Although the processes are described in a particular sequential order, many of the steps can be performed in parallel, concurrently or in any suitable order. In addition, the order of the steps can be re-arranged. The processes can be terminated when their operations are completed, but can also have additional steps not included in the figure, which can also be performed after the operations of the processes are completed. The processes can correspond in part to method steps for implementing the methods.

[0055] The embodiment of the present application further provides an electronic device, including: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are arranged to execute the method provided by the embodiment of the present application.

[0056] The embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used for executing the method provided by the embodiment of the present application.

[0057] The embodiment of the present application adopts the preset script to process the register definition file in the json format, and the register verification model can be generated without other file type conversion in the middle, so that the file conversion operation in the register verification model generation process is reduced, and the efficiency of automatically generating the register verification model is improved.

[0058] The above merely describes the preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical contents to obtain equivalent embodiments with equivalent changes, without departing from the technical solution of the present application. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A method of automatically generating a register verification model, the method comprising: The method comprises the following steps: S1, obtaining a register definition file, the register definition file being a json format file, the register definition file comprising attribute information of a register module and attribute information of each register included in the register module; S2, parsing the register definition file based on a preset script, obtaining the attribute information of the register module and the attribute information of each register included in the register module and storing them in a scope of UVM; S3, constructing a corresponding UVM class type declaration based on the attribute information of each register included in the register module by using a preset script; S4, constructing a corresponding UVM class type declaration based on the attribute information of the register module, and instantiating each register in the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to each register included in the register module; S5, generating a register verification model based on the UVM class type declaration corresponding to the register module.

2. The method of claim 1, wherein the step S1 comprises: S11, extracting register module attribute information and register attribute information from design text information corresponding to a design under test; S12, generating the register definition file by storing the register module attribute information and the register attribute information by using json, the register attribute information included in the register module in the register definition file being nested in the register module attribute information.

3. The method of claim 1, wherein the attribute information of the register module comprises path information, constraint information and function coverage information, the attribute information of the register comprises path information, constraint information, function coverage information, register group type and register group depth, and the register group type and the register group depth are set to be empty if the register does not have a corresponding register group; the constraint information of the register is used to generate a random test stimulus of the register, and the constraint information of the register module is used to generate a random test stimulus of the register based on constraint relationships between different registers included in the register module; the function coverage information of the register is used to set function coverage points and cross function coverage points information of the register, and the function coverage information of the register module is used to set function coverage points and cross function coverage points information between different registers included in the register module.

4. The method of claim 1, wherein in the step S2, the preset script is a python script.

5. The method of claim 1, wherein in the step S2, the attribute information of the register module and the attribute information of each register included in the register module are stored in a preset cache area in the form of an associative array.

6. The method of claim 3, wherein the step S3 comprises: ​ ​ ​ ​ ​ Step S31, configuring whether each register enables backdoor access through a preset command line parameter in the preset script, and if the register configuration enables backdoor access, performing step S32; Step S32, splicing the path information corresponding to the register module and the path information corresponding to the register to generate a backdoor access path corresponding to the register; Step S33, setting a backdoor access declaration in a UVM class type declaration corresponding to the register based on the backdoor access path corresponding to the register.

7. The method of claim 3, wherein the step S3 comprises: Step C31, configuring whether the register module supports factory override through a preset command line parameter in the preset script, and if it supports, performing factory registration in a UVM class type declaration corresponding to each register included in the register module; Step C32, setting constraint information corresponding to the register in the UVM class type declaration corresponding to the register; Step C33, setting function override information corresponding to the register in the UVM class type declaration corresponding to the register.

8. The method of claim 3, wherein the step S4 comprises: Step S41, adding attribute information corresponding to the register module in the UVM class type declaration corresponding to the register module using a preset script; Step S42, if the register does not exist a corresponding register group, adding a corresponding register instance in the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to the register; Step S43, if the register exists a corresponding register group, adding a corresponding register array instance in the UVM class type declaration corresponding to the register module based on the register group type, the register group depth, and the UVM class type declaration corresponding to the register. comprises: at least one processor; 9. An electronic device, comprising: and a memory connected in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method of any one of the preceding claims 1-8. computer executable instructions for performing the method of any one of the preceding claims 1-8. ​ 10. A computer-readable storage medium, characterized in that, ​

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