Pixel driving circuit and display panel

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a pixel driving circuit and a display panel, the input end of the pixel driving circuit is connected with a data line, and the pixel driving circuit is used for receiving current data voltage transmitted on the data line. The current data voltage is output to a target pixel unit according to a preset range where the current data voltage is located, so that the target pixel unit is charged by the current data voltage; two pixel units or three pixel units are connected to the same data line through the pixel driving circuit, and the pixel unit which is currently charged is distinguished through the voltage range of the current data voltage on the data line, so that the pixel unit which is currently charged is obtained on the basis of not increasing scanning lines. The problem of wrong charging of a plurality of pixel units connected to the same data line is avoided; therefore, the problem that the number of the scanning lines is not increased while the number of the source electrode driving chips is reduced is solved.

Description

Technical Field

[0001] The present disclosure belongs to the field of display driving technology, and particularly relates to a pixel driving circuit and a display panel. Background Art

[0002] In display panel pixel drive architectures, triple-gate (TRD) and double-gate (DRD-gate) drive technologies are commonly used for triple-rate and double-rate drive, respectively. Both optimize the driving speed of source driver ICs to reduce the number of chips, thereby lowering display panel costs. Their core principle is to enable one data channel to drive two or three sub-pixels through time-division multiplexing.

[0003] However, although TRD and DRD technologies reduce the number of source driver chips, the number of scan lines in the display panel increases to 3 times (TRD) or 2 times (DRD) of the traditional architecture, resulting in problems such as high power consumption, low aperture ratio and limited high resolution of the display panel.

[0004] Therefore, how to reduce the number of source driver chips without increasing the number of scan lines is an urgent problem to be solved. Summary of the Invention

[0005] The present application provides a pixel driving circuit and a display panel, which solve the problem of reducing the number of source driver chips without increasing the number of scan lines.

[0006] In a first aspect, the present application provides a pixel driving circuit, which is applied to a display panel, wherein the display panel includes a scan line, a data line, a first pixel unit, a second pixel unit and a third pixel unit; the input end of the pixel driving circuit is connected to the data line, and the output end of the pixel driving circuit is connected to the input end of the first pixel unit, the second pixel unit or / and the third pixel unit, for receiving a current data voltage transmitted on the data line, and outputting the current data voltage to a target pixel unit according to a preset range of the current data voltage, so that the current data voltage charges the target pixel unit; wherein the target pixel unit is one of the first pixel unit, the second pixel unit and the third pixel unit; the first pixel unit, the second pixel unit and the third pixel unit are charged in a preset order.

[0007] In a second aspect, the present application provides a display panel, comprising N rows of scan lines and M columns of pixel columns for progressive scanning, wherein the pixel columns comprise: one data line and N rows of pixel circuits; one end of the data line is connected to a source driver chip, and each row of pixel circuits comprises a first pixel unit, a second pixel unit, a third pixel unit, and the pixel driver circuit according to claim 2; Alternatively, the pixel column includes three columns of data lines, N rows of pixel circuits, and the pixel driving circuit according to claim 3; each row of pixel circuits includes a first pixel unit, a second pixel unit, and a third pixel unit; an input end of the pixel driving circuit is connected to a source driver chip, and an output end of the pixel driving circuit is connected to the three columns of data lines, respectively; Alternatively, the pixel column comprises: 1 column of data lines and N rows of pixel circuits; one end of the data line is connected to a source driver chip, and each row of pixel circuits comprises a first pixel unit, a second pixel unit, and the pixel driver circuit according to claim 2, or a first pixel unit, a third pixel unit, and the pixel driver circuit according to claim 2, and a second pixel unit, a third pixel unit, and the pixel driver circuit according to claim 2; Or, the pixel column includes 2 columns of data lines, N rows of pixel circuits and the pixel driving circuit according to claim 3; each row of pixel circuits includes a first pixel unit and a second pixel unit, a first pixel unit or a third pixel unit, or a second pixel unit and a third pixel unit; the input end of the pixel driving circuit is connected to the source driver chip, and the output end of the pixel driving circuit is respectively connected to the 2 columns of data lines.

[0008] The technical solution provided by this application has at least the following beneficial effects: The present application connects two or three pixel units to the same data line through a pixel driving circuit, and distinguishes the pixel unit that is currently charged according to the voltage range of the current data voltage on the data line, thereby ensuring that multiple pixel units connected to the same data line will not be mischarged without increasing the number of scan lines; therefore, the present application solves the problem of reducing the number of source driver chips without increasing the number of scan lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0010] Figure 1 FIG. 1 is a schematic diagram of a pixel circuit in related art.

[0011] Figure 2 FIG. 1 is a schematic structural diagram of a first pixel driving circuit provided in an embodiment of the present application.

[0012] Figure 3 FIG. 1 is a schematic structural diagram of a second pixel driving circuit provided in an embodiment of the present application.

[0013] Figure 4 FIG. 1 is a schematic structural diagram of a third pixel driving circuit provided in an embodiment of the present application.

[0014] Figure 5 FIG. 1 is a schematic structural diagram of a fourth pixel driving circuit provided in an embodiment of the present application.

[0015] Figure 6 FIG2 is a circuit diagram of a first pixel driving circuit provided in an embodiment of the present application.

[0016] Figure 7 FIG. 1 is a schematic structural diagram of a fifth pixel driving circuit provided in an embodiment of the present application.

[0017] Figure 8 FIG2 is a circuit diagram of a second pixel driving circuit provided in an embodiment of the present application.

[0018] Figure 9 Shown is a schematic structural diagram of a first display panel provided in an embodiment of the present application.

[0019] Figure 10 Shown is a schematic structural diagram of a second display panel provided in an embodiment of the present application.

[0020] Figure 11 Shown is a schematic structural diagram of a third display panel provided in an embodiment of the present application.

[0021] Figure 12 Shown is a schematic structural diagram of a fourth display panel provided in an embodiment of the present application.

[0022] Description of reference numerals: 10. Display panel; 11. Pixel columns; 100, pixel driving circuit; 200, scan line; 300, data line; 400, first pixel unit; 500, second pixel unit; 600, third pixel unit; 110, main control unit; 120, first control unit; 130, second control unit; 140, third control unit; Q0, control transistor; T0, drive transistor; C0, storage capacitor; OLED, light-emitting diode; T1, first switch tube; T2, second switch tube; T3, third switch tube; T4, fourth switch tube; T5, fifth switch tube; T6, sixth switch tube; T7, seventh switch tube; T8, eighth switch tube; C1, first capacitor; C2, second capacitor; D1, first diode; D2, second diode; D3, third diode; D4, fourth diode. DETAILED DESCRIPTION

[0023] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0024] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0025] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0026] In the pixel drive architecture of display panels like LCDs (Liquid Crystal Displays) and OLEDs (Organic Light-Emitting Diodes), TRD technology triples the drive speed of source driver chips, allowing a single driver chip to perform the tasks of three chips in traditional technology. Specifically, in traditional designs, each subpixel requires an independent driver channel; TRD, however, enables a single channel to drive three subpixels simultaneously. For example, for a 1024×600 resolution panel, traditional drivers require 3072 channels (corresponding to the RGB subpixels), while TRD requires only 1024 channels, achieving efficient drive through time-division multiplexing.

[0027] DRD technology doubles the driving speed of the source driver chip, allowing a single driver chip to perform the tasks of two chips in traditional technology. Specifically, in traditional designs, each subpixel requires a separate driver channel; DRD, however, enables a single channel to drive two subpixels simultaneously. For example, for a 1024×600 resolution panel, a traditional driver requires 3072 channels (corresponding to the three RGB subpixels), while DRD requires only 1536 channels, achieving efficient driving through time-division multiplexing.

[0028] The main advantages of TRD and DRD architectures are: 1. Cost reduction: The reduction of source driver chips (hereinafter referred to as ICs), COFs, and PCB components directly reduces material costs. For example, at the same resolution, the traditional 1G1D architecture requires 6 ICs, the TRD architecture requires only 2 ICs, and the DRD architecture requires only 3 ICs.

[0029] 2. Improve performance: Increased light transmittance can enhance display brightness and energy efficiency, while time-sharing drive reduces signal interference and improves picture quality.

[0030] The main disadvantages of TRD and DRD architectures are: 1. Limited support for high resolution: This technology reduces the number of source driver chips by sharing data lines, but the number of scan lines in the display panel becomes three times (TRD) or two times (DRD) of the traditional architecture (i.e., 1G1D architecture). The driving speed and the exponentially increased number of scan lines make it difficult to meet the requirements for signal transmission accuracy and stability at high pixel density. Therefore, it cannot be applied in scenarios with resolutions of 8K and above.

[0031] 2. Decreased transmittance: The multiplied scan lines occupy the pixel opening area, resulting in a decrease in transmittance (for example, the DRD opening rate is 15% lower than that of the traditional Single Gate).

[0032] 3. High power consumption: The doubled scan line routing leads to a large RC loading (resistance and capacitance loading effect), resulting in high power consumption and noise interference problems on the panel.

[0033] 4. Signal crosstalk: The multiplied scan lines lead to wiring congestion and signal crosstalk risks.

[0034] 5. Signal delay: Doubled scan lines can easily introduce signal delay.

[0035] 6. Poor scalability: TRD and DRD architectures require redesign of transistor control circuits and sub-pixel arrangements, and the resulting process complexity leads to poor scalability and compatibility.

[0036] In order to solve the above problems, the present application provides a pixel driving circuit, which specifically includes the following embodiments: The pixel driving circuit provided in this application is applied to a display panel, which includes multiple scan lines, multiple data lines, and a first pixel unit, a second pixel unit, and a third pixel unit arranged in an array. The display panel can be an LCD display or an OLED display. When the display panel is an LCD display, each pixel unit includes a liquid crystal molecule; when the display panel is an OLED display, each pixel unit includes a light-emitting diode. The first pixel unit, the second pixel unit, and the third pixel unit are respectively a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B). Because the pixel driving circuit of this application has the same operating principle when applied to LCD displays and OLED displays, OLED will be used as an example to illustrate the relevant principles below.

[0037] In this embodiment, the input end of the pixel driving circuit is connected to the data line, and the output end of the pixel driving circuit is connected to the input end of the first pixel unit, the second pixel unit or / and the third pixel unit, for receiving the current data voltage transmitted on the data line, and outputting the current data voltage to the target pixel unit according to a preset range of the current data voltage, so that the current data voltage charges the target pixel unit; wherein the target pixel unit is one of the first pixel unit, the second pixel unit and the third pixel unit, and the first pixel unit, the second pixel unit and the third pixel unit are charged in a preset order.

[0038] It should be noted that the pixel driving circuit of this embodiment includes multiple output terminals, which can be connected to the first pixel unit and the second pixel unit at the same time, or to the first pixel unit and the third pixel unit at the same time, or to the second pixel unit and the third pixel unit at the same time, or to the first pixel unit, the second pixel unit, and the third pixel unit at the same time. The pixel driving circuit receives the current data voltage currently transmitted on the data line and determines the corresponding target pixel unit based on the voltage range of the current data voltage, so that the current data voltage charges one pixel unit among the first pixel unit, the second pixel unit, and the third pixel unit. In other words, the present application uses the pixel driving circuit to allow two or three pixel units to share a data line, and the pixel driving circuit distinguishes the corresponding pixel units based on the voltage range of the data voltage on the data line, thereby avoiding the problem of incorrect charging.

[0039] In addition, the first pixel unit, the second pixel unit and the third pixel unit of this embodiment are charged in a preset order, wherein the preset order can be that the first pixel unit is charged first, then the second pixel unit is charged, and finally the third sub-pixel is charged; the preset order can also be that the first sub-pixel is charged first, then the third pixel unit is charged, and finally the second sub-pixel is charged; charging in a preset order is mainly reflected in the different order of data voltages output by the source driver chip to the data line.

[0040] The principle of setting up the pixel driving circuit in this application is that: under normal circumstances, the electrical characteristics and luminous efficiency of different color luminescent materials are different, which leads to differences in the grayscale data driving voltage (i.e., data voltage) range of RGB sub-pixels. Specifically, the blue sub-pixel (B) has a higher data voltage requirement, the red sub-pixel (R) has a lower voltage requirement, and the green sub-pixel (G) has a moderate voltage requirement. Taking the conventional 2T1C (two transistors and one capacitor) OLED pixel driving circuit as an example, Figure 1 As shown, Figure 1 The control transistor Q0 and the driving transistor T0 are P-type transistors. The driving current output by the driving transistor T0 can drive the light-emitting diode to emit light. The specific formula of the driving current is:

[0041] in, is the carrier mobility of the driving transistor, Represents the capacitance density of the gate layer, in units of , can be calculated from the dielectric constant and thickness of the gate oxide layer, Represents the channel width of the driver transistor in units of , Represents the channel length of the driver transistor in units of ; driving transistor Directly related to the mobility and size of the transistor; represents the gate-source voltage driving the crystal, Threshold voltage of the driver transistor.

[0042] From the above formula, we can know that the driving current I OLED The size of the LED determines the brightness of the LED, and the driving current I OLED The size is determined by the gate-source voltage V GS Adjustment, commonly used voltage range is: (1) Gate-source voltage V of the driving transistor GS =Data voltage V DATA -Power supply voltage V DD ; Among them, the V of the red sub-pixel (R) GSIt can be (-4~-2)V, the V of the green sub-pixel (G) GS It can be (-4.5~-2.5)V, and the V of the blue sub-pixel (B) GS It can be (-5~-3)V.

[0043] (2) Power supply voltage V DD Can be unified to 5V, cathode voltage V SS Can be unified to 0V.

[0044] (3) It can be deduced that in the related art, the V of the red sub-pixel (R) is DATA It can be (1.0-3.0)V, the V of the green sub-pixel (G) DATA (0.5-2.5)V, V of the blue sub-pixel (B) DATA It can be (0-2.0)V.

[0045] It can be seen from this that the core of this application lies in not using a unified driving voltage and cathode voltage, while satisfying the required gate-source voltage range of each pixel unit. Instead, the data voltage ranges of the three sub-pixels are adjusted so that the data voltage ranges of the first pixel unit, the second pixel unit, and the third pixel unit are staggered. This allows the pixel driving circuit to identify that different current data voltages correspond to different pixel units. For example, in this embodiment, the data voltage range corresponding to the first pixel unit (red sub-pixel) can be (6.0-8.0) V, the data voltage range corresponding to the second pixel unit (blue sub-pixel) can be (3.0-5.0) V, and the data voltage range corresponding to the third pixel unit (green sub-pixel) can be (0.5-2.5) V.

[0046] It can be seen from this that the present application connects two pixel units or three pixel units to the same data line through a pixel driving circuit, and distinguishes the pixel unit that is currently being charged through the voltage range of the current data voltage on the data line, thereby ensuring that multiple pixel units connected to the same data line will not be mischarged without increasing the number of scan lines; therefore, the present application solves the problem of reducing the number of source driver chips without increasing the number of scan lines.

[0047] Figure 2 FIG. 1 is a schematic structural diagram of a first pixel driving circuit provided in an embodiment of the present application; FIG. Figure 2 As shown, the pixel driving circuit 100 of this embodiment includes a master control unit 110 , a first control unit 120 , a second control unit 130 and a third control unit 140 .

[0048] Specifically, the control end of the main control unit 110 is connected to the scan line 200, and the input end of the main control unit 110 is connected to the data line 300, and is used to output the current data voltage on the data line 300 when the gate drive signal on the scan line 200 is in the on state; the input end of the first control unit 120 is connected to the output end of the main control unit 110, and the first output end of the first control unit 120 is connected to the input end of the first pixel unit 400, and is used to output the current data voltage to the first pixel unit 400 when the current data voltage is in a first preset range, and output a trigger signal after the first pixel unit 400 is charged; the control end of the second control unit 130 is connected to the second output end of the first control unit 120, and the input end of the second control unit 130 is connected to the The output end is connected, the first output end of the second control unit 130 is connected to the input end of the second pixel unit 500, and is used for outputting the current data voltage to the second pixel unit 500 when the current data voltage is in the second preset range and receives the trigger signal output by the first control unit 120, and outputting the trigger signal after the second pixel unit 500 is charged; the control end of the third control unit 140 is connected to the second output end of the second control unit 130, the input end of the third control unit 140 is connected to the output end of the main control unit 110, and the output end of the third control unit 140 is connected to the input end of the third pixel unit 600, and is used for outputting the current data voltage to the third pixel unit 600 when the current data voltage is in the third preset range and receives the trigger signal output by the second control unit 130.

[0049] It should be noted that, in this embodiment, the first preset range, the second preset range, and the third preset range are staggered, that is, there is no numerical overlap. The working principle of the pixel driving circuit 100 of this embodiment is as follows: (1) When the gate driving signal is output on the scan line 200 , the master control unit 110 is in the on state, receives the current data voltage output on the data line 300 , and directly outputs the current data voltage as a signal.

[0050] (2) The first control unit 120 receives the current data voltage output by the main control unit 110 and determines whether the current data voltage is within a first preset range (e.g., 6.0-8.0 V). If the current data voltage is not within the first preset range, the first control unit 120 does not output any signal. If the current data voltage is within the first preset range, the first control unit 120 outputs the current data voltage to the first pixel unit 400, so that the current data voltage charges the first pixel unit 400. When the first pixel unit 400 is fully charged, the first control unit 120 also outputs a trigger signal through the second output terminal.

[0051] (3) The second control unit 130 also receives the current data voltage output by the main control unit 110 and determines whether the current data voltage is within the second preset range (e.g., 3.0-5.0V). If the current data voltage is not within the second preset range, the second control unit 130 does not output any signal. If the current data voltage is within the second preset range and the second control unit 130 receives the trigger signal output by the first control unit 120, the second control unit 130 outputs the current data voltage so that the current data voltage charges the second pixel unit 500. When the second pixel unit 500 is fully charged, the second control unit 130 further outputs a trigger signal through the second output terminal.

[0052] (4) The third control unit 140 also receives the current data voltage output by the main control unit 110 and determines whether the current data voltage is within a third preset range (e.g., 0.5-2.5 V). If the current data voltage is not within the third preset range, the third control unit 140 does not output any signal. If the current data voltage is within the third preset range and the third control unit 140 receives the trigger signal output by the second control unit 130, the third control unit 140 outputs the current data voltage.

[0053] It can be seen that this embodiment connects three pixel units to the same data line 300 and the same scan line 200 through the pixel driving circuit 100, so that a single data channel of the source driver chip can drive three sub-pixels at the same time, and the driving rate can be increased by three times. It can be applied to a conventional TRD structure to achieve the purpose of reducing the number of scan lines 200 of the conventional TRD structure.

[0054] Figure 3 FIG. 1 is a schematic structural diagram of a second pixel driving circuit provided in an embodiment of the present application. Figure 4 FIG. 1 is a schematic structural diagram of a third pixel driving circuit provided in an embodiment of the present application. Figure 5 FIG. 1 is a structural diagram of a fourth pixel driving circuit provided in an embodiment of the present application; wherein, Figure 3 、 Figure 4 and Figure 5 The pixel driving circuit 100 shown is Figure 2 The difference is: one less output terminal (i.e. one less corresponding control unit), Figure 2 The pixel driving circuit 100 includes three output terminals, which can be connected to three different pixel units at the same time; Figure 3 、 Figure 4 and Figure 5 The pixel driving circuit 100 shown includes two output terminals, each connected to two different pixel units.

[0055] Specifically, Figure 3 The pixel driving unit includes a master control unit 110, a first control unit 120 and a second control unit 130; Figure 4 The pixel driving circuit 100 includes a main control unit 110, a first control unit 120 and a third control unit 140; Figure 5 The pixel driving circuit 100 includes a main control unit 110, a second control unit 130 and a third control unit 140. It should be noted that, Figure 3 、 Figure 4 and Figure 5 The specific working principles of the master control unit 110, the first control unit 120 and the second control unit 130 are the same as those of the Figure 2 The same, no longer repeated here.

[0056] It can be seen that in this embodiment, two pixel units are connected to the same data line 300 and the same scan line 200 through the pixel driving circuit 100, so that a single channel of the source driving signal can drive two sub-pixels at the same time, and the driving rate can be increased by two times. Figure 3 、 Figure 4 and Figure 5 The pixel driving circuit 100 shown is also applied in a conventional DRD structure to achieve the purpose of reducing the number of scan lines 200 in the conventional DRD structure.

[0057] Figure 6 FIG. 1 is a circuit diagram of a first pixel driving circuit provided in an embodiment of the present application; FIG. Figure 6 As shown, the main control unit 110 includes: a first switch tube T1, the control end of the first switch tube T1 is connected to the scan line 200, the first end of the first switch tube T1 serves as the input end of the main control unit 110, and the second end of the first switch tube T1 serves as the output end of the main control unit 110.

[0058] It should be noted that the first switch tube T1 can be a P-type MOS tube or an N-type MOS tube. In this embodiment, the first switch tube T1 is an N-type MOS tube as an example. When a high-level gate drive signal is output on the scan line 200, the first switch tube T1 is turned on, thereby outputting the data voltage received through the first end from the second end.

[0059] like Figure 6As shown, the first control unit 120 includes: a second switching transistor T2, a third switching transistor T3, a first diode, a first capacitor, and a second diode; specifically, the control terminal of the second switching transistor T2 is connected to the first power supply terminal, and the first terminal of the second switching transistor T2 is connected as the input terminal of the first control unit 400; the control terminal of the third switching transistor T3 is connected to the second terminal of the second switching transistor T2, and the first terminal of the third switching transistor T3 is used as the second output terminal of the first control unit 400; the anode of the first diode D1 is connected to the control terminal of the third switching transistor T3, and the cathode of the first diode D1 is connected to the second terminal of the third switching transistor T3; the first terminal of the first capacitor C1 is connected to the second terminal of the third switching transistor T3, and the second terminal of the first capacitor C2 is grounded; the anode of the second diode D2 is connected to the cathode of the first diode D1, and the cathode of the second diode D2 is used as the first output terminal of the first control unit 400.

[0060] It should be noted that the second switching transistor T2 and the third switching transistor T3 can be P-type MOS transistors or N-type MOS transistors; the first power supply terminal VCC1 can be a voltage output terminal that outputs any voltage value; in this embodiment, taking the second switching transistor T2 and the third switching transistor T3 as P-type MOS transistors, the first power supply terminal VCC1 outputs a 5V voltage, and the threshold voltage of the second switching transistor T2 is -1V as an example, the working principle of the first control unit will be elaborated as follows: 1. Explanation of the off and on states of the P-type MOS transistor: When the gate-source voltage Vgs (Vg - Vs) ≥ the threshold voltage V th (the V th of the P-type MOS transistor is a negative value, usually between -0.4V and -1V or lower), strong inversion does not occur on the surface of the N-type substrate under the gate. No conductive channel is formed, and a high impedance state is presented between the source and the drain, that is, it is off. When the gate-source voltage Vgs is lower than the threshold voltage Vth (i.e., Vgs < Vth), the negative voltage on the gate (relative to the source) repels the free electrons in the N-type substrate and at the same time attracts the holes in the substrate to the surface area under the gate. When Vgs is negative enough (lower than Vth) and the hole concentration is high enough, a P-type inversion layer channel is formed on the surface of the N-type substrate under the gate. This P-type channel connects the P-type source and drain, allowing holes (majority carriers) to flow from the source to the drain (the current direction is opposite), and a low impedance state is presented between the source and the drain, that is, it is on.

[0061] 2. In this embodiment, for example, the output voltage of the first power supply terminal VCC1 is 5V, and the threshold voltage Vth of the second switch T2 is -1V. At this time, the control terminal (i.e., gate) voltage Vg of the second switch T2 is 5V. If the voltage of the first terminal (i.e., source) of the second switch T2 is 6-8V, the gate-source voltage Vgs of the second switch T2 is Vg-Vs=5-(6-8)=-3--1. The gate-source voltage Vgs of the second switch T2 is less than the threshold voltage Vth, and the second switch T2 is turned on. Therefore, when the data voltage is within the first preset range, the second switch T2 is turned on, and the data voltage is output to the first pixel unit 400 after passing through the first diode D1 and the second diode D2. Conversely, when the voltage of the first terminal of the second switch T2 is less than 6V (i.e., when the data voltage is within the second preset range or the third preset range), the gate-source voltage Vgs of the second switch is greater than the Vth threshold voltage, and the second switch T2 is turned off, and no signal is output to the first pixel unit 400.

[0062] 3. When the second switch tube T2 is turned on, the data voltage passes through the first diode D1 and charges the first capacitor C1. At this time, the gate of the third switch tube T3 is at a high level, and the third switch tube T3 is turned off. When the data voltage on the data line is within a second preset range, the second switch tube T2 is turned off and the third switch tube T3 is turned on. The data voltage of the first pixel unit 400 (e.g., 6.4V) stored in the first capacitor C1 serves as a trigger signal for the first control unit 120 and is output to the second control unit 130 through the first end of the third switch tube T3, thereby achieving the purpose of charging the second pixel unit 500 after the first pixel unit 400 is fully charged.

[0063] The function of the first diode D1 in this embodiment is to isolate the gate (control terminal) and the source (second terminal) of the third switch tube T3, thereby preventing the discharge current of the first capacitor C1 from flowing back to the gate of the third switch tube T3 and affecting the conduction state of the third switch tube T3; the function of the second diode D2 in this embodiment is to isolate the first capacitor C1 and the first pixel unit 400, thereby preventing the discharge current of the first capacitor C1 from flowing back to the first pixel unit 400 and affecting the charging state of the first pixel unit 400.

[0064] Continue as Figure 6As shown, the second control unit 130 of this embodiment includes a fourth switching transistor T4, a fifth switching transistor T5, a sixth switching transistor T6, a third diode D3, a second capacitor C2, and a fourth diode D4. Specifically, the control terminal of the fourth switching transistor T4 is connected to the second power supply terminal VCC2, and the first terminal of the fourth switching transistor T4 is connected to the input terminal of the second control unit 130. The control terminal of the fifth switching transistor T5 serves as the control terminal of the second control unit 130, and the first terminal of the fifth switching transistor T5 is connected to the second terminal of the fourth switching transistor T4. The control terminal of the sixth switching transistor T6 is connected to the second terminal of the fifth switching transistor T5, and the first terminal of the sixth switching transistor T6 serves as the second output terminal of the second control unit 130. The anode of the third diode D3 is connected to the control terminal of the sixth switching transistor T6, and the cathode of the third diode D3 is connected to the second terminal of the sixth switching transistor T6. The first terminal of the second capacitor C2 is connected to the second terminal of the sixth switching transistor T6, and the second terminal of the second capacitor C2 is grounded. The anode of the fourth diode D4 is connected to the cathode of the third diode D3, and the cathode of the fourth diode D4 serves as the first output terminal of the second control unit 130.

[0065] It should be noted that the fourth switch transistor T4, the fifth switch transistor T5, and the sixth switch transistor T6 of this embodiment may be P-type MOS transistors or N-type MOS transistors. Here, taking the fourth switch transistor T4 as a P-type MOS transistor, the fifth switch transistor T5 as an N-type MOS transistor, the sixth switch transistor T6 as a P-type MOS transistor, the output voltage of the second power supply terminal VCC2 as 0V, the threshold voltage of the fourth switch transistor T4 as -2.5V, and the threshold voltage of the fifth switch transistor T5 as 2V as an example, the working principle of the second control unit 130 of this embodiment is described in detail: (1) When the data voltage is in the first preset range (e.g., 6.0-8.0V), the gate-source voltage of the fourth switch tube T4 (-8-6V) is less than the threshold voltage -2.5V, and the fourth switch tube T4 is turned on; since the first pixel unit is being charged when the data voltage is in the first preset range, the first control unit does not output a trigger signal, so the fifth switch tube is turned off, and the second control unit does not output any signal to the second pixel unit 500.

[0066] (2) When the data voltage is in the second preset range (e.g., 3.0-5.0V), the gate-source voltage of the fourth switch tube T4 (-5-3V) is less than the threshold voltage -2.5V, and the fourth switch tube T4 is turned on. Since the data voltage is in the second preset range when the second pixel unit 500 is being charged, the first pixel unit 400 has been fully charged at this time, so it can receive the trigger signal output by the first control unit 120, and the fifth switch tube T5 is turned on. The current data voltage is output to the third pixel unit 600 through the third diode D3 and the fourth diode D4.

[0067] (3) When the data voltage is in the third preset range (e.g., 0.5V to 2.5V), the gate-source voltage of the fourth switch tube T4 (-2.5V to -0.5V) is greater than the threshold voltage -2.5V, and the fourth switch tube T4 is disconnected and does not output any signal to the second pixel unit 500.

[0068] (4) When the fifth switch tube T5 is turned on, the data voltage passes through the third diode D3 and charges the second capacitor C2. At this time, the gate of the sixth switch tube T6 is at a high level and the sixth switch tube T6 is turned off. When the data voltage on the data line is within the third preset range, the fourth switch tube T4 is turned off and the sixth switch tube T6 is turned on. The data voltage of the second pixel unit 500 (e.g., 5.5V) stored in the second capacitor C2 is used as a trigger signal of the second control unit 130 and is output to the third control unit 140 through the first end of the sixth switch tube T6, thereby achieving the purpose of charging the third pixel unit 600 after the second pixel unit 500 is charged.

[0069] In another embodiment, the second control unit 130 further includes an eighth switch tube T8, wherein a control end of the eighth switch tube T8 is connected to the scan line, a first end of the eighth switch tube T8 is grounded, and a second end of the eighth switch tube T8 is connected to the first end of the second capacitor C2; wherein the eighth switch tube T8 may be a P-type MOS tube. When the scan line is turned off (i.e., outputs a low level), the eighth switch tube T8 is turned on, allowing the voltage in the second capacitor C2 to be quickly released to the ground, thereby preventing the pixel voltage from being mischarged.

[0070] The function of the third diode D3 in this embodiment is to isolate the gate (control terminal) and the source (second terminal) of the sixth switch tube T6, thereby preventing the discharge current of the second capacitor C2 from flowing back to the gate of the sixth switch tube T6 and affecting the conduction state of the sixth switch tube T6; the function of the fourth diode D4 in this embodiment is to isolate the second capacitor C2 and the second pixel unit 500, thereby preventing the discharge current of the second capacitor C2 from flowing back to the second pixel unit 500 and affecting the charging state of the second pixel unit 500.

[0071] Continue as Figure 6 As shown, the third control unit 140 of this embodiment includes a seventh switch tube T7, the control end of the seventh switch tube T7 serves as the control end of the third control unit 140, the first end of the seventh switch tube T7 serves as the input end of the third control unit 140, and the second end of the seventh switch tube T7 serves as the output end of the third control unit 140.

[0072] It should be noted that the seventh switch transistor T7 in this embodiment may be a P-type MOS transistor or an N-type MOS transistor. Here, taking the seventh switch transistor T7 as an N-type MOS transistor as an example, the working principle of the third control unit 140 in this embodiment is described in detail: (1) When the data voltage is within the first preset range (e.g., 6.0-8.0 V) and the second preset range (3.0-5.0 V), and the trigger signal (e.g., 5.5 V) output by the second control unit 130 is not received, the seventh switch tube is turned off and does not output any signal to the third pixel unit 600.

[0073] (2) When the data voltage is within the third preset range (e.g., 0.5-2.5 V) and receives the trigger signal output by the second control unit 130, the seventh switch tube T7 is turned on to output the current data voltage to the third pixel unit 600, thereby achieving the purpose of charging the third pixel unit 600 after the second pixel unit 500 is fully charged.

[0074] when Figure 6 When the pixel driving circuit 100 shown is applied to the OLED display panel 10, the first pixel unit 400, the second pixel unit 500 and the third pixel unit 600 respectively include: a storage capacitor C0, a driving transistor T0 and a light emitting diode OLED; Figure 6 As shown, the first end of the storage capacitor C0 serves as the input end of the corresponding pixel unit, the second end of the storage capacitor C0 is connected to the driving power end, the control end of the driving transistor T0 is connected to the first end of the storage capacitor C0, the first end of the driving transistor T0 is connected to the second end of the storage capacitor C0, the anode of the light-emitting diode OLED is connected to the second end of the driving transistor T0, and the cathode of the light-emitting diode OLED is connected to the cathode power end.

[0075] when Figure 6 When the pixel driving circuit 100 is applied in the LCD display panel 10 , the first pixel unit 400 , the second pixel unit 500 and the third pixel unit 600 include liquid crystal capacitors, and the pixel electrodes of the liquid crystal capacitors serve as input terminals of the corresponding pixel units.

[0076] In an application scenario, Figure 6 The output voltage of the first driving voltage terminal VDD1 is 10V, the output voltage of the second driving voltage terminal VDD2 is 5V, and the output voltage of the third driving voltage terminal VDD3 is 0V; the output voltage of the first cathode voltage terminal VSS1 is 5V, the output voltage of the second cathode voltage terminal VSS2 is 0V, and the output voltage of the third cathode voltage terminal VSS3 is -5V.

[0077] In another application scenario, Figure 6 The output voltage of the first driving voltage terminal VDD1 is 10V, the output voltage of the second driving voltage terminal VDD2 is 8V, and the output voltage of the third driving voltage terminal VDD3 is 5V; the output voltage of the first cathode voltage terminal VSS1 is 5V, the output voltage of the second cathode voltage terminal VSS2 is 0V or 3V, and the output voltage of the third cathode voltage terminal VSS3 is 0V.

[0078] It is worth noting that the above-mentioned output voltage values ​​of the first driving voltage terminal VDD1, the second driving voltage terminal VDD2, the third driving voltage terminal VDD3, the first power supply terminal VCC1, the second power supply terminal VCC2, the first preset range (6.0~8.0V), the second preset range (3.0~5.0V), the third preset range (0.5~2.5V), the first cathode voltage terminal VSS1, the second cathode voltage terminal VSS2, the third cathode voltage terminal VSS3, etc. are only used as an exemplary description. They are affected by the type, size, process, etc. of the driving transistor T0 and the light-emitting unit, and even with future material and process research and development, the voltage ranges listed above may fluctuate and be adaptively adjusted according to different application scenarios. The core of this application is to stagger the data voltage ranges of the three pixel units to ensure that the pixel units connected to the same data line will not be charged at the same time due to the problem of incorrect charging.

[0079] Figure 7 FIG. 1 is a schematic structural diagram of a fifth pixel driving circuit provided in an embodiment of the present application; FIG. Figure 7 As shown, the pixel driving circuit 100 of this embodiment includes a first control unit 120 , a second control unit 130 and a third control unit 140 .

[0080] Specifically, the input end of the first control unit 120 is connected to the data line 300, and the first output end of the first control unit 120 is connected to the input end of the first pixel unit 400, so as to output the current data voltage to the first pixel unit 400 when the current data voltage is within the first preset range, and output a trigger signal after the first pixel unit is charged; the control end of the second control unit is connected to the second output end of the first control unit, the input end of the second control unit 130 is connected to the data line 300, and the first output end of the second control unit 130 is connected to the input end of the second pixel unit 500, so as to output the current data voltage to the second pixel unit 500 when the current data voltage is within the second preset range, and output a trigger signal after the second pixel unit is charged; the control end of the third control unit is connected to the second output end of the second control unit, the input end of the third control unit 140 is connected to the data line 300, and the output end of the third control unit 140 is connected to the input end of the third pixel unit 600, so as to output the current data voltage to the third pixel unit 600 when the current data voltage is within the third preset range.

[0081] It should be noted that Figure 7 The pixel driving circuit 100 shown is Figure 2 The only difference is that the master control unit 110 is missing; the working principles of the first control unit 120, the second control unit 130 and the third control unit 140 are the same and will not be repeated here.

[0082] It can be seen from this that this embodiment connects three pixel units to the same data line 300 through the pixel driving circuit 100, so that a single data signal can drive three sub-pixels at the same time, and the driving rate can be increased by three times. It can be applied in a conventional TRD structure to achieve the purpose of reducing the number of scan lines 200 of the conventional TRD structure.

[0083] refer to Figure 3 、 Figure 4 and Figure 5 As shown, Figure 7 The pixel driving circuit 100 may also be connected only to the first pixel unit 400 and the second pixel unit 500, or only to the third pixel unit 600 and the first pixel unit 400, or only to the second pixel unit 500 and the third pixel unit 600, which will not be repeated here.

[0084] Figure 8 FIG. 1 is a circuit diagram of a second pixel driving circuit provided in an embodiment of the present application; Figure 8 The specific circuit structure and working principle of the first control unit 120, the second control unit 130 and the third control unit 140 are the same as those of the first control unit 120, the second control unit 130 and the third control unit 140. Figure 6 The embodiments shown are identical and will not be described again here.

[0085] when Figure 8 When the pixel driving circuit 100 shown is applied in the OLED display panel 10, the first pixel unit 400, the second pixel unit 500 and the third pixel unit 600 respectively include: a control transistor Q0, a storage capacitor C0, a driving transistor T0 and a light emitting diode OLED; Figure 8 As shown, the control end of the control transistor Q0 is connected to the scan line 200, the first end of the control transistor Q0 serves as the input end of the corresponding pixel unit, the second end of the control transistor Q0 is connected to the first end of the storage capacitor C0, the second end of the storage capacitor C0 is connected to the driving power supply end, the control end of the driving transistor T0 is connected to the first end of the storage capacitor C0, the first end of the driving transistor T0 is connected to the second end of the storage capacitor C0, the anode of the light-emitting diode OLED is connected to the second end of the driving transistor T0, and the cathode of the light-emitting diode OLED is connected to the cathode power supply end.

[0086] when Figure 8 When the pixel driving circuit 100 shown is applied in the LCD display panel 10, the first pixel unit 400, the second pixel unit 500 and the third pixel unit 600 include a control transistor Q0 and a liquid crystal capacitor. The control end of the control transistor Q0 is connected to the scan line 200, the first end of the control transistor Q0 serves as the input end of the corresponding pixel unit, and the second end of the control transistor Q0 is connected to the pixel electrode of the liquid crystal capacitor.

[0087] Figure 9 FIG. 1 is a schematic structural diagram of a first display panel provided in an embodiment of the present application; FIG. Figure 9 As shown, the display panel 10 includes N rows of scanning lines 200 and M columns of pixel columns 11 for progressive scanning. The pixel columns 11 include: 1 column of data lines 300 and N rows of pixel circuits; one end of the data line 300 is connected to the source driver chip, and each row of pixel circuits includes a first pixel unit 400, a second pixel unit 500, a third pixel unit 600 and the pixel driving circuit 100 of claim 2.

[0088] It should be noted that, in the display panel 10 provided in this embodiment, one column of data lines 300 charges three pixel units simultaneously. The horizontal arrangement of the three pixel units is the same as that of the traditional Stripe architecture, but different from the vertical arrangement in the conventional tripe architecture.

[0089] In addition, a conventional tripe architecture requires three times the number of scan lines 200 of a conventional stripe architecture, while the pixel architecture of this embodiment does not need to add scan lines 200 to the conventional stripe architecture. The number of scan lines 200 is 1 / 3 of that of a conventional tripe architecture, which greatly reduces the RC loading of the display panel 10 red, effectively reduces panel power consumption and noise, and can break the dilemma of being unsuitable for 8K and above resolution scenarios.

[0090] Figure 10 FIG. 1 is a schematic structural diagram of a second display panel provided in an embodiment of the present application; FIG. Figure 10 As shown, the display panel 10 includes N rows of scanning lines 200 and M columns of pixel columns 11 for progressive scanning. The pixel columns 11 include three columns of data lines 300, N rows of pixel circuits, and the pixel driving circuit 100 of claim 3. Each row of pixel circuits includes a first pixel unit 400, a second pixel unit 500, and a third pixel unit 600. The input end of the pixel driving circuit 100 is connected to the source driver chip, and the output end of the pixel driving circuit 100 is connected to the three columns of data lines 300, respectively.

[0091] It should be noted that, in the display panel 10 provided in this embodiment, the pixel driving circuit 100 can be set in the non-display area, and the data voltage emitted by one data channel in the source driver chip can be sent to different data lines 300 in the panel in a time-sharing manner through the pixel driving circuit 100, thereby achieving the purpose of reducing the number of source driver chips in the same manner as in a conventional tripe architecture. Figure 10 and Figure 9 Compared with the display panel 10 shown, Figure 10 Not only can the number of source driver chips be reduced, but the number of scan lines 200 can also be reduced accordingly; Figure 10The number of scan lines 200 shown in the structure cannot be reduced, but the number of source driver chips can be reduced in the same proportion; Figure 10 The pixel driving circuit 100 is arranged in the non-display area, which does not affect the aperture ratio of the panel. Therefore, the panel mask design can be modified on the original Striple architecture, saving product development costs.

[0092] Figure 11 FIG. 1 is a schematic structural diagram of a third display panel provided in an embodiment of the present application; FIG. Figure 11 As shown, the display panel 10 includes N rows of scanning lines 200 and M columns of pixel columns 11 for progressive scanning, and the pixel columns 11 include: 1 column of data lines 300 and N rows of pixel circuits; one end of the data line 300 is connected to the source driver chip, and each row of pixel circuits includes a first pixel unit 400, a second pixel unit 500 and the pixel driving circuit 100 of claim 2, or a first pixel unit 400, a third pixel unit 600 and the pixel driving circuit 100 of claim 2, and a second pixel unit 500, a third pixel unit 600 and the pixel driving circuit 100 of claim 2.

[0093] Figure 12 FIG. 1 is a schematic structural diagram of a fourth display panel provided in an embodiment of the present application; FIG. Figure 12 As shown, the display panel 10 includes N rows of scanning lines 200 and M columns of pixel columns 11 for progressive scanning, and the pixel columns 11 include two columns of data lines 300, N rows of pixel circuits and the pixel driving circuit 100 of claim 3; each row of pixel circuits includes a first pixel unit 400 and a second pixel unit 500, the first pixel unit 400 or the third pixel unit 600, or the second pixel unit 500 and the third pixel unit 600; the input end of the pixel driving circuit 100 is connected to the source driver chip, and the output end of the pixel driving circuit 100 is respectively connected to the two columns of data lines 300.

[0094] It is worth noting that Figure 11 The architecture and Figure 9 resemblance, Figure 12 The architecture and Figure 11 Similarly, its driving principle and effect are also the same, so I will not go into details here.

[0095] In summary, the display panel provided in this embodiment has at least the following advantages: 1. Support high resolution: While reducing the number of source chips, there is no need to increase the number of scan lines, avoiding the problem of increased parasitic capacitance / resistance caused by high-density gate lines, simplifying the array glass design, and is particularly beneficial to the stability of high-resolution panels (such as 8K).

[0096] 2. The Stripe architecture maintains the original scan line density and the pixel aperture ratio is not affected.

[0097] 3. No high-frequency drive is required, RC loading is small, overall power consumption is low, and noise performance is good; and through timing optimization or low-power charge sharing technology, the overall power consumption of the module can be reduced while reducing signal transmission loss.

[0098] 4. Strong compatibility and scalability: While meeting the DRD / Triple architecture to reduce the number of source driver chips, it is compatible with the traditional Tripe / DRD sub-pixel layout, can be directly adapted to existing production line equipment, reducing the difficulty of mass production, and supports expansion to high resolution (8K); and it can break the dilemma of being unsuitable for 8K and above resolution scenarios, and will rewrite the pixel design of high-resolution panels. It is an upgraded version of the Striple architecture with lower cost and higher transmittance, which is more competitive in high-end display and low-power scenarios.

[0099] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0100] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0101] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A pixel driving circuit, applied to a display panel, wherein the display panel comprises a scan line, a data line, a first pixel unit, a second pixel unit, and a third pixel unit; characterized in that: The input end of the pixel driving circuit is connected to the data line, and the output end of the pixel driving circuit is connected to the input end of the first pixel unit, the second pixel unit or / and the third pixel unit, and is used to receive the current data voltage transmitted on the data line, and output the current data voltage to the target pixel unit according to the preset range of the current data voltage, so that the current data voltage charges the target pixel unit; wherein the target pixel unit is one of the first pixel unit, the second pixel unit and the third pixel unit; the first pixel unit, the second pixel unit and the third pixel unit are charged in a preset order.

2. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit includes: a main control unit, wherein a control terminal of the main control unit is connected to the scan line, and an input terminal of the main control unit is connected to the data line, and is configured to output a current data voltage on the data line when the scan line is in a conducting state under the action of a gate drive signal; a first control unit, wherein an input end of the first control unit is connected to an output end of the master control unit, and a first output end of the first control unit is connected to an input end of the first pixel unit, and is configured to output the current data voltage to the first pixel unit when the current data voltage is within a first preset range, and output a trigger signal after the first pixel unit is fully charged; The pixel driving circuit further includes: a second control unit, wherein a control end of the second control unit is connected to the second output end of the first control unit, an input end of the second control unit is connected to the output end of the master control unit, and a first output end of the second control unit is connected to the input end of the second pixel unit, and is configured to output the current data voltage to the second pixel unit when the current data voltage is within a second preset range and the trigger signal is received, and output a trigger signal after the second pixel unit is completely charged; Or / and, a third control unit, the control end of the third control unit is connected to the second output end of the first control unit or the second output end of the second control unit, the input end of the third control unit is connected to the output end of the main control unit, and the output end of the third control unit is connected to the input end of the third pixel unit, for outputting the current data voltage to the third pixel unit when the current data voltage is within a third preset range and the trigger signal is received.

3. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit includes: a first control unit, wherein an input end of the first control unit is connected to the data line, and a first output end of the first control unit is connected to an input end of the first pixel unit, and is configured to output the current data voltage to the first pixel unit when the current data voltage is within a first preset range, and output a trigger signal after the first pixel unit is fully charged; The pixel driving circuit further includes: a second control unit, wherein a control end of the second control unit is connected to the second output end of the first control unit, an input end of the second control unit is connected to the data line, and an output end of the second control unit is connected to the input end of the second pixel unit, and is configured to output the current data voltage to the second pixel unit when the current data voltage is within a second preset range and the trigger signal is received, and output a trigger signal after the second pixel unit is completely charged; Or / and, a third control unit, the control end of the third control unit is connected to the second output end of the first control unit or the second output end of the second control unit, the input end of the third control unit is connected to the data line, and the output end of the third control unit is connected to the input end of the third pixel unit, for outputting the current data voltage to the third pixel unit when the current data voltage is within a third preset range and the trigger signal is received.

4. The pixel driving circuit according to claim 2, wherein: The master control unit comprises: A first switch tube, wherein a control end of the first switch tube is connected to the scan line, a first end of the first switch tube serves as an input end of the master control unit, and a second end of the first switch tube serves as an output end of the master control unit.

5. The pixel driving circuit according to claim 2 or 3, characterized in that: The first control unit includes: a second switching tube, wherein a control end of the second switching tube is connected to the first power supply end, and a first end of the second switching tube is connected as an input end of the first control unit; a third switching tube, wherein a control end of the third switching tube is connected to the second end of the second switching tube, and a first end of the third switching tube serves as a second output end of the first control unit; a first diode, wherein an anode of the first diode is connected to the control terminal of the third switch tube, and a cathode of the first diode is connected to the second terminal of the third switch tube; a first capacitor, wherein a first end of the first capacitor is connected to the second end of the third switch tube, and a second end of the first capacitor is grounded; A second diode, wherein the anode of the second diode is connected to the cathode of the first diode, and the cathode of the second diode serves as the first output end of the first control unit.

6. The pixel driving circuit according to claim 2 or 3, characterized in that: The second control unit includes: a fourth switch tube, wherein a control end of the fourth switch tube is connected to the second power supply end, and a first end of the fourth switch tube is connected as an input end of the second control unit; a fifth switching tube, wherein a control end of the fifth switching tube serves as a control end of the second control unit, and a first end of the fifth switching tube is connected to a second end of the fourth switching tube; a sixth switching tube, wherein a control end of the sixth switching tube is connected to the second end of the fifth switching tube, and a first end of the sixth switching tube serves as a second output end of the second control unit; a third diode, wherein an anode of the third diode is connected to the control terminal of the sixth switch tube, and a cathode of the third diode is connected to the second terminal of the sixth switch tube; a second capacitor, wherein a first end of the second capacitor is connected to the second end of the sixth switch tube, and a second end of the second capacitor is grounded; A fourth diode, wherein the anode of the fourth diode is connected to the cathode of the third diode, and the cathode of the fourth diode serves as the first output end of the second control unit.

7. The pixel driving circuit according to claim 2 or 3, characterized in that: The third control unit includes: A seventh switch tube, wherein the control end of the seventh switch tube serves as the control end of the third control unit, the first end of the seventh switch tube serves as the input end of the third control unit, and the second end of the seventh switch tube serves as the output end of the third control unit.

8. The pixel driving circuit according to claim 2, wherein: The first pixel unit, the second pixel unit and the third pixel unit include liquid crystal capacitors, and pixel electrodes of the liquid crystal capacitors serve as input terminals of the corresponding pixel units; Alternatively, the first pixel unit, the second pixel unit and the third pixel unit include: a storage capacitor, a driving transistor and a light-emitting diode, the first end of the storage capacitor serves as the input end of the corresponding pixel unit, the second end of the storage capacitor is connected to the driving power supply end, the control end of the driving transistor is connected to the first end of the storage capacitor, the first end of the driving transistor is connected to the second end of the storage capacitor, the anode of the light-emitting diode is connected to the second end of the driving transistor, and the cathode of the light-emitting diode is connected to the cathode power supply end.

9. The pixel driving circuit according to claim 3, wherein: The first pixel unit, the second pixel unit and the third pixel unit include a control transistor and a liquid crystal capacitor, the control end of the control transistor is connected to the scan line, the first end of the control transistor serves as the input end of the corresponding pixel unit, and the second end of the control transistor is connected to the pixel electrode of the liquid crystal capacitor; Or, the first pixel unit, the second pixel unit and the third pixel unit include: a control transistor, a storage capacitor, a driving transistor and a light-emitting diode, the control end of the control transistor is connected to the scan line, the first end of the control transistor serves as the input end of the corresponding pixel unit, the second end of the control transistor is connected to the first end of the storage capacitor, the second end of the storage capacitor is connected to the driving power supply end, the control end of the driving transistor is connected to the first end of the storage capacitor, the first end of the driving transistor is connected to the second end of the storage capacitor, the anode of the light-emitting diode is connected to the second end of the driving transistor, and the cathode of the light-emitting diode is connected to the cathode power supply end.

10. A display panel comprising N rows of scanning lines and M columns of pixel columns for progressive scanning, characterized in that: The pixel column comprises: 1 column of data lines and N rows of pixel circuits; one end of the data line is connected to the source driver chip, and each row of pixel circuits comprises a first pixel unit, a second pixel unit, a third pixel unit and the pixel driving circuit according to claim 2; Alternatively, the pixel column includes three columns of data lines, N rows of pixel circuits, and the pixel driving circuit according to claim 3; each row of pixel circuits includes a first pixel unit, a second pixel unit, and a third pixel unit; an input end of the pixel driving circuit is connected to a source driver chip, and an output end of the pixel driving circuit is connected to the three columns of data lines, respectively; Alternatively, the pixel column comprises: 1 column of data lines and N rows of pixel circuits; one end of the data line is connected to a source driver chip, and each row of pixel circuits comprises a first pixel unit, a second pixel unit, and the pixel driver circuit according to claim 2, or a first pixel unit, a third pixel unit, and the pixel driver circuit according to claim 2, and a second pixel unit, a third pixel unit, and the pixel driver circuit according to claim 2; Or, the pixel column includes 2 columns of data lines, N rows of pixel circuits and the pixel driving circuit according to claim 3; each row of pixel circuits includes a first pixel unit and a second pixel unit, a first pixel unit or a third pixel unit, or a second pixel unit and a third pixel unit; the input end of the pixel driving circuit is connected to the source driver chip, and the output end of the pixel driving circuit is respectively connected to the 2 columns of data lines.

Images