Memory capable of realizing multidirectional interaction of data between storage units and implementation method of memory

Abstract

The invention discloses a memory capable of realizing multidirectional data interaction between memory units and an implementation method, which are characterized in that any ith memory unit is controlled to keep a latch state, and the rest one or more memory units including the jth memory unit connected to the same group of bit lines are controlled to keep a non-latch state; the data is read from the ith storage unit to the bit line and is written into the other one or more storage units from the bit line to be stored; moreover, the jth storage unit is controlled to keep a latch state, and the other one or more storage units including the ith storage unit connected to the same group of bit lines are controlled to keep a non-latch state, so that data are read from the jth storage unit to the bit lines and written into the other one or more storage units from the bit lines to be stored; i and j are integers, i is not equal to j, i > = 1, and j > = 1. According to the invention, the area size of the circuit can be reduced, the data transfer efficiency is improved, the voltage swing and power consumption can be reduced, and the impact on a power network is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a memory capable of multi-directional data interaction between storage units and an implementation method thereof. Background Art

[0002] Existing data transmission between memory cells typically involves inserting a driver at a certain distance. This data transmission method subjects the signal to large voltage swings across the interconnect, significantly impacting the power supply network and consuming high power. Application of such memory to image sensors can easily lead to image quality degradation. Furthermore, due to performance constraints such as circuit scale and complexity, existing memory inter-cell data transmission methods are mostly unidirectional, meaning data can only be transmitted from the first memory cell to the second.

[0003] Traditional memories used in image sensors include Figure 1 As shown, data transmission between storage cells begins with the first storage cell, then passes through the first, ..., and nth drivers, and is then stored in the second storage cell. This circuit structure supports only unidirectional data transmission, meaning that data can only be transferred from the first storage cell to the second storage cell for storage. Drivers are typically implemented using inverters or buffers. The first storage cell acts as the data transmitter, and the second storage cell acts as the data receiver. Data transmission is accomplished by inserting a driver at regular intervals, depending on the distance between the storage cells. The use of a certain number of drivers results in a large area footprint, hindering circuit size reduction. Furthermore, the transmission signal using this type of memory experiences a large voltage swing across the entire transmission line. Since transmission power consumption P = CΔV²f, where C is the transmission line capacitance, ΔV is the voltage swing on the transmission line, and f is the data transmission frequency, a large ΔV leads to high power consumption in this type of memory, significantly impacting the power supply network. Summary of the Invention

[0004] To address the aforementioned issues, the present invention proposes a memory device capable of multi-directional data exchange between storage units and a method for implementing the same. This device enables multi-directional data exchange between storage units, avoiding long data transmission lines and the use of a certain number of drivers. This reduces the size of the memory circuit and enables a compact image sensor driver circuit. Furthermore, the device improves data transfer efficiency, reduces voltage swing, lowers power consumption, and mitigates the impact on the power supply network.

[0005] In a first aspect, the present invention proposes a method for realizing multi-directional interaction of data between storage cells, characterized in that, for any i-th storage cell connected on a group of bit lines, the method controls the i-th storage cell to maintain a latched state, and controls the remaining one or more storage cells including the j-th storage cell connected to the same group of bit lines to maintain a non-latched state, so as to realize that data is read out from the i-th storage cell to the bit line, and written from the bit line to the remaining one or more storage cells for storage; and the method also controls the j-th storage cell to maintain a latched state, and controls the remaining one or more storage cells including the i-th storage cell connected to the same group of bit lines to maintain a non-latched state, so as to realize that data is read out from the j-th storage cell to the bit line, and written from the bit line to the remaining one or more storage cells for storage; wherein i and j are integers, i≠j, and i≥1, j≥1.

[0006] In a preferred embodiment, the latched state includes a steady state, and the non-latched state includes a metastable state. The method controls the power supply voltage of several storage units for receiving data to be lower than the power supply voltage of the storage units for sending data, so that the storage units for sending data maintain a steady state and the several storage units for receiving data maintain a metastable state.

[0007] In a preferred embodiment, for any multiple storage units that interact with data, within a data interaction cycle, only one storage unit sends data, and its power supply voltage maintains the steady state by maintaining the first level voltage; several storage units are included for receiving data, and their power supply voltage is switched from the first level voltage to the first reference voltage to achieve a metastable state to receive data, and after receiving the data, the power supply voltage of the several storage units used to receive data is switched back from the first reference voltage to the first level voltage to maintain a steady state; wherein, the first reference voltage is less than the first level voltage.

[0008] In a preferred embodiment, the method further comprises providing a voltage control unit for controlling the switching of the power supply voltage of some or all of the memory cells between the first level voltage and the first reference voltage.

[0009] In a preferred embodiment, the voltage control unit is provided to include a first type of transistor and a second type of transistor corresponding one to one with the storage unit; the control ends of the first type of transistor and the second type of transistor are controlled by the same control signal to select a first level voltage or a first reference voltage as a power supply voltage to be provided to the storage unit.

[0010] In a preferred embodiment, the group of bit lines is configured to include a first bit line to implement single-ended transmission; or, the group of bit lines is configured to include a first bit line and a second bit line to implement differential transmission.

[0011] In a preferred embodiment, a first sub-control unit for controlling the electrical connection state of the first bit line and the second bit line is further provided between the first bit line and the second bit line.

[0012] In a preferred embodiment, the memory further comprises a precharge circuit for providing a second reference voltage to the one or more groups of bit lines.

[0013] In a preferred embodiment, the precharge circuit is configured to include at least a second sub-control unit and a third sub-control unit, respectively configured to control the second reference voltage to be provided to the first bit line and the second bit line.

[0014] In a preferred embodiment, the first reference voltage is less than a first level voltage, the second reference voltage is less than or equal to the first level voltage, and the first reference voltage is equal to or unequal to the second reference voltage.

[0015] In a preferred embodiment, the first level voltage is 1.1V, and the first and second reference voltages are 0.5V.

[0016] In a preferred embodiment, the storage unit is configured to include a static storage unit or a latch.

[0017] In a second aspect, the present invention proposes a memory in which data between storage cells can interact in multiple directions, characterized in that the memory includes m storage modules, at least one storage module includes a first storage cell, ..., an nth storage cell connected to the same group of bit lines, m≥1, n≥2, and m and n are integers; there is at least one storage module, at least two storage cells of which can be controlled to enable the storage cells to switch between a latched state and a non-latched state, so as to achieve multi-directional interaction of data between storage cells.

[0018] In a preferred embodiment, the multi-directional interaction method of the aforementioned memory is implemented according to the method for multi-directional interaction of data between storage units described in any of the aforementioned preferred embodiments.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: by controlling the switching of the memory cell between the latched state and the non-latched state, any memory cell of the memory can be maintained in a latched state to support data transmission, or in a non-latched state to support data reception and storage, so that within a data interaction cycle, the data of any memory cell on the same group of bit lines can be controlled to be read out and written to one or more memory cells. At the same time, within a data interaction cycle, any memory cell can store the data of any other memory cell on the same group of bit lines, thereby realizing multi-directional interaction between memory cells. In the application of image sensors, the multi-directional data interaction between memory cells can avoid the transmission and storage of data over long distances and the use of large-scale drivers, which is beneficial to reducing the size of the memory itself and the circuit using the memory. On the other hand, the voltage swing of the transmission signal on the entire transmission line can be greatly reduced, thereby providing the possibility of further reducing the power consumption of the memory and the circuit using the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings constitute a part of this specification and are used to further understand the present invention. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principle of the present invention.

[0021] Figure 1 FIG. 1 is a schematic diagram of a conventional memory structure.

[0022] Figure 2 FIG. 4 is a structure of a storage module according to an embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of a 1-bit static random access memory structure.

[0024] Figure 4 The figure illustrates the principle of differential transmission according to an embodiment of the present invention.

[0025] Figure 5a This is an example of a storage module for single-ended transmission according to an embodiment.

[0026] Figures 5b-5c FIG. 4 is a working sequence of single-ended transmission between storage units according to an embodiment.

[0027] Figure 6a This is an example of a storage module for differential transmission according to an embodiment.

[0028] Figures 6b-6c FIG. 4 is a working sequence of differential transmission between storage cells according to an embodiment.

[0029] Figure 7 Schematic diagram of the latch storage unit structure. DETAILED DESCRIPTION

[0030] The following detailed description is illustrative and is intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0031] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention.

[0032] In a first aspect, the present invention provides a method for realizing a memory for multi-directional data interaction between storage units, such as Figure 2 The figure shows a schematic diagram of a memory module. Within the memory module, a first memory cell, a second memory cell, ..., and an nth memory cell are connected to a group of bit lines (n is the number of memory cells, and the number of memory cells is greater than or equal to 2). The latching state of the memory cells can be independently controlled. For example, a first control unit, a second control unit, ..., and an nth control unit are provided corresponding to the first memory cell, the second memory cell, ..., and the nth memory cell, respectively, so that the latching state of the memory cells on the group of bit lines can be independently controlled. In a preferred embodiment, the first control unit, the second control unit, ..., and the nth control unit are provided in a one-to-one correspondence with each memory cell. Alternatively, a single control unit can be integrated for some or all memory cells. In short, as long as the latching state of the memory cells can be controlled during data transmission to facilitate data reading or writing, it is sufficient to facilitate data exchange between multiple memory cells. In addition, a precharge circuit is connected to the bit lines to reset the memory cells.

[0033] Specifically, in a memory module, for any i-th memory cell connected to a group of bit lines, its data can be sent to one or more memory cells on the group of bit lines, and data sent from any other memory cell on the group of bit lines can also be received and stored. Specifically, for any i-th memory cell connected to a group of bit lines, by controlling the i-th memory cell to maintain a latched state and controlling the remaining one or more memory cells, including the j-th memory cell, connected to the same group of bit lines to maintain an unlatched state, data can be read from the i-th memory cell to the group of bit lines and written from the group of bit lines to the remaining one or more memory cells for storage. Furthermore, the method further controls the j-th memory cell to maintain a latched state and controls the remaining one or more memory cells, including the i-th memory cell, connected to the same group of bit lines to maintain an unlatched state, so as to enable data to be read from the j-th memory cell to the group of bit lines and written from the group of bit lines to the remaining one or more memory cells for storage. Where i and j are integers, i≠j, and n≥i≥1, n≥j≥1.

[0034] In short, by controlling the memory cells to switch between latched and unlatched states, any memory cell within the memory can be maintained in a latched state to support data transmission, or in an unlatched state to support data reception and storage, thereby realizing a memory in which data can be exchanged in multiple directions between memory cells. In image sensor applications, this memory module utilizes the multi-directional exchange of data between memory cells, which facilitates data transmission nearby, avoids data transmission and storage over long distances, avoids the use of large-scale drivers, and helps reduce the size of the memory itself and the circuits that use it. Furthermore, it can significantly reduce the voltage swing of the transmission signal across the entire transmission line, thereby providing the possibility of further reducing the power consumption of the memory and the circuits that use it.

[0035] In a preferred embodiment, the memory cell may be, for example, a static memory cell, wherein the latched state includes a stable state and the non-latched state includes a metastable state, such as Figure 3 As shown in FIG, a simple static storage unit in a memory is shown. A static storage unit may include, for example, two inverters connected end to end, the first inverter being connected through a transistor P n0 、N n0 The second inverter is composed of transistor P n1 、N n1 The positive feedback is formed by two inverters; one or two read / write control units can be set corresponding to the number of bit lines in a group, for example, Figure 3 The bit line VBL is shown in FIG. a 、VBL b Connected to the node bit ia 、bit ib , and are respectively composed of two read and write control unit transistors N n2 、N n3 Control, the two read and write control units are provided with control signals WL by the word line n control.

[0036] Furthermore, the characteristic of charge transfer from high voltage to low voltage during data transmission is utilized to ensure the direction of data transmission. Specifically, by setting the control unit as a module for controlling the power supply voltage of the storage unit, by controlling the power supply voltage of the storage units used to receive data to be lower than the power supply voltage of the storage units used to send data, the storage units used to send data can be kept in a steady state, while the storage units used to receive data can be kept in a metastable state. Thus, data from one storage unit can be sent to other storage units for storage. Moreover, the storage unit used to send data can also be switched to a metastable state, while any of the other storage units can be switched to a steady state, so that the storage unit used to send data can be used to receive and store data, thereby realizing a memory with multi-directional data exchange between storage units. The implementation method of controlling the power supply voltage is simple and does not require a large circuit area, which is conducive to minimizing circuit scale and realizing a memory with multi-directional data exchange between storage units at a relatively low area cost. The multi-directional data exchange between storage units can be serial or parallel transmission.

[0037] In a preferred embodiment, the Figure 2 As shown, a first control unit, a second control unit, ..., and an nth control unit are provided as control units for controlling the power supply voltage. These control units correspond one-to-one with the storage units, or they can be integrated into a single control unit. In short, a power supply voltage control unit can be provided to control the switching of the power supply voltage of some or all storage units between a first voltage level and a first reference voltage, thereby further increasing the specific adaptability requirements of the circuit. The control unit for controlling the power supply voltage can be a simple combination of a control signal and a transistor switch.

[0038] In a preferred embodiment, to further simplify the circuitry of the power supply voltage control unit and reduce circuit scale, the power supply voltages of the plurality of storage units are configured to switch between a higher level and a lower level. For example, for any two storage units exchanging data, the power supply voltage of the storage unit transmitting data is maintained at a first voltage level to maintain a steady state; the power supply voltage of the plurality of storage units receiving data is switched from the first voltage level to a first reference voltage to achieve a metastable state, thereby receiving the data. After receiving the data, the power supply voltage of the plurality of storage units receiving data is switched back from the first reference voltage to the first voltage level to maintain a steady state; wherein the first reference voltage is lower than the first voltage level.

[0039] Specifically, as a preferred voltage control unit, the voltage control unit can be configured to include a first type transistor and a second type transistor corresponding one-to-one to the storage cells; the control terminals of the first type transistor and the second type transistor are controlled by the same control signal to select a first level voltage or a first reference voltage as the power supply voltage provided to the storage cells. The first type transistor and the second type transistor can specifically be PMOS transistors or NMOS transistors. The power supply voltage control unit, consisting of only the control signal and two transistors, has a small area and a simple circuit, which facilitates improved electrical performance of the circuit.

[0040] In a preferred embodiment, the memory includes a precharge circuit configured to provide a second reference voltage to the one or more groups of bit lines. The group of bit lines can include a single bit line, namely a first bit line, and the precharge circuit can be configured to perform a precharge reset function only on the first bit line, thereby achieving single-ended transmission. Alternatively, to further improve data transmission quality, the group of bit lines can include two bit lines, namely a first bit line and a second bit line, and the precharge circuit can be configured to perform a precharge reset function on the first bit line and the second bit line, thereby achieving differential transmission. Differential transmission can further reduce voltage swings, lower power consumption during data transfer, minimize impact on the power supply network, and reduce quantization noise of image signals, thereby further improving data transmission quality.

[0041] In a preferred embodiment, if Figure 4 As shown in FIG. 1 , the differential transmission principle of the memory of the present invention is schematically illustrated. The precharge circuit is specifically a differential transmission circuit. The power supply voltages of the i-th storage unit and the j-th storage unit are controlled by the i-th control unit and the j-th control unit respectively, so as to realize bidirectional interaction of data between each other. In order to reduce the first bit line VBL a , the second bit line VBL b The difference in charging level is still in the first line VBL a and the second bit line VBL b A first sub-control unit S1 is provided between the memory cells, which includes controlling the electrical connection state of the first bit line and the second bit line. The first sub-control unit S1 can be, for example, a transistor switch. The first sub-control unit S1 can control the electrical connection of the first bit line and the second bit line to equalize the difference when the pre-charge difference between the first bit line and the second bit line is large, thereby further improving the quality of data interaction. The working sequence of data transmission between the i-th memory cell and the j-th memory cell is mainly divided into two stages: reset and transmission. In the reset stage, switches S1, S2, and S3 can be in a closed state, and the reference voltage source V 2ref The first bit line VBL a , the second bit line VBL b The voltage is initialized to V 2refIn the transmission phase, the memory cell drives the first bit line VBL through the stored charge. a , the second bit line VBL b , creating a certain voltage difference between the two lines. The jth storage unit (or the ith storage unit) converts the received voltage difference into stored data, completing low-voltage data transmission. Switches S1, S2, and S3 can be implemented in various ways, such as NMOS, PMOS, and transmission gates. The figure is for illustrative purposes only.

[0042] Preferably, the differential transmission circuit may include at least a second sub-control unit S2 and a third sub-control unit S3, which are respectively used to control the second reference voltage V 2ref respectively provided to the first bit line VBL a and the second bit line VBL b For example, for single-ended output, the setting only includes the first bit line VBL a , the second sub-control unit S2, in differential output, not only the second sub-control unit S2 but also the third sub-control unit S3 are provided, and the second sub-control unit S2 and the third sub-control unit S3 can be transistor switches to simplify the circuit.

[0043] In a preferred embodiment, the first reference voltage is required to be less than the first voltage level to utilize the characteristic of charge transfer from high voltage to low voltage during data transmission to ensure the direction of data transmission. The second reference voltage can be less than or equal to the first voltage level, and the first reference voltage and the second reference voltage can be equal or unequal. For example, depending on the circuit application of the image sensor, to further simplify the circuit, the first voltage level can be 1.1 V, and the first and second reference voltages can be equal, for example, 0.5 V.

[0044] In a preferred embodiment, the storage unit may also be configured as a latch, and multi-directional data interaction between storage units may be achieved by controlling the switching of the latch state of the latch.

[0045] In a second aspect, the present invention provides a memory capable of multi-directional data exchange between storage cells. The memory comprises m storage modules, at least one of which comprises a first storage cell, ..., and an nth storage cell connected to the same set of bit lines, where m ≥ 1 and n ≥ 2, and m and n are integers. At least one storage module comprises at least two storage cells that can be controlled to switch between a latched state and an unlatched state, thereby enabling multi-directional data exchange between storage cells. The multi-directional data exchange method is implemented according to any of the methods for multi-directional data exchange between storage cells described above.

[0046] In a preferred embodiment, the memory cell is switched between a latched state and a non-latched state by controlling the power supply voltage of the memory cell. Preferably, the memory includes a voltage control unit for controlling the power supply voltage of the memory cell to switch between a first level voltage and a first reference voltage.

[0047] Furthermore, the present invention also provides a storage module that realizes single-ended transmission or differential transmission by controlling the power supply voltage, which will be described in detail below.

[0048] In a preferred embodiment, a single-ended output storage module is implemented, such as Figure 5a The figure shows a preferred example of a single-ended output memory module. Any two memory cells connected to the same group of bit lines, the i-th and j-th memory cells, respectively, comprise a simple static memory cell. The power supply voltages of the i-th and j-th memory cells are controlled by the i-th and j-th control units, respectively. The i-th and j-th control units each comprise two transistor switches, a PMOS transistor P j4 , (or P i4 ) An NMOS transistor N i4 (or N j4 ), the first electrodes of the two transistors are connected in common, and the second electrodes are used to connect the first level voltage VDD and the first reference voltage V 1ref , through a control signal Ctr i (or Ctr j ) controls the power supply voltage VDD_i (or VDD_j) of the memory cell to be between the first level voltage VDD and the first reference voltage V 1ref Switch between Figure 5a The diagram shows a group of bit lines including a first bit line VBL, and a single-ended precharge circuit for providing a second reference voltage V to the first bit line VBL. 2ref To achieve single-ended output, the charging circuit specifically includes a single-ended pre-charging circuit for providing a second reference voltage to the first bit line VBL. The single-ended pre-charging circuit can be a control unit, for example, including one or more transistor switches or transmission gates, for example, the figure illustrates the reset control signal rst a 、rst b Preferably, the single-ended pre-charging circuit can be used to provide the second reference voltage to the one or more groups of bit lines. By sharing the single-ended pre-charging circuit among the multiple groups of bit lines, the circuit scale can be further reduced.

[0049] Figure 5bThe timing of data transmission from the i-th storage unit to the j-th storage unit for storage in the case of single-ended transmission is illustrated. The timing of 1-bit data transmission from the i-th storage unit to the j-th storage unit and the operating state of the voltage at each node of the circuit during this process are described in detail below. The data transmission process can include four stages: the initial stage, the reset stage, the transmission stage, and the end of data transmission. During the data transmission process, the i-th storage unit that sends data needs to maintain a steady state, and the j-th storage unit that receives and stores data needs to switch to a metastable state to receive and store the data sent by the i-th storage unit. That is, during the reset and transmission stages, the j-th storage unit needs to switch the power supply voltage so that the power supply voltage is lower than the power supply voltage of the i-th storage unit, and during the initial and end of data transmission stages, the power supply voltage required by the j-th storage unit needs to be switched to be equal to the power supply voltage of the i-th storage unit to prepare for the next data interaction.

[0050] For the convenience of description, Figures 5a-5b A possible example of high and low voltages is shown. The low voltage is 0 V, the high voltage (first level voltage) VDD is 1.1 V, and the first and second reference voltages V 1ref is 0.5 V, but practical applications are not limited to these voltages.

[0051] Figure 5b This is the timing diagram of data 1 being single-endedly output from the i-th storage unit and stored in the j-th storage unit.

[0052] Initial stage node bit ia 、bit ib 1.1V and 0V respectively, bit j 、bit jb are 0V and 1.1V respectively, and the first bit line VBL is the second reference voltage V 2ref is 0.5V, the i-th word line control signal WL i , j-th word line control signal WL j is 0V, the power supply voltage VDD_i of the i-th memory cell and the power supply voltage VDD_j of the j-th memory cell are 1.1V.

[0053] In the reset phase, the first reset voltage rst is a high voltage, and the second reset voltage rst b The second sub-control unit S2 is turned on, and the first bit line VBL is initialized to the second reference voltage V 2ref At the same time, the j-th word line control signal WL j and the control signal Ctr of the jth control unit j are high, transistor P j4 Close, N j4 Turn on, the power supply voltage VDD_j of the jth storage unit and the node bit ja 、bitjb are initialized to V 1ref Voltage.

[0054] During the transmission phase, the first reset voltage rst a The voltage becomes low, the second reset voltage rst b = becomes high, and the second sub-control unit S2 is turned off. The i-th word line control signal WL i The voltage becomes high, and the j-th word line control signal WL j The voltage remains high, N i3 ,N j2 The two N-type transistors are turned on, and the voltage node bit of the i-th storage cell i Drive the first bit line VBL. Due to the characteristics of the N-type transistor, the first bit line VBL will rise to about 0.6 V. This voltage is only an example and is related to the threshold voltage of the N-type transistor and VDD. At the same time, the power supply voltage VDD_j of the j-th memory cell is maintained at the first reference voltage V 1ref , the first bit line VBL passes through N j2 Transistor driver bit j , and in transistor N j0 、N j1 、P j0 、P j1 The positive feedback of bit ja The voltage is maintained at V 1ref , bit jb The voltage is maintained at 0V.

[0055] At the end of data transmission, the i-th word line control signal WL i and the jth word line control signal WL j The voltage becomes low voltage, N i3 ,N j2 The transistors are all turned off. j The voltage becomes low, transistor P j4 Open, N j4 Turn off. VDD_ j voltage from V 1ref The voltage node bit of the jth memory cell rises to the high voltage first level voltage VDD. j The voltage across transistor N j0 、N j1 、P j0 、P j1 Under the positive feedback effect, it becomes 1.1V, that is, 1 bit of data 1 is successfully sent from the i-th storage unit to the j-th storage unit. jb The voltage across transistor N j0 、N j1 、P j0 、P j1The positive feedback is maintained at 0V.

[0056] Figure 5c This is a timing diagram of data 0 being single-endedly output from the i-th storage unit and stored in the j-th storage unit.

[0057] Initial stage node bit ia 、bit ib 0V and 1.1V respectively, bit ja 、bit jb are 1.1V and 0V respectively, and the first bit line VBL is the second reference voltage V 2ref is 0.5V, the i-th word line control signal WL i , j-th word line control signal WL j is 0V, the power supply voltage VDD_i of the i-th memory cell and the power supply voltage VDD_j of the j-th memory cell are 1.1V.

[0058] In the reset phase, the first reset voltage rst a The voltage is high voltage, the second reset voltage rst b The second sub-control unit S2 is turned on, and the first bit line VBL is initialized to the second reference voltage V 2ref At the same time, the j-th word line control signal WL j and the control signal Ctr of the jth control unit j are high, transistor P j4 Close, N j4 Turn on, the power supply voltage VDD_j of the jth storage unit and the node bit ja 、bit jb are initialized to V 1ref Voltage.

[0059] During the transmission phase, the first reset voltage rst a The voltage becomes low, the second reset voltage rst b = becomes high, and the second sub-control unit S2 is turned off. The i-th word line control signal WL i The voltage becomes high, and the j-th word line control signal WL j The voltage remains high, N i3 ,N j2 The two N-type transistors are turned on, and the voltage node bit of the i-th storage cell ia Drive the first bit line VBL. Due to the characteristics of the N-type transistor, the first bit line VBL will drop to 0 V. At the same time, the power supply voltage VDD_j of the j-th memory cell is maintained at the first reference voltage V 1ref , the first bit line VBL passes through N j2 Transistor driver bit ja , and in transistor Nj0 、N j1 、P j0 、P j1 The positive feedback of bit ja The voltage is maintained at 0V, bit jb The voltage is maintained at V 1ref .

[0060] At the end of data transmission, the i-th word line control signal WL i and the jth word line control signal WL j The voltage becomes low voltage, N i3 ,N j2 The transistors are all turned off. j The voltage becomes low, transistor P j4 Open, N j4 Turn off. VDD_ j voltage from V 1ref The voltage node bit of the jth memory cell rises to the high voltage first level voltage VDD. ja The voltage across transistor N j0 、N j1 、P j0 、P j1 Under the positive feedback effect, it becomes 0V, that is, 1 bit data 0 is successfully sent from the i-th storage unit to the j-th storage unit. jb The voltage across transistor N j0 、N j1 、P j0 、P j1 The voltage is maintained at 1.1V by the positive feedback.

[0061] According to the aforementioned data 0 is output from the i-th storage unit single-ended to the j-th storage unit, data 1 is output from the i-th storage unit single-ended to the j-th storage unit, and vice versa, so the timing of "data 0 is output from the j-th storage unit single-ended to the i-th storage unit, data 1 is output from the j-th storage unit single-ended to the i-th storage unit" will not be repeated.

[0062] In a preferred embodiment, a storage module with differential output is implemented, such as Figure 6a The example shown is a preferred example of a memory module with differential output. Different from a memory module with single-ended output, a group of bit lines includes a first bit line VBL. a , the second bit line VBL b The precharge circuit includes a differential transmission circuit, the differential transmission circuit includes a first bit line VBL a , the second bit line VBL bThe second sub-control unit S2 and the third sub-control unit S3 are electrically connected to each other to realize differential output. The second sub-control unit S2 and the third sub-control unit S3 can respectively include one or more transistor switches or transmission gates, for example, a 、rst b Preferably, the differential transmission circuit can be used to provide the second reference voltage V to the one or more groups of bit lines. 2ref By sharing the differential transmission circuit by multiple groups of bit lines, it is beneficial to further reduce the circuit scale.

[0063] In a preferred embodiment, in order to equalize the charging difference between the first bit line and the second bit line, a differential transmission circuit is further provided including a first sub-control unit S1. The first sub-control unit S1 may be, for example, one or more transistor switches, such as Figure 6a As shown, the reset control signal rst a 、rst b A pair of parallel PMOS and NMOS transistors are controlled to form a first sub-control unit S1. When the pre-charge difference between the first bit line and the second bit line is large, the first sub-control unit S1 can be controlled to realize the electrical connection between the first bit line and the second bit line, thereby balancing the pre-charge potential of the first bit line and the second bit line, and further improving the quality of data interaction.

[0064] Figure 6b The timing of example data being sent from the i-th storage unit to the j-th storage unit for storage is described in detail below. The timing of 1-bit data being transmitted from the i-th storage unit to the j-th storage unit and the operating states of the voltages at each node of the circuit during this process are described in detail below. The data transmission process may include four stages: the initial stage, the reset stage, the transmission stage, and the end of data transmission. During the data transmission process, the i-th storage unit that sends data needs to maintain a steady state, and the j-th storage unit that receives and stores data needs to switch to a metastable state to receive and store the data sent by the i-th storage unit. That is, during the reset and transmission stages, the j-th storage unit needs to switch the power supply voltage so that the power supply voltage is lower than the power supply voltage of the i-th storage unit, and during the initial and end of data transmission stages, the power supply voltage required by the j-th storage unit needs to be switched to be equal to the power supply voltage of the i-th storage unit to prepare for the next data interaction.

[0065] For the convenience of description, Figure 6b The following example shows a possible example of high and low voltages, where the low voltage is 0 V, the high voltage first level voltage VDD is 1.1 V, and the first reference voltage V 1ref is 0.5 V, but practical applications are not limited to these voltages.

[0066] Initial stage node bit ia、bit ib 1.1V and 0V respectively, bit j 、bit jb 0V and 1.1V respectively, the first bit line VBL a , the second bit line VBL b The second reference voltage V 2ref is 0.5V, the i-th word line control signal WL i , j-th word line control signal WL j is 0V, the power supply voltage VDD_i of the i-th memory cell and the power supply voltage VDD_j of the j-th memory cell are 1.1V.

[0067] In the reset phase, the first reset voltage rst is a high voltage, and the second reset voltage rst b The voltage is low, the first sub-control unit S1, the second sub-control unit S2, and the third sub-control unit S3 are turned on, and the first bit line VBL a and the second bit line VBL b Initialized to the second reference voltage V 2ref At the same time, the j-th word line control signal WL j and the control signal Ctr of the jth control unit j are high, transistor P j4 Close, N j4 Turn on, the power supply voltage VDD_j of the jth storage unit and the node bit ja 、bit jb are initialized to V 1ref Voltage.

[0068] During the transmission phase, the first reset voltage rst a The voltage becomes low, the second reset voltage rst b =WL becomes high, and the first sub-control unit S1, the second sub-control unit S2, and the third sub-control unit S3 are turned off. i The voltage becomes high, and the j-th word line control signal WL j The voltage remains high, N i2 ,N i3 ,N j2 ,N j3 The four N-type transistors are turned on, and the voltage node bit of the i-th storage cell ia and bit ib Drive the first bit line VBL respectively a and the second bit line VBL b Two transmission lines. Due to the characteristics of N-type transistors, the first bit line VBL a will rise to about 0.6 V, the second bit line VBL bIt will drop to 0 V. This voltage is only an example and is related to the threshold voltage of the N-type transistor and VDD. At the same time, the power supply voltage VDD_j of the j-th storage unit is kept at the first reference voltage V 1ref , the first bit line VBL a and the second bit line VBL b Through N j2 and N j3 Transistor driver bit j 、bit jb , and in transistor N j0 、N j1 、P j0 、P j1 Under the positive feedback effect, the voltage is maintained at 0V and V 1ref .

[0069] At the end of data transmission, the i-th word line control signal WL i and the jth word line control signal WL j The voltage becomes low voltage, N i2 ,N i3 ,N j2 ,N j3 The transistors are all turned off. j The voltage becomes low, transistor P j4 Open, N j4 Turn off. VDD_j voltage is V 1ref The voltage node bit of the jth memory cell rises to the high voltage first level voltage VDD. ja 、bit jb The voltage also changes to 1.1V and 0V, that is, 1 bit of data 1 is successfully sent from the i-th storage unit to the j-th storage unit for storage.

[0070] like Figure 6c As shown, this is the timing of 1-bit data 1 being stored in the j-th storage unit and sent to the ith storage unit. The principle is the same as the principle of 1-bit data being stored in the ith storage unit and sent to the j-th storage unit. The difference is that since the ith storage unit is used to receive and store data, the ith storage unit needs to switch the power supply voltage so that the power supply voltage is lower than the power supply voltage of the j-th storage unit during the reset and transmission stages, and the power supply voltage required by the ith storage unit needs to be switched to be equal to the power supply voltage of the j-th storage unit during the initial and data transmission end stages to prepare for the next data interaction needs.

[0071] The entire data transfer sequence described above only transmits one bit of data, with both the i-th and j-th storage cells storing one bit. In practice, a storage cell can store h bits, where h = 1, 2, 3, etc. The i-th and j-th control units can share the same h-bit storage unit to reduce area and cost.

[0072] Among them, V 1ref The voltage needs to be between the low voltage and high voltage of the circuit, which is 0V and 1.1V in the example in the figure. The entire transmission process takes advantage of the characteristic of charge transfer from high voltage to low voltage to ensure the direction of data transmission. Because of the use of low voltage difference transmission technology, the first bit line VBL a and the second bit line VBL b The voltage swing is small, which reduces the power consumption during the data transfer process, reduces the impact on the power supply network, and reduces the quantization noise of the image signal.

[0073] Figure 2 A case where n memory cells are connected to a group of bit lines is given. Through the above-mentioned data transmission technology, any one of the n memory cells can use the differential transmission method to send data to one or more other memory cells. At the same time, the memory cell used for data transmission can also receive and store data sent by any of the other one or more memory cells to complete multi-directional data interaction. Preferably, the i-th control unit is shared by the h-bit storage of the i-th memory cell to reduce area and cost. The j-th control unit is shared by the h-bit storage of the j-th memory cell to reduce area and cost. The differential transmission circuit is shared by multiple groups of bit lines to reduce area and cost.

[0074] In the embodiment, the implementation of a static random access memory cell is taken as an example, and the memory cell uses 5 and 6 transistors respectively, but this is only an example and the specific structure of the memory cell is not limited to this.

[0075] As another example of a memory cell, for example a latch, e.g. Figure 7 , which is a schematic diagram of the latch circuit structure, which includes two inverters, transistor P n0 、N n0 Forming an inverter, transistor P n1 、N n1 It forms an inverter and also includes three sub-control units S a 、S b 、S c , through three sub-control units to control the latch state of the latch. In the latch state: sub-control unit S a 、S b Disconnect, sub-control unit S c Closed; in non-latched state: Sub-control unit S cDisconnect, sub-control unit S a Closed, S b Also, in the read state included in the latch state: the sub-control unit S c Closed, sub-control unit S a Disconnect, S b closure.

[0076] According to the control of the latch state of the latch, the latch is used as a storage unit, and the data of any one of the storage units is sent to the remaining one or more storage units for storage. Moreover, any one of the remaining one or more storage units can also send data back to the storage unit for storage, thereby realizing a memory with multi-directional interaction between storage units.

[0077] In summary, the present invention controls the switching of storage units between latched and non-latched states, so that any storage unit of the memory can maintain a latched state to support data transmission, or maintain a non-latched state to support data reception and storage. Thus, within one data interaction cycle, the data of any storage unit on the same group of bit lines can be controlled to be read out and written into one or more storage units. At the same time, within one data interaction cycle, any storage unit can store the data of any other storage unit on the same group of bit lines, thereby realizing multi-directional interaction between storage units. In the application of image sensors, the multi-directional interaction of data between storage units can avoid the transmission and storage of data over long distances, avoid the use of large-scale drivers, and help reduce the size of the memory itself and the circuit using the memory. On the other hand, the voltage swing of the transmission signal on the entire transmission line can be greatly reduced, thereby providing the possibility of further reducing the power consumption of the memory and the circuit using the memory.

[0078] While the basic concepts have been described above, it will be apparent to those skilled in the art that the detailed disclosure is merely illustrative and does not limit the present invention. Although not explicitly described herein, those skilled in the art may make various modifications, improvements, and revisions to the present invention. Such modifications, improvements, and revisions are suggested in the present invention and remain within the spirit and scope of the exemplary embodiments of the present invention.

[0079] It should be understood that the embodiments described herein are intended only to illustrate the principles of the present invention. Other variations may also fall within the scope of the present invention. Therefore, by way of example and not limitation, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly described and illustrated herein.

Claims

1. A method for realizing multi-directional data interaction between storage units, characterized in that: For any i-th memory cell connected to a group of bit lines, the method controls the i-th memory cell to maintain a latched state, and controls the remaining one or more memory cells including the j-th memory cell connected to the same group of bit lines to maintain a non-latched state, so as to realize data reading from the i-th memory cell to the bit line, and writing from the bit line to the remaining one or more memory cells for storage; Furthermore, the method further controls the j-th memory cell to maintain a latched state, and controls the remaining one or more memory cells connected to the same group of bit lines, including the i-th memory cell, to maintain a non-latched state, so as to enable data to be read from the j-th memory cell to the bit line, and written from the bit line to the remaining one or more memory cells for storage; Wherein, i and j are integers, i≠j, and i≥1, j≥1.

2. The method according to claim 1, characterized in that The latched state includes a steady state, and the non-latched state includes a metastable state. The method controls the power supply voltage of several storage units for receiving data to be lower than the power supply voltage of the storage units for sending data, so that the storage units for sending data maintain a steady state and the several storage units for receiving data maintain a metastable state.

3. The method according to claim 2, characterized in that For any number of storage units of data interaction, within a data interaction cycle, There is only one storage unit sending data, and its power supply voltage maintains the first level voltage to maintain the steady state; The memory cells receiving data include a plurality of memory cells whose power supply voltage is switched from a first voltage level to a first reference voltage to achieve a metastable state so as to receive the data, and after receiving the data, the power supply voltage of the plurality of memory cells receiving the data is switched back from the first reference voltage to the first voltage level to maintain a steady state; The first reference voltage is lower than the first level voltage.

4. The method according to claim 2 or 3, characterized in that The method further includes providing a voltage control unit for controlling the switching of the power supply voltage of some or all of the memory cells between a first level voltage and a first reference voltage.

5. The method according to claim 4, characterized in that The voltage control unit is set to include a first type of transistor and a second type of transistor corresponding one to the storage unit; the control ends of the first type of transistor and the second type of transistor are controlled by the same control signal to select a first level voltage or a first reference voltage as a power supply voltage to be provided to the storage unit.

6. The method according to claim 2, characterized in that The group of bit lines is configured to include a first bit line to implement single-ended transmission; or the group of bit lines is configured to include a first bit line and a second bit line to implement differential transmission.

7. The method according to claim 6, characterized in that A first sub-control unit for controlling the electrical connection state of the first bit line and the second bit line is further provided between the first bit line and the second bit line.

8. The method according to claim 1, characterized in that The memory is further configured to include a precharge circuit for providing a second reference voltage to the one or more groups of bit lines.

9. The method according to claim 8, characterized in that The precharge circuit is configured to include at least a second sub-control unit and a third sub-control unit, respectively configured to control the second reference voltage to be provided to the first bit line and the second bit line.

10. The method according to any one of claims 3 to 9, characterized in that The first reference voltage is less than a first level voltage, the second reference voltage is less than or equal to the first level voltage, and the first reference voltage is equal to or unequal to the second reference voltage.

11. The method according to claim 10, characterized in that The first level voltage is 1.1 V, and the first and second reference voltages are 0.5 V.

12. The method according to claim 1, characterized in that The storage unit is configured to include a static storage unit or a latch.

13. A memory capable of multi-directional data exchange between storage units, characterized in that: The memory includes: m memory modules, at least one memory module including a first memory cell, ..., an nth memory cell connected to the same group of bit lines, m ≥ 1, n ≥ 2, and m and n are integers; There is at least one storage module, at least two storage units of which can be controlled to switch between a latched state and a non-latched state, so as to achieve multi-directional interaction of data between the storage units.

14. The memory capable of multi-directional interaction between storage units according to claim 13, characterized in that: The multi-directional interaction method is implemented according to the method for multi-directional interaction of data between storage units according to any one of claims 1 to 12.

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