Semiconductor layout and memory layout
By setting a word line driver layout and bonding pads in a semiconductor layout, the problem of limited word line driver arrangement is solved, the driving capability and connection simplicity are improved, and the manufacturing process and electrical performance are optimized.
Patent Information
- Application Number
- CN202510884526.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-27
- Publication Date
- 2025-09-26
AI Technical Summary
As the size of memory cell devices shrinks, the arrangement and driving capability of word line drivers are limited by the word line spacing, resulting in reduced driving capability.
A semiconductor layout is provided, including multiple word line driver layouts and bonding pad patterns. The word line drivers are no longer arranged between memory arrays. The word line drivers are connected to the word lines through bonding pads, thereby optimizing the layout and manufacturing process.
The driving capability of the word line driver is improved, the connection is simplified, the arrangement restriction caused by the word line spacing is avoided, and the manufacturing process and electrical performance are optimized.
Smart Images
Figure CN120708666A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor layout and a memory layout. Background Art
[0002] Currently, wordline drivers are arranged between memory arrays, and their placement is affected by the spacing between wordlines. As technology advances, the size of the devices that make up memory cells continues to shrink, and the spacing between wordlines is also decreasing. This requires a corresponding reduction in the size of wordline drivers, limiting their placement and routing between them and other devices. This reduces their driving capability. Summary of the Invention
[0003] The following is a summary of the subject matter of the detailed description of the present invention. This summary is not intended to limit the scope of protection of the claims.
[0004] The present invention provides a semiconductor layout and a memory layout.
[0005] According to a first aspect of an embodiment of the present invention, a semiconductor layout is provided, comprising:
[0006] a plurality of word line driver layouts, each of the word line driver layouts comprising a plurality of cell regions of an array, each of the cell regions being provided with a plurality of word line drivers;
[0007] A plurality of bonding pad patterns are arranged on the word line driver layout and are arranged one-to-one corresponding to the word line drivers. The bonding pad patterns are used to set bonding pads, and the bonding pads are used to connect the corresponding word line drivers with corresponding word lines.
[0008] According to some embodiments of the present invention, the unit area is provided with:
[0009] An N-type transistor region layout, wherein the N-type transistor region layout is used to form a plurality of N-type transistors of the word line driver;
[0010] A P-type transistor region layout, wherein the P-type transistor region layout is used to form a plurality of P-type transistors of the word line driver;
[0011] The N-type transistor region layout and the P-type transistor region layout are arranged at intervals along a first direction, a portion of the bonding pad pattern is located on the N-type transistor region layout, and another portion of the bonding pad pattern is located on the P-type transistor region layout.
[0012] According to some embodiments of the present invention, the N-type transistor region layout includes:
[0013] a first active pattern extending along a second direction, wherein the second direction is arranged at an angle to the first direction;
[0014] a plurality of first gate patterns, wherein the plurality of first gate patterns are arranged at intervals on the first active pattern and extend along the first direction;
[0015] a plurality of first conductive contact patterns, each of the first conductive contact patterns being disposed on one of the first gate patterns; and / or,
[0016] The P-type transistor region layout includes:
[0017] a second active pattern extending along the second direction;
[0018] a plurality of second gate patterns, wherein the plurality of second gate patterns are arranged at intervals on the second active pattern and extend along the first direction;
[0019] A plurality of second conductive contact patterns are provided, and each second conductive contact pattern is disposed on one second gate pattern.
[0020] According to some embodiments of the present invention, the unit region includes two word line drivers, and the two bonding pad patterns corresponding to the two word line drivers are respectively located on the N-type transistor region layout and the P-type transistor region layout.
[0021] According to some embodiments of the present invention, the bonding pad pattern located on the N-type transistor region layout overlaps at least partially with the two first gate patterns in the middle;
[0022] The bonding pad pattern located on the P-type transistor region layout overlaps at least partially with the two second gate patterns.
[0023] According to some embodiments of the present invention, the unit area is provided with:
[0024] A first pressure pattern is provided on a side of the N-type transistor region layout away from the P-type transistor region layout, and is used to set a voltage for the well region where the N-type transistor region layout is located;
[0025] The second pressure pattern is arranged on a side of the P-type transistor region layout away from the N-type transistor region layout, and is used to set a voltage for the well region where the P-type transistor region layout is located.
[0026] According to some embodiments of the present invention, the unit area is provided with:
[0027] a first isolation pattern, disposed between the first pressure pattern and the N-type transistor region layout, and extending along a second direction, wherein the second direction is disposed at an angle to the first direction;
[0028] a second isolation pattern, disposed between the second pressure pattern and the P-type transistor region layout, and extending along the second direction;
[0029] The third isolation pattern is arranged between the N-type transistor region layout and the P-type transistor region layout and extends along the second direction.
[0030] According to some embodiments of the present invention, the unit area is provided with:
[0031] The fourth isolation pattern is arranged on both sides of the P-type transistor region where the second isolation pattern and the third isolation pattern are not arranged, and extends along the first direction.
[0032] According to some embodiments of the present invention, the semiconductor layout further includes:
[0033] A plurality of first word line control signal generating module patterns, and the word line driver board Figure 1 A corresponding arrangement is used to set a first word line control signal generating module, the first word line control signal generating module is used to provide a first word line control signal for the word line driver, and the first word line control signal generating module pattern is adjacent to the corresponding word line driver layout;
[0034] and / or,
[0035] A plurality of second word line control signal generating module patterns are connected to the word line driver board Figure 1 A corresponding setting is used to set a second word line control signal generating module, which is used to provide a second word line control signal for the word line driver. The second word line control signal generating module pattern is set adjacent to the corresponding word line driver layout.
[0036] According to some embodiments of the present invention, the second word line control signal generating module pattern and the word line driver layout are arranged at intervals along a first direction, and the first word line control signal generating module pattern and the word line driver layout are arranged at intervals along a second direction, wherein the first direction and the second direction are set at an angle.
[0037] According to a second aspect of an embodiment of the present invention, a memory layout is provided. The memory layout includes any semiconductor layout as described in the first aspect of the present invention.
[0038] A semiconductor layout provided by an embodiment of the present invention includes multiple wordline driver layouts, each wordline driver layout including multiple cell regions of an array, each cell region being provided with multiple wordline drivers. Multiple bonding pad patterns are provided on the wordline driver layouts, corresponding one-to-one with the wordline drivers, for providing bonding pads that connect corresponding wordline drivers to corresponding wordlines. By providing dedicated wordline driver layouts, wordline drivers are no longer arranged between memory arrays, making their size and arrangement unaffected by wordline spacing, thereby improving their driving capability. Furthermore, by connecting wordline drivers and wordlines via bonding pads provided on the wordline driver layouts, the connection between the wordline drivers and wordlines is simplified and unaffected by wordline spacing.
[0039] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the embodiments of the present invention. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present invention, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.
[0041] Figure 1 The figure is a schematic diagram showing a semiconductor layout according to an exemplary embodiment.
[0042] Figure 2 FIG. 1 is a schematic diagram showing a unit area according to an exemplary embodiment.
[0043] Figure 3 A word line driver is shown according to an exemplary embodiment.
[0044] Figure 4 is a schematic diagram showing a unit area according to another exemplary embodiment.
[0045] Figure 5 is a schematic diagram showing a unit area according to another exemplary embodiment.
[0046] Figure 6 is a schematic diagram showing a unit area according to another exemplary embodiment.
[0047] Figure 7 is a schematic diagram of a semiconductor layout according to another exemplary embodiment.
[0048] Figure 8is a circuit diagram of a word line driver according to an exemplary embodiment.
[0049] Figure 9 FIG. 1 is a circuit diagram of a word line driver in a unit area according to an exemplary embodiment.
[0050] Figure 10 According to an exemplary embodiment, Figure 9 Schematic diagram of the layout of the unit area corresponding to the circuit schematic in .
[0051] In the figure: 1: word line driver layout; 11: cell area; 111: N-type transistor area layout; 1111: first active pattern; 1112: first gate pattern; 1113: first conductive contact pattern; 1114: third conductive contact pattern; 1115: fourth conductive contact pattern; 1116: fifth conductive contact pattern; 1117: sixth conductive contact pattern; 1118: seventh conductive contact pattern; 112: P-type transistor area layout; 1121: second active pattern; 1122: second gate pattern; 112 3: Second conductive contact pattern; 1124: Eighth conductive contact pattern; 1125: Ninth conductive contact pattern; 1126: Tenth conductive contact pattern; 113: First pressure pattern; 114: Second pressure pattern; 115: First isolation pattern; 116: Second isolation pattern; 117: Third isolation pattern; 118: Fourth isolation pattern; 2: Bonding pad pattern; 3: First word line control signal generation module pattern; 4: Second word line control signal generation module pattern; x: First direction; y: Second direction; GrDecN <0> 、GrDecN <1> : first word line control signal; N1: second transistor; N2: third transistor; P1: first transistor; PhDec <0> 、PhDecN <0> 、PhD <1> 、PhDecN <1> 、PhD <2> 、PhDecN <2> ...PhDec <31> 、PhDecN <31> : Second word line control signal; SWD0-SWD63: word line driver; WL0-WL63: word line. DETAILED DESCRIPTION
[0052] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be arbitrarily combined with each other. It should also be understood that the term "and / or" used herein refers to any or all possible combinations of one or more associated listed items.
[0053] Currently, wordline drivers are arranged between memory arrays, and their placement is affected by the spacing between wordlines. As technology advances, the size of the devices that make up memory cells continues to shrink, and the spacing between wordlines is also decreasing. This requires a corresponding reduction in the size of wordline drivers, limiting their placement and routing between them and other devices. This reduces their driving capability.
[0054] Based on this, the present invention provides a semiconductor layout. The semiconductor layout includes multiple wordline driver layouts, each wordline driver layout including multiple cell regions of an array, each cell region being provided with multiple wordline drivers. Multiple bonding pad patterns are provided on the wordline driver layouts, corresponding one-to-one with the wordline drivers, for providing bonding pads, which are used to connect corresponding wordline drivers to corresponding wordlines. By providing a dedicated wordline driver layout, the wordline drivers are no longer arranged between the memory arrays, so that the size and arrangement of the wordline drivers are not affected by the spacing between the wordlines, and the driving capability of the wordline drivers is also improved. Moreover, by connecting the wordline drivers and wordlines via bonding pads provided on the wordline driver layouts, the connection between the wordline drivers and wordlines is simplified and is not affected by the spacing between the wordlines.
[0055] An exemplary embodiment of the present invention provides a semiconductor layout, such as Figure 1 As shown, the semiconductor layout includes multiple word line driver boards Figure 1 and multiple bonding pad patterns 2. Each word line driver board Figure 1 Each of the plurality of cell regions 11 of the array is provided with a plurality of word line drivers. A plurality of bonding pad patterns 2 are provided on the word line driver board. Figure 1 The bonding pad pattern 2 is used to set a bonding pad, and the bonding pad is used to connect the corresponding word line driver with the corresponding word line.
[0056] A wordline driver is a key circuit component in memory, controlling the activation or deactivation of wordlines. For example, during read and write operations, the wordline driver activates the corresponding wordline based on a wordline control signal, thereby selecting the memory cell corresponding to that wordline.
[0057] The bonding pad is a metal contact point on the surface of the integrated circuit chip, which is used to achieve electrical connection and mechanical fixation between the chip and the external package. In this embodiment, the bonding pad pattern is set in a one-to-one correspondence with the word line driver, and each bonding pad is used to electrically connect the corresponding word line driver and the corresponding word line, so that the word line driver can be used to control the activation or deactivation of the corresponding word line. The semiconductor layout in this embodiment can be the layout of a wafer, and the word lines and storage cells can be set on another wafer. The two wafers are packaged by wafer-on-wafer (WoW) technology, and the word line driver is electrically connected to the word line on the other wafer through the bonding pad. WOW technology is an advanced semiconductor packaging technology that achieves ultra-high density interconnection by directly stacking and bonding two or more wafers.
[0058] In some examples, each word line driver board Figure 1 are arranged adjacent to at least one word line control signal generating module pattern, the word line control signal generating module pattern is used to set the word line control signal generating module, the word line control signal generating module is used to provide the word line driver board Figure 1 The word line driver in the Figure 1 The word line driver in the control unit controls the activation or deactivation of the corresponding word line. The word line driver is arranged adjacent to the word line control signal generating module that controls it, which can shorten the wiring length between the word line control signal generating module and the word line driver and reduce the wiring complexity.
[0059] In this embodiment, by providing a dedicated word line driver layout, the word line driver is no longer arranged between the memory arrays, so that the size and arrangement of the word line driver are not affected by the word line spacing, and the driving capability of the word line driver is also improved. In addition, by connecting the word line driver and the word line through the bonding pad provided on the word line driver layout, the connection between the word line driver and the word line can be simplified and not affected by the word line spacing.
[0060] In some exemplary embodiments provided by the present invention, Figure 2 As shown, an N-type transistor region layout 111 and a P-type transistor region layout 112 are provided in the cell region 11. The N-type transistor region layout 111 is used to form a plurality of N-type transistors of the word line driver. The P-type transistor region layout 112 is used to form a plurality of P-type transistors of the word line driver. The N-type transistor region layout 111 and the P-type transistor region layout 112 are arranged along a first direction (e.g. Figure 2A portion of the bonding pad pattern 2 is located on the N-type transistor region layout 111, and another portion of the bonding pad pattern 2 is located on the P-type transistor region layout 112.
[0061] Figure 3 A word line driver is shown. The word line driver includes a first transistor P1, a second transistor N1, and a third transistor N2. The first transistor P1 is a P-type transistor, and the second transistor N1 and the third transistor N2 are both N-type transistors. The gate of the first transistor P1 and the gate of the second transistor N1 are both electrically connected to a first word line control signal. The second word line control signal includes two mutually inverted sub-signals, one of which is electrically connected to the source of the first transistor P1, and the other is electrically connected to the gate of the third transistor N2. The drain of the first transistor P1, the drain of the second transistor N1, and the drain of the third transistor N2 are all electrically connected to the word line via corresponding bonding pads of the word line driver. The source of the second transistor N1 and the source of the third transistor N2 are both electrically connected to a vwln power supply, which is used to shut down the word line electrically connected to the word line driver. The voltage of the vwln power supply can be a ground voltage or other voltage that can shut down the word line electrically connected to the word line driver.
[0062] In some examples, each unit region 11 includes two Figure 3 The word line drivers shown in FIG. The second transistor N1 and the third transistor N2 of the two word line drivers are both formed in an N-type transistor region layout 111, and the first transistor P1 of the two word line drivers is both formed in a P-type transistor region layout 112. The N-type transistor region layout 111 and the P-type transistor region layout 112 are arranged alternately along a first direction. The bonding pad pattern 2 corresponding to one of the word line drivers is located on the N-type transistor region layout 111, while the bonding pad pattern 2 corresponding to the other word line driver is located on the P-type transistor region layout 112.
[0063] In other examples, each cell region 11 includes a number of word line drivers other than two, and the word line drivers are Figure 3 The word line driver shown is different, and the positions of the plurality of bonding pad patterns 2 are different from those in the above example.
[0064] In this embodiment, by setting an N-type transistor area layout and a P-type transistor area layout in the unit area, the layout can be regularized, the manufacturing process can be simplified, and the performance of the manufactured semiconductor device can be optimized. In addition, dividing the N-type transistor area layout and the P-type transistor area layout is conducive to the arrangement of the bonding pad pattern. The bonding pad patterns are respectively located on the two transistor area layouts, which can make the layout regular and save the layout area.
[0065] In some exemplary embodiments provided by the present invention, Figure 2 As shown, the cell region 11 includes two word line drivers, and the two bonding pad patterns 2 corresponding to the two word line drivers are respectively located on the N-type transistor region layout 111 and the P-type transistor region layout 112 .
[0066] In this embodiment, the two bonding pad patterns are respectively located on the N-type transistor region layout and the P-type transistor region layout, which can make the layout regular and save the layout area.
[0067] In some exemplary embodiments provided by the present invention, Figure 4 As shown, the N-type transistor region layout 111 includes a first active pattern 1111, a plurality of first gate patterns 1112, and a plurality of first conductive contact patterns 1113. The first active pattern 1111 is arranged along the second direction (eg Figure 4 The second direction extends in the y direction and the first direction (e.g. Figure 4 The first gate patterns 1112 are arranged at intervals on the first active pattern 1111 and extend along the first direction. Each first conductive contact pattern 1113 is arranged on one first gate pattern 1112.
[0068] Active patterns are areas defined on a silicon substrate through photolithography and doping processes to form the source, drain, and channel of a transistor. In semiconductor layouts, active patterns can appear as closed polygons, such as rectangles, or complex shapes.
[0069] A first active pattern 1111 is provided in the N-type transistor region layout 111. A plurality of first gate patterns 1112 are spaced apart and provided on the first active pattern 1111. The extending direction of the first gate pattern 1112 forms an angle with the extending direction of the first active pattern 1111. Figure 4 As shown, the angle between the first direction (i.e., the extension direction of the first gate pattern 1112) and the second direction (i.e., the extension direction of the first active pattern 1111) is 90°. Each first gate pattern 1112 corresponds to a first conductive contact pattern 1113. The first gate pattern 1112 can be used to form a gate of an N-type transistor, and the first conductive contact pattern 1113 can be used to form a conductive contact structure corresponding to the gate of the N-type transistor. The conductive contact structure is used to electrically connect the gate of the N-type transistor to an external device.
[0070] In some exemplary embodiments provided by the present invention, Figure 4 As shown, the P-type transistor region layout 112 includes a second active pattern 1121, a plurality of second gate patterns 1122, and a plurality of second conductive contact patterns 1123. The second active pattern 1121 is arranged along the second direction (eg Figure 4A plurality of second gate patterns 1122 are arranged on the second active pattern 1121 at intervals and extend along the first direction (eg, Figure 4 Each second conductive contact pattern 1123 is disposed on one second gate pattern 1122 .
[0071] A second active pattern 1121 is provided in the P-type transistor region layout 112. A plurality of second gate patterns 1122 are spaced apart and provided on the second active pattern 1121. The extending direction of the second gate pattern 1122 forms an angle with the extending direction of the second active pattern 1121. Figure 4 As shown, the angle between the extension direction of the second gate pattern 1122, i.e., the first direction, and the extension direction of the second active pattern 1121, i.e., the second direction, is 90°. Each second gate pattern 1122 corresponds to a second conductive contact pattern 1123. The second gate pattern 1122 can be used to form a gate of a P-type transistor, and the second conductive contact pattern 1123 can be used to form a conductive contact structure corresponding to the gate of the P-type transistor. The conductive contact structure is used to electrically connect the gate of the P-type transistor to an external device.
[0072] In some exemplary embodiments provided by the present invention, Figure 4 As shown, the bonding pad pattern 2 located on the N-type transistor region layout 111 overlaps at least partially with the two first gate patterns 1112 in the middle, and the bonding pad pattern 2 located on the P-type transistor region layout 112 overlaps at least partially with the two second gate patterns 1122.
[0073] In some examples, the unit region 11 includes two Figure 3 In the word line driver shown, the N-type transistor region layout 111 includes four first gate patterns 1112, and the P-type transistor region layout 112 includes two second gate patterns 1122. The bonding pad pattern 2 located on the N-type transistor region layout 111 overlaps at least partially with the two first gate patterns 1112 in the middle, and the bonding pad pattern 2 located on the P-type transistor region layout 112 overlaps at least partially with the two second gate patterns 1122. The two bonding pad patterns 2 are aligned along a first direction (e.g., Figure 4 x-direction in align settings.
[0074] In this embodiment, the two bonding pad patterns are arranged regularly, which is beneficial to the optimization of the manufacturing process and the improvement of the electrical performance of the semiconductor device.
[0075] In some exemplary embodiments provided by the present invention, Figure 5As shown, the cell region 11 is provided with a first pressure pattern 113 and a second pressure pattern 114. The first pressure pattern 113 is provided on the side of the N-type transistor region layout 111 away from the P-type transistor region layout 112, and is used to set a voltage for the well region where the N-type transistor region layout 111 is located. The second pressure pattern 114 is provided on the side of the P-type transistor region layout 112 away from the N-type transistor region layout 111, and is used to set a voltage for the well region where the P-type transistor region layout 112 is located.
[0076] In semiconductor layout, the pressure pattern is a graphic structure used to provide a stable voltage bias for the well region or substrate of the transistor. Its core function is to ensure the normal operation of the device and prevent reliability issues caused by potential fluctuations, such as latch-up effect and noise interference.
[0077] In this embodiment, the first pressure pattern 113 sets a stable voltage for the well region where the N-type transistor region layout 111 is located, ensuring stable operation of the N-type transistor formed in the N-type transistor region layout 111 and avoiding parasitic effects. The second pressure pattern 114 sets a stable voltage for the P-type transistor region layout 112, ensuring stable operation of the P-type transistor formed in the P-type transistor region layout 111 and avoiding parasitic effects.
[0078] The first pressure pattern 113 is arranged on the side of the N-type transistor region layout 111 away from the P-type transistor region layout 112, and the second pressure pattern 114 is arranged on the side of the P-type transistor region layout 112 away from the N-type transistor region layout 111. In other words, the second pressure pattern 114, the P-type transistor region layout 112, the N-type transistor region layout 111 and the first pressure pattern 113 are arranged along the first direction (e.g. Figure 5 The first pressure pattern 113 and the second pressure pattern 114 are arranged in sequence along the x-direction in the N-type transistor region layout 111 and the P-type transistor region layout 112. The pressure applied to the N-type transistor region layout 111 and the P-type transistor region layout 112 can be physically separated, cutting off the trigger path of the parasitic thyristor. The pressure applied on both sides can clearly define the well region boundary and prevent doping diffusion overlap during manufacturing.
[0079] In this embodiment, a first pressure pattern and a second pressure pattern are set to set stable voltages for the well region where the N-type transistor area layout is located and the well region where the P-type transistor area layout is located, respectively, to ensure stable operation of the transistors. At the same time, the two pressure patterns are located on both sides of the two transistor area layouts, which can prevent the doping diffusion from overlapping during manufacturing and cut off the trigger path of the parasitic thyristor.
[0080] In some exemplary embodiments provided by the present invention, Figure 6As shown, a first isolation pattern 115, a second isolation pattern 116 and a third isolation pattern 117 are provided in the cell region 11. The first isolation pattern 115 is provided between the first pressure pattern 113 and the N-type transistor region layout 111 and is provided along the second direction (eg Figure 6 The second direction extends in the y direction and the first direction (e.g. Figure 6 The second isolation pattern 116 is disposed between the second pressure pattern 114 and the P-type transistor region layout 112 and extends along the second direction. The third isolation pattern 117 is disposed between the N-type transistor region layout 111 and the P-type transistor region layout 112 and extends along the second direction.
[0081] In some examples, such as Figure 6 As shown, the angle between the first direction and the second direction is 90°.
[0082] In semiconductor layouts, isolation patterns are key structures used to electrically isolate different devices or components in order to prevent current leakage or signal interference between adjacent components.
[0083] A first isolation pattern 115 is provided between the first pressure pattern 113 and the N-type transistor region layout 111. The isolation structure formed on the first isolation pattern 115 can electrically isolate the pressure device formed on the first pressure pattern 113 from the N-type transistor formed on the N-type transistor region layout 111, preventing current leakage or signal interference. A second isolation pattern 116 is provided between the second pressure pattern 114 and the P-type transistor region layout 112. The isolation structure formed on the second isolation pattern 116 can electrically isolate the pressure device formed on the second pressure pattern 114 from the P-type transistor formed on the P-type transistor region layout 112, preventing current leakage or signal interference. A third isolation pattern 117 is provided between the N-type transistor region layout 111 and the P-type transistor region layout 112. The isolation structure formed on the third isolation pattern 117 can electrically isolate the N-type transistor formed on the N-type transistor region layout 111 from the P-type transistor formed on the P-type transistor region layout 112, thereby preventing a latch-up effect from occurring between the N-type transistor formed on the N-type transistor region layout 111 and the P-type transistor formed on the P-type transistor region layout 112. The latch-up effect refers to a phenomenon in which a low-impedance path is accidentally triggered by a parasitic PNPN structure inside the chip, resulting in a short circuit between the power supply and the ground, causing high current, heat, and even permanent damage. In some examples, the isolation structure formed on the first isolation pattern 115, the isolation structure formed on the second isolation pattern 116, and the isolation structure formed on the third isolation pattern 117 can all be isolation structures formed using local oxidation isolation technology or isolation structures formed using shallow trench isolation technology. Local oxidation isolation technology is a technique for isolating devices by growing a silicon dioxide insulating layer through selective thermal oxidation. Shallow trench isolation technology is a technique for etching shallow trenches in a silicon substrate and filling them with silicon dioxide or high-density plasma oxide. In other examples, the isolation structure formed on the first isolation pattern 115, the isolation structure formed on the second isolation pattern 116, and the isolation structure formed on the third isolation pattern 117 can be isolation structures formed using other isolation technologies.
[0084] like Figure 6 As shown, a fourth isolation pattern 118 is provided in the cell region 11. The fourth isolation pattern 118 is provided on both sides of the P-type transistor region layout 112 where the second isolation pattern 116 and the third isolation pattern 117 are not provided, and extends along the first direction.
[0085] Depend on Figure 6It can be seen that the fourth isolation pattern 118 consists of two parts. A part of the fourth isolation pattern 118, the P-type transistor area layout 112 and another part of the fourth isolation pattern 118 are arranged in sequence along the second direction. The fourth isolation pattern 118 is set, and the isolation structure formed on the fourth isolation pattern 118 can electrically isolate the P-type transistor formed on the P-type transistor area layout 112 and the devices formed on the adjacent device layouts on both sides of the P-type transistor area layout 112 along the second direction to prevent current leakage or signal interference. In some examples, the isolation structure formed on the fourth isolation pattern 118 is an isolation structure formed using local oxidation isolation technology, or an isolation structure formed using shallow trench isolation technology. In other examples, the isolation structure formed on the fourth isolation pattern 118 can be an isolation structure formed using other isolation technologies.
[0086] In this embodiment, isolation patterns are formed between the N-type transistor region layout and the P-type transistor region layout, between the N-type transistor region layout and other adjacent device layouts, and between the P-type transistor region layout and other adjacent device layouts, which can electrically isolate different devices or components and prevent current leakage or signal interference between adjacent components.
[0087] In some exemplary embodiments provided by the present invention, Figure 7 As shown, the semiconductor layout further includes a plurality of first word line control signal generating module patterns 3. The plurality of first word line control signal generating module patterns 3 and the word line driver board Figure 1 One-to-one correspondence is set, which is used to set the first word line control signal generating module, which is used to provide the first word line control signal for the word line driver, and the first word line control signal generating module pattern 3 is connected to the corresponding word line driver board Figure 1 Adjacent settings. For example, Figure 7 In the embodiment shown, the first word line control signal generating module pattern 3 and the word line driver board Figure 1 Along the second direction (eg Figure 7 The y direction in the figure is arranged at intervals.
[0088] In some exemplary embodiments provided by the present invention, Figure 7 As shown, the semiconductor layout further includes a plurality of second word line control signal generating module patterns 4. The plurality of second word line control signal generating module patterns 4 and the word line driver board Figure 1 One-to-one correspondence is set, which is used to set the second word line control signal generating module, which is used to provide the second word line control signal for the word line driver, and the second word line control signal generating module pattern 4 is connected to the corresponding word line driver board. Figure 1 Adjacent settings. For example, Figure 7 In the embodiment shown, the second word line control signal generating module pattern 4 and the word line driver board Figure 1 Along the first direction (eg Figure 7 The first direction and the second direction are arranged at an angle.
[0089] In some examples, such as Figure 7 As shown, the angle between the first direction and the second direction is 90°.
[0090] Each first word line control signal generating module can be a corresponding word line driver board Figure 1 The word line driver provided in the embodiment provides a plurality of first word line control signals, and each second word line control signal generating module can generate a plurality of first word line control signals for the corresponding word line driver. Figure 1 The word line driver provided in the embodiment provides a plurality of second word line control signals, and the product of the number of the first word line control signals and the number of the second word line control signals is the same as the number of word line drivers. Figure 1 1024 word line drivers are set in the system, the corresponding first word line control signal generating module provides 32 first word line control signals, and the corresponding second word line control signal generating module provides 32 second word line control signals. In other examples, each word line driver version Figure 1 The number of word line drivers set, the number of first word line control signals provided by the corresponding first word line control signal generating module, and the number of second word line control signals provided by the corresponding second word line control signal generating module may be other numbers.
[0091] Currently, as memory capacity increases, wordline lengths also increase. Line delays caused by excessively long wordlines have become a significant factor limiting the operating speed of memory. By dividing a main wordline into multiple wordlines, each wordline connects to fewer memory cells, shortening the wordline length and effectively addressing the issue of line delays affecting memory operating speed caused by excessively long wordlines. In this embodiment, the first wordline control signal can be a main wordline control signal, serving as an enable signal for multiple wordline drivers to determine whether to allow the multiple wordlines connected to these drivers to be activated. When the main wordline control signal is activated, it indicates that the memory cells connected to these wordlines may be accessed. In this embodiment, the second wordline control signal can be a wordline control signal, used to directly control at least one wordline driver to activate or deactivate the wordlines connected to the wordline drivers.
[0092] Figure 8 A circuit schematic diagram of a word line driver in some embodiments is shown. Figure 8 , 64 word line drivers SWD0-SWD63 are shown, each word line driver is as follows Figure 3The word line drivers shown in FIG. Word line drivers SWD0-SWD63 correspond one-to-one to word lines WL0-WL63. The drain of each word line driver's first transistor P1, the drain of its second transistor N1, and the drain of its third transistor N2 are electrically connected to the corresponding word line, controlling the activation or deactivation of that word line. The source of each word line driver's second transistor N1 and the source of its third transistor N2 are electrically connected to a vwln power supply, which is used to deactivate the word line electrically connected to that word line driver. The vwln power supply can be ground or another voltage that can deactivate the word line electrically connected to that word line driver.
[0093] The gates of the first transistors P1 and the second transistors N1 of the 32 even-numbered word line drivers SWD0, SWD2, SWD4, ..., SWD62 are both connected to the first word line control signal GrDecN. <0> , the first word line control signal GrDecN <0> Used as the enable signal of word line drivers SWD0, SWD2, SWD4...SWD62 to determine whether to allow the corresponding word lines WL0, WL2, WL4...WL62 to be activated. <0> When the first word line control signal GrDecN is in the active state, the corresponding word lines WL0, WL2, WL4...WL62 are allowed to be activated, and the memory cells connected to the word lines WL0, WL2, WL4...WL62 may be accessed. <0> When it is in the closed state, the corresponding word lines WL0, WL2, WL4...WL62 are not allowed to be activated, and the memory cells connected to the word lines WL0, WL2, WL4...WL62 cannot be accessed.
[0094] The gates of the first transistors P1 and the second transistors N1 of the odd-numbered 32 word line drivers SWD1, SWD3, SWD5, ..., SWD63 are both connected to the first word line control signal GrDecN. <1> , the first word line control signal GrDecN <1> Used as the enable signal of word line drivers SWD1, SWD3, SWD5...SWD63 to determine whether to allow the corresponding word lines WL1, WL3, WL5...WL63 to be activated. <1> When the first word line control signal GrDecN is in the active state, the corresponding word lines WL1, WL3, WL5 ... WL63 are allowed to be activated, and the memory cells connected to the word lines WL1, WL3, WL5 ... WL63 may be accessed. <1> When it is in the closed state, the corresponding word lines WL1, WL3, WL5...WL63 are not allowed to be activated, and the memory cells connected to the word lines WL1, WL3, WL5...WL63 cannot be accessed.
[0095] First word line control signal GrDecN <0> and the first word line control signal GrDecN <1> This setting ensures that adjacent odd-numbered word lines and even-numbered word lines are not activated at the same time, which can reduce crosstalk and noise.
[0096] Each second word line control signal includes two inverted sub-signals, one of which is electrically connected to the source of the first transistor P1 of the word line driver, and the other is electrically connected to the gate of the third transistor N2 of the same word line driver.
[0097] Among the word line drivers SWD0-SWD63, an adjacent odd-numbered word line driver and an adjacent even-numbered word line driver correspond to a second word line control signal. Figure 8 As shown, the word line driver SWD0 and the word line driver SWD1 correspond to a second word line control signal, and the second word line control signal includes two sub-signals PhDec which are mutually inverted signals. <0> and PhDDecN <0> , sub-signal PhDec <0> The source of the first transistor P1 of the word line driver SWD0 and the source of the first transistor P1 of the word line driver SWD1 are connected, and the sub-signal PhDecN <0> Connecting the gate of the third transistor N2 of word line driver SWD0 and the gate of the third transistor N2 of word line driver SWD1, the second word line control signal is used to directly control the corresponding word line driver to activate or deactivate WL0 or WL1. Similarly, word line driver SWD2 and word line driver SWD3 correspond to a second word line control signal, word line driver SWD4 and word line driver SWD5 correspond to a second word line control signal... word line driver SWD62 and word line driver SWD63 correspond to a second word line control signal. The first word line control signal GrDecN <0> and the first word line control signal GrDecN <1> The two adjacent odd-numbered word lines and even-numbered word lines are not activated at the same time. Therefore, an adjacent odd-numbered word line driver and an adjacent even-numbered word line driver correspond to the same second word line control signal. Compared with each word line driver corresponding to a second word line control signal, the number of second word line control signals can be reduced. <0> and PhDDecN <0> The second word line control signal includes a sub-signal PhDec <1> and PhDDecN <1> The second word line control signal includes a sub-signal PhDec <2> and PhDDecN <2> The second word line control signal ... and includes a sub-signal PhDec <31> and PhDDecN <31> The second word line control signals will not be activated at the same time. Only one second word line control signal will be in the active state at the same time. Therefore, only one word line will be activated at the same time, which can ensure that multiple word lines will not be activated at the same time, effectively preventing data from interfering with each other.
[0098] In some examples, each cell region 11 includes two word line drivers, and the circuit diagram is as shown in FIG. Figure 9 As shown. Figure 9 As shown, the two word line drivers SW0 and SW1 in the same cell region 11 correspond to different first word line control signals and the same second word line control signals. This ensures that the two word line drivers in the same cell region 11 are not driven simultaneously, and that the two word lines corresponding to the two word line drivers in the same cell region 11 are not activated simultaneously, thereby reducing crosstalk and noise and reducing the number of second word line control signals.
[0099] and Figure 9 The corresponding layout is as follows Figure 10 shown. Figure 10 In the embodiment, the four first gate patterns 1112 are arranged along the second direction (eg Figure 10 The y direction in the Figure 9 The gate pattern of the second transistor N1 of the word line driver SW0, the gate pattern of the third transistor N2 of the word line driver SW0, the gate pattern of the third transistor N2 of the word line driver SW1, and the gate pattern of the second transistor N1 of the word line driver SW1. The gate formed on the gate pattern of the second transistor N1 of the word line driver SW0 is connected to the first word line control signal GrDecN. <0> The gate electrode formed on the gate pattern of the third transistor N2 of the word line driver SW0 is electrically connected to the sub-signal PhDecN of the second word line control signal. <0> The gate electrode formed on the gate pattern of the third transistor N2 of the word line driver SW1 is electrically connected to the sub-signal PhDecN of the second word line control signal. <0> The gate electrode formed on the gate pattern of the second transistor N1 of the word line driver SW1 is electrically connected to the first word line control signal GrDecN. <1> Electrical connection.
[0100] like Figure 10As shown, the N-type transistor region layout 111 further includes a third conductive contact pattern 1114, a fourth conductive contact pattern 1115, a fifth conductive contact pattern 1116, a sixth conductive contact pattern 1117, and a seventh conductive contact pattern 1118. The third conductive contact pattern 1114 is used to provide a conductive contact structure corresponding to the source of the second transistor N1 of the word line driver SW0. This conductive contact structure is used to electrically connect the source of the second transistor N1 of the word line driver SW0 to the vwln power supply. The fourth conductive contact pattern 1115 is used to provide a conductive contact structure corresponding to the source of the third transistor N2 of the word line driver SW0 and a conductive contact structure corresponding to the source of the third transistor N2 of the word line driver SW1. The conductive contact structure corresponding to the source of the third transistor N2 of the word line driver SW0 is used to electrically connect the source of the third transistor N2 of the word line driver SW0 to the vwln power supply, and the conductive contact structure corresponding to the source of the third transistor N2 of the word line driver SW1 is used to electrically connect the source of the third transistor N2 of the word line driver SW1 to the vwln power supply. The fifth conductive contact pattern 1116 is used to provide a conductive contact structure corresponding to the source of the second transistor N1 of the word line driver SW1. This conductive contact structure is used to electrically connect the source of the second transistor N1 of the word line driver SW1 to the vwln power supply. The sixth conductive contact structure 1117 is used to provide a conductive contact structure corresponding to the drain of the second transistor N1 of the word line driver SW0 and a conductive contact structure corresponding to the drain of the third transistor N2 of the word line driver SW0. The conductive contact structure corresponding to the drain of the second transistor N1 of the word line driver SW0 is used to electrically connect the drain of the second transistor N1 of the word line driver SW0 to the word line WL0, and the conductive contact structure corresponding to the drain of the third transistor N2 of the word line driver SW0 is used to electrically connect the drain of the third transistor N2 of the word line driver SW0 to the word line WL0. The seventh conductive contact structure 1118 is used to set a conductive contact structure corresponding to the drain of the second transistor N1 of the word line driver SW1 and a conductive contact structure corresponding to the drain of the third transistor N2 of the word line driver SW1. The conductive contact structure corresponding to the drain of the second transistor N1 of the word line driver SW1 is used to electrically connect the drain of the second transistor N1 of the word line driver SW1 with the word line WL1, and the conductive contact structure corresponding to the drain of the third transistor N2 of the word line driver SW1 is used to electrically connect the drain of the third transistor N2 of the word line driver SW1 with the word line WL1.
[0101] Figure 10 In the embodiment, the two second gate patterns 1122 are sequentially Figure 9The gate pattern of the first transistor P1 of the word line driver SW0 and the gate pattern of the first transistor P1 of the word line driver SW1 are connected. The gate formed on the gate pattern of the first transistor P1 of the word line driver SW0 is connected to the first word line control signal GrDecN. <0> The gate electrode formed on the gate pattern of the first transistor P1 of the word line driver SW1 is electrically connected to the first word line control signal GrDecN. <1> Electrical connection.
[0102] like Figure 10 As shown, the P-type transistor region layout 112 further includes an eighth conductive contact pattern 1124, a ninth conductive contact pattern 1125, and a tenth conductive contact pattern 1126. The eighth conductive contact pattern 1124 is used to set a conductive contact structure corresponding to the source of the first transistor P1 of the word line driver SW0 and a conductive contact structure corresponding to the source of the first transistor P1 of the word line driver SW1. The conductive contact structure corresponding to the source of the first transistor P1 of the word line driver SW0 is used to connect the source of the first transistor P1 of the word line driver SW0 to the sub-signal PhDec of the second word line control signal. <0> The conductive contact structure corresponding to the source of the first transistor P1 of the word line driver SW1 is used to connect the source of the first transistor P1 of the word line driver SW1 to the sub-signal PhDec of the second word line control signal. <0> The ninth conductive contact pattern 1125 is used to provide a conductive contact structure corresponding to the drain of the first transistor P1 of the word line driver SW0. This conductive contact structure is used to electrically connect the drain of the first transistor P1 of the word line driver SW0 to the word line WL0. The tenth conductive contact pattern 1126 is used to provide a conductive contact structure corresponding to the drain of the first transistor P1 of the word line driver SW1. This conductive contact structure is used to electrically connect the drain of the first transistor P1 of the word line driver SW1 to the word line WL1.
[0103] In this embodiment, the first and second wordline control signal generation module patterns are arranged adjacent to the corresponding wordline driver layouts, resolving the issues of complex routing, high power consumption, and signal delay associated with placing the first and second wordline control signal generation module patterns on one side of all wordline driver layouts and memory array layouts in a chip. The first and second wordline control signal generation module patterns are arranged in different directions from the wordline driver layouts, allowing the transmission lines for the first and second wordline control signals to be arranged in different directions, ensuring ample and regular routing space.
[0104] An exemplary embodiment of the present invention provides a memory layout, comprising any of the semiconductor layouts described in the aforementioned embodiments. Due to the use of the semiconductor layout described in the aforementioned embodiments, the size and arrangement of wordline drivers are not affected by wordline spacing, thereby improving the driving capability of the wordline drivers. Furthermore, the connection between the wordline drivers and wordlines is simplified and unaffected by wordline spacing.
[0105] In the present invention, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, elements defined by the phrase "comprising..." do not exclude the presence of additional identical elements in the article or device comprising the elements.
[0106] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.
[0107] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.
Claims
1. A semiconductor layout, characterized in that: The semiconductor layout includes: a plurality of word line driver layouts, each of the word line driver layouts comprising a plurality of cell regions of an array, each of the cell regions being provided with a plurality of word line drivers; A plurality of bonding pad patterns are arranged on the word line driver layout and are arranged one-to-one corresponding to the word line drivers. The bonding pad patterns are used to set bonding pads, and the bonding pads are used to connect the corresponding word line drivers with corresponding word lines.
2. The semiconductor layout according to claim 1, wherein: The unit area is provided with: An N-type transistor region layout, wherein the N-type transistor region layout is used to form a plurality of N-type transistors of the word line driver; A P-type transistor region layout, wherein the P-type transistor region layout is used to form a plurality of P-type transistors of the word line driver; The N-type transistor region layout and the P-type transistor region layout are arranged at intervals along a first direction, a portion of the bonding pad pattern is located on the N-type transistor region layout, and another portion of the bonding pad pattern is located on the P-type transistor region layout.
3. The semiconductor layout according to claim 2, wherein: The N-type transistor region layout includes: a first active pattern extending along a second direction, wherein the second direction is arranged at an angle to the first direction; a plurality of first gate patterns, wherein the plurality of first gate patterns are arranged at intervals on the first active pattern and extend along the first direction; a plurality of first conductive contact patterns, each of the first conductive contact patterns being disposed on one of the first gate patterns; and / or, The P-type transistor region layout includes: a second active pattern extending along the second direction; a plurality of second gate patterns, wherein the plurality of second gate patterns are arranged at intervals on the second active pattern and extend along the first direction; A plurality of second conductive contact patterns are provided, and each second conductive contact pattern is disposed on one second gate pattern.
4. The semiconductor layout according to claim 3, wherein: The unit region includes two word line drivers, and the two bonding pad patterns corresponding to the two word line drivers are respectively located on the N-type transistor region layout and the P-type transistor region layout.
5. The semiconductor layout according to claim 4, wherein: The bonding pad pattern located on the N-type transistor region layout overlaps at least partially with the two first gate patterns in the middle; The bonding pad pattern located on the P-type transistor region layout overlaps at least partially with the two second gate patterns.
6. The semiconductor layout according to claim 2, wherein: The unit area is provided with: A first pressure pattern is provided on a side of the N-type transistor region layout away from the P-type transistor region layout, and is used to set a voltage for the well region where the N-type transistor region layout is located; The second pressure pattern is arranged on a side of the P-type transistor region layout away from the N-type transistor region layout, and is used to set a voltage for the well region where the P-type transistor region layout is located.
7. The semiconductor layout according to claim 6, wherein: The unit area is provided with: a first isolation pattern, disposed between the first pressure pattern and the N-type transistor region layout, and extending along a second direction, wherein the second direction is disposed at an angle to the first direction; a second isolation pattern, disposed between the second pressure pattern and the P-type transistor region layout, and extending along the second direction; The third isolation pattern is arranged between the N-type transistor region layout and the P-type transistor region layout and extends along the second direction.
8. The semiconductor layout according to claim 7, wherein: The unit area is provided with: The fourth isolation pattern is arranged on both sides of the P-type transistor region where the second isolation pattern and the third isolation pattern are not arranged, and extends along the first direction.
9. The semiconductor layout according to any one of claims 1 to 8, wherein: The semiconductor layout further includes: a plurality of first word line control signal generating module patterns, arranged in one-to-one correspondence with the word line driver layouts, for arranging a first word line control signal generating module, the first word line control signal generating module being configured to provide a first word line control signal for the word line driver, the first word line control signal generating module patterns being arranged adjacent to the corresponding word line driver layouts; and / or, Multiple second word line control signal generation module patterns are arranged in a one-to-one correspondence with the word line driver layout, and are used to set up a second word line control signal generation module, which is used to provide a second word line control signal for the word line driver. The second word line control signal generation module pattern is arranged adjacent to the corresponding word line driver layout.
10. The semiconductor layout according to claim 9, wherein: The second word line control signal generating module pattern and the word line driver layout are arranged at intervals along a first direction, and the first word line control signal generating module pattern and the word line driver layout are arranged at intervals along a second direction, wherein the first direction and the second direction are arranged at an angle.
11. A memory layout, characterized in that: The memory layout comprises the semiconductor layout according to any one of claims 1 to 10.