ECS circuit, ECS method and memory

Abstract

Embodiments of the present disclosure provide an ECS circuit, an ECS method and a memory, the ECS circuit comprising: an ECS command generation circuit configured to generate an ECS command signal; and the ECS control circuit is electrically connected with the ECS command generation circuit and is configured to receive the ECS command signal and generate an internal command signal based on the ECS command signal so as to control n adjacent storage positions to sequentially execute ECS operation, and n is an integer greater than or equal to 2.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to an ECS circuit, an ECS method, and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speeds when manufacturing and using computers and other devices. To achieve faster data transmission speeds, a series of devices such as memories that can transmit data at double the data rate (DDR) have emerged.

[0003] However, as memory transfer speeds increase, memory cells shrink, and row hammering occur, errors can occur. This necessitates error checking and timely correction of detected errors. For example, dynamic random access memory (DRAM) requires a complete error check and scrub (ECS) at least every 24 hours. Summary of the Invention

[0004] Embodiments of the present disclosure provide an ECS circuit, an ECS method, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides an ECS circuit, including:

[0006] an ECS command generation circuit configured to generate an ECS command signal;

[0007] The ECS control circuit is electrically connected to the ECS command generation circuit and is configured to receive the ECS command signal and generate an internal command signal based on the ECS command signal to control the execution of ECS operations on n adjacent storage locations in sequence, where n is an integer greater than or equal to 2.

[0008] In a second aspect, an embodiment of the present disclosure provides an ECS method, applied to a memory, the method comprising:

[0009] An internal command signal is generated based on the ECS command signal, where the internal command signal is used to instruct the memory to sequentially perform ECS operations on n adjacent storage locations, where n is an integer greater than or equal to 2.

[0010] In a third aspect, an embodiment of the present disclosure provides a memory, comprising a memory array and an ECS circuit as in the first aspect;

[0011] The storage array includes a plurality of storage locations, each of which is used to store data;

[0012] The ECS circuit is configured to generate an internal command signal based on the ECS command signal to control the ECS operation to be performed on n adjacent storage locations in sequence, where n is an integer greater than or equal to 2.

[0013] The disclosed embodiments provide an ECS circuit, an ECS method, and a memory. The ECS circuit includes: an ECS command generation circuit configured to generate an ECS command signal; an ECS control circuit electrically connected to the ECS command generation circuit, configured to receive the ECS command signal and generate an internal command signal based on the ECS command signal to control the sequential execution of ECS operations on n adjacent storage locations, where n is an integer greater than or equal to 2. Thus, in the disclosed embodiments, one ECS command signal corresponds to n ECS operations, thereby utilizing the idle time after executing one ECS operation, avoiding time waste, and improving the efficiency of ECS operations. Furthermore, since the n ECS operations can share the internal activation signal and the internal precharge signal, the power consumption of the memory can also be saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A timing diagram of an ECS mode provided in an embodiment of the present disclosure;

[0015] Figure 2 A schematic diagram of the structure of an ECS circuit provided in an embodiment of the present disclosure Figure 1 ;

[0016] Figure 3 A signal timing diagram provided in an embodiment of the present disclosure Figure 1 ;

[0017] Figure 4 A schematic diagram of the structure of an ECS command generation circuit provided in an embodiment of the present disclosure;

[0018] Figure 5 A schematic diagram of the structure of an ECS circuit provided in an embodiment of the present disclosure Figure 2 ;

[0019] Figure 6A A schematic diagram of a counting circuit provided in an embodiment of the present disclosure Figure 1 ;

[0020] Figure 6B A schematic diagram of a counting circuit provided in an embodiment of the present disclosure Figure 2 ;

[0021] Figure 7 A schematic diagram of the structure of an ECS circuit provided in an embodiment of the present disclosure Figure 3 ;

[0022] Figure 8A schematic diagram of the structure of an ECS circuit provided in an embodiment of the present disclosure Figure 4 ;

[0023] Figure 9 A schematic diagram of the structure of an ECS circuit provided in an embodiment of the present disclosure Figure 5 ;

[0024] Figure 10 Schematic diagram 6 of the structure of an ECS circuit provided in an embodiment of the present disclosure;

[0025] Figure 11 A schematic diagram of the structure of a storage array provided in an embodiment of the present disclosure;

[0026] Figure 12 A schematic diagram of the structure of an address generation circuit provided in an embodiment of the present disclosure Figure 1 ;

[0027] Figure 13 A schematic structural diagram of an array counter provided in an embodiment of the present disclosure;

[0028] Figure 14 A schematic diagram of the structure of an address generation circuit provided in an embodiment of the present disclosure Figure 2 ;

[0029] Figure 15 A signal timing diagram provided in an embodiment of the present disclosure Figure 2 ;

[0030] Figure 16 A signal timing diagram provided in an embodiment of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0033] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0034] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0035] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0036] Error Check and Scrub (ECS);

[0037] Dynamic Random Access Memory (DRAM);

[0038] Double Data Rate (DDR);

[0039] Low Power DDR (LPDDR);

[0040] Refresh all banks (Refab);

[0041] Error Check and Correct (ECC);

[0042] Multi Purpose Command (MPC);

[0043] Self-refresh (Self_Refresh, Sref);

[0044] D flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF);

[0045] Bank Group (BG);

[0046] Storage block (Bank, BA);

[0047] Row to Column Delay (RCD);

[0048] Row address to column address delay time (tRCD);

[0049] Read to Write (RTW);

[0050] Read-to-write delay time (tRTW);

[0051] Write to Read (WTR);

[0052] Write to read delay time (tWTR);

[0053] Write to Precharge;

[0054] Write to precharge delay time (tWTP);

[0055] Reset-Set latch (RS latch);

[0056] Read Modify Write (RMW) operations;

[0057] Current consumption when turning the word line on and off (ACT+PRE Current, IDD0).

[0058] The ECS mode allows the DRAM to read and modify the detected error codewords internally and write the corrected data back to the storage array. It is generally required to perform a complete error check and clearing of the DRAM at least once every 24 hours. The ECS operating modes include automatic and manual operating modes, and the operating mode can be selected through the relevant mode register signal. In the automatic ECS operating mode, the ECS command signal can be obtained with the help of the refresh command signal and / or the self-refresh command signal. In the manual ECS operating mode, the MPC signal is required. At the same time, the mode register can also determine whether to perform manual ECS operation during self-refresh.

[0059] Figure 1 The following is a timing diagram of an ECS mode provided by an embodiment of the present disclosure, which specifically corresponds to an automatic ECS operation mode. Each pulse signal with a pulse width of tECSC represents the ECS operation time (i.e., the ECS operation window) corresponding to each ECS command signal, during which an ECS operation needs to be performed; tECSC is the pulse width of the pulse corresponding to each ECS command signal when it is valid; the time interval between two pulses is tECSint, which is the time interval between two ECS operation windows or the time interval between two ECS command signals; and tECS represents the ECS period during which an ECS operation is performed on all storage cells in the entire memory, typically 24 hours.

[0060] In the automatic ECS operation mode, a refresh command signal (such as a Refab command signal) can be stolen as an ECS command signal to generate an ECS operation. An ECS operation includes: Activate, Read, Write, and Precharge, that is, activating the target address, reading data from the target address, correcting the read data (if there is an error), and then writing the correct data to the target address, and precharging the target address. Among them, the error checking and correction of the read data can be completed by the ECC circuit. The above-mentioned ECS operation can usually be completed in a relatively short time, for example: 140ns.

[0061] To ensure that the ECS of the memory is completed within the ECS cycle, different capacities of memory have different corresponding tECSint. For example, the tECSint corresponding to 4Gb capacity is 5.15ms, the tECSint corresponding to 6Gb capacity is 3.43ms, ..., and the tECSint corresponding to 32Gb capacity is 0.64ms.

[0062] For DDR DRAM, such as LPDDR6, the time interval between a Refab command signal and the next valid command signal in the memory is tRFCab. For example, for a 16Gb memory, tRFCab = 280ns, which is much longer than the 140ns time of an ECS operation, resulting in the remaining time being wasted.

[0063] Based on this, an embodiment of the present disclosure provides an ECS circuit, comprising: an ECS command generation circuit configured to generate an ECS command signal; and an ECS control circuit electrically connected to the ECS command generation circuit, configured to receive the ECS command signal and, based on the ECS command signal, generate an internal command signal to control the sequential execution of ECS operations on n adjacent storage locations, where n is an integer greater than or equal to 2. Thus, in the embodiment of the present disclosure, one ECS command signal corresponds to n ECS operations, thereby utilizing the idle time after executing one ECS operation within the original ECS operation window, avoiding time waste and improving the efficiency of ECS operations.

[0064] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0065] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of an ECS circuit 20 provided in an embodiment of the present disclosure. Figure 2 As shown, the ECS circuit 20 includes:

[0066] An ECS command generation circuit 201 configured to generate an ECS command signal;

[0067] The ECS control circuit 202 is electrically connected to the ECS command generation circuit 201 and is configured to receive an ECS command signal and generate an internal command signal based on the ECS command signal to control the execution of ECS operations on n adjacent storage locations in sequence, where n is an integer greater than or equal to 2.

[0068] It should be noted that the ECS command generation circuit 201 is a circuit module for generating an ECS command signal. Figure 1 The ECS operation window shown generates an ECS command signal. In the disclosed embodiment, a pulse on the ECS command signal ECS_CMD can represent a valid ECS command signal, or that the ECS command signal is in a valid state (or enabled state). All references to an ECS command signal in the subsequent description refer to a valid ECS command signal.

[0069] In some embodiments, the ECS command generation circuit 201 is configured to generate and output an ECS command signal based on a refresh command signal every preset time interval or every preset number of refresh command signals.

[0070] It should be noted that the preset time may be the aforementioned tECSint (which may be denoted as the ECS interval time), and the refresh command signal may be a Refab / Sref command signal. The time interval corresponding to the preset number of refresh command signals may be equal to or less than tECSint, and this is not specifically limited. The preset time and preset number may be set based on the actual required ECS cycle, as long as the normal execution of the ECS operation is guaranteed.

[0071] In this way, the ECS command generation circuit 201 steals a Refab / Sref command signal of the memory according to a certain period to generate an ECS command signal. Since the Refab / Sref command signal is stolen, the memory no longer performs a refresh operation, but performs an ECS operation.

[0072] The ECS control circuit 202 generates an internal command signal based on the valid ECS command signal. Figure 3 As shown, one valid ECS command signal ECS_CMD may be one positive pulse. In other embodiments, one valid ECS command signal may also be represented by one negative pulse, which is not specifically limited.

[0073] The ECS control circuit 202 generates an internal command signal whenever it receives a valid ECS command signal; otherwise, no internal command signal is generated. Based on the internal command signal, the relevant circuitry within the memory performs an ECS operation on n adjacent memory locations within the memory. Each memory location comprises one or more memory cells within the memory, each capable of storing one bit of data. In other embodiments, each memory cell within the memory can store multiple bits of data, or multiple memory cells within the memory can store a single bit of data.

[0074] Thus, in the embodiment of the present disclosure, corresponding to each ECS command signal, ECS operations of n storage locations are executed instead of executing the ECS operation of only one storage location, thereby utilizing the idle time in an ECS operation window corresponding to each ECS command signal (i.e., the idle time between the first ECS operation and the arrival of the next valid command), thereby avoiding wasting operation time.

[0075] In some embodiments, the internal command signal includes an internal activation signal, n groups of internal read and write signals, and an internal pre-charge signal generated in sequence according to preset timing conditions; each group of internal read and write signals includes an internal read signal and an internal write signal generated in sequence, and each group of internal read and write signals corresponds to a storage location.

[0076] It should be noted that the internal command signal involved here is the command signal required for the ECS circuit 20 to perform the ECS operation, and is therefore recorded as an internal command signal. The ECS operation may include an activation operation, a first read operation, a first write operation, a second read operation, a second write operation...the nth read operation, the nth write operation, and a pre-charge operation in sequence. Correspondingly, the circuit for performing the ECS operation may include an activation circuit, a read circuit, a write circuit, and a pre-charge circuit, which are circuits that reuse the original circuits inside the memory. The internal activation signal is used to control the activation circuit to perform the activation operation, the internal read signal is used to control the read circuit to perform the read operation, the internal write signal is used to control the write circuit to perform the write operation, and the internal pre-charge signal is used to control the pre-charge circuit to perform the pre-charge operation.

[0077] The preset timing conditions include the time interval between each internal command signal to ensure that the time interval between adjacent operations is sufficient to complete the corresponding action, so that the ECS operation can be executed normally and avoid operation problems caused by too small or too large intervals.

[0078] It should also be noted that, assuming that ECS is performed on the storage locations in the memory row by row, each internal command signal is used to control the execution of the ECS operation on n adjacent storage locations in a row, and the internal activation signal is used to indicate the execution of the activation operation on the storage row where the n adjacent storage locations are located. The storage row can be recorded as the current storage row, and each group of internal read and write signals corresponds to one storage location. Specifically, each internal read signal is used to indicate the reading of data from a corresponding storage location and the checking and error correction of the data. Each internal write signal is used to indicate the writing of the checked and corrected data back to a corresponding storage location, and the internal pre-charge signal is used to indicate the execution of a pre-charge operation on the current storage row.

[0079] In the embodiment of the present disclosure, each internal command signal corresponds to an ECS operation of n storage locations, and the n storage locations share the same internal activation signal and the same internal precharge signal. Assume that n=2, that is, when an ECS command signal is issued, an ECS operation is performed on the adjacent first storage location and the second storage location. Figure 3 As shown, the internal command signals include, in sequence: an internal activation signal ECSAct, an internal read signal ECSRd1 corresponding to a first storage location, an internal write signal ECSWr1 corresponding to the first storage location, an internal read signal ECSRd2 corresponding to a second storage location, an internal write signal ECSWr2 corresponding to a second storage location, and an internal pre-charge signal ECSPre. The preset timing conditions may include: a time interval tRCD between the internal activation signal ECSAct and the internal read signal ECSRd1, a time interval tRTW1 between the internal read signal ECSRd1 and the internal write signal ECSWr1, a time interval tWTR1 between the internal write signal ECSWr1 and the internal read signal ECSRd2, a time interval tRTW2 between the internal read signal ECSRd2 and the internal write signal ECSWr2, and a time interval tWTP between the internal write signal ECSWr2 and the internal pre-charge signal ECSPre. Each time interval needs to ensure that the operation corresponding to the previous command signal is completed before starting the operation corresponding to the next command signal.

[0080] In this way, the embodiment of the present disclosure only requires one internal activation signal and one precharge signal to implement n ECS operations on n adjacent storage locations, reducing the power required for activation operations and precharge operations, thereby saving power consumed by the memory.

[0081] It should also be noted that n is greater than or equal to 2, but it cannot be an arbitrary value. That is, the time required to sequentially perform ECS operations on n adjacent storage locations based on a set of internal command signals must be less than the ECS operation time tECSC specified in the standard. Otherwise, memory operation errors may occur.

[0082] Since one ECS command signal corresponds to n ECS operations (for example, n = 2), and each ECS command signal executes two ECS operations, the ECS cycle can be halved, improving the efficiency and frequency of ECS operations. Thus, since only half of the ECS command signals (ECS_CMD) are used to indicate ECS operations, the operations corresponding to the Refab / Sref command signals can be omitted within the DRAM. This saves activation and precharge operations, reduces IDD0, and saves memory power. At the same time, the internal counter counts the corresponding column addresses by half.

[0083] Alternatively, the embodiment of the present disclosure can also maintain the original ECS cycle, then the number of required ECS command signals can be halved, that is, the interval between two adjacent ECS command signals is extended by 1 times. At this time, for the scheme of ECS operation in which one ECS command signal corresponds to one storage location, taking a certain type of memory as an example, 25 Refab / Sref command signals need to be stolen for ECS operation within a 64ms refresh cycle. In contrast, assuming n=2, then for the scheme of ECS operation in which one ECS command signal corresponds to n storage locations, only 13 Refab / Sref command signals need to be stolen for ECS operation within a 64ms refresh cycle. Therefore, the technical solution disclosed in the present disclosure can effectively improve the efficiency of ECS operations and reduce the burden of ECS operations on memory chip refresh operations.

[0084] In some embodiments, the ECS control circuit 202 is further configured to, after generating an internal command signal based on an ECS command signal, mask the n-1 ECS command signals subsequently received. While maintaining the original ECS cycle and the number of ECS command signals within each ECS cycle, only one of every n ECS command signals is required to indicate the execution of an ECS operation, and the remaining n-1 ECS command signals do not need to indicate the execution of an ECS operation.

[0085] It should be noted that since one ECS command signal corresponds to ECS operations for n storage locations, the disclosed embodiments can also, after generating an internal command signal for performing n ECS operations based on one ECS command signal, mask the subsequent n-1 ECS command signals. That is, once n ECS operations have been performed, no ECS operations will be performed based on the subsequent n-1 ECS command signals. This maintains the memory's ECS cycle. Furthermore, since the ECS command signal is obtained by stealing the refresh command signal, the memory will not perform refresh operations on the n-1 refresh command signals that were stolen as ECS command signals, saving power. Furthermore, since these refresh command signals were originally intended to be stolen, rather than being stolen in addition, they will not affect the normal refresh operation of the memory. Masking here means that no internal command signals are generated and output based on the ECS command signal. Furthermore, the refresh command signals that were stolen to generate the ECS command signal are no longer used to perform refresh operations.

[0086] It should also be noted that, in the embodiment of the present disclosure, shielding of the subsequently generated n-1 ECS command signals may be controlled by the ECS control circuit 202 at the receiving end, or may be controlled by the ECS command generation circuit 201 at the generating end.

[0087] Take n=2 as an example:

[0088] The ECS control circuit 202 may shield the received ECS command signal in the following manner: after generating a set of internal command signals based on an ECS command signal, the ECS control circuit 202 does not respond to the next received ECS command signal and does not perform any operation until the next ECS command signal is received.

[0089] In this implementation, the ECS command generation circuit 201 can operate in exactly the same manner as a conventional circuit for generating ECS ​​command signals, without requiring any modification. Accordingly, the ECS control circuit 202 can include an enable control circuit to control whether the ECS control circuit 202 responds to the ECS command signal to generate an internal command signal for executing n ECS operations.

[0090] The ECS command generation circuit 201 can mask the generation of ECS command signals by: after stealing a refresh command signal and generating an ECS command signal, the ECS command signal corresponds to two ECS operations. After the next refresh command signal is stolen, the ECS command generation circuit 201 does not generate an ECS command signal until the next refresh command signal is stolen. In this example, the ECS control circuit 202 responds normally to each received ECS command signal.

[0091] In this implementation, the ECS command generation circuit 201 generates only one ECS command signal for every n refresh command signals it steals. Figure 4 As shown, the ECS command generation circuit 201 may include a sampling window generation circuit b1 and a sampling circuit b2, wherein:

[0092] The sampling window generating circuit b1 is used to generate a sampling window signal ECS_Win;

[0093] The sampling circuit b2 is used to receive the sampling window signal ECS_Win and the refresh command signal Refab / Sref (Refab command signal or Sref command signal), and samples the sampling window signal ECS_Win according to the refresh command signal Refab / Sref to obtain the ECS command signal ECS_CMD.

[0094] It should be noted that Figure 3 To correspond Figure 4 Timing diagram, combined with Figure 3 and Figure 4 As shown, the refresh command signal Refab / Sref can be used as the sampling clock of the sampling circuit b2. The duration of the valid level (taking the high level as an example) of the sampling window signal ECS_Win needs to be long enough to ensure that the refresh command signal Refab / Sref can be stolen to generate the ECS command signal ECS_CMD under the valid sampling window signal ECS_Win. In this way, during the valid level period of the sampling window signal ECS_Win, a stolen refresh command signal Refab / Sref can be stolen to generate the ECS command signal ECS_CMD. Figure 4 As shown, sampling window generation circuit b1 may include a clock circuit c1, a sampling period circuit c2, and a latch circuit c3. Clock circuit c1 generates an ECS clock signal ECS_Clk for counting by sampling period circuit c2. Sampling period circuit c2 counts based on the ECS clock signal ECS_Clk to obtain a sampling period signal SET value. Latch circuit c3 latches the sampling period signal SET value and the ECS command signal ECS_CMD to obtain a sampling window signal ECS_Win.

[0095] The clock circuit c1 may include: a ring oscillator a1 for generating an initial clock signal OSC_CLK; a frequency dividing circuit a2 for dividing the initial clock signal OSC_CLK according to a required clock frequency to obtain an ECS clock signal ECS_Clk;

[0096] The sampling period circuit c2 may include: an ECS counting circuit a3, configured to count based on the ECS clock signal ECS_Clk to obtain a counting signal Code<11:0>; wherein the ECS counting circuit a3 may be a counter composed of cascaded DFFs; a decoding circuit a4, configured to decode the counting signal Code<11:0> to obtain a valid sampling period signal SET value, thereby instructing the generation of a sampling window signal ECS_Win at a valid level; wherein the sampling period signal SET value determines the time interval between two sampling window signals ECS_Win (or two ECS command signals ECS_CMD), and the sampling period signal SET value also determines the start time of the valid level of the sampling window signal ECS_Win;

[0097] Latch circuit c3 may include: a first delay circuit a6, configured to delay the ECS command signal ECS_CMD and transmit it to latch a5; latch a5 is configured to perform a latching process based on the delayed ECS command signal ECS_CMD and the sampling period signal SETvalue to obtain a sampling window signal ECS_Win. Specifically, a valid sampling period signal SETvalue indicates that the sampling window signal ECS_Win is flipped from an inactive level to an active level, and a valid ECS command signal ECS_CMD indicates that the sampling window signal ECS_Win is flipped from an active level to an inactive level. Latch a5 may be an RS latch, and the delayed ECS command signal ECS_CMD may serve as a reset signal for the RS latch. The duration of the sampling window signal ECS_Win is determined by the delayed ECS command signal ECS_CMD.

[0098] The sampling circuit b2 may include at least one level of sampling processing, specifically, Figure 4 As shown, the sampling circuit b2 includes:

[0099] A first sampling circuit a7 is configured to receive a sampling window signal ECS_Win and a refresh command signal Refab / Sref, and to sample the sampling window signal ECS_Win according to the refresh command signal Refab / Sref to obtain a first ECS latch signal ECS_latch1. The first sampling circuit a7 may be a DFF, and the refresh command signal Refab / Sref serves as its sampling clock.

[0100] The second delay circuit a8 is used to delay the refresh command signal Refab / Sref to obtain a refresh command delayed signal Refab / Sref Dly;

[0101] The AND gate a11 is configured to receive the first ECS latch signal ECS_latch1 and the refresh command delay signal Refab / Sref Dly sent by the second delay circuit a8 , perform AND logic processing on the received signal, and then output the ECS command signal ECS_CMD.

[0102] In some embodiments, as Figure 4 As shown, the sampling circuit b2 may further include:

[0103] a second sampling circuit a9, configured to receive the first ECS latch signal ECS_latch1 and the refresh command delay signal Refab / Sref Dly, and sample the first ECS latch signal ECS_latch1 according to the refresh command delay signal Refab / Sref Dly to obtain the second ECS latch signal ECS_latch2; wherein the second sampling circuit a9 may be a DFF, and the refresh command delay signal Refab / Sref Dly serves as its sampling clock;

[0104] The third delay circuit a10 is used to delay the refresh command delay signal Refab / Sref Dly and then send it to the AND gate a11;

[0105] The AND gate a11 is configured to receive the second ECS latch signal ECS_latch2 and the delayed signal of the refresh command delay signal Refab / Sref Dly sent by the third delay circuit a10 , perform AND logic processing on the received signal, and output the ECS command signal ECS_CMD.

[0106] It should be noted that the sampling circuit b2 may also include more levels of sampling and delay-related circuits, and the specific number and delay time of each delay circuit may be set according to actual needs.

[0107] Figure 3 The timing diagram corresponds to Figure 4 FIG. 2 is a schematic diagram illustrating a process of generating an ECS command signal ECS_CMD and various internal command signals based on the ECS command generating circuit 201 .

[0108] In some embodiments, as Figure 5 As shown, the ECS control circuit 202 includes:

[0109] The counting circuit 2021 is configured to count the internal clock signal to generate a count value in response to the ECS command signal, and generate a set of enable signals based on the count value; wherein the set of enable signals includes an activation enable signal, n sets of read and write enable signals, and a precharge enable signal generated in sequence, and each set of read and write enable signals includes a read enable signal and a write enable signal generated in sequence;

[0110] The internal command generation circuit 2022 is electrically connected to the counting circuit 2021 and is configured to receive a set of enable signals and sequentially generate: an internal activation signal, n sets of internal read / write signals, and an internal pre-charge signal based on the set of enable signals.

[0111] It should be noted that the internal clock signal can be the memory's system clock, or it can be a clock signal generated by the internal clock generation circuit of the ECS circuit 20. Counting is performed based on the internal clock signal, with each count value corresponding to one clock cycle of the internal clock signal. Thus, the count value can be used to represent time, thereby ensuring that each command signal meets preset timing conditions. For example, the ECS control circuit 202 may further include an internal clock generation circuit (not shown) configured to generate and output the internal clock signal.

[0112] Upon receiving a valid ECS command signal, the counting circuit 2021 begins counting the internal clock signal in response to the valid ECS command signal and generates an enable signal based on the count value. Each enable signal is used to enable the generation of a corresponding operation signal. The activation enable signal is used to enable the generation of a corresponding internal activation signal, the read enable signal is used to enable the generation of a corresponding internal read signal, the write enable signal is used to enable the generation of a corresponding internal write signal, and the precharge enable signal is used to enable the generation of a corresponding internal precharge signal.

[0113] Specifically, the counting circuit 2021 is further configured to generate an activation enable signal at an active level when the count value reaches a first preset value, generate a read enable signal at an active level when the count value reaches a second preset value, generate a write enable signal at an active level when the count value reaches a third preset value, and generate a precharge enable signal at an active level when the count value reaches a fourth preset value;

[0114] When each enable signal is at an effective level, the corresponding internal command signal can be generated. In the embodiment of the present disclosure, the effective level can be a high level or a low level, which is not specifically limited.

[0115] Among them, the second preset value includes n second sub-preset values, and the third preset value includes n third sub-preset values; the first second sub-preset value is greater than the first preset value, the i-th third sub-preset value is greater than the i-th second sub-preset value, the i+1-th second sub-preset value is greater than the i-th third sub-preset value, the n-th third sub-preset value is greater than the n-th second sub-preset value, and the fourth preset value is greater than the n-th third sub-preset value, and i is a positive integer less than n.

[0116] Assuming n=2, the first count value < the first second sub-preset value < the first third sub-preset value < the second second sub-preset value < the second third sub-preset value < the fourth preset value. That is, when the count value reaches the first count value, an activation enable signal is generated; when the count value reaches the first second sub-preset value, a first read enable signal corresponding to the first storage location is generated; when the count value reaches the first third sub-preset value, a first write enable signal corresponding to the first storage location is generated; when the count value reaches the second second sub-preset value, a second read enable signal corresponding to the second storage location is generated; when the count value reaches the second third sub-preset value, a second write enable signal corresponding to the second storage location is generated; and when the count value reaches the fourth preset value, a precharge enable signal is generated.

[0117] Figure 6A and Figure 6B Two exemplary implementations of the counting circuit 2021 are shown, but are not limited thereto. Figure 6A As shown, the counting circuit 2021 includes:

[0118] The first counting sub-circuit 3011 is configured to count the internal clock signal and generate a count value in response to the ECS command signal;

[0119] The first enabling circuit 3021 is electrically connected to the first counting sub-circuit 3011 and configured to receive a count value and generate an activation enabling signal at an effective level when the count value reaches a first preset value;

[0120] The second enabling circuit 3022 is electrically connected to the first counting sub-circuit 3011 and configured to receive the count value and generate a read enable signal at an active level when the count value reaches a second preset value;

[0121] The third enabling circuit 3023 is electrically connected to the first counting sub-circuit 3011 and configured to receive the count value and generate a write enable signal at an active level when the count value reaches a third preset value;

[0122] The fourth enabling circuit 3024 is electrically connected to the first counting sub-circuit 3011 and is configured to receive the count value and generate a precharge enabling signal at an active level when the count value reaches a fourth preset value.

[0123] Here, the first enabling circuit 3021 to the fourth enabling circuit 3024 can all be implemented by corresponding decoders.

[0124] For example Figure 6B As shown, the counting circuit 2021 includes:

[0125] The second counting sub-circuit 3012 to the fifth counting sub-circuit 3015 are configured to count the internal clock lines in response to the ECS command signal and generate first to fourth counting values ​​respectively;

[0126] The first enabling circuit 3021 is electrically connected to the second counting sub-circuit 3012 and configured to receive a first count value and generate an activation enabling signal at an effective level when the first count value reaches a first preset value;

[0127] The second enabling circuit 3022 is electrically connected to the third counting sub-circuit 3013 and configured to receive the second counting value and generate a read enabling signal at an active level when the second counting value reaches a second preset value;

[0128] a third enabling circuit 3023 electrically connected to the fourth counting sub-circuit 3014 and configured to receive a third count value and generate a write enable signal at an active level when the third count value reaches a third preset value;

[0129] The fourth enabling circuit 3024 is electrically connected to the fifth counting sub-circuit 3015 and configured to receive the fourth count value and generate a precharge enabling signal at an active level when the fourth count value reaches a fourth preset value.

[0130] It should be noted that Figure 6 and Figure 5 The difference is that each enabling circuit is equipped with a counting sub-circuit. The first counting sub-circuit 3011 to the fifth counting sub-circuit 3015 are all the same counting sub-circuits, and the first counting value to the fourth counting value are the same as Figure 5 The count value is the same count value.

[0131] In the embodiment of the present disclosure, each counting sub-circuit may be a synchronous or asynchronous counter, and may be composed of a plurality of cascaded DFFs, but is not limited thereto.

[0132] In some embodiments, as Figure 7 As shown, the internal command generation circuit 2022 includes an activation command generation circuit 401, a read command generation circuit 402, a write command generation circuit 403 and a precharge command generation circuit 404;

[0133] The activation command generating circuit 401 is configured to generate an internal activation signal when receiving an activation enable signal at an active level;

[0134] a read command generation circuit 402 configured to generate an internal read signal upon receiving a read enable signal at an active level;

[0135] The write command generation circuit 403 is configured to generate an internal write signal when receiving a write enable signal at an active level;

[0136] The precharge command generation circuit 404 is configured to generate an internal precharge signal upon receiving a precharge enable signal at an active level.

[0137] In some embodiments, the counting circuit 2021 is further configured to reset the count value in response to the internal pre-charge signal.

[0138] It should be noted that after the internal pre-charge signal is generated, it indicates that the internal command signals required for the n ECS operations corresponding to the current ECS command signal have all been generated, and there is no need for counting circuit 2021 to continue counting to generate internal command signals. Therefore, the internal pre-charge signal can serve as a reset signal for counting circuit 2021, used to reset the count value of counting circuit 2021 until the next ECS command signal is received, at which time counting circuit 2021 is enabled again.

[0139] In some embodiments, as Figure 8 As shown, the internal command generation circuit 2022 further includes one or more of an activation command timing adjustment circuit 501, a read command timing adjustment circuit 502, a write command timing adjustment circuit 503, and a precharge command timing adjustment circuit 504;

[0140] The activation command timing adjustment circuit 501 is electrically connected between the counting circuit 2021 and the activation command generation circuit 401, and is configured to receive the first delay adjustment signal and the activation enable signal, adjust the delay of the activation enable signal according to the first delay adjustment signal, and then send the signal to the activation command generation circuit 401;

[0141] The read command timing adjustment circuit 502 is electrically connected between the counting circuit 2021 and the read command generation circuit 402, and is configured to receive the second delay adjustment signal and the read enable signal, adjust the delay of the read enable signal according to the second delay adjustment signal, and then send the signal to the read command generation circuit 402;

[0142] The write command timing adjustment circuit 503 is electrically connected between the counting circuit 2021 and the write command generation circuit 403 and is configured to receive the third delay adjustment signal and the write enable signal, adjust the delay of the write enable signal according to the third delay adjustment signal, and then send the signal to the write command generation circuit 403;

[0143] The precharge command timing adjustment circuit 504 is electrically connected between the counting circuit 2021 and the precharge command generation circuit 404, and is configured to receive the fourth delay adjustment signal and the precharge enable signal, and adjust the delay of the precharge enable signal according to the fourth delay adjustment signal before sending it to the precharge command generation circuit 404.

[0144] It should be noted that counting by the counting circuit 2021 and generating each internal command signal based on the count value can usually meet the preset timing conditions. However, in an actual circuit, based solely on the counting of the counting circuit 2021, there may be an error between the generation timing of each internal command signal and the actual required preset timing conditions. Therefore, the embodiment of the present disclosure also uses a timing adjustment circuit to adjust the delay of each enable signal, and further performs timing adjustment to ensure that the timing of each internal command signal meets the preset timing conditions. In the embodiment of the present disclosure, each timing adjustment circuit is used to adjust the delay of each enable signal, thereby adjusting the generation timing of each internal command signal; each command generation circuit can adjust the pulse width of the generated internal command signal to ensure that each internal command signal maintains a sufficient effective duration.

[0145] Here, not all four timing adjustment circuits are required, but only one or more of them are included according to actual needs. For example, if the internal read signal generated based only on the count value does not meet the preset timing conditions, the read command timing adjustment circuit 502 is used to adjust the delay of the read enable signal before sending it to the read command generation circuit 402. Among them, the basis for delay adjustment of the read enable signal is the corresponding second delay adjustment signal, and the second delay adjustment signal indicates the time or number of clock cycles for delaying the read enable signal. Based on the delay time indicated by the second delay adjustment signal, the read command timing adjustment circuit 502 delays the read enable signal for a corresponding time; or, based on the number of delayed clock cycles indicated by the second delay adjustment signal, the read command timing adjustment circuit 502 also receives a clock signal, and implements a certain delay time based on the clock signal and the second delay adjustment signal. The clock signal can be the same as or different from the aforementioned internal clock signal, and this is not specifically limited.

[0146] The same is true for other timing adjustment circuits and delay adjustment signals, which will not be described in detail here. For enable signals that do not require delay, the corresponding timing adjustment circuit may not be set, or the delay time or delay cycle number indicated by the corresponding delay adjustment signal may be zero.

[0147] In this way, the embodiment of the present disclosure can also use the timing adjustment circuit and the delay adjustment signal to adjust the delay of each enable signal to ensure that the generated internal command signal meets the preset timing conditions.

[0148] In some embodiments, the activation command timing adjustment circuit 501 is further configured to sequentially receive a plurality of first preset delay adjustment signals during a test phase, and sequentially adjust the delay of the activation enable signal according to the plurality of first preset delay adjustment signals, so as to determine the first preset delay adjustment signal that makes the internal activation signal meet the first timing condition as the first delay adjustment signal;

[0149] The read command timing adjustment circuit 502 is further configured to sequentially receive a plurality of second preset delay adjustment signals during a test phase, and sequentially adjust the delay of the read enable signal according to the plurality of second preset delay adjustment signals, so as to determine the second preset delay adjustment signal that enables the internal read signal to meet the second timing condition as the second delay adjustment signal;

[0150] The write command timing adjustment circuit 503 is further configured to, during a test phase, sequentially receive a plurality of third preset delay adjustment signals, and sequentially adjust the delay of the write enable signal according to the plurality of third preset delay adjustment signals, so as to determine a third preset delay adjustment signal that enables the internal write signal to meet a third timing condition as the third delay adjustment signal;

[0151] The pre-charge command timing adjustment circuit 504 is further configured to sequentially receive a plurality of fourth preset delay adjustment signals during a test phase, and sequentially adjust the delay of the pre-charge enable signal according to the plurality of fourth preset delay adjustment signals, so as to determine a fourth preset delay adjustment signal that makes the internal pre-charge signal meet the fourth timing condition as the fourth delay adjustment signal.

[0152] It should be noted that the preset timing conditions consist of a first timing condition, a second timing condition, a third timing condition and a fourth timing condition. The first timing condition represents the time interval between the internal activation signal and the ECS command signal; the second timing condition represents the time interval between the internal activation signal and the internal read signal. Since the ECS operation is performed on n storage locations, the second timing condition also includes the time interval between the i+1th internal read signal and the ith internal write signal. The second timing condition needs to ensure that the read operation can only be performed after the storage row where the storage location is located is activated, and that the read operation of the current storage location is performed after the write operation of the previous storage location is completed to avoid read and write confusion and errors; the third timing condition represents the time interval between the internal read signal and the internal write signal. Since the ECS operation is performed on n storage locations, the third timing condition includes the time interval between the i-th internal read signal and the i-th internal write signal. The third timing condition needs to ensure that the write operation can only be performed after the data reading and error correction of the storage location are completed, so as to write the error-corrected data to the storage location; the fourth timing condition includes the time interval between the internal precharge signal and the n-th internal write signal. The fourth timing condition needs to ensure that the precharge operation is performed only after the data writing of the n-th storage location is completed, that is, after the data writing of all n storage locations is completed.

[0153] In the disclosed embodiments, the corresponding delay adjustment signals can be determined through testing to ensure that each preset timing condition is met. The four delay adjustment signals can be determined simultaneously during the testing phase, or separately in any order. When determined separately, the determined delay adjustment signals remain fixed at their values ​​during the testing phase, thereby ensuring that the overall delay is optimal.

[0154] In some embodiments, as Figure 9 As shown, the ECS circuit 20 may further include an ECS mode indication circuit 203;

[0155] The ECS mode indication circuit 203 is configured to generate and output a mode control signal at a first level when the ECS mode parameter indicates that the burst ECS mode is in progress, and to generate and output a mode control signal at a second level when the ECS mode parameter indicates that the normal ECS mode is in progress;

[0156] The ECS control circuit 202 is further configured to receive a mode control signal and, when the mode control signal is at a first level, control the execution of ECS operations on n adjacent storage locations in sequence based on each ECS command signal, and, when the mode control signal is at a second level, control the execution of ECS operations on only one storage location based on each ECS command signal.

[0157] It should be noted that the embodiment of the present disclosure can also be combined with the ECS mode to control the working mode of the ECS control circuit 202. Here, the ECS mode may include a burst ECS mode and a normal ECS mode. Only when the mode control signal is at the first level (corresponding to the burst ECS mode), n ECS operations are continuously performed on n adjacent storage locations in sequence based on an ECS command signal, and when the mode control signal is at the second level (corresponding to the normal ECS mode), only one ECS operation is performed based on one ECS command; a control circuit may be provided inside the memory to monitor the state of the memory to determine whether to enter the burst ECS mode or the normal ECS mode. For example, if it is detected that the memory is relatively idle, the burst ECS mode can be entered. The first level can be a high level, the second level can be a low level, or vice versa, and there is no specific limitation on this.

[0158] It should also be noted that the mode control signal can be generated by decoding the ECS mode parameters (operand OP) stored in the mode register of the memory. That is, the ECS mode indication circuit 203 is implemented by the mode register storing the ECS mode parameters. The parameters in the mode register can be preset at the factory or modified by sending a mode register write command by the controller.

[0159] In some embodiments, as Figure 10 As shown, the ECS circuit 20 further includes:

[0160] The address generation circuit 204 is configured to perform address counting according to the internal command signal, and sequentially generate and output n target addresses to indicate n storage locations corresponding to the execution of the ECS operation;

[0161] The address generation circuit 204 is further configured to generate a count completion signal when all addresses have completed counting.

[0162] It should be noted that the cumulative number of internal command signals, such as the internal activation signal, the internal read signal, the internal write signal, and the internal pre-charge signal, can indicate the current ECS stage. For example, the cumulative number of internal activation signals can indicate the memory row currently undergoing an ECS operation, the cumulative number of internal read signals and internal write signals can indicate the memory location currently undergoing an ECS operation, and the cumulative number of internal pre-charge signals can indicate the memory row currently completing an ECS operation.

[0163] Therefore, the embodiment of the present disclosure may utilize the address generation circuit 204 to perform address counting based on the internal command signal to output a corresponding target address, where the target address indicates a storage location where the ECS operation is to be performed.

[0164] In some embodiments, the memory to which the ECS circuit 20 belongs includes a memory array for storing data. Figure 11 , which shows a schematic diagram of the composition structure of a storage array provided by an embodiment of the present disclosure, such as Figure 11 As shown, the memory array 60 includes at least one memory group BG, the memory group BG includes at least one memory block BA, and the memory block BA includes at least one row ROW and at least one column Col.

[0165] exist Figure 11 In the example shown, the memory array 60 (also referred to as Array, DRAM Array) includes four memory groups: BG0, BG1, BG2, and BG3. Each memory group includes four memory blocks: BA0, BA1, BA2, and BA3. Taking BA3 in BG1 as an example, the memory block BA3 includes six rows (ROW): ROW0, ROW1, ROW2, ROW3, ​​ROW4, and ROW5. The memory block BA3 includes eight columns (Col): Col0, Col1, Col2, Col3, Col4, Col5, Col6, and Col7. Figure 11 In the diagram, a circle represents a storage location.

[0166] Since n adjacent memory locations in a row of memory correspond to the same ECS command signal, these n memory locations have the same memory group address (BG address), the same memory block address (BA address), the same row address (ROW address), and the same upper column address.

[0167] Here, the high-order column address is an address at a relatively high position in the column address, and the low-order column address is an address at a relatively low position in the column address. Figure 11 As shown, assuming a row includes 8 storage locations, n = 2, then the column address is 3 bits, the high-order column address is the first 2 high-order bits, and the low-order column address is the last low-order bit. In ROW0, the two storage locations corresponding to the same ECS command signal are marked with dashed boxes. The high-order column address is used to locate the storage location group corresponding to the dashed box, and the low-order column address is used to locate a specific storage location within the storage location group.

[0168] The number of bits of the low-order column address is denoted as x, where x is a positive integer and corresponds to n, indicating n adjacent target addresses; x and n have the following relationship: x =n. For example Figure 11 In this example, if n=2, then x=1. In another example, if n=4, then x=2. The specific values ​​of n and x are not particularly limited herein, but generally, n is an even number.

[0169] In some embodiments, as Figure 12As shown, the address generation circuit 204 includes a first column counter 2041, a second column counter 2042, a row counter 2043, and an array counter 2044. The target address includes a target storage group address, a target storage block address, a target row address, and a target column address. The target column address includes an upper column address and a lower column address. The target address is the address of the storage location where the ECS operation is to be performed.

[0170] like Figure 12 As shown, the first column counter 2041 is electrically connected to the ECS control circuit 202 and is configured to count the columns of the current storage row according to the internal precharge signal, generate and output a high-order column address; and generate and output a column end signal when the high-order column address indicates that the column count of the current storage row is completed;

[0171] It should be noted that, combined with Figure 11 As shown, assuming that the current storage row is ROW0, the number of storage locations in ROW0 is the number of columns in BA3, so it is called column counting of the storage row. The n storage locations corresponding to one ECS command signal are recorded as a storage position group. Each time a precharge signal is generated, it indicates that the ECS operation of a storage position group is completed. The first column counter 2041 counts the internal precharge signal only within one storage row. If all the storage locations in the current storage row complete the ECS operation, the next row is used as the new current storage row, and the first column counter 2041 starts counting again. Compared with the column counter used to generate the column address in the scheme where each ECS command signal corresponds to one ECS operation, the count value of the first column counter 2041 is reduced when the column end signal is output. For example, when n=2, the count value is reduced by half.

[0172] For example, Figure 11The four storage location groups in ROW0 are respectively recorded as storage location group 0, storage location group 1, storage location group 2, and storage location group 3, and the corresponding high-order column addresses can be 00, 01, 10, and 11, respectively. The first column counter 2041 counts the internal precharge signal. When the count value is 0, it means that storage location group 0 has not completed ECS, and the high-order column address corresponding to storage location group 0 is output; when the count value is 1, it means that storage location group 0 has completed ECS and needs to continue ECS for storage location group 1, and the high-order column address corresponding to storage location group 1 is output; when the count value is 2, it means that storage location group 1 has completed ECS and needs to continue ECS for storage location group 2, and the high-order column address corresponding to storage location group 2 is output; when the count value is 3, it means that storage location group 2 has completed ECS and needs to continue ECS for storage location group 3, and the high-order column address corresponding to storage location group 3 is output. When the count value is 4, it indicates that the storage location group 3 completes the ECS and the column count of the current storage row ROW0 is completed. At this time, the first column counter 2041 outputs a column end signal to indicate that the column count of the current storage row is completed.

[0173] It should also be noted that a delay circuit can be connected between the first column counter 2041 and the ECS control circuit 202 to delay the precharge command signal before sending it to the first column counter 2041, so as to ensure that the ECS operations of n storage locations have been completed when the first column counter 2041 is counting.

[0174] It should also be noted that, as described above, count values ​​0 to 4 correspond to upper column addresses 00 to 11, respectively. Therefore, the output of the first column counter 2041 can be directly used as the upper column address. In this example, the output of the first column counter 2041 is at least 2 bits to ensure the output of a 2-bit upper column address. If the output of the first column counter 2041 is greater than 2 bits, only the lower 2 bits are used as the upper column address. Thus, when the count value output by the first column counter 2041 becomes 0 again, it indicates that the column count for the current storage row is complete.

[0175] like Figure 12 As shown, the second column counter 2042 is electrically connected to the ECS control circuit 202 and is configured to count the columns of the current storage row according to the internal read signal or the internal write signal, generate and output the low column address; and reset the low column address in response to the internal precharge signal.

[0176] It should be noted that each time an internal write signal or an internal read signal is generated, it indicates that an ECS operation of a storage location is in progress. Figure 11As shown, taking storage location group 0 as an example, the low-order column addresses corresponding to storage location 0 and storage location 1 are 0 and 1 respectively. The second column counter 2042 only counts internal write signals within the storage location group. When the count value is 0, it indicates that ECS is being performed on storage location 0, and a low-order column address corresponding to storage location 0 is generated. To avoid generating a low-order column address for storage location 1 before the ECS operation (read and write operations) for storage location 0 is completed, a delay circuit can be provided between the ECS control circuit 202 and the second column counter 2042. If the internal read command signal is counted, the delay circuit needs to delay the internal read command before sending it to the second column counter 2042. The delay time needs to ensure that the read and write operations for the storage location are completed. If the internal write command signal is counted, the delay circuit needs to delay the internal write command before sending it to the second column counter 2042. The delay time needs to ensure that the write operation for the storage location is completed. In this way, due to the delay effect of the delay circuit, when the count value is 1, it indicates that the ECS operation for storage location 0 is completed, and an ECS operation needs to be performed on storage location 1 to generate a low-order column address corresponding to storage location 1, so as to perform the ECS operation on storage location 1. After the ECS operation on storage location 1 is completed, a precharge command signal is generated. The precharge command signal can be used as a reset signal for the second column counter 2042 to reset the low-order column address output by the second column counter 2042 for use by the next storage location group.

[0177] It should also be noted that, as described above, the count values ​​0-1 correspond to the lower-order column addresses 0-1, respectively. Therefore, the output of the second column counter 2042 can be directly used as the lower-order column address. In this example, the output of the second column counter 2042 is at least 1 bit to ensure that a 1-bit lower-order column address is output. If the output of the second column counter 2042 is greater than 1 bit, only the lower-order bit is used as the lower-order column address. In this way, when the count value output by the second column counter 2042 becomes 0 again, it can also indicate that counting within the current storage location group is complete.

[0178] It should also be noted that the mode control signal can serve as an enable signal for the second column counter 2042. In normal ECS mode, the second column counter 2042 is inoperative based on the mode control signal at the second level, and outputs the target column address based on the count value of the first column counter 2041. The output of the first column counter 2041 can directly serve as the target column address. In burst ECS mode, the second column counter 2042 operates based on the mode control signal at the first level. The first column counter 2041 outputs the high-order column address of the target column address, and the second column counter 2042 outputs the low-order column address of the target column address.

[0179] like Figure 12As shown, the row counter 2043 is configured to count the rows of the current storage block according to the column end signal, generate and output the target row address; and generate and output the row end signal when the target row address indicates that the row count of the current storage block is completed.

[0180] It should be noted that the row counter 2043 counts according to the column end signal output by the first column counter 2041, wherein the row counter 2043 specifically counts the column end signal. Figure 11 Taking BA3 in BAG1 as the current storage block as an example, the ECS operation is performed in the order from ROW0 to ROW5. When the ECS operation of ROW0 has not yet ended, the first column counter 2041 has not yet generated a column end signal, and the count value of the row counter 2043 is 0 (in the present disclosed embodiment, the initial value of the counter is 0 as an example). At this time, the target row address output is the row address of ROW0; wherein, the count value of the row counter 2043 represents the number of storage rows in the current storage block that have completed the ECS operation. After all storage locations in ROW0 complete ECS, the first column counter 2041 generates a column end signal and sends it to the row counter 2043. The row count value of the row counter 2043 is incremented by 1, and it is necessary to switch to performing ECS ​​operations on the storage locations in ROW1, and output the row address of ROW1 as the target row address. After all storage locations in ROW1 complete ECS, the first column counter 2041 generates another column end signal and sends it to the row counter 2043. The row count value is incremented by 1, and it is necessary to switch to performing ECS ​​operations on the storage locations in ROW2, and output the row address of ROW2 as the target row address. ..., since BA3 includes 6 rows, when the row count value is 6, it means that the storage locations in all storage rows in BA3 have completed ECS, and the row count of BA3 is completed. At this time, the row counter 2043 also generates a row end signal to indicate that the ECS of BA3 is complete. Afterwards, the row counter 2043 resets the count value to zero and continues row counting for the next memory block. This process is repeated for each BA in the memory array 60 until the counting of each BA in the memory array 60 is complete. That is, the row counter 2043 is also configured to continue row counting for the next memory block after generating a row end signal, until the row counting of each memory block in the memory array is complete.

[0181] It should also be noted that, similar to the aforementioned column address, the output of the row counter 2043 can also be directly used as the target row address, and the column end signal it outputs can be used as its own reset signal to reset its own count value.

[0182] like Figure 12As shown, the array counter 2044 is configured to count the storage blocks and storage groups according to the row end signal, generate and output the target storage block address and the target storage group address; and generate and output the count end signal when the target storage block address and the target storage group address indicate that all address counting is completed.

[0183] It should be noted that the array counter 2044 counts the storage blocks and storage groups in a similar manner to the row counter 2043 counts the storage rows. Figure 13 As shown, the array counter 2044 may include a storage block counter 2045 and a storage group counter 2046, where:

[0184] The memory block counter 2045 is configured to count the memory blocks of the current memory group according to the row end signal, generate and output a target memory block address; and generate and output a memory block end signal when the target memory block address indicates that the memory block count of the current memory group is completed;

[0185] The storage group counter 2046 is configured to count the storage groups of the storage array according to the storage block end signal, generate and output a target storage group address; and generate and output a count end signal when the target storage group address indicates that the storage group counting of the storage array is completed.

[0186] It should be noted that the storage block counter 2045 counts the row end signal. Figure 11 Taking BG0 in the example, assuming that the order of executing ECS ​​operations is BA0, BA1, BA2, and BA3, the count value of the storage block counter 2045 increases by 1 every time it receives a row end signal. The row end signal indicates that all storage rows in the current storage block have completed the ECS operation.

[0187] During the ECS operation on BA0, the count value of the storage block counter 2045 is 0, and the target storage block address corresponding to BA0 (for example, 00) is output; after the ECS operation on all storage rows in BA0 is completed, the row counter 2043 will generate a row end signal and send it to the storage block counter 2045, the count value of the storage block counter 2045 will be increased by 1 to 1, and the storage block counter 2045 will output the target storage block address corresponding to BA1 (for example, 01); during the ECS operation on BA1, the count value of the storage block counter 2045 is always 1, and the target storage block address corresponding to BA1 is always output; after the ECS operation on all storage rows in BA1 is completed, the row counter 2043 will generate a row end signal and send it to the storage block counter 2045, the count value of the storage block counter 2045 will be increased by 1 to 1, and the storage block counter 2045 will output the target storage block address corresponding to BA1 (for example, 01); during the ECS operation on BA1, the count value of the storage block counter 2045 is always 1, and the target storage block address corresponding to BA1 is always output; The device 2043 will generate a row end signal and send it to the storage block counter 2045. The count value of the storage block counter 2045 will be increased by 1 to 2, and the storage block counter 2045 will output the target storage block address corresponding to BA2 (for example, 10); similarly, when the row end signal is received again, the count value of the storage block counter 2045 will be increased by 1 to 3, and the target storage block address corresponding to BA3 (for example, 11) will be output; when the row end signal is received again, all storage locations in the entire BG0 have completed the ECS operation, and the storage block counter 2045 will output 00 again, indicating that the storage block count of the current storage group (BG0) is completed, and a storage block end signal will be generated and sent to the storage group counter 2046.

[0188] It should also be noted that, similar to the aforementioned row address, the output of the storage block counter 2045 can also be directly used as the target storage block address, and the storage block end signal it outputs can be used as its own reset signal to reset its own count value.

[0189] The storage group counter 2046 counts the storage block end signal. Figure 11 For example, assuming that the order of executing the ECS operation is BG0, BG1, BG2, and BG3, the storage group counter 2046 increases the count value by 1 each time it receives a storage block end signal. The storage block end signal indicates that all storage blocks in the current storage group have completed the ECS operation.

[0190] During the execution of the ECS operation on BG0, the count value of the storage group counter 2046 is 0, and the target storage group address corresponding to BG0 (for example, 00) is output; after the ECS operation on all storage blocks in BG0 is completed, the storage block counter 2045 will generate a storage block end signal and send it to the storage group counter 2046, the count value of the storage group counter 2046 will be increased by 1 to 1, and the storage group counter 2046 will output the target storage group address corresponding to BG1 (for example, 01); during the execution of the ECS operation on BG1, the count value of the storage group counter 2046 is always 1, and the target storage group address corresponding to BG1 is always output; after the ECS operation on all storage blocks in BG1 is completed After the operation, the storage block counter 2045 will generate a storage block end signal and send it to the storage group counter 2046. The count value of the storage group counter 2046 will be increased by 1 to 2, and the storage group counter 2046 will output the target storage group address corresponding to BG2 (for example, 10); similarly, when the storage block end signal is received again, the count value of the storage group counter 2046 will be increased by 1 to 3, and the target storage group address corresponding to BG3 (for example, 11) will be output; when the storage block end signal is received again, all storage locations in the entire storage array 60 have completed the ECS operation, and the storage group counter 2046 will output 00 again, indicating that the storage group counting of the storage array 60 is completed, and a count end signal is generated.

[0191] After completing the storage group counting, the storage group counter 2046 will clear the count value and reset the target storage group address until the next ECS operation is performed on the storage array 60, and will continue counting according to the above process.

[0192] It should also be noted that, similar to the aforementioned row address, storage block address, etc., the output of the storage group counter 2046 can also be directly used as the target storage group address, and the count end signal it outputs can be used as its own reset signal to reset its own count value.

[0193] It can be understood that the storage block counter 2045 is used to count the storage blocks of the storage group, and the storage group counter 2046 is used to count the storage groups in the storage array. The storage block counter 2045 and the storage group counter 2046 can be integrated into the array counter 2044 module to realize related functions.

[0194] In other embodiments, Figure 14 As shown, the address counting module 204 includes a column counter 2047, a row counter 2043 and an array counter 2044, wherein:

[0195] The column counter 2047 is electrically connected to the ECS control circuit 202 and is configured to count the columns of the current storage row according to the internal write signal (or the internal read signal), generate and output a target column address; and generate and output a column end signal when the target column address indicates that the column count of the current storage row is completed;

[0196] The row counter 2043 is configured to count the rows of the current storage block according to the column end signal, generate and output a target row address, and generate and output a row end signal when the target row address indicates that the row count of the current storage block is completed;

[0197] The array counter 2044 is configured to count the storage blocks and storage groups according to the row end signal, generate and output the target storage block address and the target storage group address; and generate and output the count end signal when the target storage block address and the target storage group address indicate that all address counting is completed.

[0198] It should be noted that the embodiment of the present disclosure may not split the target column address into a high-order column address and a low-order column address, but instead use a column counter 2047 to count the internal write signal (or internal read signal), and output the next target column address every time the count value increases by 1.

[0199] Similarly, a delay circuit needs to be set between the column counter 2047 and the ECS control circuit 202. The column counter 2047 receives the delayed internal write signal (or internal read signal) to ensure that when the current internal write command executes the write operation, no address counting is performed and the corresponding target address remains unchanged; when the current write operation ends, counting is performed to generate a new target address corresponding to the next read or write operation.

[0200] The counting method of the row counter 2043 and the array counter 2044 is the same as that of the above embodiment and will not be described again here.

[0201] See also Figure 15 , (a) is a signal timing diagram of an ECS command signal performing an ECS operation on n (n=2 as an example) storage locations, and (b) is a signal timing diagram of an ECS command signal performing an ECS operation on only one storage location.

[0202] In contrast, in (a), corresponding to the unshielded ECS command signal ECS_CMD, the following are generated in sequence: the internal activation signal ECSAct, the first internal read signal ECSRd, the first internal write signal ECSWr, the second internal read signal ECSRd, the second internal write signal ECSWr, and the internal pre-charge signal ECSPre, thereby enabling ECS ​​operations on two storage locations; corresponding to the shielded ECS command signal ECS_CMD, no internal command signal is generated. In (b), corresponding to each ECS command signal ECS_CMD, the following are generated in sequence: the internal activation signal ECSAct, the internal read signal ECSRd, the internal write signal ECSWr, and the internal pre-charge signal ECSPre.

[0203] In this way, the disclosed embodiment utilizes the remaining time after one ECS operation to perform an additional internal read-modify-write (RMW) operation on an adjacent storage location. That is, the ECS command signal ECS_CMD generated by stealing one Refab / Sref command signal can generate internal command signals corresponding to two internal read-modify-write operations. The corresponding schemes (a) and (b) steal the same number of Refab / Sref command signals within an ECS cycle (e.g., 24 hours), but only half of the ECS command signals ECS_CMD are used to generate the ECS command signal ECS_CMD to indicate the execution of the ECS operation, and the other half do not perform any operation. Since only half of the ECS command signals ECS_CMD are used to indicate the execution of the ECS operation, the operation corresponding to the Refab / Sref command signal can be omitted within the DRAM, thereby saving activation and precharge operations, reducing IDD0 and saving memory power consumption. At the same time, the internal counter counts the corresponding column address by half.

[0204] Figure 16 and Figure 15 Similar, except that Figure 15 The ECS control circuit 202 shields the received ECS command signal. Figure 16 The corresponding ECS ​​command generation circuit 201 shields the generation of the ECS command signal. Among them, the second ECS latch signal ECSlat2 is an intermediate signal generated when the ECS command generation circuit 201 generates the ECS command signal. Its number of pulses is consistent with the number of stolen refresh command signals. By shielding the generation of the ECS command signal, the shielding of the ECS command signal is achieved. Figure 15 The same, no further details here.

[0205] In another embodiment of the present disclosure, an ECS method is provided, which is applied to a memory. The method includes:

[0206] An internal command signal is generated based on the ECS command signal, and the internal command signal is used to instruct the memory to sequentially perform ECS operations on n adjacent storage locations, where n is an integer greater than or equal to 2.

[0207] In some embodiments, the internal command signal includes an internal activation signal, n groups of internal read and write signals, and an internal pre-charge signal generated in sequence according to preset timing conditions; each group of internal read and write signals includes an internal read signal and an internal write signal generated in sequence, and each group of internal read and write signals corresponds to a storage location.

[0208] In some embodiments, generating the internal command signal based on the ECS command signal includes:

[0209] In response to the ECS command signal, the internal clock signal is counted to generate a count value, and a set of enable signals is generated according to the count value; wherein the set of enable signals includes an activation enable signal, n sets of read and write enable signals, and a precharge enable signal generated in sequence, and each set of read and write enable signals includes a read enable signal and a write enable signal generated in sequence;

[0210] Based on a set of enable signals, the following are generated in sequence: internal activation signal, n sets of internal read and write signals, and internal pre-charge signal.

[0211] In some embodiments, the method further comprises:

[0212] At intervals of a preset time or a preset number of refresh command signals, an ECS command signal is generated and output based on one refresh command signal.

[0213] In some embodiments, the method further comprises:

[0214] After each internal command signal is generated based on an ECS command signal, the n-1 ECS command signals received thereafter are masked.

[0215] It should be noted that the ECS method provided in the embodiment of the present disclosure can be implemented by the aforementioned ECS circuit 20. For details not disclosed in the embodiment of the present disclosure, reference can be made to the description of the aforementioned embodiment for understanding, and no further details will be given here.

[0216] In yet another embodiment of the present disclosure, a memory is provided, comprising a memory array and the ECS circuit 20 according to any one of the aforementioned embodiments;

[0217] The storage array includes a plurality of storage locations, and the storage locations are used to store data;

[0218] The ECS circuit 20 is configured to generate an internal command signal based on the ECS command signal to control the sequential execution of ECS operations on n adjacent storage locations, where n is an integer greater than or equal to 2.

[0219] It should be noted that the storage array may be the aforementioned storage array 60. Details not disclosed in this embodiment may be understood by referring to the description of the aforementioned embodiment and will not be repeated here.

[0220] In the embodiment of the present disclosure, the memory may be DDR DRAM, such as LPDDR6 or other memory specifications, without any limitation here.

[0221] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0222] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0223] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0224] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0225] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0226] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0227] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. An ECS circuit, characterized in that: include: an ECS command generation circuit configured to generate an ECS command signal; The ECS control circuit is electrically connected to the ECS command generation circuit and is configured to receive the ECS command signal and generate an internal command signal based on the ECS command signal to control the execution of ECS operations on n adjacent storage locations in sequence, where n is an integer greater than or equal to 2.

2. The ECS circuit according to claim 1, characterized in that The internal command signal includes an internal activation signal, n groups of internal read and write signals, and an internal pre-charge signal generated in sequence according to preset timing conditions; each group of the internal read and write signals includes an internal read signal and an internal write signal generated in sequence, and each group of the internal read and write signals corresponds to one of the storage locations.

3. The ECS circuit according to claim 2, characterized in that: The ECS control circuit includes: a counting circuit configured to, in response to the ECS command signal, count an internal clock signal to generate a count value, and generate a set of enable signals according to the count value; wherein the set of enable signals includes an activation enable signal, n sets of read and write enable signals, and a precharge enable signal generated in sequence, and each set of read and write enable signals includes a read enable signal and a write enable signal generated in sequence; The internal command generation circuit is electrically connected to the counting circuit and configured to receive the set of enable signals and generate, based on the set of enable signals, the internal activation signal, the n sets of internal read / write signals, and the internal precharge signal in sequence.

4. The ECS circuit according to claim 3, characterized in that: The counting circuit is further configured to generate the activation enable signal at an active level when the count value reaches a first preset value, generate the read enable signal at an active level when the count value reaches a second preset value, generate the write enable signal at an active level when the count value reaches a third preset value, and generate the precharge enable signal at an active level when the count value reaches a fourth preset value; Among them, the second preset value includes n second sub-preset values, and the third preset value includes n third sub-preset values; the first second sub-preset value is greater than the first preset value, the i-th third sub-preset value is greater than the i-th second sub-preset value, the i+1-th second sub-preset value is greater than the i-th third sub-preset value, the n-th third sub-preset value is greater than the n-th second sub-preset value, and the fourth preset value is greater than the n-th third sub-preset value, and i is a positive integer less than n.

5. The ECS circuit according to claim 3, characterized in that: The internal command generation circuit includes an activation command generation circuit, a read command generation circuit, a write command generation circuit and a precharge command generation circuit; the activation command generating circuit being configured to generate the internal activation signal upon receiving the activation enable signal at an active level; The read command generation circuit is configured to generate the internal read signal when receiving the read enable signal at an active level; The write command generation circuit is configured to generate the internal write signal when receiving the write enable signal at an active level; The precharge command generation circuit is configured to generate the internal precharge signal upon receiving the precharge enable signal at an active level.

6. The ECS circuit according to claim 3, characterized in that: The counting circuit is further configured to reset the count value in response to the internal precharge signal.

7. The ECS circuit according to claim 5, characterized in that: The internal command generation circuit further includes one or more of an activation command timing adjustment circuit, a read command timing adjustment circuit, a write command timing adjustment circuit, and a precharge command timing adjustment circuit; The activation command timing adjustment circuit is electrically connected between the counting circuit and the activation command generation circuit, and is configured to receive a first delay adjustment signal and the activation enable signal, adjust the delay of the activation enable signal according to the first delay adjustment signal, and then send the signal to the activation command generation circuit; The read command timing adjustment circuit is electrically connected between the counting circuit and the read command generation circuit, and is configured to receive a second delay adjustment signal and the read enable signal, and adjust the delay of the read enable signal according to the second delay adjustment signal before sending the signal to the read command generation circuit; The write command timing adjustment circuit is electrically connected between the counting circuit and the write command generation circuit, and is configured to receive a third delay adjustment signal and the write enable signal, and adjust the delay of the write enable signal according to the third delay adjustment signal before sending the signal to the write command generation circuit; The precharge command timing adjustment circuit is electrically connected between the counting circuit and the precharge command generation circuit, and is configured to receive a fourth delay adjustment signal and the precharge enable signal, and adjust the delay of the precharge enable signal according to the fourth delay adjustment signal before sending it to the precharge command generation circuit.

8. The ECS circuit according to claim 7, characterized in that: The activation command timing adjustment circuit is further configured to sequentially receive a plurality of first preset delay adjustment signals during a test phase, and sequentially adjust the delay of the activation enable signal according to the plurality of first preset delay adjustment signals, so as to determine the first preset delay adjustment signal that enables the internal activation signal to meet a first timing condition as the first delay adjustment signal; The read command timing adjustment circuit is further configured to sequentially receive a plurality of second preset delay adjustment signals during a test phase, and sequentially adjust the delay of the read enable signal according to the plurality of second preset delay adjustment signals, so as to determine the second preset delay adjustment signal that enables the internal read signal to meet a second timing condition as the second delay adjustment signal; The write command timing adjustment circuit is further configured to sequentially receive a plurality of third preset delay adjustment signals during a test phase, and sequentially adjust the delay of the write enable signal according to the plurality of third preset delay adjustment signals, so as to determine the third preset delay adjustment signal that enables the internal write signal to meet a third timing condition as the third delay adjustment signal; The pre-charge command timing adjustment circuit is further configured to sequentially receive a plurality of fourth preset delay adjustment signals during a test phase, and sequentially adjust the delay of the pre-charge enable signal according to the plurality of fourth preset delay adjustment signals, so as to determine the fourth preset delay adjustment signal that makes the internal pre-charge signal meet the fourth timing condition as the fourth delay adjustment signal.

9. The ECS circuit according to claim 1, wherein: The ECS circuit also includes an ECS mode indication circuit; The ECS mode indication circuit is configured to generate and output a mode control signal at a first level when the ECS mode parameter indicates that the burst ECS mode is in progress, and to generate and output the mode control signal at a second level when the ECS mode parameter indicates that the normal ECS mode is in progress; The ECS control circuit is further configured to receive the mode control signal and, when the mode control signal is at a first level, control the ECS operation to be performed sequentially on n adjacent storage locations based on each of the ECS command signals; and, when the mode control signal is at a second level, control the ECS operation to be performed on only one storage location based on each of the ECS command signals.

10. The ECS circuit according to claim 2, wherein: The ECS circuit further includes: An address generation circuit is configured to perform address counting according to the internal command signal, and sequentially generate and output n target addresses to indicate the n storage locations corresponding to the execution of the ECS operation; The address generation circuit is further configured to generate a count completion signal when all addresses have completed counting.

11. The ECS circuit according to claim 10, wherein: The address generation circuit includes a first column counter, a second column counter, a row counter and an array counter. The target address includes a target storage group address, a target storage block address, a target row address and a target column address. The target column address includes a high-order column address and a low-order column address. The first column counter is electrically connected to the ECS control circuit and configured to count the columns of the current storage row according to the internal precharge signal, generate and output the upper column address; and generate and output a column end signal when the upper column address indicates that the column count of the current storage row is completed; The second column counter is electrically connected to the ECS control circuit and configured to count the columns of the current storage row according to the internal read signal, generate and output the lower column address; and reset the lower column address in response to the internal precharge signal; The row counter is configured to count rows of the current storage block according to the column end signal, generate and output a target row address; and generate and output a row end signal when the target row address indicates that the row counting of the current storage block is completed; The array counter is configured to count the storage blocks and storage groups according to the row end signal, generate and output the target storage block address and the target storage group address; and generate and output the count end signal when the target storage block address and the target storage group address indicate that all address counting is completed.

12. The ECS circuit according to any one of claims 1 to 11, characterized in that: The ECS command generation circuit is configured to generate and output an ECS command signal based on a refresh command signal at intervals of a preset time or at intervals of a preset number of refresh command signals.

13. The ECS circuit according to any one of claims 1 to 11, characterized in that: The ECS control circuit is further configured to, after each time the internal command signal is generated based on one ECS command signal, mask n-1 ECS command signals received thereafter.

14. An ECS method, characterized in that: Applied to a memory, the method includes: An internal command signal is generated based on the ECS command signal, where the internal command signal is used to instruct the memory to sequentially perform ECS operations on n adjacent storage locations, where n is an integer greater than or equal to 2.

15. The ECS method according to claim 14, wherein: The internal command signal includes an internal activation signal, n groups of internal read and write signals, and an internal pre-charge signal generated in sequence according to preset timing conditions; each group of the internal read and write signals includes an internal read signal and an internal write signal generated in sequence, and each group of the internal read and write signals corresponds to one of the storage locations.

16. The ECS method according to claim 15, characterized in that Generating an internal command signal based on the ECS command signal includes: In response to the ECS command signal, the internal clock signal is counted to generate a count value, and a set of enable signals is generated according to the count value; wherein the set of enable signals includes an activation enable signal, n sets of read and write enable signals, and a precharge enable signal generated in sequence, and each set of read and write enable signals includes a read enable signal and a write enable signal generated in sequence; Based on the set of enable signals, the internal activation signal, the n sets of internal read / write signals, and the internal pre-charge signal are sequentially generated.

17. The ECS method according to any one of claims 14 to 16, characterized in that: The method further comprises: At intervals of a preset time or a preset number of refresh command signals, one ECS command signal is generated and output based on one refresh command signal.

18. The ECS method according to any one of claims 14 to 16, characterized in that: The method further comprises: After each internal command signal is generated based on one ECS command signal, n-1 ECS command signals received thereafter are masked.

19. A memory, characterized in that: comprising a memory array and an ECS circuit according to any one of claims 1 to 13; The storage array includes a plurality of storage locations, each of which is used to store data; The ECS circuit is configured to generate an internal command signal based on the ECS command signal to control the ECS operation to be performed on n adjacent storage locations in sequence, where n is an integer greater than or equal to 2.

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