Storage chip testing method and device, readable storage medium and electronic equipment

Abstract

The invention discloses a memory chip test method and device, a readable storage medium and electronic equipment, and the method comprises the steps: determining test items, test subitems and test cases required by a plurality of memory chips, determining a plurality of test boards according to the test items, the test subitems and the test cases, outputting a memory chip insertion instruction, and if the plurality of memory chips are inserted into the plurality of test boards, outputting a memory chip insertion instruction; if yes, setting a test precondition according to the test case, and issuing a test instruction to the plurality of test boards to enable the plurality of test boards to test the plurality of memory chips, so that the plurality of test boards are utilized to test the plurality of memory chips in parallel, and different test items and test cases are covered, so that a plurality of test platforms and a plurality of test items can be integrated to simplify the test process, and the test efficiency is improved. According to the method and the device, the test efficiency and the test comprehensiveness can be improved, a plurality of memory chips can be tested for one test item at the same time, test preconditions are set according to test cases after the memory chips are inserted into the test board, and the test early-stage preparation work can be simplified, so that the test efficiency and the test comprehensiveness are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a memory chip testing method, device, readable storage medium, and electronic equipment. Background Art

[0002] Chip testing is one of the important links in the chip production cycle and an important means to ensure chip quality. Existing memory chip testing modules include more than ten modules such as protocol testing, module testing, stress testing, life testing, performance testing, and compatibility testing. Each module contains multiple sub-modules or sub-use cases, with a total of hundreds of test cases. In actual testing work, hundreds of environments need to be set up for different test versions, modules, and use cases. The testing process is complex and resources are scarce. In the actual testing process, only two chips are tested for each use case or sub-module. However, the firmware is affected by probabilistic bugs and environmental factors. Therefore, testing only two chips cannot rule out contingencies.

[0003] During memory chip testing, different test items and use cases require different pre-conditions, such as data pre-filling, voltage, current, temperature, rate, and other parameter settings. The current testing method involves building the required test environment for each chip under test, which is cumbersome and inefficient. Furthermore, the test duration required for different test items varies, and the test granularity is numerous, making it difficult to track test data in real time, resulting in an inability to understand test progress and results in a timely manner. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a memory chip testing method, device, readable storage medium and electronic equipment, which can improve the efficiency and comprehensiveness of the test.

[0005] In order to solve the above technical problems, a technical solution adopted by the present invention is: A memory chip testing method comprises the following steps: Determine the test items, test sub-items, and test cases required for multiple memory chips; Determine a plurality of test boards according to the test items, the test sub-items and the test cases, and output a memory chip insertion instruction; determining whether the plurality of memory chips have been inserted into the plurality of test boards, and if so, setting a test precondition according to the test case; A test instruction is issued to the multiple test boards so that the multiple test boards test the multiple memory chips, wherein the test instruction includes the test precondition and a script execution command corresponding to the test case.

[0006] In order to solve the above technical problems, another technical solution adopted by the present invention is: A memory chip testing device comprises the following steps: A test item determination module is used to determine the test items, test sub-items and test cases required for multiple memory chips; a test board determination module, configured to determine a plurality of test boards according to the test items, the test sub-items, and the test cases, and output a memory chip insertion instruction; A setting module, configured to determine whether the plurality of memory chips have been inserted into the plurality of test boards, and if so, to set test preconditions according to the test case; The test module is used to send test instructions to the multiple test boards so that the multiple test boards test the multiple memory chips. The test instructions include the test preconditions and script execution commands corresponding to the test cases.

[0007] In order to solve the above technical problems, another technical solution adopted by the present invention is: A computer-readable storage medium stores a computer program, which implements the various steps of the above-mentioned memory chip testing method when executed by a processor.

[0008] In order to solve the above technical problems, another technical solution adopted by the present invention is: An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, each step in the above-mentioned memory chip testing method is implemented.

[0009] The beneficial effects of the present invention are: determining the test items, test sub-items and test cases required for multiple memory chips, determining multiple test boards according to the test items, test sub-items and test cases, and outputting memory chip insertion instructions. If multiple memory chips have been inserted into multiple test boards, test preconditions are set according to the test cases, and test instructions are issued to multiple test boards so that multiple test boards test multiple memory chips. In this way, it is only necessary to determine the test items, test sub-items and test cases that need to be performed, and multiple test boards can be used to test multiple memory chips in parallel, and cover different test items and test cases. It can integrate multiple test platforms and multiple test items to simplify the test process, and can test multiple memory chips for one test item at the same time to eliminate the randomness of the test. After the memory chip has been inserted into the test board, the test preconditions are also set according to the test cases, which can simplify the preliminary preparation work for the test, thereby improving the efficiency and comprehensiveness of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a flowchart of a memory chip testing method according to an embodiment of the present invention; Figure 2This is a schematic structural diagram of a memory chip testing device according to an embodiment of the present invention; Figure 3 This is a schematic structural diagram of an electronic device according to an embodiment of the present invention; Figure 4 Schematic diagram of the interaction between a host computer and a test module in a memory chip testing method according to an embodiment of the present invention; Figure 5 A schematic diagram of test items and test sub-items contained therein in a memory chip testing method according to an embodiment of the present invention; Figure 6 Schematic diagram of a test board set in a memory chip testing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0011] To illustrate the technical content, achieved objectives and effects of the present invention in detail, the following description is given in conjunction with the embodiments and accompanying drawings.

[0012] Please refer to Figure 1 , a memory chip testing method, comprising the steps of: Determine the test items, test sub-items, and test cases required for multiple memory chips; Determine a plurality of test boards according to the test items, the test sub-items and the test cases, and output a memory chip insertion instruction; determining whether the plurality of memory chips have been inserted into the plurality of test boards, and if so, setting a test precondition according to the test case; A test instruction is issued to the multiple test boards so that the multiple test boards test the multiple memory chips, wherein the test instruction includes the test precondition and a script execution command corresponding to the test case.

[0013] From the above description, it can be seen that the beneficial effects of the present invention are: determining the test items, test sub-items and test cases required for multiple memory chips, determining multiple test boards according to the test items, test sub-items and test cases, and outputting memory chip insertion instructions. If multiple memory chips have been inserted into multiple test boards, test preconditions are set according to the test cases, and test instructions are issued to multiple test boards so that multiple test boards can test multiple memory chips. In this way, it is only necessary to determine the test items, test sub-items and test cases that need to be performed, and multiple test boards can be used to test multiple memory chips in parallel, and cover different test items and test cases. It can integrate multiple test platforms and multiple test items to simplify the test process, and can test multiple memory chips for one test item at the same time to eliminate the randomness of the test. After the memory chip has been inserted into the test board, the test preconditions are also set according to the test cases, which can simplify the preliminary preparation work for the test, thereby improving the efficiency and comprehensiveness of the test.

[0014] Furthermore, the determining of a plurality of test boards according to the test items, the test sub-items and the test cases includes: Determine a test module corresponding to the test item; Determining a test board subset corresponding to the test sub-item from the test module; A plurality of test boards corresponding to the test case are determined from the test board subset.

[0015] From the above description, it can be seen that a test item includes multiple test sub-items, and a test sub-item includes multiple test cases. By integrating different test modules, one test module corresponds to one test item, and multiple test boards are integrated under one test module. The test board subset corresponding to the test sub-item is determined from the test module, and the multiple test boards corresponding to the test case are determined from the test board subset. This ensures that multiple test boards can be used to test multiple memory chips at the same time in the future, covering different test cases, thereby improving the comprehensiveness and effectiveness of the test.

[0016] Furthermore, the sending of test instructions to the multiple test boards so that the multiple test boards test the multiple memory chips includes: A test instruction is sent to a test controller, so that the test controller analyzes the test instruction and starts the multiple test boards to test the multiple memory chips.

[0017] As can be seen from the above description, the test instructions are sent to the test controller, which can parse the test instructions and accurately start the corresponding test board to perform the test, thereby ensuring the stability of the test process.

[0018] Furthermore, determining whether the plurality of memory chips have been inserted into the plurality of test boards includes: Obtaining a bitmap corresponding to the test module; Determine whether the number of memory chips displayed on the bitmap is equal to the number of the multiple memory chips; if so, determine whether the memory chips displayed on the bitmap are located on the multiple test boards; if so, determine that the multiple memory chips have been inserted into the multiple test boards.

[0019] From the above description, it can be seen that when judging whether the memory chip is ready, the number and position of the memory chips displayed on the bitmap corresponding to the test module are used to determine whether multiple memory chips are accurately and completely inserted into multiple test boards, thereby ensuring that subsequent tests can be executed reliably.

[0020] Furthermore, after sending the test instructions to the multiple test boards so that the multiple test boards test the multiple memory chips, the method further includes: receiving test data uploaded by the plurality of test boards, wherein the test data includes log information; It is determined whether there is a preset keyword in the log information. If so, an alarm message is output and an error instruction is sent to the test board corresponding to the log information to stop the test board.

[0021] From the above description, it can be seen that during the test execution process, the test board will upload the test data to the host computer. The host computer determines whether the current test is normal by judging whether there are preset keywords in the log information. After detecting an abnormality, it will output an alarm message in time and send an error instruction to stop the test board from continuing the test, so as to handle the abnormal test in time.

[0022] Furthermore, it also includes: Acquire status indicator light information of the plurality of test boards, where the status indicator light information is used to indicate a test status; Mapping the status indicator light information to the bitmap.

[0023] As can be seen from the above description, by mapping the status indicator light information of the test board to a bitmap, the test status can be monitored in real time and the test situation can be understood intuitively.

[0024] Furthermore, it also includes: Determine whether each of the memory chips has been tested, and if so, obtain the number of the plurality of memory chips, the number of chips that passed the test, the number of chips that failed the test, and a test duration distribution graph; Acquire the detected preset keyword and a storage address of log information corresponding to the preset keyword; A test report is generated according to the test items, the test preconditions, the number of the multiple storage chips, the number of chips that passed the test, the number of chips that failed the test, the test time distribution graph, the detected preset keywords, and the storage address of the log information.

[0025] From the above description, it can be seen that after the test is completed, a test report is generated based on the test items, test preconditions, the number of multiple storage chips, the number of chips that passed the test, the number of chips that failed the test, the test time distribution graph, the detected preset keywords, and the storage address of the log information. The tester can understand the test results comprehensively and intuitively based on the test report.

[0026] Please refer to Figure 2 Another embodiment of the present invention provides a memory chip testing device, comprising the steps of: A test item determination module is used to determine the test items, test sub-items and test cases required for multiple memory chips; a test board determination module, configured to determine a plurality of test boards according to the test items, the test sub-items, and the test cases, and output a memory chip insertion instruction; A setting module, configured to determine whether the plurality of memory chips have been inserted into the plurality of test boards, and if so, to set test preconditions according to the test case; The test module is used to send test instructions to the multiple test boards so that the multiple test boards test the multiple memory chips. The test instructions include the test preconditions and script execution commands corresponding to the test cases.

[0027] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program implements the various steps in the above-mentioned memory chip testing method.

[0028] Please refer to Figure 3 Another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements each step of the above-mentioned memory chip testing method when executing the computer program.

[0029] The memory chip testing method, device, readable storage medium, and electronic device of the present invention are applicable to memory chip testing scenarios, such as eMMC (Embedded MultiMediaCard, embedded multimedia card), UFS (Universal Flash Storage, universal flash storage), etc., and are described below through specific implementation methods: Please refer to Figure 1 、 Figure 4-Figure 6 , embodiment 1 of the present invention is: A memory chip testing method comprises the following steps: S1. Determine the test items, test sub-items, and test cases required for multiple memory chips.

[0030] There are multiple test items, each test item includes multiple test sub-items, and each test sub-item includes multiple test cases covering multiple scenarios.

[0031] For example, Figure 5As shown, test items may include protocol testing, functional testing, stress testing, power consumption testing, performance testing, compatibility testing, stability testing, and life testing. Protocol testing tests whether the firmware complies with the eMMC protocol or UFS protocol rules. Functional testing tests whether the particles can perform various functions such as stress writing in different partitions. Stress testing tests the stability of particles in large IO reading and writing or extreme environments. Power consumption testing tests the power consumption of particles in various states such as sleep and active. Performance testing tests sequential / random read and write capabilities. Compatibility testing verifies whether it can work normally on multiple platforms. Stability testing tests the data retention ability of particles in high temperature, low temperature, or high and low temperature alternating environments.

[0032] Testers can select test items, test sub-items and test cases required for multiple memory chips on the host computer.

[0033] S2, determining multiple test boards according to the test items, the test sub-items, and the test cases, and outputting a memory chip insertion instruction, specifically including S21-S24: S21. Determine a test module corresponding to the test item.

[0034] S22. Determine a test board subset corresponding to the test sub-item from the test module.

[0035] S23. Determine multiple test boards corresponding to the test case from the test board subset.

[0036] Among them, such as Figure 6 As shown, a test module corresponds to a test item. There are multiple test modules. Each test module contains multiple test boards. Each test board corresponds to a test case of a test sub-item.

[0037] For example, test module 1 corresponds to protocol testing, test module 2 corresponds to functional testing, and so on. The test boards from the first to the second rows under test module 1 all correspond to the write protection test (test sub-item 1 under protocol testing), and the test boards from the third to the fourth rows all correspond to the FFU (Field Firmware Update) test (test sub-item 2 under protocol testing). All test boards in the first row under test module 1 correspond to test case 1 of the write protection test, and all test boards in the second row under test module 1 correspond to test case 2 of the write protection test, and so on.

[0038] In an optional embodiment, as Figure 6 As shown, each test board includes status indicators, voltage, current and temperature controllers connected to a communication API (Application Programming Interface).

[0039] S24. Output a memory chip insertion instruction.

[0040] The memory chip insertion instruction is output to prompt the tester to insert the memory chip into the corresponding test board.

[0041] S3. Determine whether the multiple memory chips have been inserted into the multiple test boards. If so, set test preconditions according to the test case.

[0042] In an optional implementation, the test preconditions include information such as voltage, current, temperature, and rate.

[0043] After all storage chips are inserted into the test board, the tester can set corresponding test preconditions according to different test cases. For example, the write protection in the UFS protocol test may require low-level formatting, power-on and initialization processing first, while the register test in the UFS protocol test only requires low-level formatting. The flashing packages required for power-off testing or upgrade testing are different. Individual use cases in the stability test need to verify the data retention capability in a high temperature environment of 85 degrees, and the stress test requires pre-filling data accounting for 80% of the total capacity. It can be seen from the above description that there are many test cases in the actual testing process and the test process is complicated. At present, most of these preconditions are manually operated one by one, so the testing workload is large, and the above low-level formatting, flashing, heating, filling data and other operations are all preparatory work that needs to be done before the formal test. In the present invention, the above content can be independently set by one-click check in the host computer software, which can be more flexibly adapted to different test cases. Even if there are new use cases or the use cases need to be modified later, the set preconditions can be changed at any time.

[0044] In an optional implementation, the test preconditions are saved as default settings for the test items after setting, and subsequent tests do not need to be set again. If the test preconditions need to be modified, the default settings are canceled and reset.

[0045] When the test preconditions are set and the test starts, the test controller will broadcast the settings to the base of the corresponding test board. The base will perform corresponding operations such as flashing, heating to 85 degrees, and filling data according to the setting sequence in the conditions.

[0046] The step of determining whether the plurality of memory chips have been inserted into the plurality of test boards comprises: Obtaining a bitmap corresponding to the test module; Determine whether the number of memory chips displayed on the bitmap is equal to the number of the multiple memory chips. If so, determine whether the memory chips displayed on the bitmap are located in the multiple test boards. If so, determine that the multiple memory chips have been inserted into the multiple test boards. Otherwise, output corresponding prompt information to ensure that the memory chips are accurately inserted.

[0047] S4. Sending test instructions to the multiple test boards so that the multiple test boards test the multiple memory chips, the test instructions including the test preconditions and script execution commands corresponding to the test cases.

[0048] In an optional implementation, a test instruction is sent to a test controller, so that the test controller parses the test instruction and then starts the multiple test boards to test the multiple memory chips.

[0049] The test board is connected to the test controller via a serial port, and the test controller interacts with the host computer via a communication API, such as Figure 4 shown.

[0050] S5. Receive test data uploaded by the multiple test boards, where the test data includes log information.

[0051] In an optional implementation, the log information includes important information such as chip particle logs and system logs of the test platform.

[0052] S6. Determine whether there is a preset keyword in the log information. If so, output an alarm message and send an error instruction to the test board corresponding to the log information to stop the test board.

[0053] The preset keyword is generally a field provided by the firmware to be printed for a certain error. The preset keyword is detected in order to terminate the error test in time, retain the test environment, and facilitate the acquisition of information in the chip at the time of the error. If the test fails, the log information can be used to determine whether it is caused by the environment or the firmware itself. If it is a firmware problem, the root cause of the error can be further obtained by analyzing the chip log. At the same time, the logs of test failure and test success can be compared to find the differences between them, providing direction for subsequent firmware optimization.

[0054] S7. Obtain status indicator light information of the multiple test boards, where the status indicator light information is used to indicate a test status.

[0055] S8, mapping the status indicator light information to the bitmap, such as Figure 6 shown.

[0056] S7 and S8 can be executed synchronously with S4-S6.

[0057] For example, when the memory chip is inserted into the test board, the status indicator light of the test board will be yellow, which is mapped to the bitmap at this time. You can intuitively understand whether the memory chip is ready from the bitmap. During the test process, if the memory chip fails (that is, the preset keyword is detected in the log information), the status indicator light of the test board will be flashing red, which is also mapped to the bitmap at this time, so you can intuitively understand the test situation.

[0058] S9. Determine whether the test of each of the memory chips has been completed. If so, obtain the number of the plurality of memory chips, the number of chips that passed the test, the number of chips that failed the test, and a test duration distribution diagram.

[0059] S10: Acquire the detected preset keyword and the storage address of the log information corresponding to the preset keyword.

[0060] S11. Generate a test report based on the test items, the test preconditions, the number of the multiple storage chips, the number of chips that passed the test, the number of chips that failed the test, the test time distribution graph, the detected preset keywords, and the storage address of the log information.

[0061] The above-mentioned memory chip testing method of the present invention integrates different test platforms and test items into a complete test board, classifies the test board according to the test module, and tests multiple memory chips of a use case in parallel by issuing a command at one time. It can be compatible with multiple test platforms and multiple test items to simplify the manual testing process, and can test multiple memory chips for one test item at the same time to reduce probabilistic errors. In addition, the present invention monitors the test status in real time through a bitmap, automatically generates a visual test report, alarms and notifications, sets preconditions and broadcasts them to a controller modularized with test items, thereby starting the corresponding test board, forming an integrated memory chip test, simplifying the memory chip testing process, effectively improving the test efficiency, and reducing the test cost.

[0062] Please refer to Figure 2 , the second embodiment of the present invention is: A memory chip testing device comprises the following steps: A test item determination module is used to determine the test items, test sub-items and test cases required for multiple memory chips; a test board determination module, configured to determine a plurality of test boards according to the test items, the test sub-items, and the test cases, and output a memory chip insertion instruction; A setting module, configured to determine whether the plurality of memory chips have been inserted into the plurality of test boards, and if so, to set test preconditions according to the test case; The test module is used to send test instructions to the multiple test boards so that the multiple test boards test the multiple memory chips. The test instructions include the test preconditions and script execution commands corresponding to the test cases.

[0063] The third embodiment of the present invention is: A computer-readable storage medium stores a computer program, which, when executed by a processor, can implement the various steps of the memory chip testing method in embodiment 1.

[0064] The fourth embodiment of the present invention is: Please refer to Figure 3 , an electronic device includes a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein the processor implements each step of the storage chip testing method in embodiment one when executing the computer program.

[0065] In summary, the memory chip testing method, device, readable storage medium and electronic device provided by the present invention determine the test items, test sub-items and test cases required for multiple memory chips, determine multiple test boards according to the test items, test sub-items and test cases, and output memory chip insertion instructions. If multiple memory chips have been inserted into multiple test boards, test preconditions are set according to the test cases, and test instructions are issued to multiple test boards so that multiple test boards test multiple memory chips. In this way, it is only necessary to determine the test items, test sub-items and test cases that need to be performed, and multiple test boards can be used to test multiple memory chips in parallel, and different test items and test cases can be covered. Multiple test platforms and multiple test items can be integrated to simplify testing. The test process can be improved by testing multiple memory chips for one test item at the same time to eliminate the accidental nature of the test. After the memory chip has been inserted into the test board, the test preconditions are set according to the test case, which can simplify the preliminary preparations for the test and thus improve the efficiency and comprehensiveness of the test. In addition, during the test execution, the test board will upload the test data to the host computer. The host computer determines whether the current test is normal by judging whether there are preset keywords in the log information. After detecting an abnormality, it will output an alarm message in time and send an error instruction to stop the test board from continuing the test, so as to handle the abnormal test in time. Moreover, by mapping the status indicator information of the test board to a bitmap, the test status can be monitored in real time and the test situation can be intuitively understood.

[0066] In the above embodiments provided in the present application, it should be understood that the disclosed methods, devices, computer-readable storage media, and electronic devices can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple components or modules can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or components or modules, which can be electrical, mechanical or other forms.

[0067] The components described as separate parts may or may not be physically separate, and the components shown as components may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of these components may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0068] In addition, the functional modules in various embodiments of the present invention may be integrated into a single processing module, or each component may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0069] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0070] It should be noted that for the aforementioned method embodiments, for ease of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the order of the actions described, because according to the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0071] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0072] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's description and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A memory chip testing method, characterized in that: Including steps: Determine the test items, test sub-items, and test cases required for multiple memory chips; Determine a plurality of test boards according to the test items, the test sub-items and the test cases, and output a memory chip insertion instruction; determining whether the plurality of memory chips have been inserted into the plurality of test boards, and if so, setting a test precondition according to the test case; A test instruction is issued to the multiple test boards so that the multiple test boards test the multiple memory chips, wherein the test instruction includes the test precondition and a script execution command corresponding to the test case.

2. A memory chip testing method according to claim 1, characterized in that: Determining a plurality of test boards according to the test items, the test sub-items, and the test cases includes: Determine a test module corresponding to the test item; Determining a test board subset corresponding to the test sub-item from the test module; A plurality of test boards corresponding to the test case are determined from the test board subset.

3. A memory chip testing method according to claim 1, characterized in that: The sending of the test instructions to the multiple test boards so that the multiple test boards test the multiple memory chips includes: A test instruction is sent to a test controller, so that the test controller analyzes the test instruction and starts the multiple test boards to test the multiple memory chips.

4. A memory chip testing method according to claim 2, characterized in that: Determining whether the plurality of memory chips have been inserted into the plurality of test boards comprises: Obtaining a bitmap corresponding to the test module; Determine whether the number of memory chips displayed on the bitmap is equal to the number of the multiple memory chips; if so, determine whether the memory chips displayed on the bitmap are located on the multiple test boards; if so, determine that the multiple memory chips have been inserted into the multiple test boards.

5. A memory chip testing method according to claim 4, characterized in that: After issuing the test instructions to the multiple test boards so that the multiple test boards test the multiple memory chips, the method further includes: receiving test data uploaded by the plurality of test boards, wherein the test data includes log information; It is determined whether there is a preset keyword in the log information. If so, an alarm message is output and an error instruction is sent to the test board corresponding to the log information to stop the test board.

6. A memory chip testing method according to claim 4 or 5, characterized in that: Also includes: Acquire status indicator light information of the plurality of test boards, where the status indicator light information is used to indicate a test status; Mapping the status indicator light information to the bitmap.

7. A memory chip testing method according to claim 5, characterized in that: Also includes: Determine whether each of the memory chips has been tested, and if so, obtain the number of the plurality of memory chips, the number of chips that passed the test, the number of chips that failed the test, and a test duration distribution graph; Acquire the detected preset keyword and a storage address of log information corresponding to the preset keyword; A test report is generated according to the test items, the test preconditions, the number of the multiple storage chips, the number of chips that passed the test, the number of chips that failed the test, the test time distribution graph, the detected preset keywords, and the storage address of the log information.

8. A memory chip testing device, characterized in that: Including steps: A test item determination module is used to determine the test items, test sub-items and test cases required for multiple memory chips; a test board determination module, configured to determine a plurality of test boards according to the test items, the test sub-items, and the test cases, and output a memory chip insertion instruction; A setting module, configured to determine whether the plurality of memory chips have been inserted into the plurality of test boards, and if so, to set test preconditions according to the test case; The test module is used to send test instructions to the multiple test boards so that the multiple test boards test the multiple memory chips. The test instructions include the test preconditions and script execution commands corresponding to the test cases.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, each step of the memory chip testing method according to any one of claims 1 to 7 is implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, each step of the memory chip testing method according to any one of claims 1 to 7 is implemented.

Images