Semiconductor device, manufacturing method thereof and hard carrier
By fixing the wafer to be thinned on a hard carrier and combining it with a temporary bonding layer, the problem of large thickness variation of the thinned wafer is solved, achieving higher packaging reliability and yield.
Patent Information
- Application Number
- CN202410351052.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-26
- Publication Date
- 2025-09-26
AI Technical Summary
During memory manufacturing, the thickness of thinned wafers in multi-wafer stacks varies too much, resulting in reduced packaging reliability.
A temporary bonding layer is used to fix the wafer to be thinned on a hard carrier, and a thinning process is performed using the combination of the concave-convex structure of the hard carrier and the temporary bonding layer to reduce thickness differences.
It effectively reduces the thickness difference of thinned wafers, improves packaging reliability and yield, and reduces the risk of fragmentation.
Smart Images
Figure CN120709215A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and a hard carrier. Background Art
[0002] Currently, in the manufacturing process of memory, a multi-wafer stacking structure design is adopted to increase the storage capacity of the memory. To achieve multi-wafer stacking, the wafers need to be thinned to obtain thinner wafers. However, the total thickness variation (TTV) of the thinned wafers is too large, that is, the thickness of the thinned wafer varies greatly in different areas, which will reduce the packaging reliability of the stacked chip prepared by multiple stacked thinned wafers.
[0003] Therefore, a technical solution needs to be proposed to reduce the total thickness variation of the thinned wafer to improve the packaging reliability of the stacked chips. Summary of the Invention
[0004] The present application provides a semiconductor device, a manufacturing method thereof, and a hard carrier to reduce thickness differences between different regions of a thinned wafer.
[0005] In a first aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising:
[0006] A wafer to be thinned is fixed to a hard carrier using a temporary bonding adhesive layer, wherein the wafer to be thinned includes a first surface and a second surface facing each other, the first surface faces the hard carrier, the hard carrier includes a hard supporting surface facing the wafer to be thinned, the first surface is provided with a first concave-convex structure, and the hard supporting surface is provided with a second concave-convex structure that engages with the first concave-convex structure; and
[0007] The second surface of the wafer to be thinned is subjected to a thinning process to obtain a thinned wafer.
[0008] In some embodiments, the first concave-convex structure includes an annular groove provided along the edge of the wafer to be thinned, and the annular groove is sunken inwardly away from the hard supporting surface;
[0009] The second concave-convex structure includes an annular protrusion engaged with the annular groove, and the annular protrusion protrudes toward the first surface.
[0010] In some embodiments, the first concave-convex structure includes a groove located in the cutting street area, and the groove is sunken in a direction away from the hard bearing surface;
[0011] The second concave-convex structure includes opposing protrusions engaged with the groove, and the opposing protrusions protrude toward the first surface.
[0012] In some embodiments, the first concave-convex structure includes a plurality of chip concave-convex structures located in a plurality of chip regions of the wafer to be thinned;
[0013] The second concave-convex structure further includes a plurality of opposing concave-convex structures respectively engaged with the plurality of chip concave-convex structures.
[0014] In some embodiments, the thickness of the temporary bonding adhesive layer is greater than or equal to 1 micrometer and less than or equal to 10 micrometers.
[0015] In some embodiments, fixing the wafer to be thinned on the hard carrier using a temporary bonding layer includes:
[0016] forming an initial colloid layer on the hard bearing surface;
[0017] Laminating the first surface of the wafer to be thinned onto the initial colloid layer; and
[0018] The initial colloid layer is subjected to a heating treatment to obtain the temporary bonding adhesive layer.
[0019] In some embodiments, the heating temperature of the initial colloidal layer is less than or equal to 350°C.
[0020] In some embodiments, the method further includes: separating the thinned wafer and the temporary bonding adhesive layer.
[0021] In some embodiments, thinning the second surface of the wafer to be thinned includes: processing the second surface of the wafer to be thinned using a grinding process until the thickness of the obtained thinned wafer is less than or equal to 50 microns.
[0022] In some embodiments, the method further includes: fixing the hard carrier on the supporting platform by vacuum adsorption.
[0023] In some embodiments, the hard carrier includes at least one of a metal material, a ceramic material, and a composite material.
[0024] In some embodiments, the wafer to be thinned includes one wafer or multiple bonded wafers.
[0025] In a second aspect, some embodiments of the present application further provide a hard carrier for carrying a wafer, wherein the hard carrier includes a hard carrying surface, and the hard carrying surface includes a concave-convex structure.
[0026] In some embodiments, the concave-convex structure includes an annular protrusion disposed on an edge region of the hard carrier.
[0027] In some embodiments, the hard carrier includes at least one of a metal material, a glass material, a ceramic material, and a composite material.
[0028] In a third aspect, the present application further provides a semiconductor device, which is obtained by the semiconductor device manufacturing method of some of the above embodiments.
[0029] In the semiconductor devices and their manufacturing methods and hard carriers of some embodiments of the present application, a temporary bonding layer is used to fix the wafer to be thinned on the hard carrier, and then the wafer to be thinned is thinned to obtain a thinned wafer. In this way, during the thinning process, the hard carrier plays the role of a hard support for the wafer to be thinned, and the temporary bonding layer plays a fixing and buffering role for the wafer to be thinned, which can reduce the difference in thickness of the thinned wafer in different areas to meet the requirements of high-density packaging process, and reduce the risk of breakage of the thinned wafer, thereby improving the yield of manufacturing semiconductor devices. Moreover, during the thinning process, the second concave-convex structure on the hard carrier plays a supporting role for the first concave-convex structure of the wafer, further reducing the risk of breakage of the thinned wafer, and further improving the yield of manufacturing semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application;
[0031] Figure 2 A schematic diagram of a structure in which a temporary bonding layer is used to fix a wafer to be thinned on a hard carrier in some embodiments provided in the present application;
[0032] Figure 3 Schematic diagram of a structure in which a temporary bonding layer is used to fix a wafer to be thinned on a hard carrier in some other embodiments provided by the present application;
[0033] Figure 4 A schematic structural diagram of performing a thinning process on the second surface of a wafer to be thinned according to some embodiments of the present application;
[0034] Figure 5 Schematic diagram of a semiconductor device according to some embodiments of the present application;
[0035] Figure 6 A block diagram of a storage system according to some embodiments of the present application.
[0036] The reference numerals are as follows:
[0037] 11, temporary bonding layer;
[0038] 12, wafer to be thinned; 12a, first surface; 12b, second surface; 12c, chip area; 121, first concave-convex structure; 122, annular groove; 123, groove; 124, chip concave-convex structure;
[0039] 13, hard carrier; 13a, hard bearing surface; 131, second concave-convex structure; 132, annular protrusion; 133, opposite protrusion; 134, opposite concave-convex structure;
[0040] 14, carrying platform;
[0041] 15. Thin the wafer;
[0042] 100, semiconductor device; 200, memory; 300, controller; 400, storage system. DETAILED DESCRIPTION
[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.
[0044] Please refer to Figure 1 , which is a flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application. The method for manufacturing a semiconductor device comprises the following steps:
[0045] Step S101: A wafer to be thinned is fixed to a hard carrier using a temporary bonding layer, wherein the wafer to be thinned includes a first surface and a second surface facing each other, the first surface facing the hard carrier, and the hard carrier includes a hard supporting surface facing the wafer to be thinned, the first surface being provided with a first concave-convex structure, and the hard supporting surface being provided with a second concave-convex structure engaging with the first concave-convex structure; and
[0046] Step S102: performing a thinning process on the second surface of the wafer to be thinned to obtain a thinned wafer.
[0047] In the semiconductor device manufacturing methods of some embodiments of the present application, during the thinning process, a rigid carrier provides rigid support for the wafer to be thinned, and in conjunction with a temporary bonding layer, secures and cushions the wafer. This reduces the thickness differences between different regions of the thinned wafer, meeting the requirements of high-density packaging processes and reducing the risk of wafer breakage, thereby improving the yield rate of semiconductor device manufacturing. Furthermore, during the thinning process, the second concave-convex structure on the rigid carrier supports the first concave-convex structure of the wafer, further reducing the risk of wafer breakage and further improving the yield rate of semiconductor device manufacturing.
[0048] However, in the related art, the wafer to be thinned needs to be fixed on a back grinding tape (BG Tape) before being thinned. The thickness fluctuation of the grinding tape will cause the thickness of the thinned wafer to vary greatly in different areas. For example, the thickness difference is maintained in the range of ±5um to ±10um, resulting in the stacked chips prepared from the thinned wafer being difficult to meet the requirements of high-density packaging.
[0049] It should be noted that, in this application, "a first surface provided with a first concavo-convex structure" means that the first surface of the wafer to be thinned is provided with opposing raised and recessed structures, and the raised and recessed structures are not coplanar. Similarly, "a hard supporting surface provided with a second concavo-convex structure" means that the hard supporting surface is provided with opposing raised and recessed structures that are not coplanar.
[0050] The manufacturing process of the semiconductor device described above is described in detail below in conjunction with some specific embodiments. Where compatible, some of the embodiments below may be arbitrarily combined.
[0051] like Figure 2 and Figure 3 As shown, step S101 is executed. Figure 2 This is a schematic diagram of a structure in which a temporary bonding layer is used to fix a wafer to be thinned on a hard carrier in some embodiments provided in this application. Figure 3 Schematic diagram of the structure of fixing the wafer to be thinned on a hard carrier using a temporary bonding layer according to some other embodiments provided in the present application.
[0052] In some embodiments, the thickness of the wafer 12 to be thinned can be greater than or equal to 900 microns. Since the thickness of the wafer 12 to be thinned is relatively large, it is necessary to thin the wafer 12 to facilitate stacking of multiple wafers. Using stacked wafers, a semiconductor device including multiple stacked chips can be manufactured.
[0053] In some embodiments, the wafer to be thinned 12 may include one or more bonded wafers. In the case where the wafer to be thinned 12 is one wafer, the wafer to be thinned 12 may include a memory wafer, a logic wafer, or a wafer of an integrated logic circuit and a memory array. In a specific embodiment, the wafer to be thinned 12 may include a memory wafer. In the case where the wafer to be thinned 12 includes multiple bonded wafers, the multiple bonded wafers may include multiple wafers of the same type, or may include multiple wafers of different types. For example, the multiple bonded wafers may include multiple bonded memory wafers, or may include bonded memory wafers and logic wafers. In a specific embodiment, the wafer to be thinned 12 may include bonded logic wafers and memory wafers.
[0054] The second surface 12b of the wafer 12 to be thinned may be a surface of the semiconductor substrate of the wafer 12 to be thinned where no wafer circuitry is provided. This allows the thickness of the wafer 12 to be thinned to be reduced while reducing the impact of the thinning process on the thinned wafer. In some embodiments, the first surface 12a of the wafer 12 to be thinned may be provided with wafer circuitry. In other embodiments, the first surface 12a of the wafer 12 to be thinned may also be a surface of the semiconductor substrate where no wafer circuitry is provided.
[0055] The rigid carrier 13 possesses significant rigidity, resulting in minimal or no deformation under grinding pressure and unaffected by wafer warpage. The rigid support surface 13a of the rigid carrier 13 can be highly precise. This high-precision rigid carrier 13 provides stable, rigid support for the wafer 12 to be thinned, minimizing variations in thickness across different regions of the thinned wafer. Furthermore, the rigid carrier 13 is reusable.
[0056] In some embodiments, the hard carrier 13 includes at least one of a metal material, a glass, a ceramic material, and a composite material. In this way, the hard carrier 13 can be processed from a hard material, and the hard carrier 13 can have a higher dimensional accuracy, which can improve the effect of the processing error of the thick adhesive layer and the base layer of the grinding tape in the related art on the thickness difference of the thinned wafer. In a specific embodiment, the hard carrier 13 includes a metal material to reduce the risk of static electricity generated during the thinning process and affecting the thinned wafer. In another specific embodiment, the hard carrier 13 may include quartz glass, so that the hard carrier 13 has rigidity while also being light-transmissive, so as to facilitate the formation of a temporary bonding adhesive layer 11 by light irradiation.
[0057] The temporary bonding layer 11 is viscous and can secure the wafer 12 to be thinned to the rigid carrier 13, thereby positioning the wafer 12. The flexibility of the temporary bonding layer 11 allows it to act as a buffer between the rigid support surface 13a of the rigid carrier 13 and the wafer 12 to be thinned. It also acts as a buffer against the polishing pressure applied to the wafer 12 to be thinned, reducing the risk of damage to the wafer 12 from the rigid carrier 13 and the polishing pressure.
[0058] The hard carrier 13 and the temporary bonding layer 11 work together to fix the wafer 12 to be thinned. This can improve the problem of damage caused by direct contact between the circuit surface of the wafer and the vacuum suction cup of the thinning machine, while also reducing the thickness difference of the thinned wafer. For example, the total thickness difference of the thinned wafer can be optimized to ±3 microns or less, which can also reduce the risk of breakage of the thinned wafer and improve the yield rate of manufacturing semiconductor devices.
[0059] In some embodiments, the thickness of the temporary bonding adhesive layer 11 is greater than or equal to 1 micron and less than or equal to 10 microns. In this way, the thickness of the temporary bonding adhesive layer 11 can ensure that it performs good bonding, cushioning, and protection functions while reducing the risk of the temporary bonding adhesive layer 11 being too thick, resulting in large thickness differences in the thinned wafer. Optionally, the thickness of the temporary bonding adhesive layer 11 is greater than or equal to 1 micron and less than or equal to 8 microns. Optionally, the thickness of the temporary bonding adhesive layer 11 is greater than or equal to 2 microns and less than or equal to 6 microns.
[0060] In some embodiments, the temporary bonding adhesive layer 11 may include at least one of a thermoplastic material, a thermosetting material, and a light-curable material. For example, the temporary bonding adhesive layer 11 may be made of a natural resin, a synthetic resin, liquid wax, or glue. In a specific embodiment, the temporary bonding adhesive layer 11 may include a light-cured material.
[0061] In some embodiments, reference Figure 2 As shown, the first concave-convex structure 121 may include an annular groove 122 provided along the edge of the wafer to be thinned 12, and the annular groove 122 is sunken in the direction away from the hard supporting surface 13a. Correspondingly, the second concave-convex structure 131 includes an annular protrusion 132 engaged with the annular groove 122, and the annular protrusion 132 protrudes in the direction close to the first surface 12a. In this way, the annular protrusion 132 of the hard carrier 13 plays a hard supporting role for the surface of the wafer to be thinned 12 that defines the annular groove 122, and the thinner temporary bonding layer 11 is also located between the annular protrusion 132 and the annular groove 122, thereby reducing the risk of cracking at the edge of the wafer to be thinned 12 during the thinning process and reducing the difference in thickness between the edge of the thinned wafer and the thickness of other areas.
[0062] In some embodiments, when two wafers of different sizes are bonded, for example, a logic wafer and a memory wafer of different sizes are bonded, a step is formed at the edge of the bonded structure, and an annular groove 122 is formed at the step. The annular groove 122 may be in the shape of a ring.
[0063] It should be noted that in the related art, when using abrasive tape to secure the wafer to be thinned, the thickness of the adhesive layer at the edge of the abrasive tape is generally greater than the thickness of the adhesive layer in other areas. The thicker adhesive layer at the edge provides support and protection for the grooves at the edge of the wafer to be thinned 12. However, variations in the thickness of the thicker adhesive layer at the edge of the abrasive tape can result in significant variations in the thickness of the resulting thinned wafer.
[0064] In other embodiments, referring to Figure 3 As shown, the first concave-convex structure 121 may include a groove 123 located in the cutting path area, and the groove 123 is sunken in the direction away from the hard bearing surface 13a. Correspondingly, the second concave-convex structure 131 includes an opposing protrusion 133 that engages with the groove 123, and the opposing protrusion 133 protrudes in the direction close to the first surface 12a. In this way, the opposing protrusion 133 of the hard carrier 13 plays a role of hard support for the surface of the wafer to be thinned 12 that defines the groove 123, and the thinner temporary bonding layer 11 is located between the opposing protrusion 133 and the groove 123, reducing the risk of the wafer to be thinned 12 being broken due to uneven stress during the thinning process, and reducing the difference in thickness between the area corresponding to the groove 123 and the thickness of other areas of the final thinned wafer.
[0065] In some embodiments, a groove 123 has different depths in at least two regions. Accordingly, the heights of the opposing protrusions 133 engaging with the groove 123 also differ in at least two corresponding regions. The depth and height are the dimensions of the groove 123 and the opposing protrusion 133, respectively, in the direction from the rigid carrier toward the wafer 12 to be thinned.
[0066] It should be noted that a test pad (not shown) is provided in the cutting path area of the wafer to be thinned, and the groove 123 is formed by removing the insulating layer on the test pad. The groove 123 exposes the test pad so that a test voltage can be applied to the test pad. Moreover, after the thinned wafer is obtained, it can be cut along the cutting path area to obtain a plurality of chips. In order to perform the cutting process in the cutting path area, part of the insulating layer in the cutting path area is thinner than the thickness of the same insulating layer in the chip area 12c. Therefore, the insulating layer removed from the test pad and the insulating layer with a thinner thickness cause the cutting path area to be recessed relative to the chip area 12c, thereby forming a groove 123, and the recessed depth of a groove 123 in at least two areas may be different.
[0067] In a specific embodiment, the groove 123 may include a plurality of first grooves extending along a first direction and a plurality of second grooves extending along a second direction, wherein the first direction intersects with the second direction. The plurality of first grooves intersect with the plurality of second grooves, respectively, and two adjacent first grooves and two adjacent second grooves define the chip area 12c. The opposing protrusions 133 may include a plurality of first opposing protrusions extending along the first direction and a plurality of second opposing protrusions extending along the second direction. The plurality of first opposing protrusions intersect with the plurality of second opposing protrusions. The first opposing protrusions and the first grooves intersect with each other, and a temporary bonding adhesive layer 11 is provided between the two. The second opposing protrusions and the second grooves intersect with each other, and a temporary bonding adhesive layer 11 is provided between the two.
[0068] In other embodiments, continue to refer to Figure 3 As shown, the first concave-convex structure 121 includes multiple chip concave-convex structures 124 located in multiple chip regions 12c of the wafer to be thinned 12. Correspondingly, the second concave-convex structure 131 also includes multiple opposing concave-convex structures 134 that respectively engage with the multiple chip concave-convex structures 124. In this way, the opposing concave-convex structures 134 on the hard carrier 13 can provide rigid support for the uneven surface of the chip region 12c formed by the circuit, and the thin temporary bonding adhesive layer 11 is located between the opposing concave-convex structures 134 and the chip concave-convex structures 124, which can reduce the risk of damage to the chip concave-convex structures 124 due to uneven stress.
[0069] In some embodiments, step S101 may include: forming an initial colloid layer on a hard supporting surface 13a; attaching the first surface 12a of the wafer 12 to be thinned to the initial colloid layer; and heating the initial colloid layer to form a temporary bonding adhesive layer 11. Thus, compared to the adhesive application and removal processes, which can generate static electricity and affect the performance of devices on the wafer 12 to be thinned, some embodiments of the present application form the initial colloid layer by coating, etc., and then heat the initial colloid layer to form the temporary bonding adhesive layer 11, thereby reducing the risk of the formation of the temporary bonding adhesive layer 11 adversely affecting the wafer 12 to be thinned.
[0070] In some embodiments, the heating temperature for the initial colloidal layer is less than or equal to 350° C. This reduces the risk of the heating process affecting the performance of the thinned wafer 12. Optionally, the heating temperature for the initial colloidal layer is greater than or equal to 60° C. This ensures that the initial colloidal layer disposed between the first concave-convex structure 121 and the second concave-convex structure 131 is sufficiently heated, thereby reducing the difference between the temporary bonding adhesive layer 11 between the first concave-convex structure 121 and the second concave-convex structure 131 and the temporary bonding adhesive layer 11 in other areas.
[0071] In some embodiments, before step S101, the method for manufacturing a semiconductor device further includes step S100. Step S100 includes securing the rigid carrier 13 to the carrier 14 using vacuum suction. Thus, by securing the rigid carrier 13 to the carrier 14 using vacuum suction, and securing the wafer 12 to be thinned to the rigid carrier 13 using the temporary bonding layer 11, the risk of movement of the wafer 12 to be thinned during the thinning process is reduced, as well as the risk of damage to the wafer 12 due to direct contact between the wafer 12 and the carrier 14.
[0072] Next, please refer to Figure 4 As shown, execute the above step S102. Figure 4 This is a structural diagram of thinning the second surface of the wafer to be thinned.
[0073] In some embodiments, step S102 may include: processing the second surface 12b of the wafer 12 to be thinned using a grinding process until the thickness of the resulting thinned wafer 15 is less than or equal to 50 microns. In this way, the thickness of the thinned wafer 15 is relatively thin, and multiple thinned wafers 15 are stacked to obtain a stacked wafer, and the stacked wafer is cut to obtain a stacked chip. From a functional perspective, a stacked chip can be more diverse than a single chip. In the case where the stacked chip includes multiple memory chips, the storage capacity of the stacked chip can be larger.
[0074] Finally, after step S102 , the method for manufacturing the semiconductor device further includes: separating the thinned wafer 15 and the temporary bonding adhesive layer 11 to obtain a thinned wafer 15 .
[0075] In some embodiments, heating can be used to achieve separation between the thinned wafer 15 and the temporary bonding layer 11, reducing the risk of damage to the thinned wafer 15 during the separation process. In other embodiments, laser irradiation can be used to achieve separation between the thinned wafer 15 and the temporary bonding layer 11, so as to achieve separation quickly and efficiently. In other embodiments, multiple separation processes can also be used to achieve separation between the thinned wafer 15 and the temporary bonding layer 11 to optimize the separation process. For example, the temperatures of the multiple heatings are different, or the energies of the multiple laser irradiations are different, or heating and laser irradiation are combined.
[0076] In some embodiments, after the thinned wafer 15 is obtained, a dicing process may be performed along the scribe line region of the thinned wafer 15 to obtain a plurality of semiconductor devices 100 .
[0077] This application also provides a hard carrier 13, which can be found in Figure 2 and Figure 3 , and refer to the above-mentioned related content, which will not be repeated here.
[0078] Based on the same invention concept, please refer to Figure 5 As shown, Figure 5 Schematic diagrams of semiconductor devices according to some embodiments of the present application. Semiconductor device 100 is obtained by the above-described semiconductor device manufacturing method. Semiconductor device 100 may include one or more memory chips. Semiconductor device 100 may also include a logic chip.
[0079] The semiconductor device 100 of some embodiments provided in the present application is thin, and the thickness difference of the semiconductor device 100 is small, thereby improving the reliability of the semiconductor device 100 during the packaging process.
[0080] Based on the same inventive concept, the present application further provides a storage system 400, which includes a memory 200 and a controller 300. The controller 300 is connected to the memory 200 and is used to control the memory 200. The memory 200 includes the semiconductor device 100 according to any of the above embodiments.
[0081] The description of the above embodiments is only used to help understand the technical solutions and core ideas of this application; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: A wafer to be thinned is fixed to a hard carrier using a temporary bonding adhesive layer, wherein the wafer to be thinned includes a first surface and a second surface facing each other, the first surface faces the hard carrier, the hard carrier includes a hard supporting surface facing the wafer to be thinned, the first surface is provided with a first concave-convex structure, and the hard supporting surface is provided with a second concave-convex structure that engages with the first concave-convex structure; and The second surface of the wafer to be thinned is subjected to a thinning process to obtain a thinned wafer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The first concave-convex structure includes an annular groove provided along the edge of the wafer to be thinned, wherein the annular groove is sunken in a direction away from the hard supporting surface; The second concave-convex structure includes an annular protrusion engaged with the annular groove, and the annular protrusion protrudes toward the first surface.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: The first concave-convex structure includes a groove located in the cutting street area, and the groove is sunken in a direction away from the hard bearing surface; The second concave-convex structure includes opposing protrusions engaged with the groove, and the opposing protrusions protrude toward the first surface.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The first concave-convex structure includes a plurality of chip concave-convex structures located in a plurality of chip areas of the wafer to be thinned; The second concave-convex structure further includes a plurality of opposing concave-convex structures respectively engaged with the plurality of chip concave-convex structures.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the temporary bonding adhesive layer is greater than or equal to 1 micron and less than or equal to 10 microns.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The method of fixing the wafer to be thinned on the hard carrier by using a temporary bonding layer includes: forming an initial colloid layer on the hard bearing surface; Laminating the first surface of the wafer to be thinned onto the initial colloid layer; and The initial colloid layer is subjected to a heating treatment to obtain the temporary bonding adhesive layer.
7. The method for manufacturing a semiconductor device according to claim 6, wherein: The heating temperature for heating the initial colloidal layer is less than or equal to 350°C.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further comprises: The thinned wafer and the temporary bonding layer are separated.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: The thinning process on the second surface of the wafer to be thinned includes: The second surface of the wafer to be thinned is processed by a grinding process until the thickness of the obtained thinned wafer is less than or equal to 50 microns.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further comprises: The hard carrier is fixed on the carrying platform by vacuum adsorption.
11. The method for manufacturing a semiconductor device according to claim 1, wherein: The hard carrier includes at least one of metal material, glass, ceramic material and composite material.
12. The method for manufacturing a semiconductor device according to claim 1, wherein: The wafer to be thinned includes one wafer or multiple bonded wafers.
13. A hard carrier for carrying a wafer, characterized in that: The hard carrier includes a hard bearing surface, and the hard bearing surface includes a concave-convex structure.
14. The hard carrier according to claim 13, characterized in that: The concave-convex structure includes an annular protrusion arranged in an edge area of the hard carrier.
15. The hard carrier according to claim 13, characterized in that: The hard carrier includes at least one of a metal material, a ceramic material and a composite material.
16. A semiconductor device, characterized in that: The semiconductor device is obtained by the method according to any one of claims 1 to 12.