Display panel and driving method thereof

Abstract

The embodiment of the invention provides a display panel, a driving method thereof, a driving device and a display device. The display panel comprises at least one display sub-area, the display sub-area comprises a plurality of pixel units, the plurality of pixel units are divided into at least two pixel blocks arranged in the first direction, each pixel block comprises at least one column of pixel units, and each pixel unit comprises a plurality of sub-pixels arranged in the first direction; the data lines extend in the second direction, and the sub-pixels are connected with the corresponding data lines; the grid lines extend in the first direction, each pair of grid lines corresponds to one row of pixel units, each pair of grid lines comprises odd grid lines and even grid lines, and the odd grid lines and the even grid lines are arranged on the two opposite sides of the corresponding row of pixel units respectively; at least one sub-pixel in the pixel block is coupled with the odd-numbered grid line, and at least one sub-pixel is coupled with the even-numbered grid line. According to the technical scheme, the poor vertical lines of the display picture can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a driving method thereof. Background Art

[0002] With the continuous advancement of flat panel display technology, liquid crystal displays have been successfully applied to display devices such as flat panels, televisions, and computers. Each liquid crystal pixel on the liquid crystal display is driven by a thin film transistor integrated thereon, which can display information at high speed, high brightness, and high contrast.

[0003] Figure 1 FIG. 1 is a planar schematic diagram of a liquid crystal display. Figure 1 As shown, the liquid crystal display includes a plurality of sub-pixels P arranged in an array, with each three sub-pixels R, G, and B forming a pixel unit. The liquid crystal display also includes a plurality of gate lines Gate and a plurality of data lines Data, and the thin film transistors of each sub-pixel are connected to the corresponding gate lines and data lines. The display also includes a gate driver module and a data driver module, with the plurality of gate lines connected to the gate driver module and the plurality of data lines connected to the data driver module. The gate driver module provides gate signals to the thin film transistors via the gate lines, and the data driver module provides data signals to the thin film transistors via the data lines. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display panel and a driving method thereof to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a display panel, including a display area, the display area including at least one display sub-area, the display sub-area including:

[0006] A plurality of pixel units arranged in an array, the plurality of pixel units being divided into at least two pixel blocks arranged along a first direction, the pixel block including at least one column of pixel units, and the pixel unit including a plurality of sub-pixels arranged along the first direction;

[0007] a plurality of data lines extending along a second direction, the plurality of data lines corresponding one-to-one to the plurality of columns of sub-pixels, the sub-pixels being connected to the corresponding data lines, wherein the second direction intersects the first direction;

[0008] a plurality of pairs of gate lines, the gate lines extending along a first direction, each pair of gate lines corresponding to a row of pixel units, each pair of gate lines including odd-numbered gate lines and even-numbered gate lines, the odd-numbered gate lines and the even-numbered gate lines being respectively arranged on opposite sides of the corresponding row of pixel units;

[0009] At least one sub-pixel in the pixel block is coupled to an odd-numbered gate line, and at least one sub-pixel is coupled to an even-numbered gate line.

[0010] In some embodiments, in at least two pixel blocks, data lines corresponding to corresponding columns of sub-pixels are coupled to the same data signal.

[0011] In some embodiments, in a same pixel block, at least one sub-pixel in a same row is coupled to an odd-numbered gate line, and at least one sub-pixel is coupled to an even-numbered gate line.

[0012] In some embodiments, in the same pixel block, the number of sub-pixels coupled to odd-numbered gate lines is the same as the number of sub-pixels coupled to even-numbered gate lines.

[0013] In some embodiments, in the same row of the same pixel block, the number of sub-pixels coupled to the odd-numbered gate lines is the same as the number of sub-pixels coupled to the even-numbered gate lines.

[0014] In some embodiments, two adjacent sub-pixels in a pixel unit are coupled to different gate lines.

[0015] In some embodiments, in the same row of sub-pixels in the same pixel block, two adjacent sub-pixels are coupled to different gate lines.

[0016] In some embodiments, in the same row of pixel units, the number of sub-pixels coupled to odd-numbered gate lines is the same as the number of sub-pixels coupled to even-numbered gate lines.

[0017] In some embodiments, in the same row of sub-pixels, one of two adjacent sub-pixels coupled to the same data signal is coupled to an odd-numbered gate line, and the other is coupled to an even-numbered gate line.

[0018] In some embodiments, the display sub-region includes two pixel blocks arranged along a first direction.

[0019] In some embodiments, the pixel block includes two columns of pixel units, and the pixel unit includes three sub-pixels.

[0020] In some embodiments, the pixel block includes at least one pixel group arranged along the second direction, and the pixel group includes at least two rows of pixel units;

[0021] In the same frame, a row of pixel units in each pixel group is illuminated, and at least one of the illuminated sub-pixels in the same frame is coupled to a corresponding odd-numbered gate line, and at least one is coupled to a corresponding even-numbered gate line.

[0022] In some embodiments, in a same pixel block, at least one of the multiple sub-pixels located in a same column is coupled to an odd-numbered gate line, and at least one is coupled to an even-numbered gate line.

[0023] In some embodiments, the pixel block includes at least one pixel group arranged along the second direction, the pixel group includes at least two rows of pixel units, and in the same column of sub-pixels, sub-pixels in corresponding rows in two adjacent pixel groups are coupled to different gate lines.

[0024] In some embodiments, the pixel group includes two rows of pixel units; and / or the pixel block includes two pixel groups arranged along the second direction.

[0025] In some embodiments, sub-pixels in the same column of the same pixel group are coupled to the same corresponding gate line.

[0026] In some embodiments, the plurality of gate lines are configured to be sequentially provided with gate drive signals, the gate drive signals including a pre-charge phase and a real charge phase, the pre-charge phase overlapping with a previous gate drive signal;

[0027] The coupled data lines are configured to be periodically provided with data signals, so that in the same frame, the pixel units in the odd-numbered rows are illuminated or the pixel units in the even-numbered rows are illuminated.

[0028] In some embodiments, including:

[0029] first base;

[0030] A first metal layer is located on one side of the first substrate, and the first metal layer includes gate lines and data connection lines corresponding to data signals;

[0031] a first insulating layer, located on a side of the first metal layer facing away from the first substrate;

[0032] The second metal layer is located on a side of the first insulating layer away from the first substrate. The second metal layer includes data lines. A plurality of data lines coupled to the same data signal are connected via data connection lines.

[0033] In some embodiments, a second insulating layer and a first transparent conductive layer are further included, the second insulating layer is located on the side of the second metal layer facing away from the first substrate, the first transparent conductive layer is located on the side of the second insulating layer facing away from the first substrate, the first transparent conductive layer includes a first adapter line, the data line is connected to the data connection line through the first adapter line, the data connection line is connected to the data transmission line, the data transmission line is located in the first metal layer, and the data transmission line is used to couple with the data driving module.

[0034] In some embodiments, the present invention includes a first substrate and a second substrate arranged opposite to each other, and also includes a support column located between the first substrate and the second substrate, the first substrate includes a first base, the data line and the gate line are both located on the side of the first base facing the second substrate, the pixel unit includes a blue sub-pixel, the blue sub-pixel is coupled to one of the two gate lines, and the orthographic projection of the support column on the first base is located at a position of the blue sub-pixel close to the other gate line.

[0035] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for driving a display panel, which is applied to the display panel in the embodiments of the present disclosure, and the method includes:

[0036] sequentially providing gate drive signals to the plurality of gate lines in the display sub-area, wherein the gate drive signals include a pre-charge phase and a real charge phase, wherein the pre-charge phase overlaps with a portion of the previous gate drive signal;

[0037] The data signal is provided periodically so that in the same frame, the odd-numbered rows of pixel units in the display sub-area are lighted or the even-numbered rows of pixel units are lighted.

[0038] In some embodiments, the data signal includes a first data writing phase and a second data writing phase, and periodically providing the data signal includes:

[0039] In the first data writing phase, the sub-pixels coupled to the odd-numbered gate lines in the corresponding row of pixel units are lit;

[0040] In the second data writing phase, the sub-pixels coupled to the even-numbered gate lines in the corresponding row of pixel units are lit.

[0041] In some embodiments, during the pre-charging phase, the sub-pixels coupled to the gate lines are pre-charged with the current signal in the data lines.

[0042] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a driving device for a display panel, which is applied to the display panel in the embodiments of the present disclosure. The driving device includes:

[0043] A gate drive module is used to sequentially provide gate drive signals to multiple gate lines in the display sub-area, wherein the gate drive signals include a pre-charge phase and a real charge phase, wherein the pre-charge phase overlaps with a portion of the previous gate drive signal;

[0044] The data driving module is used to periodically provide data signals to the data signal, so that in the same frame, the pixel units in the odd-numbered rows are lit or the pixel units in the even-numbered rows are lit.

[0045] As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide an electronic device, including:

[0046] at least one first processor; and

[0047] a first memory communicatively connected to at least one first processor; wherein,

[0048] The first memory stores instructions that can be executed by at least one first processor. The instructions are executed by the at least one first processor so that the at least one first processor can execute the driving method in the embodiment of the present disclosure.

[0049] As a fifth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, including the display panel in the embodiments of the present disclosure.

[0050] In some embodiments, the display device further includes a driving device according to an embodiment of the present disclosure or an electronic device according to an embodiment of the present disclosure.

[0051] The technical solution disclosed herein is that at least one of the multiple sub-pixels in the same pixel block is coupled to an odd-numbered gate line Gate, and at least one is coupled to an even-numbered gate line Gate. That is, in the first pixel block, at least one sub-pixel is coupled to the corresponding odd-numbered gate line Gate, and at least one sub-pixel is coupled to the corresponding even-numbered gate line Gate; in the second pixel block, at least one sub-pixel is coupled to the corresponding odd-numbered gate line Gate, and at least one sub-pixel is coupled to the corresponding even-numbered gate line Gate. Thus, for each pixel block, the sub-pixels coupled to the odd-numbered gate line Gate have a poor pre-charging effect, while the sub-pixels coupled to the even-numbered gate line Gate have a good pre-charging effect. This avoids the situation where all sub-pixels in the pixel block have a good pre-charging effect or all sub-pixels have a poor pre-charging effect, so that each pixel block is composed of a mixture of sub-pixels with a good pre-charging effect and sub-pixels with a poor pre-charging effect, making the overall brightness of the pixel block more balanced, improving the situation where one pixel block of the entire display panel is bright and one pixel block is dark, and improving the vertical stripes of the overloaded H1-Line display screen.

[0052] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0054] Figure 1 is a planar schematic diagram of a liquid crystal display;

[0055] Figure 2 A partial plan view of a display panel in a related art;

[0056] Figure 3 for Figure 2 The driving timing diagram of the display panel shown is as follows;

[0057] Figure 4 for Figure 2 The display panel shown uses Figure 3 Schematic diagram of the display effect of the driving timing shown;

[0058] Figure 5 is a partial plan view of a display panel in one embodiment of the present disclosure;

[0059] Figure 6 is a partial plan view of a display panel in another embodiment of the present disclosure;

[0060] Figure 7 is a schematic cross-sectional view of a first substrate in a display panel according to an embodiment of the present disclosure;

[0061] Figure 8 is a partial plan view of the first substrate;

[0062] Figure 9 for Figure 6 corresponding schematic diagram of the display panel layout;

[0063] Figure 10 for Figure 9 The layout structure diagram of the black matrix;

[0064] Figure 11 A schematic diagram of a 19T1C shift register;

[0065] Figure 12 To adopt Figure 11 The gate drive circuit operation timing diagram of the shift register shown;

[0066] Figure 13 This is a diagram showing the working sequence and display effect of the display sub-area in the display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] In the following, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure, and different embodiments may be combined in any manner without conflict. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0068] Figure 2 FIG. 1 is a partial plan view of a display panel in a related art, such as Figure 2 As shown, the display panel adopts a Dual Gate pixel architecture design (C3 architecture). Figure 2 4 shows four rows and four columns of pixel units, each pixel unit includes three sub-pixels P, namely R, G, and B, and the three sub-pixels are arranged along the row direction. Figure 2The three sub-pixels R, G, and B are arranged from left to right, but this does not mean that the arrangement order of the three sub-pixels R, G, and B is limited. Those skilled in the art should understand that the arrangement order of the three sub-pixels R, G, and B is not limited to Figure 2 The arrangement shown in the figure can be set in the order of the three sub-pixels R, G, and B as needed. Figure 2 The three sub-pixels R, G, and B are arranged in sequence from left to right.

[0069] The display panel includes multiple data lines (Data) and multiple gate lines (Gate). The multiple data lines (Data) correspond one-to-one with multiple columns of sub-pixels. A row of sub-pixels corresponds to two gate lines (Gate), which are located above and below the sub-pixel row, respectively. The gate lines (Gate) located above the sub-pixel row are called odd-numbered gate lines (Gate), and the gate lines (Gate) located below the sub-pixel row are called even-numbered gate lines (Gate).

[0070] The display panel also includes a plurality of thin film transistors TFT, each of which corresponds to a plurality of sub-pixels. The gate of the thin film transistor is connected to the gate line Gate, the source of the thin film transistor is connected to the data line Data, and the drain of the thin film transistor is connected to the pixel electrode of the sub-pixel. Figure 2 As shown, in the C3 architecture, the gates of the thin film transistors in the first to sixth columns are connected to the even-numbered gate line Gate. For example, the gates of the thin film transistors in the first to sixth columns in the first row are connected to the even-numbered gate line Gate2; the gates of the thin film transistors in the first to sixth columns in the second row are connected to the even-numbered gate line Gate4. The gates of the thin film transistors in the seventh to twelfth columns are connected to the odd-numbered gate lines. For example, the gates of the thin film transistors in the seventh to twelfth columns in the first row are connected to the odd-numbered gate line Gate1; the gates of the thin film transistors in the seventh to twelfth columns in the second row are connected to the odd-numbered gate line Gate3.

[0071] like Figure 2 As shown, the first data line Data1 is connected to the seventh data line Data7 and is simultaneously connected to the first data signal V D1 The second data line Data2 is connected to the eighth data line Data8, and is also connected to the second data signal V D2 The third data line Data3 is connected to the ninth data line Data9, and is also connected to the third data signal V D3 The fourth data line Data4 is connected to the tenth data line Data10, and is also connected to the fourth data signal V D4 The fifth data line Data5 is connected to the eleventh data line Data11, and is also connected to the fifth data signal V D5The sixth data line Data6 is connected to the twelfth data line Data12, and is also connected to the sixth data signal V D6 connect.

[0072] Two data lines Data and the same data signal V D The connection halves the data signal while doubling the number of gate lines, enabling a dual-gate design. Halving the data signal reduces the number of data driver modules, such as the data COF (Chip On Film), lowering costs.

[0073] Figure 3 for Figure 2 The driving timing diagram of the display panel shown is as follows: Figure 4 for Figure 2 The display panel shown uses Figure 3 The diagram of the display effect of the driving timing is shown in FIG. Figure 3 In the data signal waveform diagram, "0" is used to indicate that the data signal 0 is not provided; "1" is used to indicate that the data signal is provided. The "0" and "1" here should not be understood as specific data signal voltage values. In actual implementation, the specific voltage value of the data signal can be determined according to actual needs. For example, "V1" is used to indicate that the data signal is not provided, or it can be understood that when the data signal voltage value is V1, the corresponding sub-pixel is extinguished; "V2" is used to indicate that the data signal is provided, or it can be understood that when the data signal voltage value is V2, the corresponding sub-pixel is illuminated.

[0074] Figure 2-Figure 4 In the related technology shown, the gate line Gate is driven by a gate drive circuit (GOA), and a gate drive module such as a gate COF (Chip On Film) is no longer used. The data line Data is driven by a data COF. The number of gate lines Gate is doubled, and the number of data signals is halved, thereby halving the data COF, reducing costs and improving market competitiveness. At present, there are demands for products of 100Hz and 120Hz. Taking FHD products as an example, due to the doubling of the number of gate lines Gate, at 100Hz, the charging time for 1H is 4.6μs, and at 120Hz, the charging time for 1H is 3.8μs. The shorter the charging time, the more difficult it is to charge.

[0075] In the case of a single gate, the gate line is open for 1 hour. When the gate line is open, the sub-pixel is written with data, that is, the sub-pixel is charged and illuminated. Therefore, the actual sub-pixel charging phase is 1 hour. To meet the charging requirements of dual gate products, a precharge method can be used. Figure 2In the figure, the opening time of the gate line Gate is 3 hours. Correspondingly, the charging time of the sub-pixel is 3 hours. The first 2 hours are the pre-charging stage, and the last 1 hour is the actual charging stage. Taking the gate line Gate1 as an example, the two Hs marked as "0H" of Gate1 are the pre-charging stage, and the one H marked as "1H" is the actual charging stage. In the actual charging stage, data is written to the sub-pixel; taking the gate line Gate2 as an example, the two Hs marked as "0H" and "1H" of Gate2 are the pre-charging stage, and the one H marked as "2H" is the actual charging stage; and so on, the one H marked as "3H" is the actual charging stage of the gate line Gate3; the one H marked as "4H" is the actual charging stage of the gate line Gate4; the one H marked as "5H" is the actual charging stage of the gate line Gate5; the one H marked as "6H" is the actual charging stage of the gate line Gate6; the one H marked as "7H" is the actual charging stage of the gate line Gate7; and the one H marked as "8H" is the actual charging stage of the gate line Gate8.

[0076] Before the actual charging stage of writing data to each sub-pixel, there is a two-hour period during which the corresponding gate line Gate is open, and the data of the first two rows are written to the corresponding sub-pixels. For example, in the 1H actual charging stage corresponding to gate line Gate1, gate line Gate2 is also turned on. At this time, the sub-pixels corresponding to gate line Gate2 are pre-charged with the data of the sub-pixels corresponding to gate line Gate1; in the 2H actual charging stage corresponding to gate line Gate2, gate line Gate3 is also turned on. At this time, the sub-pixels corresponding to gate line Gate3 are pre-charged with the data of the sub-pixels corresponding to gate line Gate2, and so on. Therefore, the sub-pixels are pre-charged with the data of the previous row before the actual charging stage. It should be noted that the gate line Gate has a two-hour pre-charging time, and the data of the previous row written in advance is usually used as the pre-charged data.

[0077] like Figure 3 and Figure 4 As shown, under the heavy-load H1-Line screen, one row of sub-pixels is bright and one row of sub-pixels is dark. D1 For example, Gate1 turns on the seventh column of red sub-pixels to brighten, recorded as high level 1, Gate2 turns on the first column of red sub-pixels to brighten, recorded as high level 1; Gate3 turns on the seventh column of red sub-pixels to darken, recorded as low level 0, Gate4 turns on the first column of red sub-pixels to darken, recorded as low level 0; Gate5 turns on the seventh column of red sub-pixels to brighten, recorded as high level 1, Gate6 turns on the first column of red sub-pixels to brighten, recorded as high level 1; Gate7 turns on the seventh column of red sub-pixels to darken, recorded as low level 0, Gate8 turns on the first column of red sub-pixels to darken, recorded as low level 0; the following cycle is repeated, and the data signal V D1 The timing is 11001100, and similarly the data signal VD2 ~Data signal V D6 Turn on the green sub-pixel, blue sub-pixel, etc. respectively, and the timing is consistent with the data signal V D1 consistent.

[0078] In one cycle, taking Gate2 to open the R sub-pixel in the first column and first row as an example, the data written to the R sub-pixel when Gate1 in the previous row is turned on is a high level, and the sub-pixel corresponding to Gate2 row is pre-charged to a high level, that is, the R sub-pixel in the first column and first row is pre-charged to a high level, and the pre-charging effect is better, so the R sub-pixel in the first column and first row is marked as "+". Similarly, taking Gate5 to open the R sub-pixel in the seventh column and third row as an example, the data written to the R sub-pixel in the previous row by Gate4 is a low level, and the R sub-pixel corresponding to Gate5 row is pre-charged to a low level, and the pre-charging effect is poor, so the R sub-pixel in the seventh column and third row is marked as "-". By analogy, the pre-charging effect of the R sub-pixels in the first column is all "+", and the pre-charging effect of the R sub-pixels in the seventh column is all "-". By the same token, it can be deduced that the pre-charging effect of the R sub-pixels in the fourth column is all "+", and the pre-charging effect of the R sub-pixels in the tenth column is all "-". Similarly, the pre-charging effect of each sub-pixel can be deduced, such as Figure 3 shown.

[0079] Figure 2-Figure 4 In the example, a pixel unit includes three sub-pixels of R, G, and B. The three sub-pixels of R, G, and B form a pixel, and a cycle can include four columns of pixels. Figure 4 It can be seen that the pre-charge effect of the first two columns of pixels is better, and the pre-charge effect of the last two columns of pixels is worse, so the first two columns of pixels are brighter and the last two columns of pixels are darker. Figure 2 As shown in the cycle, the entire display panel appears as two columns of bright pixels and two columns of dark pixels, resulting in vertical stripes on the heavy-load H1-Line screen.

[0080] Figure 5 FIG. 1 is a partial plan view of a display panel according to an embodiment of the present disclosure. An embodiment of the present disclosure provides a display panel such as Figure 5 As shown, the display panel includes a display area, which includes at least one display sub-area. The display sub-area includes a plurality of pixel units arranged in an array. The plurality of pixel units are divided into at least two pixel blocks PB arranged along a first direction X. The pixel block PB includes at least one column of pixel units. The pixel units include a plurality of sub-pixels arranged along the first direction X.

[0081] The display sub-area further includes a plurality of data lines Data, which extend along a second direction Y. The second direction Y is not parallel to the first direction X. Figure 5 In the embodiment, the second direction Y intersects the first direction X. The plurality of data lines Data correspond to the plurality of columns of sub-pixels one by one. The sub-pixels are coupled to the corresponding data lines Data. Figure 5 In the embodiment, the first direction X is a horizontal direction, the second direction Y is perpendicular to the first direction X, and the second direction Y is a vertical direction. In other embodiments, the first direction may be other directions.

[0082] Figure 5 In the embodiment, the display sub-area includes two pixel blocks PB1 and PB2 arranged along a first direction. The pixel blocks include two columns of pixel units. A pixel unit includes three sub-pixels arranged along the first direction. For example, the three sub-pixels can be R, G, and B, respectively. Therefore, the display sub-area includes 12 columns of sub-pixels. Correspondingly, the display sub-area has 12 data lines Data1 to Data12, and the 12 data lines Data correspond one-to-one to the 12 columns of sub-pixels.

[0083] It should be noted that Figure 5 and the following text Figure 6 The three sub-pixels R, G, and B are arranged from left to right, but this does not mean that the arrangement order of the three sub-pixels R, G, and B is limited. Those skilled in the art should understand that the arrangement order of the three sub-pixels R, G, and B is not limited to Figure 5 or Figure 6 The arrangement shown in the figure can be set in the order of the three sub-pixels R, G, and B as needed. Figure 5 and Figure 6 The three sub-pixels R, G, and B are arranged in sequence from left to right.

[0084] The display sub-area further includes a plurality of pairs of gate lines, each of which extends along a first direction and corresponds to a row of pixel units. Each pair of gate lines includes odd gate lines and even gate lines, which are disposed on opposite sides of the corresponding row of pixel units.

[0085] For example, in Figure 5 In the example, the first row of pixels corresponds to odd-numbered gate lines Gate1 and even-numbered gate lines Gate2; the second row of pixels corresponds to odd-numbered gate lines Gate3 and even-numbered gate lines Gate4; the third row of pixels corresponds to odd-numbered gate lines Gate5 and even-numbered gate lines Gate6; and the fourth row of pixels corresponds to odd-numbered gate lines Gate7 and even-numbered gate lines Gate8. The two gate lines corresponding to a row of pixels are located above and below the row of pixels, respectively.

[0086] At least one of the multiple sub-pixels located in the same pixel block is coupled to an odd-numbered gate line Gate, and at least one is coupled to an even-numbered gate line Gate.

[0087] For example, Figure 5Taking the first pixel block PB1 in the example, at least one of the multiple sub-pixels in the first pixel block PB1 is coupled to the corresponding odd-numbered gate line Gate. For example, in the first pixel block PB1, the G sub-pixel in the second column and first row is coupled to the corresponding odd-numbered gate line Gate1, and the G sub-pixel in the second column and second row is coupled to the corresponding odd-numbered gate line Gate3. At least one of the multiple sub-pixels in the first pixel block PB1 is coupled to the corresponding even-numbered gate line Gate. For example, in the first pixel block PB1, the R sub-pixel in the first column and first row is coupled to the corresponding even-numbered gate line Gate2, and the R sub-pixel in the first column and second row is coupled to the corresponding even-numbered gate line Gate4.

[0088] It should be noted that, in this article, the coupling of the sub-pixel and the data line Data should be understood as the coupling of the source of the thin film transistor corresponding to the sub-pixel and the data line Data, and the coupling of the sub-pixel and the gate line Gate should be understood as the coupling of the gate of the thin film transistor corresponding to the sub-pixel and the gate line Gate.

[0089] In related technologies, such as Figure 2-Figure 4 As shown, the first two columns of pixels (i.e., the 1st to 6th columns of sub-pixels) can be regarded as the first pixel block, and the last two columns of pixels (i.e., the 7th to 12th columns of sub-pixels) can be regarded as the second pixel block. Since each sub-pixel in the first pixel block is connected to the corresponding even-numbered gate line Gate, and each sub-pixel in the second pixel block is connected to the corresponding odd-numbered gate line Gate, the pre-charging effect of each sub-pixel in the first pixel block is better, and the pre-charging effect of each sub-pixel in the second pixel block is worse. As a result, the entire display panel appears as two columns of bright pixels and two columns of dark pixels, resulting in vertical stripes under the overloaded H1-Line screen.

[0090] In the embodiment of the present disclosure, at least one of the multiple sub-pixels located in the same pixel block is coupled to the odd-numbered gate line Gate, and at least one is coupled to the even-numbered gate line Gate. That is, in the embodiment of the present disclosure, in the first pixel block, at least one sub-pixel is coupled to the corresponding odd-numbered gate line Gate, and at least one sub-pixel is coupled to the corresponding even-numbered gate line Gate; in the second pixel block, at least one sub-pixel is coupled to the corresponding odd-numbered gate line Gate, and at least one sub-pixel is coupled to the corresponding even-numbered gate line Gate. Thus, for each pixel block, the sub-pixels coupled to the odd-numbered gate line Gate have a poor pre-charging effect, while the sub-pixels coupled to the even-numbered gate line Gate have a good pre-charging effect. This avoids the situation where all sub-pixels in the pixel block have a good pre-charging effect or all sub-pixels have a poor pre-charging effect, so that each pixel block is composed of a mixture of sub-pixels with a good pre-charging effect and sub-pixels with a poor pre-charging effect, making the overall brightness of the pixel block more balanced, improving the situation where one pixel block of the entire display panel is bright and one pixel block is dark, and improving the vertical stripes of the overloaded H1-Line display screen.

[0091] In one embodiment, Figure 5 As shown, in at least two pixel blocks, the data lines Data corresponding to the corresponding columns of sub-pixels are coupled to the same data signal.

[0092] For example, in Figure 5 In the two pixel blocks, the first column of sub-pixels corresponds to the seventh column of sub-pixels, and the first data line Data1 and the seventh data line Data7 are connected to the same data signal V D1 The second column of sub-pixels corresponds to the eighth column of sub-pixels, the second data line Data2 and the eighth data line Data8 and the same data signal V D2 The third column of sub-pixels corresponds to the ninth column of sub-pixels, the third data line Data3 and the ninth data line Data9 and the same data signal V D3 The fourth column of sub-pixels corresponds to the tenth column of sub-pixels, the fourth data line Data4 and the tenth data line Data10 and the same data signal V D4 The fifth column of sub-pixels corresponds to the eleventh column of sub-pixels, the fifth data line Data5 and the eleventh data line Data11 and the same data signal V D5 The sixth column of sub-pixels corresponds to the twelfth column of sub-pixels, the sixth data line Data6 and the twelfth data line Data12 and the same data signal V D6 Coupling.

[0093] In this way, two data lines Data are coupled to the same data signal, which can reduce the number of data signals, so that the number of data signals is halved, and the number of data driving modules such as data COF (Chip On Film) is reduced, thereby reducing costs.

[0094] Figure 6 FIG1 is a partial plan view of a display panel in another embodiment of the present disclosure. In another embodiment, in a same pixel block, at least one of the multiple sub-pixels located in the same row is coupled to an odd-numbered gate line Gate, and at least one is coupled to an even-numbered gate line Gate. For example, Figure 6 In the second row of sub-pixels in the first pixel block, the sub-pixels in the 2nd, 4th and 6th columns are coupled to the odd gate line Gate3, and the sub-pixels in the 1st, 3rd and 5th columns are coupled to the even gate line Gate4.

[0095] In this way, the sub-pixels in the same row of a pixel block are composed of a mixture of sub-pixels with good pre-charging effects and sub-pixels with poor pre-charging effects, making the brightness of the same row in the pixel block more balanced, and thus making the brightness of the entire pixel block more balanced, further improving the situation where one pixel block is bright and one pixel block is dark in the entire display panel, and improving the vertical stripes of the heavy-load H1-Line display screen.

[0096] For example, Figure 6 As shown, in the same pixel block, the number of sub-pixels coupled to the odd-numbered gate lines Gate is the same as the number of sub-pixels coupled to the even-numbered gate lines Gate. Therefore, the pixel block is not only composed of a mixture of sub-pixels with good pre-charging effects and sub-pixels with poor pre-charging effects, but also the number of sub-pixels with good pre-charging effects and sub-pixels with poor pre-charging effects is the same. Therefore, when displaying, the brightness of the sub-pixels with good pre-charging effects and the sub-pixels with poor pre-charging effects in the pixel block can be balanced with each other, making the overall brightness of the pixel block more balanced, which can further improve the vertical stripes of the heavy-load H1-Line display screen.

[0097] In one embodiment, Figure 6 As shown, in the same row of the same pixel block, the number of sub-pixels coupled to the odd-numbered gate lines "Gate" is the same as the number of sub-pixels coupled to the even-numbered gate lines "Gate." With this arrangement, a row of sub-pixels in a pixel block is composed of a mixture of sub-pixels with good pre-charging effects and sub-pixels with poor pre-charging effects. Furthermore, the number of sub-pixels with good pre-charging effects and sub-pixels with poor pre-charging effects is the same, which can improve the brightness uniformity of sub-pixels in the same row of the pixel block and further improve the vertical streaks of heavy-load H1-Line display images.

[0098] like Figure 6 As shown, two adjacent sub-pixels in a pixel unit are coupled to different gate lines Gate. Figure 6 In the example, the R subpixel in pixel unit P1 is coupled to the even-numbered gate line Gate2, the G subpixel is coupled to the odd-numbered gate line Gate1, and the B subpixel is coupled to the even-numbered gate line Gate2. This way, a pixel unit is composed of a mixture of subpixels with good pre-charge effects and subpixels with poor pre-charge effects, making the brightness of the pixel unit more balanced, and thus the brightness of the entire pixel block more balanced, further improving the vertical stripes on the heavily loaded H1-Line display screen.

[0099] In one embodiment, Figure 6 As shown, in the same row of sub-pixels in the same pixel block, two adjacent sub-pixels are coupled to different gate lines. This way, in the same row of sub-pixels in the same pixel block, one of the two adjacent sub-pixels has a good pre-charge effect, while the other has a poor pre-charge effect. This allows the brightness of the two adjacent sub-pixels to compensate for each other, improving the brightness uniformity of the sub-pixels in the same row within the pixel block and helping to improve the vertical streaks that can be seen on heavy-load H1-Line displays.

[0100] like Figure 6As shown, in the same row of pixel units, the number of sub-pixels coupled to odd-numbered gate lines Gate is the same as the number of sub-pixels coupled to even-numbered gate lines Gate. In this way, multiple sub-pixels with good pre-charging effects can correspond one-to-one with multiple sub-pixels with poor pre-charging effects. Therefore, the sub-pixels with good pre-charging effects and the sub-pixels with poor pre-charging effects can compensate each other's brightness in a one-to-one manner, improving the brightness uniformity of the pixel units in the same row and further improving the vertical stripes of the heavy-load H1-Line display screen.

[0101] In one embodiment, Figure 6 As shown, in the same row of sub-pixels, one of the two adjacent sub-pixels coupled to the same data signal is coupled to an odd-numbered gate line Gate, and the other is coupled to an even-numbered gate line Gate. Figure 6 In the first row of sub-pixels, the data signal V D1 Two adjacent sub-pixels are coupled: the first column sub-pixel and the seventh column sub-pixel. One of the two sub-pixels is coupled to an odd-numbered gate line, Gate, and the other is coupled to an even-numbered gate line, Gate. For example, the first column sub-pixel is coupled to an even-numbered gate line, Gate, and the seventh column sub-pixel is coupled to an odd-numbered gate line, Gate; or, the first column sub-pixel is coupled to an odd-numbered gate line, Gate, and the seventh column sub-pixel is coupled to an even-numbered gate line, Gate.

[0102] In this way, during the actual charging time of each gate line Gate, a data signal is only written into one sub-pixel, which ensures the data stability of the sub-pixel and is conducive to ensuring the display effect.

[0103] like Figure 5 and Figure 6 As shown, the display sub-area includes two pixel blocks arranged along a first direction. The pixel block includes two columns of pixel units. The pixel unit includes three sub-pixels, and the three sub-pixels are arranged along the first direction.

[0104] In one embodiment, the pixel block may include at least one pixel group PZ arranged along the second direction, and the pixel group PZ includes at least two rows of pixel units. Figure 5 and Figure 6 In the embodiment of the present invention, the pixel block includes two pixel groups PZ1 and PZ2 arranged along the second direction. The pixel groups include two rows of pixel units. In the same frame, a row of pixel units in each pixel group is illuminated. In the same frame, at least one of the illuminated sub-pixels is coupled to the corresponding odd-numbered gate line Gate, and at least one is coupled to the corresponding even-numbered gate line Gate.

[0105] For example, in one frame, one row of pixel units in a pixel group is lit, and multiple rows of pixel units in a pixel group are lit in sequence in multiple frames. Figure 6In the embodiment, the pixel group includes two rows of pixel units, the first row of pixel units in each pixel group is illuminated in the first frame, and the second row of pixel units in each pixel group is illuminated in the second frame. Thus, the corresponding row of pixel units in each pixel group is illuminated in the same frame.

[0106] In this embodiment, in the same frame, the sub-pixels coupled to the odd-numbered gate lines Gate have a poor pre-charging effect, while the sub-pixels coupled to the even-numbered gate lines Gate have a good pre-charging effect. This avoids the situation where all sub-pixels in a frame have good pre-charging effects or all sub-pixels have poor pre-charging effects, so that a frame is composed of a mixture of sub-pixels with good pre-charging effects and sub-pixels with poor pre-charging effects, making the overall brightness of the frame more balanced, and further improving the vertical stripes of the overloaded H1-Line display of the entire display panel.

[0107] In one embodiment, Figure 6 As shown, in the same pixel block, at least one of the multiple sub-pixels located in the same column is coupled to an odd-numbered gate line, Gate, and at least one is coupled to an even-numbered gate line, Gate. This approach allows the sub-pixels coupled to the odd-numbered gate lines and the sub-pixels coupled to the even-numbered gate lines to be aligned with each other in the column direction, further improving the vertical streaks of the H1-Line display image of the entire display panel.

[0108] For example, in the same frame, a row of pixel units in each pixel group is illuminated, and at least one of the illuminated sub-pixels in the same column is coupled to the corresponding odd-numbered gate line Gate, and at least one is coupled to the corresponding even-numbered gate line Gate.

[0109] In one embodiment, Figure 6 As shown, the pixel block includes at least one pixel group arranged along the second direction, and the pixel group includes at least two rows of pixel units. In the same column of sub-pixels, the sub-pixels in corresponding rows in two adjacent pixel groups are coupled to different gate lines Gate.

[0110] Figure 6 The pixel architecture shown can be called a C4 architecture. In the C4 architecture, the corresponding row pixel units in each pixel group in the same frame are illuminated. In the same column of sub-pixels, the sub-pixels in the corresponding rows in two adjacent pixel groups are coupled to different gate lines, Gate. Thus, in the multiple rows of sub-pixels illuminated in one frame, two adjacent sub-pixels in the same column of sub-pixels are coupled to different gate lines, Gate. The sub-pixels coupled to the odd-numbered gate lines, Gate, have a poor pre-charging effect, while the sub-pixels coupled to the even-numbered gate lines, Gate, have a good pre-charging effect. Thus, the brightness of the sub-pixels with a good pre-charging effect in the column direction can compensate for the brightness of the sub-pixels with a poor pre-charging effect, further improving the vertical stripe defects of the overloaded H1-Line display screen of the entire display panel.

[0111] like Figure 6 As shown, the pixel group may include two rows of pixel units. The pixel block may include two pixel groups arranged along the second direction.

[0112] The sub-pixels in the same column of the same pixel group are coupled to the same corresponding gate line. Figure 6 In the first pixel group, the sub-pixels in the first column are coupled to the corresponding even-numbered gate lines (Gate2 and Gate4), and the sub-pixels in the second column are coupled to the corresponding odd-numbered gate lines (Gate1 and Gate3). In the second pixel group, the sub-pixels in the first column are coupled to the corresponding odd-numbered gate lines (Gate5 and Gate7), and the sub-pixels in the second column are coupled to the corresponding even-numbered gate lines (Gate6 and Gate8).

[0113] In one embodiment, Figure 3 As shown, multiple gate lines Gate are configured to be sequentially provided with gate drive signals, and the gate drive signals include a pre-charge phase and a real charge phase, and the pre-charge phase overlaps with the previous gate drive signal. Multiple data lines Data coupled thereto are configured to be periodically provided with data signals, so that in the same frame, the pixel units of odd rows are illuminated or the pixel units of even rows are illuminated.

[0114] exist Figure 6 In the embodiment, the display sub-area includes two pixel blocks, the pixel block includes two pixel groups, and the pixel group includes two rows of pixel units. Therefore, in this embodiment, the display sub-area includes four rows and twelve columns of sub-pixels. The connection relationship between each sub-pixel and the gate line Gate is as follows: Figure 6 shown.

[0115] Figure 7 : is a cross-sectional schematic diagram of a first substrate in a display panel according to an embodiment of the present disclosure. Figure 8 is a partial plan view of the first substrate, Figure 7 Can include Figure 8 AA section in.

[0116] The display panel may include a first substrate and a second substrate disposed opposite to each other. From the plan view of the first substrate, a plurality of data lines Data are connected to the data signal on the upper side or the lower side of the display area. For example, Figure 8 As shown, in the display sub-area, the corresponding data lines Data are connected to each other at the lower side of the display area and coupled to the data signal. D1 ~V D6 The 12 data lines Data1 to Data12 enter the display area from bottom to top. Common signal lines are arranged around the display area to provide common signals to the common electrodes of the sub-pixels.

[0117] like Figure 8 As shown, the first data line Data1 and the seventh data line Data7 are connected at the lower side of the display area via a first data link line DL1; the second data line Data2 and the eighth data line Data8 are connected at the lower side of the display area via a second data link line DL2; the third data line Data3 and the ninth data line Data9 are connected at the lower side of the display area via a third data link line DL3; the fourth data line Data4 and the tenth data line Data10 are connected at the lower side of the display area via a fourth data link line DL4; the fifth data line Data5 and the eleventh data line Data11 are connected at the lower side of the display area via a fifth data link line DL5; and the sixth data line Data6 and the twelfth data line Data12 are connected at the lower side of the display area via a sixth data link line DL6. The six data link lines DL and the data lines Data can be located on different layers.

[0118] like Figure 7 As shown, the first substrate may include a first base 11, a first metal layer 12, a first insulating layer 13, and a second metal layer 14. The first metal layer 12 is located on one side of the first base 11. The first metal layer 12 may include a gate line Gate and a gate electrode 121 of a thin film transistor, as well as data connection lines DL corresponding to data signals. For example, the first metal layer 12 may include a first data connection line DL1, a second data connection line DL2, a third data connection line DL3, a fourth data connection line DL4, a fifth data connection line DL5, and a sixth data connection line DL6. The first insulating layer 13 is located on the side of the first metal layer 12 facing away from the first base 11.

[0119] Second metal layer 14 is located on the side of first insulating layer 13 facing away from first substrate 11. Second metal layer 14 includes data lines (Data). Multiple data lines coupled to the same data signal are connected via data connection lines. Second metal layer 14 may also include source and drain electrodes for thin-film transistors.

[0120] For example, the first substrate may further include a second insulating layer 15, which is located on a side of the second metal layer 14 facing away from the first base 11. The second insulating layer 15 is provided with a first via hole 151 and a second via hole 152. The first via hole 151 penetrates the second insulating layer 15 to expose a portion of the surface of the data line Data, and the second via hole 152 penetrates the second insulating layer 15 and the first insulating layer 13 to expose a portion of the surface of the data connection line.

[0121] The first substrate may further include a first transparent conductive layer 16, which is located on a side of the second insulating layer 15 away from the first base 11. The first transparent conductive layer 16 includes a first adapter line 161, which is connected to the data line Data through the first via hole 151 and to the data connection line D1 through the second via hole 152. Thus, the data line Data is connected to the data connection line DL through the first adapter line 161. Figure 7 As shown, the first transparent conductive layer 16 may further include a pixel electrode 162 .

[0122] The data connection line is connected to the data signal, and the data signal is transmitted through the data transmission line. Thus, the data connection line is connected to the data transmission line. The data transmission line is located on the first metal layer 12. The data transmission line is used to couple with the data driving module. Therefore, the data signal generated by the data driving module can be transmitted to the data line Data through the data transmission line.

[0123] like Figure 8 As shown, the six pairs of data lines Data can be connected to the data transmission lines DS1 to DS6 in sequence through the second adapter lines ZJ1 to ZJ6. The second adapter lines can be located in the second metal layer or the first metal layer. Figure 8 In the data signal V D1 ~V D3 The second connecting wires ZJ1, ZJ2, and ZJ3 can be located in the second metal layer 14; D4 ~V D6 The three connected second transition wires ZJ4 , ZJ5 , and ZJ6 may be located in the first metal layer 12 .

[0124] Illustratively, the first substrate may further include a semiconductor layer 17, which is located between the second metal layer 14 and the first insulating layer 13. The semiconductor layer 17 includes a first portion 171 and a second portion 172. The first portion 171 is located between the source and the drain, and serves as a channel of the thin film transistor. The orthographic projection of the second portion 172 on the first substrate 11 coincides with the orthographic projection of the second metal layer 14 on the second substrate.

[0125] The first substrate may further include a second transparent conductive layer 18, and the second transparent conductive layer 18 is located between the first base 11 and the first insulating layer 13. The second transparent conductive layer 18 includes a common electrode.

[0126] The following combination Figure 7The preparation process of the first substrate is described. It is understood that the "patterning" mentioned herein includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping when the patterned material is an inorganic material or metal, and includes processes such as mask exposure and development when the patterned material is an organic material. The evaporation, deposition, coating, and coating mentioned herein are all mature preparation processes in the relevant art.

[0127] like Figure 7 As shown, a second transparent conductive layer 18 is formed on one side of the first substrate 11. The second transparent conductive layer 18 may be made of a transparent conductive material such as indium tin oxide or indium zinc oxide, and has a thickness of about 700 angstroms. The second transparent conductive layer may include a common electrode.

[0128] A first metal layer 12 is formed on one side of the first substrate 11. The first metal layer 12 may be a molybdenum / aluminum / molybdenum laminated structure with a thickness of 150 / 3000 / 800 angstroms. The first metal layer 12 and the second transparent conductive layer are located on the same side of the first substrate 11.

[0129] A first insulating layer 13 is deposited on the side of the first substrate 11 where the first metal layer 12 and the second transparent conductive layer are formed. The thickness of the first insulating layer 13 is about 4000 angstroms.

[0130] A semiconductor film and a second metal film are sequentially deposited on the side of the first insulating layer 13 facing away from the first substrate 11. The semiconductor film has a thickness of about 1700 angstroms. The second metal film can be a molybdenum / aluminum / molybdenum laminated structure with a thickness of 150 / 3000 / 800 (angstroms). Photoresist is coated on the upper side of the second metal film. After the photoresist is exposed and developed using a gray tone mask, the photoresist outside the second metal layer 12 and the channel is completely removed, and the photoresist at the second metal layer and channel position is retained, and the thickness of the photoresist retained at the channel position is less than the thickness of the photoresist at the second metal layer position; a wet etching process is used to remove the second metal film and semiconductor film outside the photoresist to form a data line; an ashing process is used to remove the photoresist at the channel position, and a partial thickness of photoresist is retained at the second metal layer 12 position; a dry etching process is used to remove the second metal film at the channel position to form a source and a drain, and the semiconductor film retained between the source and the drain forms a channel.

[0131] A second insulating layer 15 with a thickness of approximately 4000 angstroms is deposited on the side of the second metal layer 14 facing away from the first substrate 11. A patterning process is used to form a first via 151, a second via 152, and a third via 153. The first via 151 and the third via 153 penetrate the second insulating layer 15. The first via 151 exposes a portion of the surface of the data line Data, and the third via 153 exposes a portion of the surface of the drain electrode; the second via 152 penetrates the second insulating layer 15 and the first insulating layer 13, and the second via 152 exposes a portion of the surface of the data connection line.

[0132] A first transparent conductive layer 16 is formed on the side of the second insulating layer 15 facing away from the first substrate 11. The thickness of the first transparent conductive layer 16 is approximately 700 angstroms. The material of the first transparent conductive layer 16 can be a transparent conductive material such as indium tin oxide or indium zinc oxide. The first transparent conductive layer 16 includes a pixel electrode 162 and a first adapter line 161. The pixel electrode 162 is connected to the drain electrode through the third via 153. The first adapter line 161 is connected to the data line Data through the first via 151. The first adapter line 161 is also connected to the data link line DL through the second via 152. Thus, the data line Data is connected to the data link line DL through the first adapter line 161.

[0133] The first insulating layer 13 and the second insulating layer 15 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer. The gate, source, and drain can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure.

[0134] Figure 9 for Figure 6 The corresponding display panel layout diagram. Figure 9 As shown, in order to maximize the aperture ratio, each sub-pixel corresponds to a TFT, for example, TFT1 corresponds to the first row and first column sub-pixel, TFT2 corresponds to the first row and first column sub-pixel, TFT3 corresponds to the first row and first column sub-pixel, and TFT4 corresponds to the first row and first column sub-pixel. The TFT position is shielded by a black matrix to maximize the aperture ratio. Figure 6 In the structure shown, there are cases where TFTs are adjacent to each other, for example, Figure 6 The TFTs corresponding to the sub-pixels in the second row and odd columns are located on the side close to the gate line Gate4, and the TFTs corresponding to the sub-pixels in the third row and odd columns are located on the side close to the gate line Gate5, so that two TFTs are arranged side by side. Figure 9Thus, the black matrix width between the sub-pixels in the second and third rows in the first column is greater than the black matrix width between the sub-pixels in the first and second rows in the first column.

[0135] In one embodiment, the display panel may further include a support column 30 located between the first substrate and the second substrate. The first substrate includes a first base 11, with the data line Data and the gate line Gate both located on the side of the first base 11 facing the second substrate. The pixel unit includes a blue sub-pixel B, which is coupled to one of the two gate lines Gate. The orthographic projection of the support column 30 on the first base 11 is located near the other gate line Gate of the blue sub-pixel. The pixel unit may also include a red sub-pixel R and a green sub-pixel G.

[0136] It should be noted that Figure 9 and the following text Figure 10 The three sub-pixels R, G, and B are arranged from left to right, but this does not mean that the arrangement order of the three sub-pixels R, G, and B is limited. Those skilled in the art should understand that the arrangement order of the three sub-pixels R, G, and B is not limited to Figure 9 and Figure 10 The arrangement shown in the figure can be set in the order of the three sub-pixels R, G, and B as needed. Figure 9 and Figure 10 The three sub-pixels R, G, and B are arranged in sequence from left to right.

[0137] For example Figure 9 In the example, the blue sub-pixel in the first row and sixth column is coupled to the corresponding odd-numbered gate line (Gate) (upper gate line). Therefore, the orthographic projection of the support column 30 on the first substrate 11 is located near the even-numbered gate line (Gate) of the blue sub-pixel. That is, the orthographic projection of the support column 30 on the first substrate 11 is located below the blue sub-pixel. A support column 30 is also provided above the blue sub-pixel in the second row and third column.

[0138] Compared to the red sub-pixel R and green sub-pixel G, the blue sub-pixel B has a lower brightness, which has the least impact on transmittance. Placing the support pillars in the blue sub-pixel B ensures a larger aperture ratio for the red and green sub-pixels R and G, not only ensuring the red and green sub-pixels R and G, but also maximizing transmittance. Furthermore, placing the support pillars in the blue sub-pixel B maximizes their area, ensuring the maximum support pillar area for the entire display panel.

[0139] A base can be set at the corresponding position of the blue sub-pixel, and the support column is located on the base. The base can be located on the first metal layer 12, and the width of the base can be the same as that of the TFT. Therefore, the width of the black matrix at the support column position is approximately CD2.

[0140] It should be noted that the number of support columns 30 can be set as needed, and the orthographic projection of the support column 30 on the first substrate 11 is located near another gate line Gate of the blue sub-pixel. It is understandable that not every blue sub-pixel is provided with a corresponding support column.

[0141] Figure 9 The boundary of the black matrix BM is shown in FIG. Figure 9 As can be seen from the figure, there are four types of black matrix position structures. The first one is as follows: Figure 9 The structure shown in A1 is that two TFTs are adjacent to each other; the second one is as Figure 9 The structure shown in A2 is that the TFT and the support column are adjacent to each other; the third one is as shown in Figure 9 The structure shown in A3 is that two support columns are adjacent to each other; the third type is as follows Figure 9 The structure shown in A4 is without TFT and support pillars.

[0142] Figure 10 for Figure 9 The layout structure diagram of the black matrix, such as Figure 10 As shown in FIG, the black matrix of the display panel has a staggered opening structure. Figure 9 and Figure 10 It can be seen that, compared with sub-pixel No. 1 and No. 2, the black matrix width of sub-pixel No. 2 is larger than that of sub-pixel No. 1, and the opening of sub-pixel No. 1 is larger than that of sub-pixel No. 2; similarly, compared with sub-pixel No. 3 and No. 4, the black matrix width of sub-pixel No. 4 is larger than that of sub-pixel No. 3, and the opening of sub-pixel No. 3 is larger than that of sub-pixel No. 4. In the display panel of the embodiment of the present disclosure, the black matrix is ​​as follows: Figure 10 The structure shown can maximize the aperture ratio.

[0143] Figure 11 This is a schematic diagram of a 19T1C shift register. Figure 12 To adopt Figure 11 The gate drive circuit of the shift register shown in the figure works as a timing diagram. Among them, the gate drive circuit GOA uses 6 CLK signals. In this disclosure, the gate signal of the display area uses Figure 11 GOA can adopt 19T1C architecture, such as Figure 11 shown.

[0144] refer to Figure 11, the input of the first row shift register is connected to the trigger signal STV1. When the trigger signal STV1 arrives, GOA starts working, the first transistor M1 turns on, and charges the pull-up node PU. At this time, the clock signal CLK is low. When the clock signal CLK becomes high, due to the effect of capacitor C, the pull-up node PU becomes higher, thereby turning on M3 and M13, G OUT and G OUTC Both output CLK high level. OUT The output signal charges the sub-pixels in the display area, G OUTC The output signal is given to the signal input terminal of the next row, thereby outputting the gate signal in sequence to realize the GOA function.

[0145] G OUT Used to provide gate signal to the display area to realize charging of the display area, G OUTC As the cascade signal of the shift register, avoid affecting the display area.

[0146] Figure 11 In the circuit, VDDO and VDDE are alternately high, which can control the potential of the pull-down node PD1 or PD2. When PU is low, PD can reduce noise, making PU low so as not to affect the output. This is equivalent to two sets of circuits staggered to control PD (VDDE is low when VDDO is high, and VDDE is low when VDDO is high). VDDO and VDDE are alternately high, which can prevent the TFT from being damaged by the bias (high level) all the time.

[0147] Figure 12 Taking FHD (1920*1080) Dual Gate as an example, there are 1080 rows of pixels. The number of gate lines in the Dual Gate architecture is 2160. Gate1 to Gate2160 of the GOA with 6 clock signals are output sequentially with 6 clock signals as one cycle. The actual charging phase of each gate line is 1 hour, and each gate line gate adds a 2 hour pre-charging phase. Therefore, the high level phase and low level phase of each clock signal are both 3 hours. The actual charging time of each gate line gate (i.e., data writing time) is 1 hour.

[0148] The present disclosure also provides a display panel driving method, which is applied to the display panel in the present disclosure. The driving method includes: sequentially providing gate drive signals to multiple gate lines (Gate) in a display sub-region, the gate drive signals including a pre-charge phase and a real charge phase, the pre-charge phase overlapping a portion of the previous gate drive signal; and periodically providing data signals so that in the same frame, odd-numbered rows of pixel units in the display sub-region are illuminated or even-numbered rows of pixel units are illuminated.

[0149] Exemplarily, the data signal includes a first data write phase and a second data write phase, and the data signal is periodically provided, including: in the first data write phase, the sub-pixels coupled to the odd gate line Gate in the corresponding row pixel unit are lit; in the second data write phase, the sub-pixels coupled to the even gate line Gate in the corresponding row pixel unit are lit.

[0150] Illustratively, in the pre-charging stage, the sub-pixels coupled to the gate line Gate are pre-charged with the current signal in the data line Data.

[0151] Figure 13 This is a working sequence and display effect diagram of the display sub-area in the display panel according to an embodiment of the present disclosure. Figure 13 The driving method of the display panel according to the embodiment of the present disclosure is described in detail.

[0152] like Figure 13 As shown, gate drive signals are sequentially provided to multiple gate lines Gate in the display sub-area. For example, gate drive signals are sequentially provided to gate lines Gate1 to Gate8. The gate drive signal includes a pre-charge phase and a real charge phase. The pre-charge phase overlaps with a portion of the previous gate drive signal. For example, in the signal of gate line Gate2, the phase marked with 2H is the real charge phase, and the phases marked with 0H and 1H are the pre-charge phase. The pre-charge phase overlaps with a portion of the signal of the previous gate line Gate1.

[0153] exist Figure 13 In the data signal waveform diagram, "0" is used to indicate that the data signal 0 is not provided; "1" is used to indicate that the data signal is provided. The "0" and "1" here should not be understood as specific data signal voltage values. In actual implementation, the specific voltage value of the data signal can be determined according to actual needs. For example, "V1" is used to indicate that the data signal is not provided, or it can be understood that when the data signal voltage value is V1, the corresponding sub-pixel is extinguished; "V2" is used to indicate that the data signal is provided, or it can be understood that when the data signal voltage value is V2, the corresponding sub-pixel is illuminated.

[0154] In one embodiment, the data signal is provided periodically so that in the same frame, the odd-numbered rows of pixel units in the display sub-area are illuminated or the even-numbered rows of pixel units are illuminated. Figure 13 In one frame, the first row of sub-pixels and the second row of sub-pixels are lit, and the second row of sub-pixels and the fourth row of sub-pixels are extinguished.

[0155] Since the two corresponding data lines Data in the two pixel blocks are coupled to the same data signal, in order to ensure that the corresponding row of sub-pixels is lit, the data signal may include a first data writing phase and a second data writing phase. The first data writing phase overlaps with the actual charging phase of the odd-numbered gate lines Gate of the corresponding row of sub-pixels, and the second data writing phase overlaps with the actual charging phase of the even-numbered gate lines Gate of the corresponding row of sub-pixels. For example, Figure 13 In the embodiment, the first data writing phase of the first pulse of the data signal overlaps with the real charging phase of the odd-numbered gate line Gate1 corresponding to the first row of sub-pixels, and the second data writing phase overlaps with the real charging phase of the even-numbered gate line Gate2 corresponding to the first row of sub-pixels; the first data writing phase of the second pulse of the data signal overlaps with the real charging phase of the odd-numbered gate line Gate5 corresponding to the third row of sub-pixels, and the second data writing phase overlaps with the real charging phase of the even-numbered gate line Gate6 corresponding to the third row of sub-pixels. Therefore, in Figure 13 In the example, the first row of sub-pixels and the second row of sub-pixels are lit.

[0156] At the first pulse time of the data signal, the first pulse of the data signal overlaps with the pre-charging phase of the odd gate line Gate3 of the second row of sub-pixels. Therefore, the sub-pixels coupled to the odd gate line Gate3 in the second row of sub-pixels are pre-charged with the current data signal.

[0157] In a cycle, for example, when Gate 2 opens the R subpixel in the first column and first row, the data written to the R subpixel when Gate 1 was opened in the previous row was high, and the subpixel corresponding to Gate 2 is pre-charged to a high level. This means the R subpixel in the first column and first row is pre-charged to a high level, resulting in a good pre-charge effect. Therefore, the R subpixel in the first column and first row is marked as "+." Similarly, when Gate 5 opens the R subpixel in the first column and third row, the data written to the R subpixel in the previous row by Gate 4 was low, and the R subpixel corresponding to Gate 5 is pre-charged to a low level, resulting in a poor pre-charge effect. Therefore, the R subpixel in the first column and third row is marked as "-." Similarly, the R subpixel in the fourth column and first row has a pre-charge effect of "-," while the R subpixel in the fourth column and third row has a pre-charge effect of "+." The R subpixel in the seventh column and first row has a pre-charge effect of "-," while the R subpixel in the seventh column and third row has a pre-charge effect of "+." The R subpixel in the tenth column and first row has a pre-charge effect of "+," while the R subpixel in the tenth column and third row has a pre-charge effect of "-." Similarly, the pre-charge effect of G sub-pixel and B sub-pixel can be derived, such as Figure 13As shown, the G sub-pixels in the second column have a pre-charge effect of "-" for the first row and a pre-charge effect of "+" for the third row; the G sub-pixels in the fifth column have a pre-charge effect of "+" for the first row and a pre-charge effect of "-" for the third row; the G sub-pixels in the eighth column have a pre-charge effect of "+" for the first row and a pre-charge effect of "-" for the third row; the G sub-pixels in the eleventh column have a pre-charge effect of "-" for the first row and a pre-charge effect of "+" for the third row; the B sub-pixels in the third column have a pre-charge effect of "+" for the first row and a pre-charge effect of "-" for the third row; the B sub-pixels in the sixth column have a pre-charge effect of "-" for the first row and a pre-charge effect of "+" for the third row; the B sub-pixels in the ninth column have a pre-charge effect of "-" for the first row and a pre-charge effect of "+" for the third row; the B sub-pixels in the twelfth column have a pre-charge effect of "+" for the first row and a pre-charge effect of "-" for the third row.

[0158] from Figure 13 It can be seen that, judging from the number of columns, in the sub-pixels of different rows, the sub-pixels with the pre-charge effect of "+" and the sub-pixels with the pre-charge effect of "-" are adjacent to each other, and the brightness of the sub-pixels with the pre-charge effect of "+" and the sub-pixels with the pre-charge effect of "-" can compensate each other to avoid the brightness difference between the two, thereby avoiding the vertical stripes caused by the brightness difference between odd and even columns, and fundamentally solving the H1-Line vertical stripes problem of the overloaded screen; at the same time, judging from the number of rows, in the sub-pixels of different columns, the sub-pixels with the pre-charge effect of "+" and the sub-pixels with the pre-charge effect of "-" are adjacent to each other, which will not cause horizontal stripes.

[0159] An embodiment of the present disclosure also provides a driving device for a display panel, which is applied to the display panel in any embodiment of the present disclosure. The driving device may include: a gate driving module, which is used to sequentially provide gate driving signals to multiple gate lines Gate in the display sub-area, and the gate driving signal includes a pre-charging stage and a real charging stage, and the pre-charging stage overlaps with a portion of the previous gate driving signal; a data driving module, which is used to periodically provide data signals to the data signal, so that in the same frame, the pixel units in odd rows are lit or the pixel units in even rows are lit.

[0160] An embodiment of the present disclosure also provides an electronic device, comprising: at least one first processor; and a first memory communicatively connected to the at least one first processor; wherein the first memory stores instructions that can be executed by the at least one first processor, and the instructions are executed by the at least one first processor so that the at least one first processor can execute the driving method of the display panel in any embodiment of the present disclosure.

[0161] The present disclosure further provides a display device, comprising the display panel in any embodiment of the present disclosure, and may further comprise the driving device or electronic device in an embodiment of the present disclosure.

[0162] The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0163] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0164] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0165] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0166] In the present disclosure, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0167] The disclosure above provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, these are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0168] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily conceive of various changes or substitutions within the technical scope disclosed in this disclosure. Different parts of different embodiments can be combined with each other without conflict, and all of these should be included in the scope of protection of this disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: The device comprises a display area, wherein the display area comprises at least one display sub-area, and the display sub-area comprises: A plurality of pixel units arranged in an array, the plurality of pixel units being divided into at least two pixel blocks arranged along a first direction, the pixel block comprising at least one column of pixel units, and the pixel unit comprising a plurality of sub-pixels arranged along the first direction; a plurality of data lines extending along a second direction, the plurality of data lines corresponding one-to-one to a plurality of columns of sub-pixels, the sub-pixels being connected to the corresponding data lines, wherein the second direction intersects the first direction; a plurality of pairs of gate lines, the gate lines extending along the first direction, each pair of gate lines corresponding to a row of pixel units, each pair of gate lines comprising odd-numbered gate lines and even-numbered gate lines, the odd-numbered gate lines and the even-numbered gate lines being respectively arranged on opposite sides of the corresponding row of pixel units; At least one sub-pixel in the pixel block is coupled to the odd-numbered gate lines, and at least one sub-pixel is coupled to the even-numbered gate lines.

2. The display panel according to claim 1, wherein: In the at least two pixel blocks, data lines corresponding to corresponding columns of sub-pixels are coupled to the same data signal.

3. The display panel according to claim 1, wherein: In the same pixel block, at least one sub-pixel in the same row is coupled to the odd-numbered gate lines, and at least one sub-pixel is coupled to the even-numbered gate lines.

4. The display panel according to claim 3, wherein: In the same pixel block, the number of sub-pixels coupled to the odd-numbered gate lines is the same as the number of sub-pixels coupled to the even-numbered gate lines.

5. The display panel according to claim 3, wherein: In the same row of the same pixel block, the number of sub-pixels coupled to the odd-numbered gate lines is the same as the number of sub-pixels coupled to the even-numbered gate lines.

6. The display panel according to claim 1, wherein: Two adjacent sub-pixels in the pixel unit are coupled to different gate lines.

7. The display panel according to claim 6, wherein: In the same row of sub-pixels in the same pixel block, two adjacent sub-pixels are coupled to different gate lines.

8. The display panel according to claim 6, wherein: In the same row of pixel units, the number of sub-pixels coupled to the odd-numbered gate lines is the same as the number of sub-pixels coupled to the even-numbered gate lines.

9. The display panel according to claim 2, wherein: In the same row of sub-pixels, one of the two adjacent sub-pixels coupled to the same data signal is coupled to the odd-numbered gate line, and the other is coupled to the even-numbered gate line.

10. The display panel according to claim 1, wherein The display sub-area includes two pixel blocks arranged along a first direction.

11. The display panel according to claim 1, wherein The pixel block includes two columns of pixel units, and the pixel unit includes three sub-pixels.

12. The display panel according to claim 1, wherein The pixel block includes at least one pixel group arranged along the second direction, and the pixel group includes at least two rows of pixel units; In the same frame, a row of pixel units in each pixel group is illuminated, and at least one of the illuminated sub-pixels in the same frame is coupled to a corresponding odd-numbered gate line, and at least one is coupled to a corresponding even-numbered gate line.

13. The display panel according to any one of claims 1 to 12, characterized in that: In the same pixel block, at least one of the multiple sub-pixels located in the same column is coupled to the odd-numbered gate lines, and at least one is coupled to the even-numbered gate lines.

14. The display panel according to any one of claims 1 to 12, characterized in that: The pixel block includes at least one pixel group arranged along the second direction, the pixel group includes at least two rows of pixel units, and in the same column of sub-pixels, sub-pixels in corresponding rows in two adjacent pixel groups are coupled to different gate lines.

15. The display panel according to claim 14, wherein: The pixel group includes two rows of pixel units; and / or the pixel block includes two pixel groups arranged along the second direction.

16. The display panel according to claim 15, wherein: Sub-pixels in the same column of the same pixel group are coupled to the same corresponding gate line.

17. The display panel according to claim 1, wherein: The plurality of gate lines are configured to be sequentially provided with gate drive signals, wherein the gate drive signals include a pre-charge phase and a real charge phase, and the pre-charge phase overlaps with a previous gate drive signal; The coupled data lines are configured to be periodically provided with data signals by the data signal, so that in the same frame, the pixel units in the odd-numbered rows are illuminated or the pixel units in the even-numbered rows are illuminated.

18. The display panel according to claim 1, wherein include: first base; a first metal layer located on one side of the first substrate, the first metal layer including the gate line and a data connection line corresponding to the data signal; a first insulating layer, located on a side of the first metal layer facing away from the first substrate; The second metal layer is located on a side of the first insulating layer away from the first substrate. The second metal layer includes the data line. A plurality of data lines coupled to the same data signal are connected via the data connection line.

19. The display panel according to claim 18, wherein: It also includes a second insulating layer and a first transparent conductive layer, the second insulating layer is located on the side of the second metal layer facing away from the first substrate, the first transparent conductive layer is located on the side of the second insulating layer facing away from the first substrate, the first transparent conductive layer includes a first adapter line, the data line is connected to the data connection line through the first adapter line, the data connection line is connected to the data transmission line, the data transmission line is located in the first metal layer, and the data transmission line is used to couple with a data driving module.

20. The display panel according to claim 1, wherein The invention comprises a first substrate and a second substrate arranged opposite to each other, and also comprises a support column located between the first substrate and the second substrate, the first substrate comprises a first base, the data line and the gate line are both located on the side of the first base facing the second substrate, the pixel unit comprises a blue sub-pixel, the blue sub-pixel is coupled to one of the two gate lines, and the orthographic projection of the support column on the first base is located at a position of the blue sub-pixel close to the other gate line.

21. A method for driving a display panel, characterized in that: Applied to the display panel according to any one of claims 1 to 20, the method comprising: sequentially providing a gate drive signal to a plurality of gate lines in the display sub-area, wherein the gate drive signal includes a pre-charging phase and a real charging phase, wherein the pre-charging phase overlaps with a portion of a previous gate drive signal; The data signal is provided periodically so that in the same frame, the odd-numbered rows of pixel units in the display sub-area are lighted or the even-numbered rows of pixel units are lighted.

22. The driving method according to claim 21, wherein: The data signal includes a first data writing phase and a second data writing phase, and periodically provides the data signal, including: In the first data writing phase, the sub-pixels coupled to the odd-numbered gate lines in the corresponding row of pixel units are lit; In the second data writing phase, the sub-pixels coupled to the even-numbered gate lines in the corresponding row of pixel units are lit.

23. The driving method according to claim 21, wherein: In the pre-charging stage, the sub-pixels coupled to the gate lines are pre-charged with the current signals in the data lines.

Images