A read-after-write conflict prediction method, device and equipment

Abstract

The application provides a read-after-write conflict prediction method, device and equipment, applied to the technical field of data processing. The method comprises reading a load instruction to be transmitted. The load instruction is located in a load queue of an out-of-order execution processor. An index value of the load instruction is determined. The index value is used to quickly locate a conflict record matched with the load instruction in a history conflict table of the out-of-order execution processor. The conflict record comprises a first store instruction corresponding to the load instruction. In the case that the conflict record corresponding to the index value exists in the history conflict table, the load instruction is set to a suspended state. After the execution of the first store instruction ends, the load instruction is executed. The problem that the execution efficiency of the processor is affected due to the pipeline emptying and stalling caused by the read-after-write conflict can be solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to a read-after-write conflict prediction method, device and equipment. BACKGROUND

[0002] In modern high-performance processor design, a load-store unit (LSU) as a core component of a memory subsystem is responsible for managing data load and store operations between a cache and a register.

[0003] With the continuous increase of the depth of the processor pipeline and the wide application of out-of-order execution (OoO) technology, the dependency relationship between instructions becomes increasingly complex, especially in the case of a read-after-write (RAW) conflict, a Load instruction may read an old value before a Store instruction updates the data, thereby causing subsequent instructions to perform calculations based on the wrong old value, ultimately triggering pipeline flushing and stalling, which seriously affects the execution efficiency of the processor. SUMMARY

[0004] The purpose of the present application is to provide a read-after-write conflict prediction method, device and equipment, to solve the problem of pipeline flushing and stalling caused by read-after-write conflict, thereby affecting the execution efficiency of the processor.

[0005] In a first aspect, the embodiments of the present application provide a read-after-write conflict prediction method applied to an out-of-order execution processor, which comprises reading a to-be-fired Load instruction. The Load instruction is located in a Load queue of the out-of-order execution processor. An index value of the Load instruction is determined. The index value is used to quickly locate a conflict record matched with the Load instruction in a history conflict table of the out-of-order execution processor. The conflict record comprises a first Store instruction corresponding to the Load instruction. In the case where the history conflict table contains the conflict record corresponding to the index value, the Load instruction is set to a suspended state. After the execution of the first Store instruction ends, the Load instruction is executed.

[0006] The read-after-write conflict prediction method provided by the embodiments of the present application can accurately predict whether there is a read-after-write conflict by reading the to-be-fired Load instruction, quickly locating the conflict record matched with the Load instruction in the history conflict table by determining the index value of the Load instruction, and processing the conflict by controlling the state of the Load instruction in the Load queue in the case where the read-after-write conflict is detected, which can effectively avoid the entire pipeline stalling or flushing caused by conflict processing and reduce the loss of processor performance.

[0007] In a possible implementation, the read-after-write conflict prediction method provided by the embodiments of the present application further includes: in a case where it is determined that the store buffer of the out-of-order execution processor has the second store instruction and the second store instruction is not completely executed, adding the load instruction to the conflict risk table. The second store instruction is a store instruction located before the load instruction in the instruction queue of the out-of-order execution processor. In a case where it is determined that the second store instruction and the load instruction have address overlap, flushing the current pipeline of the out-of-order execution processor. Storing the instruction information of the load instruction and the instruction information of the second store instruction as a conflict record in the history conflict table. The instruction information of the load instruction includes an index value.

[0008] In a possible implementation, the step of determining that the second store instruction and the load instruction have address overlap includes: in a case where the physical address of the store instruction is obtained, obtaining the physical address of the load instruction. In a case where it is determined that the physical address of the store instruction is partially the same as the physical address of the load instruction, it is determined that the second store instruction and the load instruction have address overlap.

[0009] In a possible implementation, the step of determining that the second store instruction and the load instruction have address overlap includes: in a case where the physical address of the store instruction is not obtained, obtaining the virtual address and the identifier of the load instruction. The identifier includes one or more of the following: an address space identifier and a virtual machine identifier. In a case where it is determined that the virtual address of the store instruction and the virtual address of the load instruction have address overlap, and the identifier of the store instruction is the same as the identifier of the load instruction, it is determined that the second store instruction and the load instruction have address overlap.

[0010] In a possible implementation, the read-after-write conflict prediction method provided by the embodiments of the present application further includes: in a case where it is determined that the store buffer has the second store instruction, the second store instruction has been completely executed, and the second store instruction and the load instruction have address overlap, determining that the data stored by the second store instruction is the execution result of the load instruction. And / or, in a case where it is determined that the store buffer does not have the second store instruction, executing the load instruction.

[0011] In a possible implementation, the history conflict table further includes a counter configured to record, for each index value, the number of times that the load instruction matches the conflict record in the history conflict table after being read. Before the instruction information of the load instruction and the instruction information of the second store instruction are stored in the history conflict table, the method further includes: in a case where it is determined that the number of conflict records in the history conflict table exceeds a threshold value, screening a target conflict record with the least number of times from all the conflict records. Deleting the target conflict record from the history conflict table.

[0012] In a possible implementation, after the load instruction is set to the suspended state, the method further includes: listening to an execution state of the first store instruction. After determining that the execution of the first store instruction ends, it is verified whether there is a real read-after-write conflict between the first store instruction and the load instruction. After determining that there is no real read-after-write conflict, the suspended state of the load instruction is released to continue executing the load instruction.

[0013] In a possible implementation, determining the index value of the load instruction includes: obtaining a program counter value of the load instruction read by the out-of-order processor. A preset bit number of the program counter value is extracted from the program counter value. According to the preset bit number of the program counter value, the index value is determined.

[0014] In a second aspect, an embodiment of the present application provides a read-after-write conflict prediction device, applied to an out-of-order processor, and the device includes: a reading module, a determining module, a setting module, and an executing module.

[0015] The reading module is configured to read a to-be-transmitted load instruction. The load instruction is located in a load queue of the out-of-order processor.

[0016] The determining module is configured to determine an index value of the load instruction. The index value is used to quickly locate a conflict record matched with the load instruction in a history conflict table of the out-of-order processor. The conflict record includes a first store instruction corresponding to the load instruction.

[0017] The setting module is configured to set the load instruction to a suspended state in a case where the history conflict table includes the conflict record corresponding to the index value.

[0018] The executing module is configured to execute the load instruction after the execution of the first store instruction ends.

[0019] In a third aspect, an embodiment of the present application provides a read-after-write conflict prediction device. The read-after-write conflict prediction device has a function of implementing the read-after-write conflict prediction method in the first aspect or any possible implementation manner of the first aspect. The function can be implemented by hardware, or the function can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0020] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium. The computer readable storage medium stores instructions. When the instructions are run on a computer, the computer can execute the read-after-write conflict prediction method in the first aspect or any possible implementation manner of the first aspect.

[0021] In a fifth aspect, the embodiments of the present application provide a computer program product containing instructions, which, when executed on a computer, cause the computer to perform the read-after-write conflict prediction method of the first aspect or any possible implementation manner thereof.

[0022] The technical effects brought by any design manner of the second aspect to the fifth aspect can refer to the technical effects brought by the first aspect or the different possible implementation manners of the first aspect, and will not be described here again. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the specific embodiments of the present application or the prior art, the drawings needed in the description of the specific embodiments or the prior art will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0024] Figure 1 A structural schematic diagram of an out-of-order processor provided by the embodiments of the present application is shown in the figure.

[0025] Figure 2 A flowchart of a read-after-write conflict prediction method provided by the embodiments of the present application is shown in the figure.

[0026] Figure 3 Another flowchart of a read-after-write conflict prediction method provided by the embodiments of the present application is shown in the figure.

[0027] Figure 4 A structural schematic diagram of a read-after-write conflict prediction device provided by the embodiments of the present application is shown in the figure.

[0028] Figure 5 A structural schematic diagram of a read-after-write conflict prediction system provided by the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0029] In order to make the purposes, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application as claimed, but merely represents selected embodiments of the application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0031] In the related art, an out-of-order execution processor improves the instruction throughput and overall performance of the processor by allowing instructions to be executed out of order during execution. Then, the out-of-order execution of instructions introduces complex instruction dependencies, especially the read-after-write conflict problem between load instructions and store instructions.

[0032] Specifically, in the out-of-order execution processor, load instructions are used to read data from memory, and store instructions are used to write data to memory. If a load instruction attempts to read data that has not been written by a store instruction, the load instruction can read incorrect data (e.g., old data or invalid data), causing pipeline flush or stall problems.

[0033] To alleviate the read-after-write conflict problem, the related art usually uses a load prediction technique to predict the address or return value of the load data, identify dependent instructions in advance, and thus predict the occurrence of read-after-write to reduce the sending of pipeline conditions or stalls. However, the prediction scheme of the related art still has significant deficiencies in accuracy, coverage, and hardware overhead.

[0034] Specifically, the related art can predict potential read-after-write conflict problems by analyzing the numerical relationship between load instructions and store instructions. For example, if the value read by the load instruction is the same as the value written by the store instruction, it is predicted that the load instruction may depend on the store instruction. However, this process usually requires maintaining a large number of historical records of load and store data values, which requires additional on-chip storage. At the same time, since the prediction process has no historical data in the initial prediction stage, it cannot cover the process of predicting read-after-write conflict in the initial prediction stage, and the prediction accuracy is low.

[0035] Based on this, the embodiment of the present application provides a read-after-write conflict prediction method, device and equipment applied to an out-of-order execution processor, which comprises reading a to-be-transmitted load instruction. The load instruction is located in a load queue of the out-of-order execution processor. An index value of the load instruction is determined. The index value is used to quickly locate a conflict record matched with the load instruction in a history conflict table of the out-of-order execution processor. The conflict record comprises a first store instruction corresponding to the load instruction. In the case that the conflict record corresponding to the index value exists in the history conflict table, the load instruction is set to a suspended state. After the execution of the first store instruction ends, the load instruction is executed.

[0036] The read-after-write conflict prediction method provided by the embodiment of the present application can accurately predict whether there is a read-after-write conflict at present by reading a to-be-transmitted load instruction, quickly locating a conflict record matched with the load instruction in a history conflict table through determining an index value of the load instruction. Meanwhile, in the case that it is detected that there is a read-after-write conflict, the conflict can be handled by controlling the state of the load instruction in the load queue, so that the entire pipeline stall or flushing caused by conflict handling can be effectively avoided, and the loss of processor performance is reduced.

[0037] The method provided by the embodiment of the present application will be described below in combination with specific drawings.

[0038] In one aspect, the embodiment of the present application provides an out-of-order execution processor. As shown in the figure, the out-of-order execution processor 100 can comprise an address generator 101, a load queue 102, a store buffer 103 and a read-after-write risk predictor 104. Figure 1

[0039] The address generator 101 is configured to receive a load instruction and a store instruction, and convert a virtual address of the load instruction and the store instruction into a physical address.

[0040] Specifically, the address generator 101 can complete the address conversion process by querying a page table. The page table stores the mapping relationship between the virtual address and the physical address. The address generator 101 extracts a virtual page number (VPN) and an offset in the virtual address, maps the virtual page number to a physical page frame number (PFN) by querying the page table, and then combines the physical page frame number and the offset to generate the final physical address. Finally, the address generator 101 provides the generated physical address to the load queue 102 and the store buffer 103, so that they can correctly execute the instructions.

[0041] The load queue 102 is configured to temporarily store the load instruction until the load instruction has an execution condition. Specifically, the load queue 102 not only tracks the state of each load instruction, including the program counter (PC) value and the execution age of the instruction, but also ensures that the instructions are executed in the correct order during the process of storing the load instruction. ​

[0042] A store buffer 103 is configured to temporarily store the store instructions including the target addresses and the store data until the physical addresses of the store instructions are resolved and can be written to the cache or the main memory.

[0043] Specifically, the store buffer 103 receives the physical addresses of the store instructions converted by the address generator and temporarily stores the target addresses and the store data of the store instructions. After the physical addresses of the store instructions are resolved, the store buffer 103 writes the data to the cache or the main memory and tracks the execution status of the store instructions, including the program counter (PC) value and the execution age of the instructions.

[0044] A read-after-write risk predictor 104 is configured to determine the index value of the load instruction and compare it with the historical conflict table to predict a potential read-after-write (RAW) conflict by using the read-after-write conflict prediction method provided in the embodiments of the present application. If a conflict is predicted, the read-after-write risk predictor suspends the load instruction until the dependent store instruction is executed.

[0045] It should be noted that the above Figure 1 The out-of-order processor 100 is only an example of the application scenario of the scheme of the present application and is not a limitation on the application scenario of the scheme of the present application.

[0046] In one aspect, the embodiments of the present application provide a read-after-write conflict prediction method, which can be executed by Figure 1 the out-of-order processor 100 as shown in the figure. As shown in the figure, the method can include the following steps. Figure 2

[0047] S201, reading a load instruction to be emitted.

[0048] The load instruction is located in the load queue of the out-of-order processor. The load instruction can come from the code segment or the data segment of the program, which is not limited by the present application. The load instruction can contain a plurality of instruction information, such as the target register, the source address, the instruction type, the program counter value and the execution age. Each load instruction in the load queue has a state flag indicating the current state of the load instruction, such as to-be-emitted, suspended or executed.

[0049] Specifically, the processor reads the load instruction to be emitted from the load queue.

[0050] S202, determining the index value of the load instruction.

[0051] The index value is used to quickly locate the conflict record matched with the load instruction in the historical conflict table of the out-of-order processor. The historical conflict table is used to record and manage the read-after-write conflict records between the load instructions and the store instructions. The conflict record includes a first store instruction corresponding to the load instruction.​

[0052] Specifically, the history conflict table can store a plurality of conflict records. Each conflict record can record an index value of a load instruction, address information of a store instruction, a counter, a confidence and a valid flag.

[0053] The index value of the load instruction can be determined according to instruction information of the load instruction. The address information of the store instruction can include virtual address information or physical address information of the store instruction. The counter is used to record the number of times that the load instruction corresponding to each index value matches the conflict record in the history conflict table after being read, i.e., the number of times of the conflict between the load instruction and the store instruction. The confidence is used to evaluate the reliability of the prediction, for example, the confidence can be a 2-bit saturating counter. The valid flag is used to mark whether the conflict record is valid.

[0054] It should be noted that the history conflict table can also record other information related to the read-after-write conflict, such as the PC value of the load instruction, the execution age of the load instruction and the execution age of the store instruction, etc. The information recorded in the history conflict table is not limited in the present application.

[0055] Specifically, the process of determining the index value of the load instruction can be obtaining a program counter value of the load instruction read by the out-of-order processor. A preset number of bits of the program counter value is extracted from the program counter value. The index value is determined according to the preset number of bits of the program counter value.

[0056] In a possible implementation, the preset number of bits can include a first preset number of bits and a second preset number of bits. After obtaining the program counter value of the load instruction read by the out-of-order processor, the first preset number of bits of the program counter value and the second preset number of bits of the program counter value are extracted from the program counter value respectively. The first preset number of bits of the program counter value and the second preset number of bits of the program counter value are subjected to an exclusive OR operation to obtain the index value.

[0057] For example, the out-of-order instruction processor extracts the low 12 bits and the high 10 bits of the PC value of the load instruction, and then performs an exclusive OR operation on the two parts of values to generate a hashed PC value (i.e., the index value of the load instruction) with a fixed bit width.

[0058] In another possible implementation, after extracting the preset number of bits of the program counter value from the program counter value, the preset number of bits of the program counter value is taken as the index value.

[0059] For example, the out-of-order instruction processor extracts the low 12 bits of the PC value of the load instruction, and determines the low 12 bits as the index value.

[0060] The process can quickly query the history conflict table by using the partial value of the load instruction PC value as an index value of the load instruction, without complex address resolution or comparison, thereby improving the efficiency of conflict detection and reducing hardware overhead.

[0061] S203, in a case where it is determined that the history conflict table has a conflict record corresponding to the index value, setting the load instruction to a pending state.

[0062] Specifically, the out-of-order execution processor queries the history conflict table using the determined index value of the load instruction. In a case where it is determined that the history conflict table has a conflict record corresponding to the index value of the current load instruction, the out-of-order execution processor sets the state of the load instruction to a pending state. The pending state is used to indicate that the execution of the load instruction is suspended. At this time, the out-of-order execution processor records the pending state of the load instruction and places the load instruction in a pending queue, so as to facilitate subsequent tracking and management of the load instruction in the pending state.

[0063] In one possible implementation, the out-of-order execution processor queries the history conflict table using the determined index value of the load instruction. In a case where the history conflict table has a conflict record matching the index value of the current load instruction, the out-of-order execution processor first detects the validity of the conflict record. In a case where it is determined that the conflict record is valid, the out-of-order execution processor sets the state of the load instruction to a pending state.

[0064] Specifically, the out-of-order execution processor can determine whether the conflict record is valid according to the validity flag of the conflict record in the history conflict table. Meanwhile, the out-of-order execution processor can also detect whether the conflict record is valid by verifying whether the address of the store instruction is associated with the target address of the load instruction.

[0065] For example, the out-of-order execution processor verifies the association between the address of the store instruction and the target address of the load instruction by comparing them. In a case where the address of the store instruction partially or completely matches the target address of the load instruction, or the store instruction and the load instruction belong to the same memory region (for example, the same cache line or the same page), the conflict record is considered valid.

[0066] In this process, the out-of-order execution processor, upon detecting a read-after-write conflict, places the load instruction in a pending state instead of directly performing pipeline flushing, thereby avoiding unnecessary pipeline flushing caused by read-after-write conflicts and reducing the loss of performance of the out-of-order execution processor.

[0067] S204, after the execution of the first store instruction ends, executing the load instruction.

[0068] Specifically, after the load instruction is set to the suspended state, the out-of-order processor continuously monitors the execution state of the first store instruction. After determining that the execution of the first store instruction ends, i.e., the first store address completes physical address resolution, the out-of-order processor determines the specific execution mode of the load instruction according to the relationship between the first store instruction and the load instruction.

[0069] The relationship between the first store instruction and the load instruction can be whether there is a real read-after-write conflict between the first store instruction and the load instruction.

[0070] For example, whether there is a real read-after-write conflict between the first store instruction and the load instruction can be determined by the following method. After the execution of the first store instruction ends, it is detected whether the first store instruction matches the address of the load instruction in the suspended state. If the first store instruction matches the address of the load instruction in the suspended state, it can be determined that there is a real read-after-write conflict between the first store instruction and the load instruction in the suspended state.

[0071] In a possible implementation, after determining that the execution of the first store instruction ends, the out-of-order processor verifies whether there is a real read-after-write conflict between the first store instruction and the load instruction. After determining that there is no real read-after-write conflict between the first store instruction and the load instruction, the suspended state of the load instruction is released to continue executing the load instruction.

[0072] For example, after determining that there is no real read-after-write conflict between the first store instruction and the load instruction, the suspended state of the load instruction is released to continue executing the load instruction. At the same time, this read-after-write conflict prediction is marked as a false prediction, and at this time, the confidence of the conflict record in the history conflict table can be reduced.

[0073] In another possible implementation, after determining that the execution of the first store instruction ends, the out-of-order processor verifies whether there is a real read-after-write conflict between the first store instruction and the load instruction. After determining that there is a real read-after-write conflict between the first store instruction and the load instruction, the load instruction is executed to enable the load instruction to directly read the data stored by the first store instruction.

[0074] Specifically, after determining that there is a real read-after-write conflict between the first store instruction and the load instruction, it can be determined that the data loaded by the load instruction is the data stored by the first store instruction. The suspended state of the load instruction is released, and the load instruction is executed to enable the load instruction to directly read the data stored by the first store instruction.

[0075] The read-after-write conflict prediction method provided by the embodiments of the present application can accurately predict whether a read-after-write conflict exists by reading a to-be-transmitted load instruction, determining an index value of the load instruction, and quickly locating a conflict record matched with the load instruction in a history conflict table. Meanwhile, in the case where a read-after-write conflict is detected, the conflict can be handled by controlling the state of the load instruction in the load queue, so that the entire pipeline can be prevented from being stalled or flushed due to the conflict handling, and the loss of processor performance can be reduced.

[0076] Further, as shown in Figure 3 The method provided by the embodiments of the present application can further include S205-S207. For example, S205-S207 can be executed after S202.

[0077] S205, in the case where it is determined that the reorder execution processor has a second store instruction in the storage buffer and the second store instruction is not completely executed, the load instruction is added to the conflict risk table.

[0078] The second store instruction is a store instruction located before the load instruction in the instruction queue of the reorder execution processor, that is, the second store instruction is a store instruction older than the load instruction, and the number of the second store instructions can be one or more. The conflict risk table is used to record the load instructions that can conflict with the store instruction, so as to facilitate subsequent conflict detection and processing of the reorder execution processor.

[0079] Specifically, in the case where it is determined that the history conflict table does not have a conflict record corresponding to the index value, the reorder execution processor first checks the storage buffer to determine whether there is a second store instruction older than the load instruction. After determining that there is a second store instruction in the storage buffer, the reorder execution processor first verifies the execution state of the second store instruction. In the case where it is determined that the second store instruction is not completely executed, the processor adds the load instruction to the conflict risk table.

[0080] Further, in the case where it is determined that the storage buffer has a second store instruction, the second store instruction has been completely executed, and the second store instruction and the load instruction have address overlap, it is determined that the data stored by the second store instruction is the execution result of the load instruction.

[0081] Still further, in the case where it is determined that the storage buffer does not have a second store instruction, the load instruction is executed.

[0082] S206, in the case where it is determined that the second store instruction and the load instruction have address overlap, the current pipeline of the reorder execution processor is flushed.

[0083] Specifically, after adding the load instruction to the conflict risk table, the out-of-order processor obtains instruction information of the second store instruction and instruction information of the load instruction. According to the instruction information of the second store instruction and the instruction information of the load instruction, it is determined whether the second store instruction and the load instruction have address overlap. In the case where it is determined that the second store instruction and the load instruction have address overlap, the current pipeline of the out-of-order processor is flushed.

[0084] In a possible implementation, the physical address of the load instruction is obtained in the case where the physical address of the store instruction is obtained. In the case where it is determined that the physical address of the store instruction is partially the same as the physical address of the load instruction, it is determined that the second store instruction and the load instruction have address overlap.

[0085] Specifically, after the second store instruction has completely ended, at this time, the physical address of the second store instruction has been resolved, and the out-of-order processor can directly obtain the physical address of the second store instruction. After obtaining the physical address of the second store instruction, the out-of-order processor also obtains the physical address of the load instruction, and compares the physical address of the store instruction with the physical address of the load instruction. In the case where it is determined that the physical address of the store instruction is partially the same as the physical address of the load instruction, it is determined that the second store instruction and the load instruction have address overlap.

[0086] In another possible implementation, the virtual address and the identifier of the load instruction are obtained in the case where the physical address of the store instruction is not obtained. The identifier includes one or more of the following: an address space identifier and a virtual machine identifier. In the case where it is determined that the virtual address of the store instruction is partially the same as the virtual address of the load instruction, and the identifier of the store instruction is the same as the identifier of the load instruction, it is determined that the second store instruction and the load instruction have address overlap.

[0087] Specifically, if the second store instruction is in a state of not completely ending, at this time, the physical address of the second store instruction has not been resolved, and the out-of-order processor obtains the virtual address and the identifier of the second store instruction. Meanwhile, the out-of-order processor obtains the storage address and the identifier of the load instruction, and respectively compares the storage address and the identifier of the second store instruction with the storage address and the identifier of the load instruction. In the case where it is determined that the virtual address of the store instruction is partially the same as the virtual address of the load instruction, and the identifier of the store instruction is the same as the identifier of the load instruction, it is determined that the second store instruction and the load instruction have address overlap.

[0088] S207, the instruction information of the load instruction and the instruction information of the second store instruction are stored as a conflict record in the history conflict table.

[0089] The instruction information of the load instruction includes an index value.

[0090] Specifically, after determining that the second store instruction and the load instruction have address overlap, the out-of-order processor records the dependency relationship between the second store instruction and the load instruction as a conflict record in the history conflict table, so that a load instruction with the same index value as the load instruction can more accurately predict a possible read-after-write conflict in subsequent execution.

[0091] Further, when the instruction information of the load instruction and the instruction information of the second store instruction are stored as a conflict record in the history conflict table, if the number of conflict records in the history conflict table exceeds a threshold value, at least one conflict record can be selected from the history conflict table based on a preset screening rule for deletion, so that the newly created conflict record is stored in the history conflict table.

[0092] In one possible implementation, in a case where the number of conflict records in the history conflict table exceeds a threshold value, a target conflict record with the least number of times is selected from all conflict records. The target conflict record is deleted from the history conflict table.

[0093] In another possible implementation, in a case where the number of conflict records in the history conflict table exceeds a threshold value, a target conflict record is randomly selected from all conflict records. The target conflict record is deleted from the history conflict table.

[0094] The scheme provided by the embodiments of the present application will be described below in conjunction with specific examples.

[0095] For example, a reduced instruction set computer-five (RISC-V) out-of-order processor is taken as an example. In the initial state, the conflict history table of the RISC-V out-of-order processor is empty. At this time, even if there are older store instructions and the physical addresses of these store instructions have not been resolved, all load instructions will be executed normally.

[0096] When a load instruction (the PC value of the load instruction is 0x8000A1B2) is executed in the RISC-V out-of-order processor, a pipeline flush operation is triggered due to a read-after-write conflict. At this time, the RISC-V out-of-order processor obtains the index value (0xA1B2 XOR 0x8000 = 0x21B2) of the PC value of the load instruction by performing an exclusive OR operation on the low 12 bits and the high 10 bits of the PC value. Then, the RISC-V out-of-order processor writes the index value (0x21B2) into the history conflict table, so that subsequent load instructions can query this table to predict potential conflicts.

[0097] When a load instruction with a PC value of 0x8000A1B2 is emitted again, the RISC-V out-of-order processor queries the history table. If the query hits, i.e., a conflict record is found that matches the index value of the load instruction, the RISC-V out-of-order processor considers that there is a read-after-write conflict for this load instruction.

[0098] At this time, in order to avoid potential conflicts leading to incorrect data reading, the RISC-V out-of-order processor will put this load instruction in a pending state until the completion of the physical address resolution of the storage instruction it depends on.

[0099] The above mainly introduces the scheme provided by the embodiments of the application from the perspective of the working principle of the device. It can be understood that, in order to realize the above functions, the read-after-write conflict prediction device comprises corresponding hardware structures and / or software modules for executing various functions. Those skilled in the art should easily realize that, in combination with the algorithm steps of each example described in the embodiments disclosed in the present application, the application can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driven hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0100] The embodiments of the present application can divide the read-after-write conflict prediction device into functional modules according to the above method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be realized in the form of hardware or software functional module.

[0101] It should be noted that the division of modules in the embodiments of the present application is illustrative, and is only a logical functional division. Actual implementation can have another division method. In the case of dividing each functional module according to each function, Figure 4 A possible composition schematic diagram of the read-after-write conflict prediction device involved in the above and embodiments is shown. As Figure 4 shown, the read-after-write conflict prediction device 400 can include a reading module 401, a determination module 402, a setting module 403, and an execution module 404.

[0102] The reading module 401 is configured to support the read-after-write conflict prediction device 400 to perform Figure 2 S201 in the read-after-write conflict prediction method.

[0103] The determination module 402 is configured to support the read-after-write conflict prediction device 400 to perform Figure 2S202 in the schematic read-after-write conflict prediction method.

[0104] The setting module 403 is configured to support the read-after-write conflict prediction apparatus 400 to perform the following operation. Figure 2 S203 in the schematic read-after-write conflict prediction method.

[0105] The execution module 404 is configured to support the read-after-write conflict prediction apparatus 400 to perform the following operation. Figure 2 S204 in the schematic read-after-write conflict prediction method.

[0106] In a possible implementation, the read-after-write conflict prediction apparatus is further configured to add the load instruction to the conflict risk table in a case where it is determined that the store buffer of the out-of-order execution processor has the second store instruction, and the second store instruction is not completely executed. The second store instruction is a store instruction located before the load instruction in the instruction queue of the out-of-order execution processor. In a case where it is determined that the second store instruction and the load instruction have address overlap, the current pipeline of the out-of-order execution processor is flushed. The instruction information of the load instruction and the instruction information of the second store instruction are stored as a conflict record in the history conflict table. The instruction information of the load instruction includes an index value.

[0107] In a possible implementation, the read-after-write conflict prediction apparatus is further configured to, in a case where the physical address of the store instruction is obtained, obtain the physical address of the load instruction. In a case where it is determined that the physical address of the store instruction is partially the same as the physical address of the load instruction, it is determined that the second store instruction and the load instruction have address overlap.

[0108] In a possible implementation, the read-after-write conflict prediction apparatus is further configured to, in a case where the physical address of the store instruction is not obtained, obtain the virtual address and an identifier of the load instruction. The identifier includes one or more of the following: an address space identifier and a virtual machine identifier. In a case where it is determined that the virtual address of the store instruction is the same as the virtual address of the load instruction, and the identifier of the store instruction is the same as the identifier of the load instruction, it is determined that the second store instruction and the load instruction have address overlap.

[0109] In a possible implementation, the read-after-write conflict prediction apparatus is further configured to, in a case where it is determined that the store buffer has the second store instruction, the second store instruction has been completely executed, and the second store instruction and the load instruction have address overlap, determine that the data stored by the second store instruction is the execution result of the load instruction. And / or, in a case where it is determined that the store buffer does not have the second store instruction, the load instruction is executed.

[0110] In a possible implementation, the history conflict table further includes a counter configured to record a number of times that the load instruction corresponding to each index value matches a conflict record in the history conflict table after being read. The read-after-write conflict prediction apparatus is further configured to, in a case where the number of conflict records in the history conflict table exceeds a threshold, filter a target conflict record with the least number of times from all the conflict records. The target conflict record is deleted from the history conflict table.

[0111] In a possible implementation, the read-after-write conflict prediction apparatus is further configured to monitor an execution state of the first store instruction. After determining that the execution of the first store instruction ends, it is verified whether a real read-after-write conflict exists between the first store instruction and the load instruction. In a case where it is determined that no real read-after-write conflict exists, the suspension state of the load instruction is released to continue execution of the load instruction.

[0112] In a possible implementation, the read-after-write conflict prediction apparatus is further configured to obtain a program counter value of the load instruction read by the out-of-order execution processor. A preset number of bits of the program counter value is extracted from the program counter value. The index value is determined according to the preset number of bits of the program counter value.

[0113] It should be noted that all related contents of each step involved in the above method embodiments can be cited to the function description of the corresponding function module, which will not be repeated here.

[0114] The read-after-write conflict prediction apparatus 400 provided by the embodiments of the present application is used for executing the read-after-write conflict prediction method shown in the above Figure 2 or 3, and thus can achieve the same effect as the read-after-write conflict prediction method.

[0115] The embodiments of the present application further provide a read-after-write conflict prediction device, which can execute the read-after-write conflict prediction method and related steps in the above method embodiments.

[0116] The embodiments of the present application further provide a computer readable storage medium, which stores instructions, and the instructions are executed to execute the read-after-write conflict prediction method and related steps in the above method embodiments.

[0117] The embodiments of the present application further provide a computer program product, which, when running on a computer, causes the computer to execute the read-after-write conflict prediction method and related steps in the above method embodiments.

[0118] In some embodiments, the method shown in the present application can be implemented as computer program instructions encoded in a machine-readable storage medium in a machine-readable format or encoded in other non-transitory media or articles.

[0119] The embodiments of the present application further provide a read-after-write conflict prediction system 500, as shown in the aboveFigure 5 As shown in the figure, the read-after-write conflict prediction system 500 includes at least one processor 501 and at least one interface circuit 502.

[0120] As an example, when the read-after-write conflict prediction system 500 includes one processor and one interface circuit, the one processor can be Figure 5 the processor 501 shown in the solid line box (or the processor 501 shown in the dashed line box), and the one interface circuit can be Figure 5 the interface circuit 502 shown in the solid line box (or the interface circuit 502 shown in the dashed line box). When the read-after-write conflict prediction system 500 includes two processors and two interface circuits, the two processors include Figure 5 the processor 501 shown in the solid line box and the processor 501 shown in the dashed line box, and the two interface circuits include Figure 5 the interface circuit 502 shown in the solid line box and the interface circuit 502 shown in the dashed line box. No limitation is made in this regard.

[0121] The processor 501 and the interface circuit 502 can be interconnected through a line. For example, the interface circuit 502 can be used to receive a signal. As another example, the interface circuit 502 can be used to send a signal to other devices (such as the processor 501). For example, the interface circuit 502 can read computer instructions stored in a memory and send the computer instructions to the processor 501. The processor 501 executes the instructions and, in combination with input and output devices, implements various steps in the above embodiments, such as implementing Figure 2 or Figure 3 any of the method embodiments shown in the solid line box or the dashed line box. Of course, the read-after-write conflict prediction system can also include other discrete devices, and the embodiments of the present application do not make specific limitations in this regard.

[0122] From the above description of the embodiments, those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional modules is taken as an example for illustration, and in actual application, the above functions can be completed by different functional modules according to needs, i.e., the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0123] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are merely illustrative, for example, the division of the modules or units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another apparatus, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical, mechanical or other forms.

[0124] The units described as separate components can or can not be physically separate, and the components shown as units can be one physical unit or a plurality of physical units, that is, can be located in one place, or can be distributed to a plurality of different places. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0125] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0126] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product in essence or the part that contributes or the whole or part of the technical solutions. The software product is stored in a storage medium, and includes a plurality of instructions for causing an apparatus (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various storage program codes.

[0127] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A read-after-write conflict prediction method, characterized in that, Applied to out-of-order execution processors, the method includes: Read the load instruction to be launched; the load instruction is located in the load queue of the out-of-order execution processor; The index value of the load instruction is determined; the index value is used to quickly locate the conflict record matching the load instruction in the history conflict table of the out-of-order execution processor; the conflict record includes a first stored instruction corresponding to the load instruction; If it is determined that a conflict record corresponding to the index value exists in the historical conflict table, the loading instruction is set to a suspended state; After the first storage instruction is executed, the load instruction is executed; The method further includes: if it is determined that there is a second stored instruction in the storage buffer of the out-of-order execution processor, and the second stored instruction has not been fully executed, adding the load instruction to the conflict risk table; the second stored instruction is a stored instruction in the instruction queue of the out-of-order execution processor that is located before the load instruction; If the physical address of the storage instruction is obtained, then the physical address of the load instruction is obtained; If it is determined that the physical address of the storage instruction is partially the same as the physical address of the load instruction, it is determined that the second storage instruction and the load instruction have address overlap. If it is determined that the second store instruction and the load instruction have overlapping addresses, the current pipeline of the out-of-order execution processor is flushed. The instruction information of the loading instruction and the instruction information of the second storage instruction are stored as a conflict record in the historical conflict table; the instruction information of the loading instruction includes the index value.

2. The method according to claim 1, characterized in that, The step of determining that the second storage instruction and the load instruction have overlapping addresses includes: If the physical address of the storage instruction is not obtained, the virtual address and identifier of the load instruction are obtained; the identifier includes one or more of the following: address space identifier and virtual machine identifier; If it is determined that the virtual address of the storage instruction overlaps with the virtual address of the load instruction, and the identifier of the storage instruction is the same as the identifier of the load instruction, then it is determined that the second storage instruction and the load instruction have overlapping addresses.

3. The method according to claim 1, characterized in that, The method further includes: If it is determined that the storage buffer contains the second storage instruction, the second storage instruction has been fully executed, and the second storage instruction overlaps with the load instruction in terms of address, then the data stored in the second storage instruction is determined to be the execution result of the load instruction. And / or, if it is determined that the second storage instruction does not exist in the storage buffer, the load instruction is executed.

4. The method according to claim 1, characterized in that, The historical conflict table also includes a counter, which is used to record the number of times the loading instruction corresponding to each index value matches the conflict record in the historical conflict table after being read; Before storing the instruction information of the load instruction and the instruction information of the second storage instruction into the historical conflict table, the method further includes: If the number of conflict records in the historical conflict table exceeds a threshold, the target conflict record with the fewest occurrences is selected from all conflict records. The target conflict record is deleted from the historical conflict table.

5. The method according to claim 1, characterized in that, After setting the load instruction to a suspended state, the method further includes: Monitor the execution status of the first storage instruction; After the execution of the first storage instruction is completed, verify whether there is a real read-write conflict between the first storage instruction and the load instruction; Once it is determined that there is no real read-write conflict, the suspended state of the load instruction is released so that the load instruction can continue to be executed.

6. The method according to claim 1, characterized in that, Determining the index value of the load instruction includes: Obtain the program counter value of the load instruction read by the out-of-order execution processor; Extract a program counter value with a preset number of bits from the program counter value; The index value is determined based on the program counter value with a preset number of bits.

7. A read-after-write conflict prediction device, characterized in that, The apparatus, used in an out-of-order execution processor, comprises: A reading module is used to read the load instruction to be launched; the load instruction is located in the load queue of the out-of-order execution processor; A determination module is used to determine the index value of the load instruction; the index value is used to quickly locate the conflict record matching the load instruction in the out-of-order execution processor's history conflict table; the conflict record includes a first stored instruction corresponding to the load instruction; The setting module is used to set the loading instruction to a suspended state when it is determined that there is a conflict record corresponding to the index value in the historical conflict table; An execution module is configured to execute the load instruction after the first storage instruction has been executed; The determining module is further configured to, if it is determined that a second stored instruction exists in the storage buffer of the out-of-order execution processor and the second stored instruction has not been fully executed, add the load instruction to the conflict risk table; the second stored instruction is a stored instruction in the instruction queue of the out-of-order execution processor that precedes the load instruction; if the physical address of the stored instruction is obtained, obtain the physical address of the load instruction; if it is determined that the physical address of the stored instruction is partially the same as the physical address of the load instruction, determine that the second stored instruction and the load instruction have address overlap; if it is determined that the second stored instruction and the load instruction have address overlap, flush the current pipeline of the out-of-order execution processor; store the instruction information of the load instruction and the instruction information of the second stored instruction as a conflict record in the historical conflict table; the instruction information of the load instruction includes the index value.

8. A read-write conflict prediction device, characterized in that, The read-after-write conflict prediction device includes a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, and the processor executing the machine-executable instructions to implement the read-after-write conflict prediction method according to any one of claims 1 to 6.

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