Data access method, device and system

Abstract

The invention relates to a data access method, device and system, and relates to the technical field of electronics. The method comprises the following steps: a first processing node in a plurality of processing nodes obtains an access permission of a shared storage space in a storage node through a spin lock; the plurality of processing nodes are used for accessing the shared storage space through the spin lock; the first processing node indicates the management node and / or at least one second processing node in the plurality of processing nodes to stop sending a first access request to the first processing node, the first access request is used for requesting to access the shared storage space, and the management node is used for managing access of the plurality of processing nodes to the shared storage space; and the first processing node accesses the shared storage space according to the access permission. Therefore, the bus transmission efficiency can be optimized.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic technology, and in particular to a data access method, device, and system. Background Art

[0002] Symmetric multi-processing (SMP) technology involves integrating multiple processors on a single computer, sharing the same memory and bus architecture. With the development of SMP technology, more processors can be used to execute programs in parallel. Data variables between threads running on multiple processors can be synchronized using locks.

[0003] Taking a spin lock as an example, when a thread needs to access shared storage space, it can acquire the spin lock for the access operation, thereby obtaining access rights to the shared storage space. When the thread acquires the spin lock, other threads that need to access the shared storage space will also attempt to grab the lock. Since the thread has already acquired the spin lock, other threads fail to grab the lock. The thread that fails to grab the lock will enter a polling loop state, continuously trying to grab the lock until the lock is released. Since the thread that fails to grab the lock constantly attempts to grab the lock, the bus will be blocked for messages with the same address. Therefore, the existing technology has the problem of low bus transmission efficiency. Summary of the Invention

[0004] The embodiments of the present application provide a data access method, device, and system, which solve the problem of low bus transmission efficiency in the prior art.

[0005] To achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, a data access method is provided. The method includes: a first processing node among multiple processing nodes obtains access rights to a shared storage space in a storage node through a spin lock; the multiple processing nodes are configured to access the shared storage space through the spin lock. The first processing node instructs a management node and / or at least one second processing node among the multiple processing nodes to stop sending a first access request to the first processing node, the first access request being used to request access to the shared storage space; the management node is configured to manage access to the shared storage space by the multiple processing nodes. The first processing node accesses the shared storage space based on the access rights.

[0007] In the above technical solution, when the first processing node obtains access to the shared storage space through a spin lock, the first processing node instructs the management node and / or at least one second processing node to stop sending first access requests. This reduces the number of first access requests continuously sent to the first processing node on the bus, and only adds a single instruction process to each node, thereby reducing request storms on the bus. Furthermore, the number of first access requests transmitted to the first processing node address is reduced, and only instructions for different node addresses are added, thereby alleviating the problem of bus congestion caused by messages with the same address. Therefore, bus transmission efficiency can be improved.

[0008] In a possible implementation of the first aspect, the first processing node instructs the management node and / or at least one second processing node among the multiple processing nodes to stop sending the first access request to the first processing node, including: the first processing node sends a first indication message to the at least one second processing node, and the first indication message is used to instruct the at least one second processing node to stop sending the first access request to the management node. In the above possible implementation, at least one second processing node stops sending the first access request, the management node will not receive the first access request, and will not forward the first access request to the first processing node. The first processing node can directly instruct at least one second processing node to stop sending the first access request without going through the management node. In this way, the delay is smaller, the processing overhead of the management node is smaller, and the amount of information on the bus is smaller.

[0009] In a possible implementation of the first aspect, the first processing node instructs the management node and / or at least one second processing node among the plurality of processing nodes to stop sending the first access request to the first processing node, including: the first processing node sends first indication information to the management node, where the first indication information is used to instruct the management node to stop sending the first access request to the first processing node. In the above possible implementation, the first processing node instructs the management node to stop sending the first access request to the first processing node. Even if the management node receives the first access request from at least one second processing node, it will not send the first access request to the first processing node. The first processing node only instructs the management node, and the processing overhead of the first processing node is relatively small.

[0010] In a possible implementation of the first aspect, the first processing node instructs the management node and / or at least one second processing node among the multiple processing nodes to stop sending the first access request to the first processing node. The method also includes: the first processing node receives at least one second access request from the management node, and the second access request is used to request access to the shared storage space. In the above possible implementation, the first processing node sends the first indication information after receiving the second access request from the management node. On the one hand, the first processing node can determine the second processing node that has a shared storage space access requirement based on the second access request. On the other hand, it can avoid the first processing node instructing at least one second processing node when there is no second processing node that needs to access the shared storage space, thereby avoiding unnecessary processing. In this way, bus transmission resources can be saved.

[0011] In a possible implementation of the first aspect, the first processing node instructs the management node and / or at least one second processing node among the multiple processing nodes to stop sending the first access request to the first processing node, including: when the number of at least one second access request reaches a preset number, the first processing node instructs the management node and / or at least one second processing node among the multiple processing nodes to stop sending the first access request to the first processing node. In the above possible implementation, when the number of second access requests is small, the pressure on the bus transmission request is not large. At this time, the first processing node does not need to instruct the management node and / or at least one second processing node to stop sending the first access request to the first processing node. When the number of second access requests reaches a preset number, the pressure on the bus transmission request is relatively large. Only then does the first processing node give an instruction. In this way, the processing overhead of the first processing node can be reduced.

[0012] In a possible implementation of the first aspect, the method further includes: the first processing node sends at least one data to at least one second processing node and / or management node, and the at least one data is data accessed by at least one second access request. In the above possible implementation, on the one hand, the first processing node actively sends data. Even if at least one second processing node and / or management node stops sending the first access request, the second processing node that needs to access the shared storage space can also obtain the required data. This can provide a basis for optimizing bus transmission efficiency. On the other hand, the first processing node can send data in parallel. In this way, there will be no situation where the second processing node needs to wait, and the delay of serial processing of access requests from multiple second processing nodes in the queue can be reduced, thereby improving the efficiency of synchronizing data between producers and multiple consumers.

[0013] In a possible implementation of the first aspect, the method further includes: after the first processing node releases the spin lock, the first processing node instructs the management node and / or at least one second processing node to send a first access request to the first processing node. In the above possible implementation, the first processing node actively instructs at least one second processing node and / or management node to start sending the first access request. Even if at least one second processing node and / or management node stops sending the first access request, the second processing node that needs to access the shared storage space can continue to grab the lock after the spin lock is released. This can provide a basis for optimizing bus transmission efficiency.

[0014] In a second aspect, a data access method is provided. The method includes: a management node determining that a first processing node among multiple processing nodes obtains access rights to a shared storage space in a storage node; the management node is configured to manage access to the shared storage space by the multiple processing nodes; and the multiple processing nodes are configured to access the shared storage space in the storage node using a spin lock. Under instruction from the first processing node, the management node stops sending a first access request from at least one second processing node among the multiple processing nodes to the first processing node, the first access request being for access to the shared storage space.

[0015] In the above technical solution, the management node, under the instruction of the first processing node, stops sending first access requests to the first processing node. This reduces the number of first access requests continuously sent to the first processing node on the bus, and only increases the instruction process to the management node. This can reduce request storms on the bus. Furthermore, the number of first access requests transmitted to the first processing node address is reduced, which can alleviate the problem of bus congestion caused by messages with the same address. Therefore, bus transmission efficiency can be improved.

[0016] In a possible implementation of the second aspect, at the instruction of the first processing node, the management node stops sending a first access request from at least one second processing node among the multiple processing nodes to the first processing node, including: the management node receives first instruction information from the first processing node. In response to the first instruction information, the management node stops sending the first access request to the first processing node. In this possible implementation, instructing the management node to stop sending the first access request to the first processing node through the first instruction information provides a basis for improving bus transmission efficiency.

[0017] In one possible implementation of the second aspect, the method further includes: the management node, under the instruction of the first processing node, instructing at least one second processing node to stop sending first access requests to the management node. In the above possible implementation, the management node instructs the second processing node to stop sending first access requests to the management node. This further reduces the number of first access requests sent by at least one second processing node to the management node. In this way, request storms on the bus can be reduced and the problem of bus congestion caused by same-address messages can be alleviated. Therefore, bus transmission efficiency can be improved.

[0018] In a possible implementation of the second aspect, before the management node stops sending a first access request from at least one second processing node among a plurality of processing nodes to the first processing node under the instruction of the first processing node, the method further includes: the management node receives at least one second access request from at least one second processing node, and the second access request is used to request access to a shared storage space. The management node sends at least one second access request to the first processing node. In the above possible implementation, after the management node sends the second access request to the first processing node, the first processing node instructs at least one second processing node and / or the management node to stop sending the first access request. On the one hand, the first processing node and / or the management node can determine the second processing node that has a shared storage space access requirement based on the second access request. On the other hand, it can avoid the first processing node also giving an instruction when there is no second processing node that needs to access the shared storage space, thereby causing unnecessary processing. This can save bus transmission resources.

[0019] In a possible implementation of the second aspect, the method further includes: when the management node receives at least one second access request, it determines that the first processing node is a producer. Under the instruction of the first processing node, the management node stops sending the first access request from at least one second processing node among the multiple processing nodes to the first processing node, including: when the management node determines that the first processing node is a producer, under the instruction of the first processing node, it stops sending the first access request to the first processing node. In the above possible implementation, the management node determines that the first processing node is a consumer, so that the management node can know that the instruction of the first processing node is to stop sending the first access request. This can provide a basis for improving bus transmission efficiency.

[0020] In a possible implementation of the second aspect, the method further includes: the management node receives at least one data from the first processing node, and the at least one data is data accessed by at least one second access request. The management node sends at least one data to at least one second processing node. In the above possible implementation, on the one hand, the first processing node actively sends data. Even if at least one second processing node and / or the management node stops sending the first access request, the second processing node that needs to access the shared storage space can also obtain the required data. This can provide a basis for optimizing bus transmission efficiency. On the other hand, the management node can send data to multiple second processing nodes in parallel. In this way, there will be no situation where the second processing node needs to wait, and the delay of serial processing of access requests from multiple second processing nodes in the queue can be reduced, thereby improving the efficiency of synchronizing data between producers and multiple consumers.

[0021] In a possible implementation of the second aspect, the method further includes: the management node obtains the correspondence between each second processing node in at least one second processing node and each data in at least one data. The management node sends at least one data to at least one second processing node, including: the management node sends the corresponding data to each second processing node in at least one second processing node according to the correspondence. In the above possible implementation, the management node records the correspondence between each second processing node and the required data. According to the correspondence, when the management node receives the data actively sent by the first processing node, it can send the required data to each second processing node in parallel. Therefore, the delay of serial processing of access requests of multiple second processing nodes in the queue can be reduced, thereby improving the efficiency of data synchronization between producers and multiple consumers.

[0022] In a possible implementation of the second aspect, the method further includes: the management node, under the instruction of the first processing node, sending a first access request to the first processing node. In the above possible implementation, the management node begins sending the first access request under the instruction of the first processing node. Even if at least one second processing node and / or the management node stops sending the first access request, the second processing node that needs to access the shared memory space can continue to grab the lock after the spin lock is released. This provides a basis for optimizing bus transmission efficiency.

[0023] In a possible implementation of the second aspect, the method further includes: the management node, under the instruction of the first processing node, instructing at least one second processing node to send a first access request to the management node. In the above possible implementation, the management node instructs the second processing node to send the first access request to the management node. Even if at least one second processing node and / or the management node stops sending the first access request, the second processing node that needs to access the shared memory space can continue to grab the lock after the spin lock is released. This provides a basis for optimizing bus transmission efficiency.

[0024] In a third aspect, a data access method is provided. The method includes: a second processing node among multiple processing nodes, under the instruction of a management node and / or a first processing node among the multiple processing nodes, stops sending a first access request to the management node; the multiple processing nodes are configured to access a shared storage space in a storage node through a spin lock; the first processing node is a node that obtains access rights to the shared storage space through the spin lock; and the management node is configured to manage access to the shared storage space by the multiple processing nodes.

[0025] In the above technical solution, when the first processing node obtains access rights to the shared storage space through a spin lock, the second processing node stops sending the first access request to the first processing node according to the instructions of the first processing node and / or the management node. The continuous sending of the first access request to the first processing node and / or the management node on the bus is reduced, and only one instruction process to the second processing node is added, which can reduce the request storm on the bus. In addition, the first access request transmitted to the address of the first processing node is reduced, and only the instruction process to the address of the second processing node is added, which can alleviate the problem of bus congestion caused by the same address message. Therefore, the bus transmission efficiency can be improved.

[0026] In a possible implementation of the third aspect, a second processing node among multiple processing nodes stops sending a first access request to a first processing node under the instruction of a management node and / or a first processing node among multiple processing nodes, including: the second processing node receives first instruction information from the first processing node and / or the management node. The second processing node stops sending the first access request to the management node in response to the first instruction information. In the above possible implementation, at least one second processing node stops sending the first access request, and the management node will not receive the first access request and will not forward the first access request to the first processing node. In this way, bus transmission efficiency can be improved.

[0027] In a possible implementation of the third aspect, before the second processing node among the multiple processing nodes stops sending the first access request to the first processing node under the instruction of the management node and / or the first processing node among the multiple processing nodes, the method also includes: the second processing node sends a second access request to the management node, and the second access request is used to request access to the shared storage space. In the above possible implementation, after the second processing node sends the second access request to the management node, the first processing node and / or the management node instructs the second processing node to stop sending the first access request to the first processing node. On the one hand, the first processing node and / or the management node can determine the second processing node that has a shared storage space access requirement based on the second access request. On the other hand, it can avoid the first processing node also giving an instruction when there is no second processing node that needs to access the shared storage space, thereby causing unnecessary information transmission. This can save bus transmission resources.

[0028] In a possible implementation of the third aspect, the method further includes: the second processing node receives data from the first processing node and / or the management node, and the data is the data accessed by the second access request. In the above possible implementation, on the one hand, the first processing node actively sends data. Even if at least one second processing node and / or the management node stops sending the first access request, the second processing node that needs to access the shared storage space can also obtain the required data. This can provide a basis for optimizing bus transmission efficiency. On the other hand, multiple second processing nodes can receive data in parallel. In this way, there will be no situation where the second processing node needs to wait, and the delay of serial processing of access requests from multiple second processing nodes in the queue can be reduced, thereby improving the efficiency of synchronizing data between producers and multiple consumers.

[0029] In a possible implementation of the third aspect, the method further includes: the second processing node sends a first access request to the management node under the instruction of the first processing node and / or the management node. In the above possible implementation, the second processing node starts sending the first access request under the instruction of the first processing node and / or the management node. Even if at least one second processing node and / or the management node stops sending the first access request, the second processing node that needs to access the shared memory space can continue to grab the lock after the spin lock is released. This can provide a basis for optimizing bus transmission efficiency.

[0030] In a fourth aspect, a data access device is provided. The device includes multiple processing modules, a storage module, and a control module. A first processing module among the multiple processing modules is configured to obtain access rights to a shared storage space through a spin lock. The multiple processing modules are configured to access the shared storage space in the storage module through a spin lock. The first processing module is further configured to instruct the control module and / or at least one second processing module among the multiple processing modules to stop sending a first access request to the first processing module, wherein the first access request is configured to request access to the shared storage space, and the management node is configured to manage access to the shared storage space by multiple processing nodes. The first processing module is further configured to access the shared storage space based on the access rights.

[0031] In a possible implementation of the fourth aspect, the first processing module is specifically used to send first indication information to at least one second processing module, and the first indication information is used to instruct the at least one second processing module to stop sending the first access request to the control module.

[0032] In a possible implementation manner of the fourth aspect, the first processing module is specifically configured to send first indication information to the control module, where the first indication information is configured to instruct the control module to stop sending the first access request to the first processing module.

[0033] In a possible implementation manner of the fourth aspect, the first processing module is further configured to receive at least one second access request from the control module, where the second access request is used to request access to the shared storage space.

[0034] In a possible implementation of the fourth aspect, the first processing module is specifically used to instruct the control module and / or at least one second processing module to stop sending the first access request to the first processing node when the number of at least one second access request reaches a preset number.

[0035] In a possible implementation manner of the fourth aspect, the first processing module is further used to send at least one data to the control module and / or at least one second processing module, where the at least one data is data accessed by at least one second access request.

[0036] In a possible implementation manner of the fourth aspect, the first processing module is further configured to, after releasing the spin lock, instruct the control module and / or at least one second processing module to send a first access request to the first processing module.

[0037] In a fifth aspect, a data access device is provided. The device includes multiple processing modules, a storage module, and a control module. The control module is configured to determine whether a first processing module among the multiple processing modules has access rights to a shared storage space in the storage module; the control module is configured to manage access to the shared storage space by the multiple processing modules; and the multiple processing modules are configured to access the shared storage space using a spin lock. The control module is configured to, under the direction of the first processing module, stop sending a first access request from a second processing module among the multiple processing modules to the first processing module, the first access request being used to request access to the shared storage space.

[0038] In a possible implementation manner of the fifth aspect, the control module is specifically configured to receive first indication information from the first processing module; and in response to the first indication information, stop sending the first access request to the first processing module.

[0039] In a possible implementation manner of the fifth aspect, the control module is further configured to, under the instruction of the first processing module, instruct at least one second processing module to stop sending the first access request to the control module.

[0040] In a possible implementation of the fifth aspect, the control module is further configured to receive at least one second access request from at least one second processing module. The second access request is for requesting access to the shared storage space. The control module is further configured to send the at least one second access request to the first processing module.

[0041] In a possible implementation of the fifth aspect, the control module is further configured to, upon receiving at least one second access request, determine that the first processing module is a producer. Specifically, the control module is configured to, upon determining that the first processing module is a producer, stop sending the first access request to the first processing module under the instruction of the first processing module.

[0042] In a possible implementation of the fifth aspect, the control module is further configured to receive at least one data item from the first processing module. The at least one data item is data accessed by at least one second access request. The control module is further configured to send the at least one data item to the at least one second processing module.

[0043] In a possible implementation of the fifth aspect, the control module is further configured to obtain a correspondence between each second processing module in the at least one second processing module and each piece of data in the at least one piece of data. The control module is specifically configured to send the corresponding data to each second processing module in the at least one second processing module based on the correspondence.

[0044] In a possible implementation manner of the fifth aspect, the control module is further configured to send a first access request to the first processing module under the instruction of the first processing module.

[0045] In a possible implementation manner of the fifth aspect, the control module is further configured to, under the instruction of the first processing module, instruct at least one second processing node to send a first access request to the management node.

[0046] In a sixth aspect, a data access device is provided. The device includes multiple processing modules, a storage module, and a control module. Under the instruction of the control module and / or the first processing module, a second processing module among the multiple processing modules stops sending a first access request to the control module. The multiple processing modules are configured to access shared storage space in the storage module through a spin lock. The first processing module is a module that obtains access rights to the shared storage space through the spin lock. The control module is configured to manage access to the shared storage space by the multiple processing modules.

[0047] In a possible implementation manner of the sixth aspect, the second processing module is specifically used to receive first indication information from the first processing module and / or the control module; and in response to the first indication information, stop sending the first access request to the control module.

[0048] In a possible implementation of the sixth aspect, the second processing module is also used to send a second access request to the control module before stopping sending the first access request to the control module under the instruction of the control module and / or the first processing module among the multiple processing modules, and the second access request is used to request access to the shared storage space.

[0049] In a possible implementation manner of the sixth aspect, the second processing module is further configured to receive data from the first processing module and / or the control module, where the data is data accessed by the second access request.

[0050] In a possible implementation manner of the sixth aspect, the second processing module is further configured to send a first access request to the control module under the instruction of the first processing module and / or the control module.

[0051] In a seventh aspect, a data access system is provided. The system includes multiple processing nodes, storage nodes, and management nodes according to the method provided in the first aspect, any possible implementation of the first aspect, the second aspect, any possible implementation of the second aspect, the third aspect, or any possible implementation of the third aspect. The system is used to implement the method provided in the first aspect, any possible implementation of the first aspect, the second aspect, any possible implementation of the second aspect, the third aspect, or any possible implementation of the third aspect.

[0052] In an eighth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores program code. The program code can be invoked by a processor to implement the method provided by the first aspect, any possible implementation of the first aspect, the second aspect, any possible implementation of the second aspect, or the third aspect or any possible implementation of the third aspect.

[0053] In a ninth aspect, a computer program product is provided. When the computer program product is executed on a computer, the computer is caused to perform the method provided by the first aspect, any possible implementation of the first aspect, the second aspect, any possible implementation of the second aspect, or the third aspect or any possible implementation of the third aspect.

[0054] It can be understood that any of the data access devices, systems, computer storage media or computer program products provided above are used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic diagram of the structure of a system on a chip provided in an embodiment of the present application;

[0056] Figure 2 A schematic diagram of the structure of a data access system provided in an embodiment of the present application;

[0057] Figure 3 A schematic diagram of a data access method provided in an embodiment of the present application Figure 1 ;

[0058] Figure 4 A schematic diagram of a data access method provided in an embodiment of the present application Figure 2 ;

[0059] Figure 5 A schematic diagram of a data access method provided in an embodiment of the present application Figure 3 ;

[0060] Figure 6 A schematic diagram of a data access method provided in an embodiment of the present application Figure 4 ;

[0061] Figure 7 A schematic diagram of a data access method provided in an embodiment of the present application Figure 5 ;

[0062] Figure 8 A schematic diagram of a data access method provided in an embodiment of the present application Figure 6 ;

[0063] Figure 9 A schematic diagram of a data access method provided in an embodiment of the present application Figure 7 ;

[0064] Figure 10 A schematic diagram of a data access method provided in an embodiment of the present application Figure 8 ;

[0065] Figure 11 A schematic diagram of a data access device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] The terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0067] The terms "exemplary" or "for example" in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0068] The terms "coupling" and "connection" involved in the embodiments of this application should be understood in a broad sense. For example, they may refer to a physical direct connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0069] Before introducing the specific contents of the embodiments of the present application, the relevant technical terms of the embodiments of the present application are first introduced.

[0070] 1. Processor core, single-core processor and multi-core processor

[0071] A processor core refers to the core circuitry of a processor, excluding the packaging and auxiliary circuitry (such as pin interface circuitry, power supply circuitry, and clock circuitry). The processor core circuitry performs control and information processing functions. For example, a processor core reads instructions from the processor's internal memory and executes the control and computing tasks specified by those instructions. A processor core may be referred to as a processor core or simply a core.

[0072] A single-core processor is one that integrates a single processor core and associated supporting circuitry. A multi-core processor is one that integrates multiple processor cores and associated supporting circuitry. Multi-core processors typically include more supporting circuitry than single-core processors to facilitate communication and coordination between the multiple processor cores. Like single-core processors, multi-core processors can handle single-threaded tasks, but they can break down tasks and run them simultaneously across multiple cores to increase processing speed.

[0073] 2. Shared storage space

[0074] Shared memory space refers to the memory space that can be accessed by multiple processors (or processor cores). Figure 1 As shown, a system on chip (SOC) 100 includes two processor clusters, a multi-level cache, a memory controller 110, and memory 120. One cluster includes a first processor 131 and a second processor 132, and the other cluster includes a third processor 133 and a fourth processor. The multi-level cache may include a first-level cache, a second-level cache, and a third-level cache. The first-level cache includes: L1-first cache 141, L1-second cache 142, L1-third cache 143, and L1-fourth cache 144. The second-level cache includes: L2-fifth cache 145 and L2-sixth cache 146. The third-level cache includes: L3-seventh cache 147. Figure 1 For example only, the embodiments of the present application do not limit the number of processor clusters, the number of processors in each cluster, the number of cache levels, and the number of caches in each cache level.

[0075] Exemplarily, since the processor accesses the memory 120 at a slow speed, a cache is provided between the processor and the memory 120 to increase the access rate. The memory controller 110 is used to manage access operations to data in the memory 120. The first-level cache is located inside the processor. For example, the L1-first cache 141 is located inside the first processor 131 and is used by the first processor 131 to cache data. Other processors cannot access the L1-first cache 141. The second-level cache and the third-level cache are located outside the processor. All processors in the same cluster share one cache in the second-level cache. All processors in different clusters share the third-level cache. The third-level cache is coupled to the memory controller 110 and the memory 120 via a bus. For example, the first processor 131 and the second processor 132 belonging to the same cluster share the L2-fifth cache 145, and the third processor 133 and the fourth processor 134 belonging to the same cluster share the L2-sixth cache 146. The first processor 131, the second processor 132, the third processor 133 and the fourth processor 134 share the L3-seventh cache 147. Exemplarily, the shared storage space may refer to Figure 1 The second level cache, the third level cache and the storage space in the memory 120.

[0076] 3. Lock

[0077] A lock ensures that only one thread accesses the shared memory space corresponding to the lock at any given time. Access operations can include writes, reads, or other operations. Locks are used in scenarios where threads running on multiple processors (or processor cores) access data variables in a shared memory space. For example, if one thread needs to write to a data variable and a second thread needs to read from the data variable, the two threads cannot perform the required access operations simultaneously. To ensure data variable synchronization between multiple threads, the first thread must write to the shared memory space before the second thread can read from the shared memory space. A lock variable can be written to a specific address in the shared memory space to ensure data variable synchronization between multiple threads. For example, if the lock variable is 0, the lock has not been acquired by any thread. The first thread can change the lock variable to 1 to acquire the lock. The first thread can also change the lock variable to 0 to release the lock. By acquiring the lock (also known as grabbing the lock or locking), the first thread obtains access to the shared memory space. If the first thread acquires the lock, the second thread cannot acquire the lock and therefore cannot obtain access to the shared memory space. After the first thread releases the lock, the second thread can acquire the lock and thus obtain access to the shared storage space, thus ensuring data variable synchronization between multiple threads.

[0078] The following examples illustrate this concept using mutexes and spin locks. When a thread needs to access shared memory, it acquires the mutex lock for that access operation, thereby gaining access to the shared memory. Once the thread has acquired the mutex, other threads that need to access the shared memory will also attempt to grab the lock. Because the thread already has the mutex, the other threads fail to grab the lock. The thread that failed to grab the lock enters the sleep state. After the thread releases the mutex, the sleeping thread is awakened. Because context switching between sleep and wakeup can cause performance loss, if the mutex lock duration is short, the context switching time between sleep and wakeup can account for a significant portion of the entire lock acquisition process. This results in a significant time overhead in the lock acquisition process.

[0079] Spin locks are often used in scenarios where lock durations are short. When a thread needs to access shared storage, it acquires a spin lock for that access operation, thereby gaining access to the shared storage. Once the thread has acquired the spin lock, other threads that need to access the shared storage will also attempt to retake the lock. Because the thread has already acquired the spin lock, other threads fail to retake the lock. Unlike mutex locks, threads that fail to retake the lock enter a polling loop. Threads in this loop continuously attempt to retake the lock until the lock is released. This continuous retry by threads that fail to retake the lock can cause bus request storms and blockage of messages with the same address on the bus. This results in low bus efficiency.

[0080] 4. MESI consistency protocol

[0081] In the MESI consistency protocol, the data in the cache corresponding to the processor (or processor core) has four consistency states: modify (modify, M) state, exclusive (exclusive, E) state, share (share, S) state and invalid (invalid, I) state. For example, the data in the cache corresponding to the processor (or processor core) can be: the data in a cache line (cache line) of the first-level cache, second-level cache or third-level cache corresponding to the processor (or the processor core). These states can be marked on the cache line and can also be marked on the home node (home node). For example Figure 1As shown, the memory controller 110 may include a home agent (not shown in the figure). The home agent is used to implement access operations to the memory 120. For example, for data in the first-level cache (e.g., L1-first cache 141), the HN may be the corresponding second-level cache (e.g., L2-fifth cache 145). For data in the second-level cache (e.g., L2-fifth cache 145), the HN may be the corresponding third-level cache (e.g., L3-seventh cache 147). For data in the third-level cache, the HN may be the HA. The HN has a directory, which is used to manage the consistency state.

[0082] The M state indicates that the data in the processor's corresponding cache line (i.e., the aforementioned data variable) has been modified and is inconsistent with the data in memory. Before allowing other processors to read the corresponding data in memory, the processor must write the data back to memory. After the data is written back to memory, the state of the data in the cache line changes to the E state.

[0083] The E state means that the data in the cache line corresponding to the processor is consistent with the data in the main memory and exists only in the cache of the processor, that is, the processor has exclusive ownership of the data. When the processor modifies the data, the state of the data in the cache line changes to the M state. When other processors read the data, the state of the data in the cache line changes to the S state.

[0084] The S state means that the data in the cache line corresponding to the processor is consistent with the data in the memory, and the data exists in the cache lines corresponding to multiple processors, that is, multiple processors share the data. When the processor modifies the data, the state of the data in the cache lines corresponding to other processors changes to the I state.

[0085] The I state means that the data in the cache line corresponding to the processor is invalid data that is unavailable.

[0086] After introducing the relevant technical terms of the embodiments of this application, the application scenarios of the embodiments of this application are introduced. The embodiments of this application can be applied to electronic devices. Such electronic devices include but are not limited to servers, terminals, mobile phones, tablet computers, computers, laptop computers, video cameras, cameras, wearable devices, or vehicle-mounted devices.

[0087] The embodiment of the present application provides a data access system, which can be the above-mentioned electronic device or a chip system in the electronic device. Figure 2 As shown, the data access system 2000 includes multiple processing nodes, such as a first processing node 210 and at least one second processing node (e.g., a second processing node 220, a second processing node 230, and a second processing node 240); the data access system 2000 also includes a storage node 300 and a management node 400.

[0088] For example, the plurality of processing nodes may all be processors. Alternatively, the plurality of processing nodes may all be processor cores, and the plurality of processing nodes may all be arranged on the same processor or on different processors. The storage node 300 may refer to a memory shared by at least two of the plurality of processing nodes, for example Figure 1 The second-level cache, third-level cache or memory 120 in the storage node 300. The management node 400 can be an HN. Multiple processing nodes are used to access the shared storage space in the storage node 300 through a spin lock. Access can refer to writing data, reading data or other operations on data. The management node 400 is used to manage the access of multiple processing nodes to the shared storage space. For example, the management node 400 can manage the cache consistency state corresponding to multiple processing nodes. The target cache line corresponding to each processing node in the multiple processing nodes can be a cache line in its corresponding first-level cache, and the target cache line is used to store data in the shared storage space. Alternatively, the target cache line corresponding to each processing node in the multiple processing nodes can also be its corresponding shared storage space. Exemplarily, the first processing node 210 is a node that has acquired the spin lock, and the second processing nodes (including the second processing node 220, the second processing node 230 and the second processing node 240) are nodes that have not acquired the spin lock.

[0089] For example, Figure 3As shown, the process of first processing node 210 acquiring a spin lock and modifying the cache coherence state is described, taking the example of first processing node 210 being a producer and second processing node 220 and second processing node 230 being consumers. Before first processing node 210 acquires the spin lock, the data in the shared memory space is the first data. The state of the first data in the target cache line corresponding to second processing node 220 and second processing node 230 is in the S state. The state of the data in the target cache line corresponding to first processing node 210 is either the I state or the S state, and the I state is used as an example below. First processing node 210 accesses the lock variable in the shared memory space and changes the lock variable to the locked state (for example, changing the data to 1). First processing node 210 accesses its corresponding target cache line and attempts to modify the data in the shared memory space. Because the state of the data in the target cache line corresponding to first processing node 210 is the I state, a cache miss occurs in the target cache line, so first processing node 210 sends a write request to management node 400. The write request is used to instruct the modification of the data in the shared memory space (in this case, the first data). In response to the write request, management node 400 queries the consistency status of the first data. Management node 400 learns that the state of the first data in the target cache lines corresponding to second processing node 220 and second processing node 230 is both in the S state. In response to the write request and the consistency status of the first data, management node 400 sends a first status message to second processing node 220 and a first status message and a first data read request to second processing node 230. The first status message indicates that the state of the first data should be changed to the I state. The first data read request is used to read the first data. In response to the first status message, second processing node 220 changes the state of the first data in the corresponding target cache line to the I state and sends a first status response to management node 400. In response to the first status message and the first data read request, second processing node 230 changes the state of the first data in the corresponding target cache line to the I state and sends a first status response and the first data to management node 400. The first status response indicates that the first status message has been processed. Based on the first status responses from second processing node 220 and second processing node 230, management node 400 sends a write grant message and the first data to first processing node 210. First processing node 210 obtains the first data and, in response to the write authorization message, changes the state of the data in the corresponding target cache line to the M state. During these processes, the management node determines that the first processing node among the multiple processing nodes has obtained access rights to the shared storage space in the storage node. For example, management node 400 changes the consistency state of the data in the shared storage space (not the first data at this time) to: the data is in the M state and has been modified by the first processing node 210.

[0090] In a possible implementation, when the first processing node 210 obtains access rights to the shared storage space through a spin lock, at least one second processing node is in a loop state, continuously sending access requests to grab the lock.

[0091] In some examples, such as Figure 4 As shown, when the first processing node 210 obtains access to the shared storage space through the spin lock, the second processing node 220 accesses its corresponding target cache line and attempts to read the data in the shared storage space. Since the state of the data in the target cache line corresponding to the second processing node 220 is I state, a cache miss occurs in the target cache line, so the second processing node 220 sends a read request to the management node 400. The read request is used to indicate the reading of data in the shared storage space. In response to the read request from the second processing node 220, the management node 400 finds that the consistency state of the data is M state and is modified by the first processing node 210. In response to the read request and the consistency state of the data, the management node 400 forwards the read request to the first processing node 210. Since the first processing node 210 has not yet modified the data, the first processing node 210 has not released the lock. Therefore, the second processing node 220 and the second processing node 230 cannot access the data variable. The process of the second processing node 230 accessing its corresponding target cache line can refer to the process of the second processing node 220 accessing its corresponding target cache line and Figure 4 , the embodiments of this application will not be described in detail here.

[0092] In this example, because the read request of at least one second processing node is missed within the second processing node, the at least one second processing node continuously sends read requests in a loop. During the process of first processing node 210 acquiring the spin lock, a large number of read requests are present on the bus, and these read requests are sent to the same area. This can cause a request storm on the bus and blockage of messages with the same address on the bus, ultimately leading to low bus transmission efficiency.

[0093] In some examples, such as Figure 4As shown, after first processing node 210 obtains access to the shared memory space through a spin lock, it changes the first data in the corresponding target cache line to the second data. After the data modification is complete, first processing node 210 accesses the lock variable in the shared memory space and changes the lock variable to a released state (e.g., changing the data to 0), thereby releasing the spin lock. Second processing node 220 also sends a read request to management node 400. Management node 400 forwards the read request to first processing node 210. After releasing the spin lock, first processing node 210 sends the second data to management node 400 in response to the read request. Furthermore, first processing node 210 changes the state of the second data in the corresponding target cache line to the S state in response to the read request. Based on the received second data, management node 400 changes the coherence state of the data (in this case, the second data) in the shared memory space to: the data is in the S state and is shared by first processing node 210 and second processing node 220. Furthermore, management node 400 sends a second status message and the second data to second processing node 220 based on the received second data. The second status message is used to indicate that the state of the second data is changed to the S state. The second processing node 220 writes the received second data into its corresponding target cache line. In response to the second status message, the second processing node 220 changes the state of the second data in its corresponding target cache line to the S state, and the second processing node 220 sends a second status response to the management node 400. The second status response is used to indicate that the second status message has been processed. Please refer to Figure 4 The first dotted line in . After the management node 400 forwards the read request from the second processing node 220 to the first processing node 210 and before the management node 400 receives the second data from the first processing node 210, the second processing node 230 sends a read request to the management node 400. Moreover, the address requested to be read by the second processing node 230 is the same as the address requested to be read by the second processing node 220. Since the management node 400 has not yet processed the read request from the second processing node 220, the management node 400 will not process the read request from the second processing node 230 for the time being. Please refer to Figure 4 When the management node 400 receives the second status response from the second processing node 220, the management node 400 confirms that the read request from the second processing node 220 has been processed and starts processing the read request from the second processing node 230. The process of the management node 400 processing the read request from the second processing node 230 can refer to the process of the management node 400 processing the read request from the second processing node 220 and Figure 4 , the embodiments of this application will not be described in detail here.

[0094] In this example, there are multiple second processing nodes. After first processing node 210 releases the spin lock, management node 400 serially processes read requests from different second processing nodes. Management node 400 will not process the read request from the next second processing node until it has completed processing the read request from the previous second processing node, forcing the next second processing node to wait. This results in low data read efficiency for multiple second processing nodes.

[0095] In one possible implementation, when the first processing node 210 obtains access rights to the shared memory space through a spin lock, the management node 400 and / or at least one second processing node does not send an access request to the first processing node, thereby avoiding a request storm on the bus.

[0096] In some examples, such as Figure 5 As shown. First processing node 210 obtains access rights to the shared memory space through a spin lock. First processing node 210 instructs management node 400 and / or at least one second processing node to stop sending first access requests to first processing node 210. First processing node 210 accesses the shared memory space according to the access rights. Under the instruction of first processing node 210, management node 400 stops sending the first access request from at least one second processing node among the plurality of processing nodes to first processing node 210. Management node 400, under the instruction of first processing node 210, instructs at least one second processing node to stop sending the first access request to management node 400. At least one second processing node, under the instruction of first processing node 210 and / or management node 400, stops sending the first access request to management node 400.

[0097] Exemplarily, a first access request is used to request access to a shared memory space. A first access request generally refers to an access request that has not yet been sent, and is directed to operations for all second processing nodes to access the shared memory space. Access can refer to writing data, reading data, or other operations on data. The first processing node 210 accessing the shared memory space can mean that the first processing node 210 rewrites data in the shared memory space. The first processing node 210 accessing the shared memory space can also mean that the first processing node 210 reads data in the shared memory space.

[0098] For example, first processing node 210 may instruct all second processing nodes (taking second processing node 220, second processing node 230, and second processing node 240 as examples, second processing node 240 not shown in the figure) at once to stop sending first access requests to first processing node 210. In this way, the processing of first processing node 210 is relatively simple. Alternatively, first processing node 210 may only instruct second processing nodes (taking second processing node 220 and second processing node 230 as examples) that have shared memory space access requirements to stop sending first access requests to first processing node 210. First processing node 210 does not need to instruct second processing nodes (taking second processing node 240 as an example) that do not have shared memory space access requirements. In this way, the overhead of second processing nodes 230 that do not have access requirements responding to instructions can be avoided, and the amount of information on the bus can also be reduced.

[0099] In this embodiment, the first processing node 210 obtains access rights to the shared storage space through a spin lock, and the first processing node 210 instructs the management node 400 and / or at least one second processing node to stop sending first access requests. This reduces the number of first access requests continuously sent to the first processing node 210 on the bus, and only adds one instruction process to each node, thereby reducing request storms on the bus. Furthermore, the number of first access requests transmitted to the address of the first processing node 210 is reduced, and only the instruction process for different node addresses is added, thereby alleviating the problem of bus congestion caused by messages with the same address. Therefore, bus transmission efficiency can be improved.

[0100] In some examples, the first processing node 210 sends first indication information to the management node 400. The first indication information is used to instruct the management node 400 to stop sending the first access request to the first processing node 210. The management node 400 receives the first indication information from the first processing node 210. In response to the first indication information, the management node 400 stops sending the first access request from at least one second processing node to the first processing node 210. In this embodiment, the first processing node 210 sends the first indication information to the management node 400. Even if the management node 400 receives the first access request from at least one second processing node, it will not send the first access request to the first processing node 210 in response to the first indication information. Since the first processing node 210 only sends the first indication information to the management node 400, the processing overhead of the first processing node 210 is relatively low.

[0101] In some examples, management node 400 sends second indication information to at least one second processing node in response to the first indication information. The at least one second processing node may include only second processing node 220 and second processing node 230, or may include second processing node 220, second processing node 230, and second processing node 240. The first indication information instructs management node 400 to stop sending the first access request to first processing node 210. The second indication information instructs management node 400 to stop sending the first access request to management node 400. For example, management node 400 sends the second indication information to second processing node 220, second processing node 230, and second processing node 240. Second processing nodes 220, 230, and second processing node 240 receive the second indication information from management node 400. In response to the second indication information, second processing nodes 220, 230, and second processing node 240 stop sending the first access request. Exemplarily, second processing nodes 220, 230, and second processing node 240 send a first indication response to management node 400. The first indication response indicates that the second indication information has been processed. In this embodiment, the management node 400 instructs the second processing node to stop sending first access requests to the management node 400. This further reduces the number of first access requests sent by at least one second processing node to the management node 400. This reduces request storms on the bus and alleviates the problem of bus congestion caused by messages with the same address. Consequently, bus transmission efficiency can be improved.

[0102] In some examples, first processing node 210 sends first indication information to at least one second processing node. The at least one second processing node may include only second processing node 220 and second processing node 230, or may include second processing node 220, second processing node 230, and second processing node 240. The first indication information is used to instruct the at least one second processing node to stop sending first access requests to management node 400. For example, first processing node 210 sends the first indication information to second processing node 220, second processing node 230, and second processing node 240. Second processing node 220, second processing node 230, and second processing node 240 receive the first indication information from first processing node 210. In response to the first indication information, second processing node 220 and second processing node 230 stop sending first access requests. Exemplarily, the first indication information is used to instruct any second processing node to stop sending first access requests to management node 400. In response to the first indication information, second processing node 220 and second processing node 230 stop sending first access requests to management node 400. In this embodiment, the at least one second processing node stops sending the first access request, and management node 400 does not receive the first access request, and therefore does not forward the first access request to first processing node 210. First processing node 210 directly sends the first indication information to the at least one second processing node without going through management node 400. In this way, the latency for the at least one second processing node to receive the first indication information is reduced, the processing overhead of management node 400 is reduced, and the amount of information on the bus is reduced.

[0103] In some examples, in addition to sending the first instruction information to at least one second processing node, the first processing node 210 also sends the second instruction information to the management node 400. The first instruction information is used to instruct the management node 400 to stop sending the first access request. The second instruction information is used to instruct the management node 400 to stop sending the first access request to the first processing node 210. In this embodiment, the first processing node 210 not only instructs the at least one second processing node to stop sending the first access request to the management node 400, but also instructs the management node 400 to stop sending the first access request to the first processing node 210. This allows the instructions to stop sending the first access request to be aligned across the three nodes, facilitating management.

[0104] In one possible implementation, Figure 6 Before the first processing node 210 instructs the management node 400 and / or at least one second processing node to stop sending the first access request to the first processing node 210, the first processing node 210 receives the second access request.

[0105] In some examples, because second processing node 220 and second processing node 230 are in a loop state, second processing node 220 and second processing node 230 both send second access requests to management node 400. Management node 400 receives multiple second access requests from second processing node 220 and second processing node 230. Management node 400 sends multiple second access requests to first processing node 210. First processing node 210 receives multiple second access requests from management node 400. Exemplarily, the second access request is for access to a shared memory space. The second access request specifically refers to an access request that has already been sent, specifically for a specific second processing node accessing the shared memory space. In this embodiment, first processing node 210 sends the first indication information after receiving the second access request from management node 400. First processing node 210 can determine the second processing node that requires access to the shared memory space based on the second access request. Furthermore, this can avoid unnecessary information transmission caused by first processing node 210 sending the first indication information when no second processing node requires access to the shared memory space. This can conserve bus transmission resources.

[0106] In one possible implementation, upon receiving multiple second access requests, management node 400 determines first processing node 210 as a producer and determines second processing node 220 and second processing node 230 as consumers based on the multiple second access requests.

[0107] In some examples, when the management node 400 determines that the first processing node 210 is a producer, it stops sending the first access request to the first processing node 210 under the instruction of the first processing node 210. For example, the first processing node 210 is a producer when the first processing node 210 writes data in the shared storage space, and the written data is requested to be accessed by other processing nodes. The second processing node 220 and the second processing node 230 are consumers when the second processing node 220 and the second processing node 230 need to access the data. For example, Figure 6As shown. When the management node 400 determines that the first processing node 210 is a producer, it can change the state of the data in the target cache line corresponding to the first processing node 210 to the D state. The D state is used to indicate that the first processing node 210 is a producer. Exemplarily, when the management node 400 determines that the second processing node 220 and the second processing node 230 are processed, it can change the state of the data in the target cache line corresponding to the second processing node 220 and the second processing node 230 to the X state (not shown in the figure). The X state is used to indicate that the second processing node 220 and the second processing node 230 are consumers. Alternatively, when the management node 400 determines that the second processing node 220 and the second processing node 230 are processed, the corresponding relationship between the second processing node 220 and the second processing node 230 and the consumer is recorded in the directory. In this embodiment, the management node 400 determines that the first processing node 210 is a consumer, so that the management node 400 can know that the instruction of the first processing node 210 is to stop sending the first access request. This can provide a basis for improving bus transmission efficiency.

[0108] In one possible embodiment, when the number of multiple second access requests reaches a preset number, the first processing node 210 instructs the management node 400 and / or at least one second processing node to stop sending first access requests. In this embodiment, when the number of second access requests is small, the pressure on the bus to transmit requests is not great. In this case, the first processing node 210 does not need to instruct the management node 400 and / or at least one second processing node to stop sending first access requests. When the number of second access requests reaches a preset number, the pressure on the bus to transmit requests is greater. Only then does the first processing node 210 instruct the management node 400 and / or at least one second processing node to stop sending first access requests. In this way, the processing overhead of the first processing node 210 can be reduced.

[0109] In one possible implementation, the first processing node 210 may proactively send the required data to the second processing node or the management node 400. For example, the first processing node 210 may write data and send the partially written data before releasing the spin lock. Alternatively, the first processing node 210 may send the entire written data after releasing the spin lock.

[0110] In some examples, such as Figure 7 As shown, the first processing node 210 sends at least one data to the management node 400. The at least one data is data accessed by multiple second access requests.

[0111] Exemplarily, the address requested to be read by second processing node 230 is the same as the address requested to be read by second processing node 220. For example, the at least one data item is the third data item. Management node 400 receives the third data item from first processing node 210. Management node 400 concurrently sends a third status message and the third data item to second processing node 220 and second processing node 230. The third status message indicates that the state of the third data item in the corresponding target cache line should be changed to the S state. Second processing node 220 and second processing node 230 receive the third data item from management node 400, store the third data item in the corresponding target cache line, and change the state of the third data item in the corresponding target cache line to the S state in response to the third status message. Second processing node 220 and second processing node 230 send a third status response to management node 400. The third status response indicates that the third status message has been processed. In response to the third status response, management node 400 sends an acknowledgment response to first processing node 210, second processing node 220, and second processing node 230. In response to the confirmation response, the first processing node 210 changes the state of the third data in the corresponding target cache line to the S state. During these processes, the management node 400 changes the consistency state of the data (the third data in this case) in the shared memory space to: the data is in the S state and is shared by the first processing node 210, the second processing node 220, and the second processing node 230.

[0112] Exemplarily, the address requested to be read by the second processing node 230 is different from the address requested to be read by the second processing node 220. For example, the at least one data item is the fourth data item and the fifth data item. Exemplarily, when the management node 400 receives a second access request from the second processing node 220, the management node 400 records a first correspondence between the second processing node 220 and the fourth data item indicated by the second access request. When the management node 400 receives a second access request from the second processing node 230, the management node 400 records a second correspondence between the second processing node 230 and the fifth data item indicated by the second access request. When the management node 400 receives the fourth data item and the fifth data item from the first processing node 210, the management node 400 obtains the first correspondence and the second correspondence. Based on the first and second correspondences, the management node 400 sends the fourth data item to the second processing node 220 and the fifth data item to the second processing node 230 in parallel. In this embodiment, the management node 400 records the correspondence between each second processing node and the required data item. Based on the corresponding relationship, upon receiving data proactively sent by the first processing node 210, the management node 400 can send the required data to each second processing node in parallel. This can reduce the delay in serial processing of access requests from multiple second processing nodes in the queue, thereby improving the efficiency of data synchronization between producers and multiple consumers.

[0113] In other examples, first processing node 210 sends at least one data to second processing node 220 and second processing node 230. The at least one data is data accessed by multiple second access requests. The content of the at least one data sent by first processing node 210 to second processing node 220 and second processing node 230 can refer to the content of the at least one data sent by management node 400 to second processing node 220 and second processing node 230, which will not be repeated here in this embodiment of the present application. Second processing node 220 and second processing node 230 receive third data from first processing node 210, store the third data in the corresponding target cache line, and change the state of the third data in the corresponding target cache line to the S state.

[0114] In this embodiment, on the one hand, the first processing node 210 actively sends data. Even if at least one second processing node and / or the management node 400 stops sending the first access request, the second processing node that needs to access the shared storage space can still obtain the required data. This can provide a basis for optimizing bus transmission efficiency. On the other hand, the management node 400 and / or the first processing node 210 can send data to multiple second processing nodes in parallel. In this way, there will be no situation where the second processing node needs to wait, and the delay of serial processing of access requests from multiple second processing nodes in the queue can be reduced, thereby improving the efficiency of data synchronization between the producer and multiple consumers.

[0115] In one possible implementation, after first processing node 210 releases the spin lock, first processing node 210 may instruct management node 400 and / or at least one second processing node to send a first access request to first processing node 210. The second processing node may then begin to grab the lock based on the instructions. For example, first processing node 210 may proactively send third instruction information to a second processing node or management node 400, where the third instruction information is used to instruct the first processing node 210 to send the first access request.

[0116] In some examples, the first instruction information is used to instruct the management node 400 to stop sending the first access request to the first processing node 210. In response to the first instruction information from the first processing node 210, the management node 400 stops sending the first access request to the first processing node 210. However, the management node 400 may continue to receive the first access request, but will not send the first access request to the first processing node 210. In this case, after the first processing node 210 releases the spin lock, the first processing node 210 instructs the management node 400 to send the first access request to the first processing node 210. Under the instruction of the first processing node 210, the management node 400 sends the first access request to the first processing node 210.

[0117] In other examples, after first processing node 210 releases the spin lock, first processing node 210 instructs management node 400 to send a first access request to first processing node 210. Under the instruction of first processing node 210, management node 400 instructs second processing node 220 and second processing node 230 to send the first access request to management node 400.

[0118] In some further examples, after first processing node 210 releases the spin lock, first processing node 210 instructs second processing node 220 and second processing node 230 to send a first access request to management node 400. Under the instruction of first processing node 210, second processing node 220 and second processing node 230 send the first access request to management node 400.

[0119] In this embodiment, first processing node 210 proactively instructs management node 400 and / or at least one second processing node to begin sending first access requests to first processing node 210. Even if management node 400 and / or at least one second processing node stops sending first access requests, the second processing node that needs to access the shared memory space can continue to acquire the spin lock after the spin lock is released. This provides a basis for optimizing bus transmission efficiency.

[0120] Based on the above including Figure 2 The data access system 2000 of the structure shown in FIG. Figure 3 、 Figure 5 、 Figure 6 and Figure 7 According to the functions of each node shown, the data access system 2000 can execute the following data access method.

[0121] Figure 8 A data access method is shown, which is applicable to the first processing node 210. The method includes S100-S120.

[0122] S100: The first processing node 210 obtains access rights to a shared storage space through a spin lock.

[0123] S110: The first processing node 210 instructs the management node 400 and / or at least one second processing node to stop sending the first access request to the first processing node 210. Exemplarily, the first access request is used to request access to a shared storage space.

[0124] S120 : The first processing node 210 accesses the shared storage space according to access rights.

[0125] Figure 9 Another data access method is shown, which is applicable to the management node 400. The method includes S210 and S220.

[0126] S210 : The management node 400 determines that the first processing node 210 obtains access rights to the shared storage space.

[0127] S220 : Under the instruction of the first processing node 210 , the management node 400 stops sending the first access request from the at least one second processing node to the first processing node 210 .

[0128] Figure 10 Another data access method is shown. This data access method is applicable to the second processing node described above. The method includes S310 and S320.

[0129] S310 : The second processing node receives an instruction from the management node 400 and / or the first processing node 210 .

[0130] S320 : Under the instruction of the management node 400 and / or the first processing node 210 , the second processing node stops sending the first access request to the management node 400 .

[0131] Taking the at least one second processing node including the second processing node 220 as an example, the interaction process among the first processing node 210, the management node 400, the second processing node 220 and the second processing node 230 is introduced below.

[0132] In an example, the first processing node 210 may send first indication information to the management node 400 .

[0133] For example, when first processing node 210 obtains access to the shared memory space through a spin lock, first processing node 210 sends first instruction information to management node 400, instructing management node 400 to stop sending the first access request to first processing node 210. Management node 400 receives the first instruction information from first processing node 210. In response to the first instruction information, management node 400 stops sending the first access request from at least one second processing node to first processing node 210. First processing node 210 accesses the shared memory space.

[0134] In another example, the first processing node 210 may send first indication information to the management node 400 , and the management node 400 forwards the first indication information to the second processing node 220 .

[0135] For example, when first processing node 210 obtains access rights to a shared memory space through a spin lock, first processing node 210 sends first instruction information to management node 400. The first instruction information is used to instruct second processing node 220 to stop sending first access requests to management node 400. Management node 400 sends the first instruction information to second processing node 220. The second processing node receives the first instruction information from management node 400. In response to the first instruction information, second processing node 220 stops sending the first access request to management node 400. First processing node 210 accesses the shared memory space according to the access rights.

[0136] In yet another example, the first processing node 210 may send first indication information to the second processing node 220 .

[0137] For example, when first processing node 210 obtains access to the shared memory space through a spin lock, first processing node 210 sends first instruction information to second processing node 220. The first instruction information is used to instruct second processing node 220 to stop sending the first access request to management node 400. The second processing node receives the first instruction information from first processing node 210. In response to the first instruction information, second processing node 220 stops sending the first access request to management node 400. First processing node 210 accesses the shared memory space.

[0138] In yet another example, the first processing node 210 may send the first indication information to both the management node 400 and the second processing node 220 , where the first indication information is used to instruct to stop sending the first access request.

[0139] In one possible implementation, before first processing node 210 sends any first indication information, second processing node 220 sends a second access request. For example, second processing node 220 sends a second access request to management node 400, where the second access request is for accessing the shared storage space. Management node 400 receives at least one second access request from second processing node 220. Management node 400 sends at least one second access request to first processing node 210. First processing node 210 receives at least one second access request from management node 400.

[0140] In one possible implementation, S110 includes: when the number of second access requests received by the first processing node 210 is excessive (reaching a preset number), the first processing node 210 instructs the management node 400 and / or at least one second processing node to stop sending the first access request to the first processing node 210.

[0141] In one possible implementation, management node 400 may identify first processing node 210 as a producer. The method further includes: upon receiving at least one second access request, management node 400 determines that first processing node 210 is a producer. S220 includes: upon determining that first processing node 210 is a producer, management node 400, under the instruction of first processing node 210, stops sending the first access request to first processing node 210.

[0142] In one possible implementation, first processing node 210 proactively sends data required by second processing node 220 to management node 400 and / or second processing node 220. Exemplarily, the method further includes: first processing node 210 sending at least one data item to second processing node 220 and / or management node 400, where the at least one data item is data accessed by at least one second access request. Management node 400 receives the at least one data item from first processing node 210. Management node 400 sends the at least one data item to second processing node 220. Second processing node 220 receives the at least one data item from first processing node 210 and / or management node 400.

[0143] For example, management node 400 may record the correspondence between second processing node 220 and the data indicated by the second access request sent by the second processing node 220. The method further includes: management node 400 obtaining the correspondence between second processing node 220 and each piece of at least one piece of data. Management node 400 sends the corresponding data to second processing node 220 based on the correspondence.

[0144] In a possible implementation, the first processing node 210 actively instructs the management node 400 and / or the second processing node 220 to start sending the first access request.

[0145] Exemplarily, the method further includes: after the first processing node 210 releases the spin lock, the first processing node 210 instructs the management node 400 to send a first access request to the first processing node 210. Under the instruction of the first processing node 210, the management node 400 sends the first access request to the first processing node 210.

[0146] As another example, the method further includes: after first processing node 210 releases the spin lock, first processing node 210 instructs management node 400 to send a first access request to first processing node 210. Under the instruction of first processing node 210, management node 400 instructs second processing node 220 to send the first access request to management node 400. Under the instruction of first processing node 210, management node 400 sends the first access request from second processing node 220.

[0147] In another exemplary embodiment, the method further includes: after first processing node 210 releases the spin lock, first processing node 210 instructs second processing node 220 to send a first access request to first processing node 210. Under the instruction of first processing node 210, second processing node 220 sends the first access request to management node 400. Management node 400 forwards the first access request to first processing node 210.

[0148] It is understandable that the above data access method can be applied to the aforementioned data access system 2000. Since the functions and effects have been described in detail in the aforementioned embodiment of the data access system 2000, they will not be repeated here.

[0149] Combination of the above Figure 8 、 Figure 9 and Figure 10 The data access method provided by the embodiment of the present application is described. Figure 11 A data access device provided by an embodiment of the present application is described.

[0150] Exemplarily, the data access device 3000 includes multiple processing modules, including a first processing module 310 and at least one second processing module (e.g., a second processing module 320, a second processing module 330, and a second processing module 340). The data access device 3000 also includes a storage module 400 and a control module 500. The first processing module 310 is configured to implement the functions of the first processing node 210 in the above-described method, such as executing S100, S110, and S120. The control module 500 is configured to implement the functions of the management node 400 in the above-described method, such as executing S210 and S220. The at least one second processing module, such as the second processing module 320, is configured to implement the functions of the second processing node 220 in the above-described method, such as executing S310. The storage module 400 is configured to implement the functions of the storage node 300 in the above-described method. The first processing module 310, the at least one second processing module, the storage module 400, and the control module 500 may also cooperate with each other to implement one or more steps in the above-described method embodiments.

[0151] It is understood that the components of the data access device 3000 can be applied to the data access system 2000 to implement one or more steps of the data access method. Since the functions and effects have been described in detail in the embodiment of the data access system 2000, they will not be repeated here.

[0152] Combination of the above Figure 11 The data access device provided by the embodiment of the present application is described. Figure 2 A data access system provided in an embodiment of the present application is described.

[0153] Exemplarily, each of the multiple processing nodes can be a processor. The processor can be a single processor structure, a multi-processor structure, a single-threaded processor, a multi-threaded processor, etc.; in some feasible embodiments, the processor can include at least one of a central processing unit (CPU), a general-purpose processor, a digital signal processor, a neural network processor, a graphics processing unit (GPU), an image signal processor, a microcontroller, or a microprocessor. In addition, the processor may further include other hardware circuits or accelerators, such as application-specific integrated circuits, field programmable gate arrays or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like.

[0154] Exemplarily, the storage node 300 may be a memory. The memory may be used to store data, software programs, and modules. The memory primarily includes a program storage area and a data storage area. The program storage area may store software programs, such as instructions in the form of code. These software programs include, but are not limited to, an operating system, an application required for at least one function, and the like. The data storage area may store data generated based on the use of the image processing device, such as image data. The memory may include a floppy disk, a hard disk such as an internal hard disk and a removable hard disk, a magnetic disk, an optical disk, a magneto-optical disk such as a compact disc read-only memory (CD-ROM), a non-volatile storage device such as a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an electrical programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, or any other form of storage medium known in the art.

[0155] An embodiment of the present application also provides a computer-readable storage medium, which stores program code. When the computer-readable storage medium is run on a device (for example, the device can be a single-chip microcomputer, chip, computer or processor, etc.), the program code therein can be called by the processor to execute one or more steps in the above method embodiment.

[0156] Based on this understanding, the embodiments of the present application also provide a computer program product containing instructions. The technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or the processor therein to execute all or part of the steps of the method described in each embodiment of the present application.

[0157] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0158] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0159] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0160] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0161] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of this embodiment based on actual needs.

[0162] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0163] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0164] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A data access method, characterized in that: The method comprises: A first processing node among the plurality of processing nodes obtains access rights to a shared storage space in a storage node through a spin lock; the plurality of processing nodes are configured to access the shared storage space through the spin lock; The first processing node instructs the management node and / or at least one second processing node among the plurality of processing nodes to stop sending a first access request to the first processing node, where the first access request is used to request access to the shared storage space, and the management node is used to manage access to the shared storage space by the plurality of processing nodes; The first processing node accesses the shared storage space according to the access permission.

2. The method according to claim 1, characterized in that The first processing node instructing the management node and / or at least one second processing node among the plurality of processing nodes to stop sending the first access request to the first processing node, including: The first processing node sends the first indication information to the at least one second processing node, where the first indication information is used to instruct the at least one second processing node to stop sending the first access request to the management node.

3. The method according to claim 1 or 2, characterized in that The first processing node instructing the management node and / or at least one second processing node among the plurality of processing nodes to stop sending the first access request to the first processing node, including: The first processing node sends the first indication information to the management node, where the first indication information is used to instruct the management node to stop sending the first access request to the first processing node.

4. The method according to any one of claims 1 to 3, characterized in that Before the first processing node instructs the management node and / or at least one second processing node among the plurality of processing nodes to stop sending the first access request to the first processing node, the method further includes: The first processing node receives at least one second access request from the management node, where the second access request is used to request access to the shared storage space.

5. The method according to claim 4, characterized in that The first processing node instructing the management node and / or at least one second processing node among the plurality of processing nodes to stop sending the first access request to the first processing node, including: When the number of the at least one second access request reaches a preset number, the first processing node instructs the management node and / or at least one second processing node among the plurality of processing nodes to stop sending the first access request to the first processing node.

6. The method according to claim 4 or 5, characterized in that The method further comprises: The first processing node sends at least one data to the management node and / or the at least one second processing node, where the at least one data is the data accessed by the at least one second access request.

7. The method according to any one of claims 1 to 5, characterized in that The method further comprises: After the first processing node releases the spin lock, the first processing node instructs the management node and / or the at least one second processing node to send the first access request to the first processing node.

8. A data access method, characterized in that: The method comprises: The management node determines that a first processing node among the plurality of processing nodes obtains access rights to a shared storage space in the storage node, the management node being used to manage access to the shared storage space by the plurality of processing nodes, the plurality of processing nodes being used to access the shared storage space in the storage node through a spin lock; Under the instruction of the first processing node, the management node stops sending a first access request from at least one second processing node among the plurality of processing nodes to the first processing node, where the first access request is used to request access to the shared storage space.

9. The method according to claim 8, characterized in that The step of stopping, by the management node, sending, to the first processing node, a first access request from at least one second processing node among the plurality of processing nodes under the instruction of the first processing node includes: The management node receives first indication information from the first processing node; In response to the first indication information, the management node stops sending the first access request to the first processing node.

10. The method according to claim 9, characterized in that The method further comprises: Under the instruction of the first processing node, the management node instructs the at least one second processing node to stop sending the first access request to the management node.

11. The method according to any one of claims 8 to 10, characterized in that: Before the management node stops sending the first access request from at least one second processing node among the plurality of processing nodes to the first processing node under the instruction of the first processing node, the method further includes: The management node receives at least one second access request from the at least one second processing node, where the second access request is used to request access to the shared storage space; The management node sends the at least one second access request to the first processing node.

12. The method according to claim 11, characterized in that The method further comprises: The management node determines, upon receiving the at least one second access request, that the first processing node is a producer; The step of stopping, by the management node, sending, to the first processing node, a first access request from at least one second processing node among the plurality of processing nodes under the instruction of the first processing node includes: When the management node determines that the first processing node is the producer, the management node stops sending the first access request to the first processing node under the instruction of the first processing node.

13. The method according to claim 11 or 12, characterized in that The method further comprises: The management node receives at least one data from the first processing node, where the at least one data is the data accessed by the at least one second access request; The management node sends the at least one data to the at least one second processing node.

14. The method according to claim 13, characterized in that The method further comprises: The management node obtains a correspondence between each second processing node in the at least one second processing node and each data in the at least one data; The management node sending the at least one data to the at least one second processing node includes: The management node sends corresponding data to each second processing node of the at least one second processing node according to the corresponding relationship.

15. The method according to any one of claims 8 to 12, characterized in that: The method further comprises: Under the instruction of the first processing node, the management node sends the first access request to the first processing node.

16. The method according to any one of claims 8 to 12, characterized in that: The method further comprises: Under the instruction of the first processing node, the management node instructs the at least one second processing node to send the first access request to the management node.

17. A data access method, characterized in that: The method comprises: Under the instruction of the management node and / or the first processing node among the multiple processing nodes, the second processing node among the multiple processing nodes stops sending the first access request to the management node, and the multiple processing nodes are used to access the shared storage space in the storage node through the spin lock. The first processing node is a node that obtains access rights to the shared storage space through the spin lock.

18. The method according to claim 17, characterized in that The second processing node among the plurality of processing nodes stops sending the first access request to the first processing node under the instruction of the management node and / or the first processing node among the plurality of processing nodes, including: The second processing node receives first indication information from the first processing node and / or the management node; In response to the first indication information, the second processing node stops sending the first access request to the management node.

19. The method according to claim 17 or 18, characterized in that Before the second processing node among the plurality of processing nodes stops sending the first access request to the first processing node under the instruction of the management node and / or the first processing node among the plurality of processing nodes, the method further includes: The second processing node sends a second access request to the management node, where the second access request is used to request access to the shared storage space.

20. The method according to claim 19, characterized in that The method further comprises: The second processing node receives data from the first processing node and / or the management node, where the data is the data accessed by the second access request.

21. The method according to any one of claims 17 to 19, characterized in that: The method further comprises: Under the instruction of the first processing node and / or the management node, the second processing node sends the first access request to the management node.

22. A data access device, characterized in that: The apparatus comprises: a module for executing the method according to any one of claims 1-21.

23. A data access system, characterized in that: The system comprises: a plurality of processing nodes, storage nodes and management nodes according to the method according to any one of claims 1 to 21.

24. A computer-readable storage medium, characterized in that The method comprises computer instructions, which, when executed on an electronic device, cause the electronic device to execute the method according to any one of claims 1 to 21.

25. A computer program product, characterized in that When the computer program product is run on a computer, the computer is caused to perform the method according to any one of claims 1 to 21.

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