A chip emulation acceleration system

Abstract

This invention relates to the field of chip technology, and more particularly to a chip emulation acceleration system, comprising {A1, A2, ..., A...} m ,...,A M} and {B1,B2,...,B m ,...,B M};B m ={B0 m B1 m B2 m ,...,B i m ,...,B f(m) m}; Type I B i m Used from A m The input port acquires input stimuli and data packets and transmits them to B0. m ;B0 m Used to process A m The corresponding input stimulus and data packet are used to generate output data, which is then sent to the first type B. i m Category B i m Category B i m Used to process received output data and output it to the corresponding downstream module according to a preset timing sequence; Type B i m Used for based on received output data and Type B i m The output of the algorithm controls the input of the next data packet. This invention accelerates the chip simulation process and improves chip simulation efficiency while ensuring chip timing.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip simulation acceleration system. Background Technology

[0002] During chip verification, after receiving a data packet, the chip sends it to the firmware for parsing and processing. During this process, the chip control module, with its control functions, manages the configuration registers, receiving, storing, and parsing data packets. The chip control module can spend hundreds of cycles or even longer processing a single data packet. The larger the chip, the longer the chip control module takes to process a single data packet, resulting in a very slow and inefficient chip simulation process. Chip simulation requires processing according to the chip's timing sequence. Therefore, accelerating the chip simulation process and improving its efficiency while maintaining chip timing is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a chip simulation acceleration system that accelerates the chip simulation process and improves chip simulation efficiency while ensuring chip timing.

[0004] According to a first aspect of the present invention, a chip emulation acceleration system is provided, comprising {A1, A2, ..., A...} m ,...,A M} and {B1,B2,...,B m ,...,B M}, where A m B is the interface module corresponding to the m-th chip control module. m For the chip acceleration module corresponding to the m-th chip control module, A m With B m Interconnection, where m ranges from 1 to M, and M is the total number of chip control modules;

[0005] A m Generated based on a hardware description language, A m It only includes the input and output interfaces of the m-th chip control module;

[0006] B m ={B0 m B1 m B2 m ,...,B i m ,...,B f(m) m}, B0 m For the behavior model corresponding to the m-th chip control module, B0m Based on high-level language generation, B i m For A m The corresponding i-th verification unit, B i m For generation based on UVM, the value of i ranges from 1 to f(m), where f(m) is A m The corresponding number of verification units, B i m With B0 m Interconnect to the input or output interfaces of B0 m B input interface interconnection i m Class B i m Type I B i m Also with A m The corresponding upstream module interconnection, with B0 m B output interface interconnection i m Category B i m Category B i m Also with A m Corresponding downstream module interconnection;

[0007] Category B i m Used from A m The input port acquires input stimuli and data packets and transmits them to B0. m ;

[0008] B0 m Used to process A m The corresponding input stimulus and data packet are used to generate output data, which is then sent to the first type B. i m And Category B i m ;

[0009] Category B i m Used to process the received output data and output it to the corresponding downstream module according to the preset timing;

[0010] Category B i m It is also used based on the received output data and the second type B i m The output of the function controls the input of the next data packet.

[0011] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the chip simulation acceleration system provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value, possessing at least the following beneficial effects:

[0012] The system described in this invention replaces the chip control module with an acceleration module, and uses a corresponding behavioral model to replace the processing of the chip control module, greatly improving the processing speed. The timing of the chip is guaranteed through coordination between verification units. Therefore, the system of this invention accelerates the chip simulation process and improves chip simulation efficiency while ensuring chip timing. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a chip simulation acceleration system provided in an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This invention provides a chip simulation acceleration system, including {A1, A2, ..., A...} m ,...,A M} and {B1,B2,...,B m ,...,B M}, where A m B is the interface module corresponding to the m-th chip control module. m For the chip acceleration module corresponding to the m-th chip control module, A m With B m Interconnection, where m ranges from 1 to M, and M is the total number of chip control modules. It should be noted that a chip may include one or more chip control modules. The simulation acceleration of this invention mainly targets the simulation acceleration of the chip control modules. The simulation acceleration for each chip control module is independent, and the simulation acceleration logic is consistent. Therefore, in this embodiment of the invention, one A...m A detailed explanation of the simulation acceleration structure is sufficient. Figure 1 Only one set of A is shown in the middle. m and B m .

[0017] A m Generated based on a hardware description language, which can be Verilog, VHDL, SystemVerilog, etc. A m This only includes the input and output interfaces of the m-th chip control module. It should be noted that in existing chip simulation systems, the chip control module includes input interfaces, output interfaces, and internal operational logic, while A... m It only includes the input and output interfaces of the m-th chip control module, and the internal operation logic is empty. The internal operation process is executed by the corresponding acceleration module.

[0018] like Figure 1 As shown, B m ={B0 m B1 m B2 m ,...,B i m ,...,B f(m) m}, B0 m For the behavior model corresponding to the m-th chip control module, B0 m Generated based on a high-level language, specifically C and C++, etc. B i m For A m The corresponding i-th verification unit, where i ranges from 1 to f(m), and f(m) is A m The corresponding number of verification units. B i m It is generated based on the Universal Verification Methodology (UVM), which is specifically implemented in the SystemVerilog language.

[0019] like Figure 1 As shown, B i m With B0 m Interconnect to the input or output interfaces of B0 m B input interface interconnection i m Class B i m Type I B i m Also with A mCorresponding upstream module interconnection, A m The corresponding upstream module can specifically be a CPU (Central Processing Unit) or other chip components implemented using a hardware description language. (This is related to B0.) m B output interface interconnection i m Category B i m Category B i m Also with A m The corresponding downstream modules are interconnected, and the downstream modules can be other chip components implemented based on hardware description languages.

[0020] Category B i m Used from A m The input port acquires input stimuli and data packets and transmits them to B0. m B0 m Used to process A m The corresponding input stimulus and data packet are used to generate output data, which is then sent to the first type B. i m And Category B i m It should be noted that B0 m It replaced the processing of the original chip control module, and because of B0 m Since it's a behavior model implemented using a high-level language, its processing speed is much faster than the original chip control module. (Type B) i m Used to process received output data and output it to the corresponding downstream module according to a preset timing sequence. Type B i m It is also used based on the received output data and the second type B i m The output of the function controls the input of the next data packet.

[0021] In some application scenarios, the chip control module needs to send a handshake signal to perform a handshake operation before it can transmit data. However, in the system described in this embodiment of the invention, A m The system only includes the input and output interfaces of the m-th chip control module, and its internal operational logic is empty. Therefore, it cannot perform a handshake operation. If this is not handled, the system will enter an infinite loop. To avoid this situation, as an example, if the m-th chip control module needs to perform a handshake operation, the system also includes A. mThe input interface is set to a start signal (ready), which will be set to 1 at a preset time to replace the handshake operation that the m-th chip control module needs to perform. The preset time is set based on the specific handshake operation scenario.

[0022] As one embodiment, Class B i m This includes one or more of the following: a routing unit for implementing routing functions; an address translation unit for implementing virtual address and physical address translation; a graphical processing unit for performing graphical processing; and a resource distribution unit for distributing computing resources. (Type B) i m Configure according to specific application requirements.

[0023] As one embodiment, the first type B i m Includes a register configuration unit, which is used to configure B during the initialization phase. m And B m The corresponding registers in the downstream module. When it is necessary to configure B m When referring to the registers in the corresponding downstream module, it can be used in conjunction with the second type B configured as a routing unit. i m To achieve this, set it as the second type B of the routing unit. i The corresponding register configuration information is sent to the corresponding downstream module to implement the corresponding register configuration.

[0024] As one embodiment, the first type B i m The system includes a stimulus acquisition unit, which acquires transaction information corresponding to the input stimulus, performs transaction-level modeling (TLM), and converts the result of the transaction-level modeling into a high-level language struct before sending it to the B0. m It should be noted that all existing transaction-level modeling methods fall within the scope of protection of this invention, and will not be elaborated upon here.

[0025] As one embodiment, the first type B i m The system includes a data packet acquisition unit, which is used to acquire data packets from the upstream module's memory and send them to B0 at the end of the initialization phase or after the current data packet processing is completed. mIt should be noted that the first data packet can be obtained and processed at the end of the initialization phase. Different data packets correspond to different services. In order to ensure the timing, data packets need to be obtained in sequence. Therefore, the next data packet can only be obtained and processed after the current data packet has been processed.

[0026] As one example, B0 m Used to process A m Given the corresponding input stimuli and data packets, the output results are obtained in the form of high-level language structures. These high-level language structure output results are then converted into transaction-level output results, and transaction-level modeling is performed. Finally, the output data processed by transaction-level modeling is sent to the first type of B according to a preset processing order. i m And Category B i m It should be noted that, based on A m The corresponding input stimuli and data packets can determine the order in which the output data is sent. Therefore, the output data after transaction-level modeling processing can be sent to the first type B according to the preset processing order. i m And Category B i m This is to ensure chip timing.

[0027] As one embodiment, the first type B i m Includes a processing feedback unit, which is used in the second type B i m After processing the received output data, a current data packet processing completion instruction is sent to the upstream module. Upon receiving the current data packet processing completion instruction, the upstream module sends the next data packet to the data packet acquisition unit.

[0028] It should be noted that B0 m It can only control the output order of the output data after transaction-level modeling processing, but cannot directly guarantee the first type B. i m And Category B i m The timing of the output data, for B with time-series dependencies i m It is essential to ensure the chip timing requirements are met. To guarantee the accuracy of the chip timing, as one embodiment, if B1... im and B2 im It has a temporal dependency, B1 im For one of the first type B i m B2 im For one of the second type Bi m The system also includes B1 im The corresponding first-in-first-out queue F1 im B2 im The corresponding first-in-first-out queue F2 im .

[0029] If an upstream module writes data to a downstream module, and the upstream module can only issue one write task at a time, issuing the next write task only after receiving a response from the current write task, then B2 im Used to store the data currently to be written, B1 im Used to store the current write response, when B2 im When the data to be written in B2 is completed in the downstream module, im If B1 is empty, it means that all the data to be written has been written to the downstream module. im The response information is fed back to the upstream module, which then issues the next writing task, thus satisfying B1. im and B2 im The corresponding order preservation requirements.

[0030] If the upstream module writes data to the downstream module, and the upstream module can issue multiple write tasks at once, then B2 im Used to store currently sent data to be written, including a write task identifier, B1. im Used to store write task response information in sequence. The write task response information includes a write task identifier. If B1 im The write task identifier corresponding to the reply information of the currently pending write task is in B2. im If it does not exist in B1, it means that B1 is missing. im The write task identifier corresponding to the reply information of the currently pending write task has been completely written to the downstream module, and B1 will be... im The response information for the currently pending write tasks is fed back to the upstream module, satisfying B1. im and B2 im The corresponding order preservation requirements.

[0031] If the upstream module reads data from the downstream module, then the upstream module sends a read task instruction to the downstream module, B2. im Used in accordance with B0 m Receive read tasks sequentially, store and read data, and follow B0. m The read task is received and transmitted sequentially to B1. im In the middle, B1 im After adjusting the data reading order to allow the upstream module to send read task instructions to the downstream module, B1 will... im The data read from B0 is sent to the upstream module. It should be noted that... mThe order in which read tasks are received may differ from the order in which the upstream module sends read task instructions to the downstream module. Therefore, B1... im After adjusting the data reading order to allow the upstream module to send read task instructions to the downstream module, B1 will... im The data read from B0 is sent to the upstream module. m Other B0 m If there are no dependencies, then the current B0 m Able to directly adjust B1 im The order in which data is read is determined; otherwise, the preset order adjustment function is called to adjust B1. im The order in which data is read satisfies B1. im and B2 im The corresponding order preservation requirements.

[0032] It should be noted that in some application scenarios, the second type B i m The chip timing is not only similar to that of the first type B i m It is also related to the timing of downstream modules, when the second type B i m When timing is related to downstream modules, the operating status of the downstream modules also needs to be taken into account. As one example, if the second type B i m If it has a time-series dependency with the corresponding downstream module, then it belongs to the second type B. i m Set up a corresponding first-in-first-out queue and assign status flags to the corresponding downstream modules. These status flags include active and inactive status flags. Specifically, a busy status bit can be set. When the busy status bit is set to 1, it indicates that the corresponding downstream module is in an active state; when the busy status bit is set to 0, it indicates that the corresponding downstream module is in an inactive state. When the second type B... i m When all corresponding first-in-first-out queues are not empty and the status flag of the corresponding downstream module is a non-working status flag, the second type B... i m Data in the corresponding FIFO queue is sent to the corresponding downstream module. By setting the FIFO queue and the status flags of the downstream module, execution can be precisely controlled according to the chip timing.

[0033] The system described in this embodiment replaces the chip control module with an acceleration module, and uses a corresponding behavioral model to replace the processing of the chip control module, greatly improving the processing speed. The timing of the chip is guaranteed through coordination between verification units. Therefore, the system of this invention accelerates the chip simulation process and improves chip simulation efficiency while ensuring chip timing.

[0034] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A chip emulation acceleration system, characterized in that, Including {A1,A2,...,A m ,...,A M } and {B1,B2,...,B m ,...,B M }, where A m B is the interface module corresponding to the m-th chip control module. m For the chip acceleration module corresponding to the m-th chip control module, A m With B m Interconnection, where m ranges from 1 to M, and M is the total number of chip control modules; A m A is generated based on a hardware description language. m It only includes the input and output interfaces of the m-th chip control module; B m ={B0 m B1 m B2 m ,...,B i m ,...,B f(m) m }, B0 m B0 is the behavioral model corresponding to the m-th chip control module. m Based on high-level language generation, B i m For A m The corresponding i-th verification unit, B i m For generation based on UVM, the value of i ranges from 1 to f(m), where f(m) is A m The corresponding number of verification units, B i m With B0 m Interconnect to the input or output interfaces of B0 m B input interface interconnection i m Class B i m Type I B i m Also with A m The corresponding upstream module interconnection, with B0 m B output interface interconnection i m Category B i m Category B i m Also with A m Corresponding downstream module interconnection; Category B i m Used from A m The input port acquires input stimuli and data packets and transmits them to B0. m ; B0 m Used to process A m The corresponding input stimulus and data packet are used to generate output data, which is then sent to the first type B. i m And Category B i m ; Category B i m Used to process the received output data and output it to the corresponding downstream module according to the preset timing; Category B i m It is also used based on the received output data and the second type B i m The output of the function controls the input of the next data packet.

2. The system according to claim 1, characterized in that, If the m-th chip control module needs to perform a handshake operation, then the system also includes A. m The input interface is set to a start signal, which will be set to 1 at a preset time to replace the handshake operation that the m-th chip control module needs to perform.

3. The system according to claim 1, characterized in that, The first type B i m Includes a register configuration unit, which is used to configure B during the initialization phase. m And B m The registers in the corresponding downstream module.

4. The system according to claim 1, characterized in that, The first type B i m The system includes a stimulus acquisition unit, which acquires transaction information corresponding to input stimuli, performs transaction-level modeling, and converts the result of the transaction-level modeling into a high-level language structure before sending it to B0. m .

5. The system according to claim 1, characterized in that, The first type B i m The system includes a data packet acquisition unit, which is used to acquire data packets from the upstream module's memory and send them to B0 at the end of the initialization phase or after the current data packet processing is completed. m .

6. The system according to claim 1, characterized in that, B0 m Used to process A m Given the corresponding input stimuli and data packets, the output results are obtained in the form of high-level language structures. These high-level language structures are then converted into transaction-level output results, and transaction-level modeling is performed. Finally, the output data processed by transaction-level modeling is sent to the first type of B according to a preset processing order. i m And Category B i m .

7. The system according to claim 1, characterized in that, The first type B i m Includes a processing feedback unit, which is used in the second type B i m After processing the received output data, a current data packet processing completion instruction is sent to the upstream module. Upon receiving the current data packet processing completion instruction, the upstream module sends the next data packet to the data packet acquisition unit.

8. The system according to claim 1, characterized in that, Category B i m It includes one or more of the following: a routing unit for implementing routing functions, an address translation unit for implementing virtual address and physical address translation, a graphical processing unit for performing graphical processing, and a resource distribution unit for distributing computing resources.

9. The system according to claim 1, characterized in that, If B1 im and B2 im It has a temporal dependency, B1 im For one of the first type B i m B2 im For one of the second type B i m The system also includes B1 im The corresponding first-in-first-out queue F1 im B2 im The corresponding first-in-first-out queue F2 im ; If an upstream module writes data to a downstream module, and the upstream module can only issue one write task at a time, issuing the next write task only after receiving a response from the current write task, then B2 im B1 is used to store the data currently to be written. im Used to store the current write response, when B2 im When the data to be written in B2 is completed in the downstream module, im If it is empty, then B1 im The response information is fed back to the upstream module, which then issues the next writing task. If the upstream module writes data to the downstream module, and the upstream module can issue multiple write tasks at once, then B2 im Used to store currently sent data to be written, including a write task identifier, B1. im Used to store write task response information in sequence. The write task response information includes a write task identifier. If B1 im The write task identifier corresponding to the reply information of the currently pending write task is in B2. im If B1 does not exist, then... im The response information for the currently pending write tasks is fed back to the upstream module; If the upstream module reads data from the downstream module, then the upstream module sends a read task instruction to the downstream module, B2. im Used in accordance with B0 m Receive read tasks sequentially, store and read data, and follow B0. m The read task is received and transmitted sequentially to B1. im In the middle, B1 im After adjusting the data reading order to allow the upstream module to send read task instructions to the downstream module, B1 will... im The data read from the module is sent to the upstream module.

10. The system according to claim 1, characterized in that, If the second type B i m If it has a time-series dependency with the corresponding downstream module, then it belongs to the second type B. i m Set up the corresponding first-in-first-out queue and set status flags for the corresponding downstream modules. The status flags include working status flags and non-working status flags. When the second type B i m When the corresponding first-in-first-out queue is not empty and the status flag of the corresponding downstream module is a non-working status flag, the second type B i m The data in the corresponding first-in-first-out queue is sent to the corresponding downstream module.

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