Wafer mark graph generation method and device, equipment and medium

Abstract

The invention provides a wafer mark graph generation method and device, equipment and a medium, and can be applied to the technical field of chips. The method comprises the following steps: acquiring a marking rule customized by a user for a target test; the marking rule is used for marking position chips on the wafer; acquiring test data of the wafer for the target test; according to the test data, determining a target position chip conforming to a marking rule from a plurality of position chips on the wafer; generating a mark graph corresponding to the wafer according to the coordinates and the mark information corresponding to the chips at the positions on the wafer; the mark information indicates that the test passes, the test fails or the quality risk exists. According to the method and the device, the position chips are automatically screened, diversified service requirements of users can be met, the users do not need to manually write codes according to different service requirements, and the marking efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method, device, equipment and medium for generating a wafer marking image. Background Art

[0002] Based on the wafer test results, wafer fabrication plants mark failed chips, allowing downstream packaging houses to select those that passed the test for packaging. Inkless testing technology generates a marking diagram based on the test results of the chips, marking each chip on the wafer with different symbols to indicate whether it passes or fails. This marking diagram is then used by downstream packaging houses as a guide for wafer packaging.

[0003] During actual production and processing, some chips fail testing, while surrounding chips, while passing, still exhibit issues like poor quality and unstable performance. To minimize losses, these chips with quality risks need to be marked. Currently, wafer fabrication plants typically manually write code to mark these chips based on specific business needs, which is inefficient. Summary of the Invention

[0004] The present application provides a method, device, equipment and medium for generating a wafer marking image, thereby improving marking efficiency.

[0005] In a first aspect, the present application provides a method for generating a wafer marking image, comprising:

[0006] Obtaining a user-defined marking rule for a target test; the marking rule is used to mark a position chip on a wafer;

[0007] Acquiring test data of the wafer for the target test;

[0008] Determining, based on the test data, a target position chip that meets the marking rule from a plurality of position chips on the wafer;

[0009] A marking map corresponding to the wafer is generated based on the coordinates and marking information corresponding to each chip at each position on the wafer; the marking information indicates whether the test passed, failed, or there is a quality risk.

[0010] Optionally, obtaining a user-defined marking rule for a target test includes:

[0011] Determine the target test selected by the user among multiple tests;

[0012] Get the marking rules set by the user for the target test.

[0013] Optionally, obtaining a marking rule set by a user for the target test includes:

[0014] Display the rule setting items corresponding to the target test;

[0015] Obtaining the setting item value entered by the user for the rule setting item;

[0016] According to the rule setting items corresponding to the target test and the corresponding setting item values, a marking rule corresponding to the target test is generated.

[0017] Optionally, the plurality of tests include wafer testing, wafer acceptance testing, and defect detection;

[0018] Among them, the rule setting items corresponding to the wafer test include the distance between the chip and the location where the test failed; the rule setting items corresponding to the defect detection include multiple defect parameter items; and the rule setting items corresponding to the wafer acceptability test include multiple wafer acceptable test parameter items.

[0019] Optionally, the target test is a wafer test, and determining a target position chip that meets the marking rule from a plurality of position chips on a wafer according to the test data includes:

[0020] For each chip on the wafer, perform the following operations in sequence:

[0021] If the test data corresponding to the chip at the current position indicates that the chip at the current position fails the test, the chip at the current position is skipped;

[0022] If the test data corresponding to the chip at the current position indicates that the chip at the current position has passed the test, determining whether the chip at the current position meets the marking rule;

[0023] If there is no test data corresponding to the chip at the current position, the chip at the current position is determined as the chip at the target position.

[0024] Optionally, it also includes:

[0025] The ratio of the number of position chips on the wafer that passed the test and had no quality risk to the total number of position chips on the wafer is determined as the marking yield;

[0026] The marked yield is output.

[0027] Optionally, before determining the ratio of the number of position chips on the wafer that have passed the test and do not have quality risks to the total number of position chips on the wafer as the marking yield, the method further includes:

[0028] Determine whether the wafer is fully pattern tested;

[0029] Correspondingly, if the wafer is fully tested, the step of determining the marking yield as the ratio of the number of position chips on the wafer that have passed the test and have no quality risk to the total number of position chips on the wafer is performed; otherwise, the product of the reference yield and the wafer yield is determined as the marking yield; the reference yield is the difference between 1 and the marked proportion, and the marked proportion is the ratio of the number of target position chips to the total number of position chips on the wafer.

[0030] Optionally, after generating a marking map corresponding to the wafer according to the coordinates and marking information corresponding to the chips at each position on the wafer, the method further includes:

[0031] In response to the user updating the marking rule, an updated marking map of the wafer is generated according to the updated marking rule.

[0032] In a second aspect, the present application provides a wafer marking image generating device, comprising:

[0033] The first acquisition module is used to obtain a marking rule customized by the user for the target test; the marking rule is used to mark the position chip on the wafer;

[0034] A second acquisition module is used to acquire test data of the wafer for the target test;

[0035] a determination module, configured to determine, based on the test data, a target position chip that meets the marking rule from a plurality of position chips on the wafer;

[0036] The generation module is used to generate a marking map corresponding to the wafer based on the coordinates and marking information corresponding to each chip at each position on the wafer; the marking information indicates whether the test passed, failed, or there is a quality risk.

[0037] In a third aspect, the present application provides an electronic device, comprising: a processor and a memory communicatively connected to the processor;

[0038] The memory stores computer-executable instructions;

[0039] The processor executes the computer-executable instructions stored in the memory to implement the wafer marking image generation method as described in any one of the first aspects.

[0040] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the wafer marking image generation method described in any one of the first aspects.

[0041] In a fifth aspect, the present application provides a computer program product, comprising computer-executable instructions, which, when executed by a processor, implement the wafer marking image generation method described in any one of the first aspects.

[0042] The present application provides a method, device, equipment and medium for generating a wafer marking map. The present application provides a solution for screening and marking position chips on a wafer to obtain a marking map. The user only needs to customize corresponding marking rules for a certain test based on actual business needs. By dividing the corresponding test data according to the test, the target position chip that meets the marking rules is determined from multiple position chips on the wafer, and a marking map is generated, thereby realizing automatic screening of position chips, being able to meet the diverse business needs of users, and eliminating the need for users to manually write code according to different business needs, thereby improving marking efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0044] Figure 1 is a schematic diagram showing an application scenario according to an exemplary embodiment;

[0045] Figure 2 This is a flow chart of a method for generating a wafer marking image according to an exemplary embodiment;

[0046] Figure 3 is a schematic flow chart of a method for generating a wafer marking image according to another exemplary embodiment;

[0047] Figure 4 1 is a schematic structural diagram of a wafer marking image generating device according to an exemplary embodiment;

[0048] Figure 5 The figure is a schematic structural diagram of an electronic device according to an exemplary embodiment.

[0049] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0050] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0051] The terms "first," "second," etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. In the description of the following embodiments, "plurality" means more than two, unless otherwise specifically defined.

[0052] First, let’s explain the terms involved in this application:

[0053] Die: Also known as a positional chip, it refers to a chip at a certain location on the wafer, which contains a complete functional unit or a group of related functional units. In chip design, the die is cut into small squares and encapsulated in the chip shell.

[0054] In order to clearly understand the technical solution of the present application, the solution of the prior art is first introduced in detail.

[0055] The wafer fabrication plant (Fab) will mark (ink) the position chips that failed the test based on the test results of the wafer, so as to facilitate the screening of some position chips for delivery or to facilitate the downstream packaging factory to select the position chips that passed the test for packaging.

[0056] With the advancement of integrated circuit technology, chip sizes are shrinking. Due to the limitations of ink dot size, chip marking is increasingly being achieved through inkless testing technology. This technology generates a marking diagram based on the test results of positional chips, marking the qualified chips on the wafer with different symbols. This allows downstream packaging factories to use this marking diagram as a basis for wafer packaging.

[0057] During the actual production process, some position chips fail testing. While the surrounding position chips pass testing, they still have issues like poor quality and unstable product performance. To reduce losses caused by subsequent process failures, these position chips with quality risks (referred to as weak dies) need to be marked.

[0058] Since the quality of positioning chips depends on multiple tests, and each test has corresponding passing standards, wafer processing plants need to screen positioning chips based on the test data corresponding to multiple tests according to actual business needs to reduce the probability of quality problems after delivery to downstream customers.

[0059] Currently, wafer processing plants usually need to manually write code according to different business needs to screen and mark location chips, which is inefficient.

[0060] The present application provides a solution for screening and marking position chips on a wafer to obtain a marking map. Users only need to customize corresponding marking rules for a certain test based on actual business needs. By dividing the corresponding test data according to the test, the target position chip that meets the marking rules is determined from multiple position chips on the wafer, and a marking map is generated. This realizes the automatic screening of position chips, can meet the diverse business needs of users, and eliminates the need for users to manually write code according to different business needs, thereby improving marking efficiency.

[0061] The following introduces the application scenarios of the wafer marking image generation method provided in the embodiment of the present application.

[0062] Figure 1 FIG. 1 is a schematic diagram showing an application scenario according to an exemplary embodiment. Figure 1 As shown, this application scenario includes electronic devices. Exemplarily, the electronic devices are terminal devices used by technicians in a wafer fabrication plant. In this embodiment, technicians customize marking rules for location chips using the electronic devices based on actual business needs. The electronic devices are then triggered to screen the location chips on the wafers according to the marking rules, generating a marking map corresponding to the wafers.

[0063] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0064] Figure 2 This is a flow chart of a method for generating a wafer mark map according to an exemplary embodiment. The execution subject of the wafer mark map generation method provided in this application is a wafer mark map generation device, which is integrated into an electronic device. Figure 2 As shown, the method for generating a wafer marking image provided in this embodiment includes the following steps:

[0065] Step S101: obtaining a user-defined marking rule for a target test; the marking rule is used to mark the position chip on the wafer.

[0066] In this embodiment, when the wafer needs to be marked, the user can select a test through the electronic device according to actual business needs, and customize the marking rules corresponding to the test, thereby triggering the electronic device to execute the wafer marking map generation method provided in this application, and generate a marking map corresponding to the wafer, so as to facilitate the downstream packaging factory to package the wafer based on the marking map.

[0067] In one application scenario, for any position chip on a wafer, if the position chip meets the marking rules, it is considered a position chip with quality risks. Conversely, if the position chip does not meet the marking rules, it is considered a position chip without quality risks. This shows that the marking rules can be used to determine whether a position chip is a position chip with quality risks.

[0068] Target tests are tests performed during the wafer production process. For example, target tests include defect detection, inline / offline metrology, wafer acceptance test (WAT), chip probing (CP), or other possible tests.

[0069] Step S102 , obtaining test data of the wafer for the target test.

[0070] In this embodiment, the user customizes the marking rules for the target test, and the target test has a corresponding passing standard. Therefore, the test data corresponding to the target test can be used as a reference for determining whether there is a quality risk in the position chip on the wafer.

[0071] In an optional implementation, the test data of the wafer for various tests are stored in a database, and the electronic device is connected to the database via a network. Accordingly, the electronic device obtains the test data of the wafer for the target test from the database.

[0072] For example, the test data corresponding to the CP test is CP data, and the method for obtaining CP data is: obtaining the product identification, batch identification, and wafer identification input by the user, and obtaining the CP data stored corresponding to the product identification, batch identification, and wafer identification from the database. Among them, the product identification (Product Id) is used to refer to the product, the batch identification (Lot Id) is used to refer to the batch of the product, and the wafer identification (Wafer Id) is used to refer to the wafer. A wafer processing plant will set up multiple batches for a product, and each batch contains multiple wafers.

[0073] Exemplarily, the test data corresponding to defect detection is defect data, and the method for obtaining defect data is: obtaining the product identification, batch identification and wafer identification input by the user, and obtaining the defect data stored corresponding to the product identification, batch identification and wafer identification from the database.

[0074] Exemplarily, the test data corresponding to the WAT test is WAT data, and the method for obtaining the WAT data is: obtaining the product identification, batch identification and wafer identification input by the user, and obtaining the WAT data stored corresponding to the product identification, batch identification and wafer identification from the database.

[0075] The database contains data at multiple levels, including wafer level, lot level, and location chip level, while defect data and WAT data are obtained from the data at the location chip level.

[0076] It should be noted that the user can customize the marking rules corresponding to a product. Accordingly, the electronic device executes the wafer marking image generation method provided in this application on the wafers related to the product to obtain the marking image corresponding to each wafer.

[0077] It should be noted that the electronic device may also import test data corresponding to various tests in advance, so that in step S102, corresponding test data is obtained from the imported data, for example, WAT data, defect data, and CP data.

[0078] Step S103 : determining a target position chip that meets the marking rule from a plurality of position chips on the wafer according to the test data.

[0079] Among them, the target position chip is also the position chip with quality risks. Exemplarily, the implementation method of step S103 includes: judging each position chip on the wafer in turn to determine whether the position chip complies with the marking rule, and generating reference information corresponding to the position chip for each position chip judged. Among them, the reference information includes the judgment result of the position chip for the marking rule, and the judgment result is used to indicate whether the position chip complies with the marking rule. Exemplarily, if it complies, the judgment result is 1, and if it does not comply, the judgment result is 0. For any position chip on the wafer, if the reference information corresponding to the position chip indicates that the position chip complies with the marking rule, the position chip is determined to be the target position chip. In the above operation, when judging each position chip on the wafer in turn, it can be judged in turn according to the position of the position chip on the wafer. Exemplarily, the position is expressed in the form of coordinates.

[0080] In this embodiment, after step S103, tag information corresponding to each position chip is generated, and the coordinates corresponding to each position chip are stored in association with the tag information to generate a tag map. The coordinates corresponding to the position chip are used to represent the position of the position chip on the wafer. The coordinate representation method can be set according to actual needs and is not limited in this embodiment.

[0081] In an optional implementation, the tag information corresponding to the position chip is determined by the test result of the target test and whether there is a quality risk. Accordingly, for any position chip on the wafer, if the position chip is the target position chip, the tag information corresponding to the position chip is determined to have a quality risk; if the position chip is not the target position chip and the test result of the position chip is a pass, the tag information corresponding to the position chip is determined to have a pass; if the position chip is not the target position chip and the test result of the position chip is a fail, the tag information corresponding to the position chip is determined to have a test fail.

[0082] Step S104 , generating a marking map corresponding to the wafer based on the coordinates and marking information corresponding to each chip at each position on the wafer; the marking information indicates whether the test has passed, failed, or there is a quality risk.

[0083] The format of the marking map can be set according to actual needs and is not limited in this embodiment. For example, the format is a text document (txt). When generating the marking map, different symbols can be used for different marking information to facilitate differentiation. The symbols corresponding to different marking information can be set according to actual needs and are not limited in this embodiment. For example, the marking map is displayed in the form of a text document, with the symbol "1" representing the position chip that passed the test, the symbol "X" representing the position chip that failed the test, and the symbol "R" representing the position chip with quality risk.

[0084] After the signature map is generated, it can be stored so that the user can send the signature map to the downstream packaging factory according to business needs. Specifically, the wafer identification corresponding to the wafer and the signature map are stored accordingly, so that the signature map can be obtained according to the wafer identification later.

[0085] After the markup map is generated, the markup map can be output for user viewing, for example, by displaying or downloading it locally.

[0086] This embodiment provides a solution for screening and marking position chips on a wafer to obtain a marking map. The user only needs to customize the corresponding marking rules for a certain test according to actual business needs. By dividing the corresponding test data according to the test, the target position chip that meets the marking rules is determined from multiple position chips on the wafer, and a marking map is generated. This realizes the automatic screening of position chips, can meet the diverse business needs of users, and eliminates the need for users to manually write code according to different business needs, thereby improving marking efficiency.

[0087] In an exemplary embodiment, when customizing marking rules, a user selects a target test that meets the requirements from multiple tests, thereby setting corresponding marking rules for the target test. Accordingly, the implementation of step S101 includes: determining the target test selected by the user from the multiple tests; and obtaining the marking rules set by the user for the target test.

[0088] Among them, the multiple tests include at least two of Defect, Inline / Offline Metrology, WAT test and CP test. Specifically, the electronic device displays the selection controls corresponding to each test in the multiple tests, and the user triggers any selection control through the electronic device. After the selection is completed, the electronic device determines that the test to which the triggered test control belongs is the target test. The user can also set corresponding marking rules for the target test, and accordingly, the electronic device obtains the set marking rules. Among them, the style of the selection control can be set as needed, for example, the style of the selection control is a button.

[0089] In this embodiment, when customizing marking rules, the user can select a target test that meets the requirements from a variety of tests and set corresponding marking rules for the selected target test, thereby meeting the user's business needs as much as possible.

[0090] Based on the above embodiment, optionally, the implementation method of obtaining the marking rules set by the user for the target test includes: displaying the rule setting items corresponding to the target test; obtaining the setting item values ​​entered by the user for the rule setting items; and generating the marking rules corresponding to the target test based on the rule setting items corresponding to the target test and the corresponding setting item values.

[0091] The content and quantity of the rule setting items may be set according to specific tests, and this embodiment does not limit this.

[0092] In this embodiment, when customizing marking rules, the user can set corresponding rule setting items for the selected target test according to actual needs, thereby obtaining marking rules corresponding to the target test, which is highly flexible.

[0093] The following uses CP test, defect detection and WAT test as examples to illustrate the process of customizing marking rules and determining the target position chip.

[0094] In the first case, the target test is the CP test.

[0095] Optionally, the rule setting items corresponding to the CP test include the distance between the position chip and the position chip that failed the test. Among them, test failure means that the test result of the CP test is a test failure. The position chip that is closer to the position chip that failed the test is very likely to have a quality risk, while the position chip that is farther away from the position chip that failed the test is unlikely to have a quality risk, so the user can flexibly set the value of the distance according to actual needs. Among them, the distance between the two position chips can be expressed by coordinates, and the coordinates of the position chip that failed the test are (x0, y0). If the coordinates (x, y) of any position chip on the wafer satisfy |x-x0|<=ink range, |y-y0|<=ink range, and ink range is the value of the distance, then this position chip is the target position chip. For example, if the value of the distance is 0, 1, 2, or 3, then for a position chip on the wafer that failed the test, the number of target position chips determined around it is 0, 8, 24, and 48, respectively.

[0096] Optionally, the rule settings for the CP test also include the category of the location chips that failed the test. In one application scenario, after the CP test, the location chips are classified to obtain the category (Softbin) to which each location chip belongs. In some scenarios, the user may only want to filter location chips of a specific category. Therefore, the rule settings for the CP test also include the category to which the location chips that failed the test belong, so that the user can set the category value according to actual needs.

[0097] In actual applications, when generating marking rules corresponding to the CP test based on the rule setting items corresponding to the CP test and the corresponding setting item values, if the user only sets the distance value corresponding to the distance between the position chip that failed the test, the corresponding marking rule is that the distance between the position chip that failed the test is less than or equal to the distance value; if the user sets both the distance value corresponding to the distance between the position chip that failed the test and the category value corresponding to the category to which the position chip that failed the test belongs, the corresponding marking rule is that the distance between the position chip that belongs to the preset category and failed the test is less than or equal to the distance value, wherein the preset category refers to the category referred to by the category value set by the user.

[0098] In this case, illustratively, the implementation of step S103 includes:

[0099] For each chip on the wafer, perform the following operations in sequence:

[0100] If the test data corresponding to the chip at the current position indicates that the chip at the current position fails the test, the chip at the current position is skipped;

[0101] If the test data corresponding to the chip at the current position indicates that the chip at the current position has passed the test, then determine whether the chip at the current position meets the marking rule;

[0102] If there is no test data corresponding to the chip at the current position, the chip at the current position is determined as the chip at the target position.

[0103] If the target test is a CP test, the test data acquired in step S102 includes the wafer's CP data. The wafer's CP data includes the CP data corresponding to each chip at the wafer position that has undergone a CP test. Accordingly, the test data corresponding to the chip at the current position in the above operation refers to this CP data. This CP data includes the CP test result for the chip at that position, which can be either a pass or a fail.

[0104] Among them, for the position chip that failed the test, the test failed precisely because of the existence of quality problems, and this application is to screen the position chips with quality risks other than the position chip that failed the test, so the position chip that failed the test can be skipped directly; for the position chip that passed the test, since the position chip may be located around the position chip that failed the test, it is necessary to determine whether the position chip meets the marking rules; for the position chip that has no corresponding test data, there is no corresponding test data as a basis for determining whether the position chip has a quality risk. In order to reduce the losses caused by the failure of the subsequent process, it can be directly considered that the position chip has a quality risk and it can be determined as the target position chip.

[0105] Regarding how to determine whether there is test data corresponding to the current position chip: the position chip that has passed the CP test has corresponding CP data, while the position chip that has not passed the CP test does not have corresponding CP data, and the CP data of each position chip on the wafer is stored corresponding to its coordinates. Therefore, it can be determined whether there is CP data stored corresponding to the coordinates of the current position chip in the CP data of the wafer. If there is, it means that there is test data corresponding to the current position chip. If not, it means that there is no test data corresponding to the current position chip.

[0106] In this embodiment, for the case where the target test is a CP test, an implementation method is provided for determining the target position chip that meets the marking rules from the wafer. This implementation method takes into account a variety of situations and provides corresponding determination methods for the position chips that failed the test, the position chips that passed the test, and the position chips that were not tested, and has strong adaptability.

[0107] In the second case, the target test is defect detection.

[0108] Optionally, the rule setting items corresponding to defect detection include multiple defect parameter items. Exemplarily, the multiple defect parameter items include defect class number, defect size, defect area, equipment ID, layer step ID, and recipe ID.

[0109] In actual applications, when customizing marking rules, users can input setting item values ​​for at least one defect parameter item according to actual business needs, and each defect parameter item and the corresponding setting item value can be regarded as a screening condition, so that when the electronic device generates a marking rule based on the at least one defect parameter item and the corresponding setting item value, the generated marking rule contains at least one screening condition, and only the position chips that meet the at least one screening condition at the same time are considered to comply with the marking rule. For example, the setting item value entered by the user for the defect type number is 1, and the setting item value entered for the layer process identifier is A, then the marking rule corresponding to the defect detection is the defect type number is 1 and the layer process identifier is A. Correspondingly, for any position chip on the wafer, if the defect type number of the position chip is 1 and the layer process identifier is A, it means that the position chip complies with the marking rule corresponding to the defect detection.

[0110] In this case, optionally, the implementation of step S103 includes: for each position chip on the wafer, if the defect data corresponding to the position chip is consistent with the marking rule, then determining that the position chip is a target position chip that complies with the marking rule.

[0111] In the third case, the target test is the WAT test.

[0112] Optionally, the rule setting items corresponding to the WAT test include multiple WAT parameter items. Exemplarily, the multiple WAT parameter items include a parameter threshold (Parameter Limit), an equipment identifier (Equipment Id), and a scanning recipe identifier (Recipe Id).

[0113] In actual applications, when customizing marking rules, users can input setting item values ​​for at least one WAT parameter item based on actual business needs, and each WAT parameter item and the corresponding setting item value can be regarded as a filtering condition. Therefore, when the electronic device generates a marking rule based on the at least one WAT parameter item and the corresponding setting item value, the generated marking rule includes at least one filtering condition, and only the location chip that meets the at least one filtering condition at the same time is considered to comply with the marking rule.

[0114] Among them, the parameter threshold refers to the threshold range that users can set for a specific WAT parameter according to actual needs. If the true value of the shot for this WAT parameter meets the threshold range, it means that the shot meets the corresponding screening conditions. When performing WAT testing on the wafer, one shot is tested at a time, and one shot contains multiple position chips. For example, the number of position chips contained in a shot is 9 or 30. If a WAT ​​parameter of a shot is abnormal, it means that there is a position chip with an abnormal WAT parameter in this shot. For example, the WAT parameter is parameter A. When the value of parameter A is greater than 10, it belongs to the normal range, and when it is less than or equal to 10, it belongs to the abnormal range. In order to filter out position chips with quality risks from the wafer based on the WAT data, the user needs to filter out position chips with abnormal WAT parameters from the wafer as much as possible. Therefore, the parameter threshold can be set to a value of parameter A less than or equal to 10.

[0115] In this case, step S103 may optionally be implemented by randomly selecting a preset number of position chips from each shot in the wafer, if the WAT data corresponding to the shot matches the marking rule corresponding to the WAT test, or selecting a preset number of position chips from the periphery of the shot, and determining the selected position chips as target position chips that meet the marking rule. The preset number may be set as needed and is not limited in this embodiment.

[0116] In this embodiment, corresponding rule setting items are provided for the three tests respectively, which has strong richness and flexibility.

[0117] It should be noted that the above-mentioned defect parameter items and WAT parameter items are only examples. When implementing the method provided in this application, those skilled in the art may set the defect parameter items and WAT parameter items as needed, and this embodiment does not limit this.

[0118] In an exemplary embodiment, after step S104, the marking yield (InkYield) corresponding to the wafer may also be determined. Accordingly, the method provided in this application further includes the following steps 1-2.

[0119] Step 1: Determine the marking yield as the ratio of the number of position chips on the wafer that have passed the test and do not have quality risks to the total number of position chips on the wafer.

[0120] Step 2: Output the marked yield.

[0121] Among them, the position chip being tested refers to the position chip on the wafer that has undergone the target test, and after the target test, the position chip has its own test result, and the test result indicates that the test passed or failed. The target position chip determined in this application is a chip that complies with the marking rules, that is, a chip with quality risks. Since the position chips that pass the test and do not have quality risks are usable, and the position chips with quality risks and the position chips that fail the test are not usable, the ratio of the number of position chips that pass the test and do not have quality risks to the total number of position chips on the wafer can be determined as the marking yield.

[0122] In this embodiment, after generating the marking image corresponding to the wafer, the marking yield corresponding to the wafer may be determined and output for the user to view.

[0123] In one application scenario, there may be position chips on the wafer that have not undergone the target test. Accordingly, the method provided in the present application further includes, before step 1, determining whether the wafer is a full-image test. Accordingly, if the wafer is a full-image test, steps 1-2 are executed; otherwise, the product of the reference yield and the wafer yield is determined as the marked yield. The reference yield is the difference between 1 and the marked proportion, and the marked proportion is the ratio of the number of target position chips to the total number of position chips on the wafer. The wafer yield refers to the ratio of the number of position chips that have passed the test to the total number of position chips tested.

[0124] For example, if the full map test is performed, the ink yield is calculated as follows: 1-(ink die count + fail die count) / gross die count, where ink die count represents the number of target position chips, fail die count represents the number of position chips that failed the test, and gross die count represents the total number of position chips on the wafer. Therefore, the number of position chips on the wafer that passed the test and do not present quality risks is the total number of position chips on the wafer minus the number of target position chips minus the number of position chips that failed the test.

[0125] For example, if it is not a full-image test, then Ink Yield=(1-Ink Die Count / Gross Die Count)*CP Yield, where CP Yield represents the wafer yield.

[0126] In this embodiment, by first determining whether the wafer is fully tested, the marking yield is calculated for different situations, so that the determined marking yield is more accurate.

[0127] It should be noted that the method for determining whether a wafer is fully tested is: if the total number of position chips on the wafer is the same as the total number of position chips being tested, then the wafer is determined to be fully tested; otherwise, it is determined that the wafer is not fully tested.

[0128] In an exemplary embodiment, after step S104 , the method provided by the present application further includes: in response to a user updating the marking rule, generating an updated marking map of the wafer according to the updated marking rule.

[0129] In this embodiment, after checking the marking yield, the user can also modify and adjust the marking rules according to actual business needs to obtain updated marking rules, so that the electronic device can also execute the wafer marking map generation method provided in this application according to the updated marking rules to generate an updated marking map, and so on, until the user's actual business needs are met.

[0130] In an exemplary embodiment, after step S104, a mark summary information (InkSummary) may be generated and output for the user to view. The format of the mark summary information may be set as needed and is not limited in this embodiment. For example, the format of the mark summary information is Excel.

[0131] For example, if the target test is CP testing, the marking summary information includes: product ID, batch ID, wafer ID, tester ID, test start time, test end time, marking time, total number of position chips on the wafer, total number of position chips tested, number of position chips that passed the test, number of position chips that passed the test but have quality risks, wafer yield, marking yield, number of target position chips, and number of lost position chips. The number of lost position chips refers to the sum of the number of target position chips and the number of position chips that failed the test.

[0132] In an exemplary embodiment, in addition to the above-mentioned method of customizing marking rules, the present application also supports users to set personalized marking rules (Ink Custom). Specifically, the electronic device obtains a location chip list and determines at least one location chip included in the location chip list as a target location chip, and then executes step S104.

[0133] Exemplarily, one way to obtain a list of location chips is for a user to trigger an electronic device to display a wafer map containing all the location chips on a wafer. The user then selects at least one location chip from the wafer map, and the electronic device stores the selected location chip in the list of location chips. Alternatively, another way to obtain a list of location chips is for the user to manually create and import a list of location chips through the electronic device. Exemplarily, the list of location chips to be marked is in a table format.

[0134] For the wafer marking image generation method provided in this application, see Figure 3 If a wafer has quality issues and needs to be marked, the user sets the marking rules (Ink Rules) corresponding to the target test, imports the test data through the electronic device, generates an inkless map (Inkless Map) and marking summary information (Ink Summary), displays the inkless map and marking summary information, and then runs the production line according to the inkless map. Users can also modify the marking rules after viewing the inkless map and marking summary information.

[0135] The above embodiment is described by taking as an example that a user selects a target test from multiple tests for a product, customizes a marking rule for the target test, and generates a marking map according to the marking rule.

[0136] In other embodiments, users can also customize marking rules corresponding to multiple different tests for a product, thereby obtaining multiple marking charts. This makes it easy to switch at any time according to business needs when it is necessary to grade products and set different selling prices.

[0137] In some other embodiments, the user can also perform compound screening for a product by combining multiple tests to generate a marking map. For example, the first test is selected from the multiple tests, and the first marking map of the wafer is generated after the marking rules are customized for the first test. Then, the second test is selected from the multiple tests, and the second marking map is generated on the basis of the first marking map after the marking rules are customized for the second test, and so on, until the final marking map is generated. Among them, the first marking map divides the position chips into three categories for the first test: test passed, test failed, and quality risk. The second marking map divides the position chips into three categories for the first test: test passed, test failed, and quality risk. Test passed means that both the first test and the second test have passed, test failed means that at least one of the first test and the second test has failed, and quality risk means that at least one of the marking rules corresponding to the first test and the marking rules corresponding to the second test is met.

[0138] It can be seen that this application supports users to flexibly customize marking rules according to different business scenarios, and also supports the synchronous processing of large amounts of data, meeting the business needs of multiple products.

[0139] Figure 4 FIG. 1 is a schematic structural diagram of a wafer marking image generating device according to an exemplary embodiment. Figure 4 As shown, in this embodiment, the wafer signature diagram generating device 200 can be set in an electronic device, and the wafer signature diagram generating device 200 includes:

[0140] The first acquisition module 201 is used to obtain a user-defined marking rule for a target test; the marking rule is used to mark the position chip on the wafer;

[0141] The second acquisition module 202 is used to obtain test data of the wafer for the target test;

[0142] A determination module 203 is configured to determine a target position chip that meets the marking rule from a plurality of position chips on the wafer according to the test data;

[0143] The generation module 204 is used to generate a marking map corresponding to the wafer according to the coordinates and marking information corresponding to each chip at each position on the wafer; the marking information indicates whether the test has passed, failed, or there is a quality risk.

[0144] Optionally, the first acquisition module 201 includes:

[0145] A determination unit, used to determine a target test selected by a user among multiple tests;

[0146] The acquisition unit is used to obtain the marking rules set by the user for the target test.

[0147] Optionally, the acquisition unit is used to display the rule setting items corresponding to the target test; obtain the setting item values ​​entered by the user for the rule setting items; and generate the marking rules corresponding to the target test based on the rule setting items corresponding to the target test and the corresponding setting item values.

[0148] Optionally, the multiple tests include wafer testing, wafer acceptance testing and defect detection; wherein, the rule setting items corresponding to the wafer testing include the distance between the chip and the location where the test failed; the rule setting items corresponding to the defect detection include multiple defect parameter items; and the rule setting items corresponding to the wafer acceptance testing include multiple wafer acceptance test parameter items.

[0149] Optionally, the target test is a wafer test, and the determination module 203 is configured to:

[0150] For each chip on the wafer, perform the following operations in sequence:

[0151] If the test data corresponding to the chip at the current position indicates that the chip at the current position fails the test, the chip at the current position is skipped;

[0152] If the test data corresponding to the chip at the current position indicates that the chip at the current position has passed the test, then determine whether the chip at the current position meets the marking rule;

[0153] If there is no test data corresponding to the chip at the current position, the chip at the current position is determined as the chip at the target position.

[0154] Optionally, the wafer marking map generating device 200 also includes a yield determination module; the yield determination module is used to determine the ratio of the number of position chips on the wafer that have passed the test and have no quality risk to the total number of position chips on the wafer as the marking yield; and output the marking yield.

[0155] Optionally, the yield determination module is further configured to determine whether the wafer is fully pattern tested;

[0156] Correspondingly, if the wafer is fully tested, the yield determination module is used to execute the step of determining the ratio of the number of position chips on the wafer that have passed the test and have no quality risk to the total number of position chips on the wafer as the marking yield; conversely, the yield determination module is also used to determine the product of the reference yield and the wafer yield as the marking yield; the reference yield is the difference between 1 and the marked proportion, and the marked proportion is the ratio of the number of target position chips to the total number of position chips on the wafer.

[0157] Optionally, the wafer marking map generating apparatus 200 further includes an updating module, and the updating module is configured to generate an updated wafer marking map according to the updated marking rule in response to a user updating the marking rule.

[0158] The wafer marking image generating device provided in this embodiment can execute the technical solution of the corresponding method embodiment. Its implementation principle and technical effects are similar to those of the corresponding method embodiment, and will not be described in detail here.

[0159] The present application also provides an electronic device. For example, the electronic device is a terminal device used by technicians in a wafer fab. For example, the electronic device is a computer, a workbench, a personal digital assistant, or other suitable terminal device. Figure 5 FIG. 1 is a schematic diagram showing the structure of an electronic device according to an exemplary embodiment. Figure 5 As shown, the electronic device 300 includes: a processor 301 and a memory 302 communicatively connected to the processor 301 .

[0160] The memory 302 stores computer-executable instructions; the processor 301 executes the computer-executable instructions stored in the memory 302 to implement the wafer marking image generation method provided in this application.

[0161] In the embodiment of the present application, the memory 302 and the processor 301 are connected via a bus. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, and the like.

[0162] The components, their connections and relationships, and their functions shown herein are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein. The various components are interconnected using different buses and can be mounted on a common motherboard or in other ways as needed.

[0163] In an exemplary embodiment, a computer-readable storage medium is further provided, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the wafer marking image generation method provided in the present application.

[0164] In an exemplary embodiment, a computer program product is also provided, comprising computer-executable instructions. When the computer-executable instructions in the computer program product are executed by a processor, the method for generating a wafer marking image provided in the present application is used to implement the method.

[0165] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required by this application.

[0166] It should be further noted that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the flowchart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0167] It should be understood that the above-described device embodiments are merely illustrative, and the device of the present application may also be implemented in other ways. For example, the division of units / modules in the above-described embodiments is merely a logical functional division, and actual implementations may employ other division methods. For example, multiple units, modules, or components may be combined or integrated into another system, or some features may be omitted or not implemented.

[0168] In addition, unless otherwise specified, the functional units / modules in the various embodiments of the present application may be integrated into a single unit / module, each unit / module may exist physically separately, or two or more units / modules may be integrated together. The aforementioned integrated units / modules may be implemented in the form of hardware or software program modules.

[0169] If the integrated unit / module is implemented in hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, the processor may be any appropriate hardware processor, such as a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a digital signal processor (DSP), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic components. Unless otherwise specified, the memory may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a USB flash drive, random-access memory (RAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), enhanced dynamic random-access memory (EDRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), high-bandwidth memory (HBM), hybrid memory cube (HMC), and other media that can store program code.

[0170] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a memory and includes a number of instructions for enabling an electronic device to execute all or part of the steps of the various embodiments of the method of the present application.

[0171] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0172] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0173] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for generating a wafer marking image, characterized in that: include: Obtaining a user-defined marking rule for a target test; the marking rule is used to mark a position chip on a wafer; Acquiring test data of the wafer for the target test; Determining, based on the test data, a target position chip that meets the marking rule from a plurality of position chips on the wafer; A marking map corresponding to the wafer is generated based on the coordinates and marking information corresponding to each chip at each position on the wafer; the marking information indicates whether the test passed, failed, or there is a quality risk.

2. The method according to claim 1, characterized in that The step of obtaining the user-defined marking rules for the target test includes: Determine the target test selected by the user among multiple tests; Get the marking rules set by the user for the target test.

3. The method according to claim 2, characterized in that The obtaining of the marking rules set by the user for the target test includes: Display the rule setting items corresponding to the target test; Obtaining the setting item value entered by the user for the rule setting item; According to the rule setting items corresponding to the target test and the corresponding setting item values, a marking rule corresponding to the target test is generated.

4. The method according to claim 3, characterized in that The various tests include wafer testing, wafer acceptance testing, and defect detection; Among them, the rule setting items corresponding to the wafer test include the distance between the chip and the location where the test failed; the rule setting items corresponding to the defect detection include multiple defect parameter items; and the rule setting items corresponding to the wafer acceptability test include multiple wafer acceptable test parameter items.

5. The method according to claim 1, wherein The target test is a wafer test, and determining a target position chip that meets the marking rule from a plurality of position chips on the wafer according to the test data includes: For each chip on the wafer, perform the following operations in sequence: If the test data corresponding to the chip at the current position indicates that the chip at the current position fails the test, the chip at the current position is skipped; If the test data corresponding to the chip at the current position indicates that the chip at the current position has passed the test, determining whether the chip at the current position meets the marking rule; If there is no test data corresponding to the chip at the current position, the chip at the current position is determined as the chip at the target position.

6. The method according to claim 1, characterized in that Also includes: The ratio of the number of position chips on the wafer that passed the test and had no quality risk to the total number of position chips on the wafer is determined as the marking yield; The marked yield is output.

7. The method according to claim 6, characterized in that Before determining the ratio of the number of position chips on the wafer that have passed the test and do not have quality risks to the total number of position chips on the wafer as the marking yield, the method further includes: Determine whether the wafer is fully pattern tested; Correspondingly, if the wafer is fully tested, the step of determining the marking yield as the ratio of the number of position chips on the wafer that have passed the test and have no quality risk to the total number of position chips on the wafer is performed; otherwise, the product of the reference yield and the wafer yield is determined as the marking yield; the reference yield is the difference between 1 and the marked proportion, and the marked proportion is the ratio of the number of target position chips to the total number of position chips on the wafer.

8. The method according to claim 1, characterized in that After generating a marking map corresponding to the wafer according to the coordinates and marking information corresponding to the chips at each position on the wafer, the method further includes: In response to the user updating the marking rule, an updated marking map of the wafer is generated according to the updated marking rule.

9. A wafer marking pattern generating device, characterized in that: include: The first acquisition module is used to obtain a marking rule customized by the user for the target test; the marking rule is used to mark the position chip on the wafer; A second acquisition module is used to acquire test data of the wafer for the target test; a determination module, configured to determine, based on the test data, a target position chip that meets the marking rule from a plurality of position chips on the wafer; The generation module is used to generate a marking map corresponding to the wafer based on the coordinates and marking information corresponding to each chip at each position on the wafer; the marking information indicates whether the test passed, failed, or there is a quality risk.

10. An electronic device, characterized in that: include: a processor and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the wafer marking image generation method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the wafer marking image generation method according to any one of claims 1 to 8.

12. A computer program product comprising computer-executable instructions, characterized in that: When the computer-executable instructions are executed by a processor, the method for generating a wafer marking image according to any one of claims 1 to 8 is implemented.

Images