A surge protection circuit

Abstract

The application discloses a kind of surge protection circuits, belong to the field of semiconductor surge protection device, including multiple resistors, multiple zener diodes and multiple transistors, the first end of first resistor is connected bus voltage, the first end of first transistor and the second end of second transistor, the second end of first resistor is connected the third end of first transistor and the cathode of first zener diode, the anode of first zener diode is connected the cathode of second zener diode and the third end of third transistor, the anode of second zener diode is connected the second end of third resistor, the second end of third transistor, the first end of second transistor and ground, the second end of first transistor is connected the first end of second resistor, the second end of second resistor is connected the first end of third resistor, the first end of third transistor and the third end of second transistor.The application can solve electrostatic discharge, electric fast transient pulse group, lightning stroke, peak and other surge voltage and transient voltage generated in hot plug process and other problems.

Description

Technical Field

[0001] This invention relates to the field of semiconductor surge protection devices, and more particularly to a surge protection circuit. Background Technology

[0002] In the power supply system of airborne electronic equipment, the airborne power port, as a critical interface for energy transmission, directly affects the reliable operation of downstream circuits and the entire device. In practical applications, this port typically operates under the following conditions:

[0003] Firstly, under normal operating conditions, the port bus withstands a typical input voltage;

[0004] Secondly, since airborne power ports are usually exposed to the external environment to achieve connection functions, they are susceptible to various transient interferences, including but not limited to electrostatic discharge (ESD), electrical fast transient bursts (EFT), lightning strikes, and surge voltages such as spike voltages generated inside the power system.

[0005] Third, during the assembly and maintenance of airborne power systems, the front-end power supply and the back-end circuits are often electrically connected via connectors. The insertion and removal of these connectors puts the ports into a hot-swappable state. Under this condition, the bus voltage will generate a rapid rising edge, and the sudden change in voltage may trigger abnormal circuit responses.

[0006] Taking a typical 28V airborne power supply system as an example, its bus voltage is usually 36V at its highest. Therefore, the withstand voltage of downstream components only needs to be higher than 36V with a certain safety margin. However, the surge voltages caused by electrostatic discharge, electrical fast transient bursts, lightning strikes, spikes, and transient voltages generated during hot-plugging often far exceed 36V. Without protective measures, these surge voltages can easily cause overvoltage damage to downstream circuits. Therefore, appropriate protection circuits must be added at the ports. Summary of the Invention

[0007] The present invention aims to provide a surge protection circuit.

[0008] To achieve the above objectives, the technical solution of the present invention is as follows:

[0009] A surge protection circuit includes multiple resistors, multiple Zener diodes, and multiple transistors. A first terminal of a first resistor is connected to a bus voltage, a first terminal of a first transistor, and a second terminal of a second transistor. The second terminal of the first resistor is connected to a third terminal of the first transistor and the cathode of a first Zener diode. The anode of the first Zener diode is connected to the cathode of a second Zener diode and the third terminal of the third transistor. The anode of the second Zener diode is connected to a second terminal of the third resistor, a second terminal of the third transistor, a first terminal of the second transistor, and ground. The second terminal of the first transistor is connected to a first terminal of the second resistor. The second terminal of the second resistor is connected to a first terminal of the third resistor, a first terminal of the third transistor, and a third terminal of the second transistor.

[0010] In one specific embodiment, the third transistor operates as follows: when V GS_Q3 <V GS(th)_Q3 When V is active, the third transistor remains normally open; when V is active... GS_Q3 ≥V GS(th)_Q3 When the third transistor is turned off, V GS(th)_Q3 >0, V GS_Q3 V is the gate-source voltage of the third transistor. GS(th)_Q3 The gate-source threshold voltage of the third transistor is denoted as .

[0011] Furthermore, the first transistor and the second transistor are MOSFETs.

[0012] Furthermore, the first transistor is a P-type MOSFET, and the second transistor is an N-type MOSFET.

[0013] Furthermore, the third transistor is a JFET.

[0014] Furthermore, the third transistor is a P-type JFET.

[0015] Furthermore, when the bus voltage is lower than the sum of the breakdown voltages of the first Zener diode and the second Zener diode, the first Zener diode and the second Zener diode are turned off, the first transistor is turned off, the second transistor is turned off, and the third transistor is turned on.

[0016] Furthermore, when the bus voltage is higher than the sum of the breakdown voltages of the first Zener diode and the second Zener diode, the first Zener diode and the second Zener diode are turned on, the first transistor is turned on, the second transistor is turned on, and the third transistor is turned off.

[0017] Furthermore, when the bus voltage has a fast rising edge, the first Zener diode and the second Zener diode are turned off, the first transistor is turned on, the second transistor is turned off, and the third transistor is turned on.

[0018] Furthermore, the first terminal of each transistor is its source, the second terminal of each transistor is its drain, and the third terminal of each transistor is its gate.

[0019] Beneficial effects: When the bus voltage is lower than the sum of the breakdown voltages of the first and second Zener diodes, the surge protection circuit of this invention does not operate, and in this operating mode, the third transistor remains normally open. When the bus voltage rises above the sum of the breakdown voltages of the first and second Zener diodes, the third transistor changes from normally open to off without affecting the normal operation of the surge protection circuit. At this time, the second transistor conducts, discharging the bus current and providing surge protection. When there is a fast rising edge in the bus voltage, the third transistor remains normally open, effectively preventing the second transistor from being mistakenly turned on at lower bus voltages and preventing over-power damage to the second transistor. This invention can significantly solve problems such as surge voltages caused by electrostatic discharge, electrical fast transient bursts, lightning strikes, spikes, and transient voltages generated during hot-plugging.

[0020] To make the above-mentioned features and advantages of the invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a surge protection circuit according to the present invention.

[0022] Figure 2 This is a schematic diagram of the current path of a surge protection circuit according to the present invention.

[0023] Figure 3 This is a simulation circuit diagram of a surge protection circuit according to the present invention.

[0024] Figure 4 The diagram shows a comparison of the simulation waveforms of a traditional surge protection circuit and a surge protection circuit of the present invention. Detailed Implementation

[0025] To make the objectives and technical solutions of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0026] Figure 1 This is a circuit diagram of a surge protection circuit according to the present invention. Figure 1 As shown, a surge protection circuit includes multiple resistors, multiple Zener diodes, and multiple transistors. The first terminal of resistor R1 is connected to the bus voltage V. BUS The first terminal of transistor Q1 and the second terminal of transistor Q2 are connected. The second terminal of resistor R1 is connected to the third terminal of transistor Q1 and the cathode of Zener diode D1. The anode of Zener diode D1 is connected to the cathode of Zener diode D2 and the third terminal of transistor Q3. The anode of Zener diode D2 is connected to the second terminal of resistor R3, the second terminal of transistor Q3, the first terminal of transistor Q2, and ground. The second terminal of transistor Q1 is connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to the first terminal of resistor R3, the first terminal of transistor Q3, and the third terminal of transistor Q2.

[0027] Optionally, transistors Q1 and Q2 are MOSFETs, transistor Q3 is a JFET, the first terminal of each transistor is its source, the second terminal of each transistor is its drain, and the third terminal of each transistor is its gate.

[0028] More specifically, transistor Q1 is a P-type MOSFET, transistor Q2 is an N-type MOSFET, and transistor Q3 is a P-type JFET.

[0029] More specifically, the operating characteristics of transistor Q3 are as follows: when V GS_Q3 <V GS(th)_Q3 When V is normally open, transistor Q3 remains open; when V is closed... GS_Q3 ≥V GS(th)_Q3 When this occurs, transistor Q3 is turned off, where V GS(th)_Q3 >0, V GS_Q3 V is the gate-source voltage of transistor Q3. GS(th)_Q3 This is the gate-source threshold voltage of transistor Q3.

[0030] Figure 2 This is a schematic diagram of the current path of a surge protection circuit according to the present invention. The following will be combined with... Figure 2 The working process of the surge protection circuit of the present invention is described in three working modes.

[0031] When the bus voltage V BUS When the voltage is lower than the sum of the breakdown voltages of Zener diodes D1 and D2, Zener diodes D1 and D2 are cut off, and no current flows through this path. The gate-source voltage V of transistor Q1... GS_Q1 When the voltage is 0, transistor Q1 is off, and at this time the gate-source voltage V of transistor Q2 is 0. GS_Q2 With no charging current, transistor Q2 is cut off, and the surge protection circuit of this invention does not operate. In this operating mode, transistor Q3 remains normally open.

[0032] When the bus voltage V BUS The voltage rises above the sum of the breakdown voltages of Zener diodes D1 and D2, i.e., V. BUS >V BR_D1 +V BR_D2 At that time, V GS_Q3 = V BR_D2 V BR_D1 V is the breakdown voltage of diode D1. BR_D2 This is the breakdown voltage of diode D2. Select appropriate parameters for the Zener diode D2 and set V... BR_D2 >V GS(th)_Q3 Therefore, transistor Q3 changes from the normally on state to the off state. For example... Figure 2 As shown, since the current flows along the first path from the bus voltage V BUS The gate-source capacitance C of transistor Q1 GS_Q1 With Zener diodes D1 and D2 flowing through them, the gate-source voltage V of transistor Q1 is... GS_Q1 The gate-source threshold voltage V of transistor Q1 is greater than GS(th)_Q1 When transistor Q1 is turned on, current flows along the second path from the bus voltage V. BUS Transistor Q1, resistor R2, gate-source capacitance C of transistor Q2 GS_Q2 The gate-source voltage V of transistor Q2 flows through it. GS_Q2 The gate-source threshold voltage V of transistor Q2 is greater than GS(th)_Q2 When transistor Q2 is turned on, it discharges the bus current, thus providing surge protection. Therefore, under this operating condition, transistor Q3 will not affect the normal operation of the surge protection circuit.

[0033] When the bus voltage V BUS When a fast rising edge exists, the current flows along the third path from the bus voltage V. BUS The drain-source junction capacitance C of transistor Q1 DS-Q1 Resistor R2, transistor Q3, and the drain-source junction capacitance C of transistor Q1 are all present. DS-Q1 Coupled current is generated due to the fast rising edge, and due to the bus voltage V BUS The voltage is low; both Zener diodes D1 and D2 are in the off state, and the gate-source voltage V of transistor Q3 is low. GS_Q3 Less than the gate-source threshold voltage V of transistor Q3 GS(th)_Q3 Transistor Q3 is in the normally open state, discharging the coupling current, and the gate-source voltage V of transistor Q2 is... GS_Q2 The voltage V is always below the gate-source threshold voltage of transistor Q2. GS(th)_Q2Transistor Q2 remains off. Without transistor Q3, transistor Q2 might mistakenly turn on at a lower bus voltage. Since the source resistance of the bus voltage is generally low, premature turn-on would cause excessive energy to be released into the surge protection circuit, potentially damaging transistor Q2 due to over-power discharge.

[0034] Figure 3 This is a simulation circuit diagram of a surge protection circuit according to the present invention. Figure 3 As shown, the first terminal of resistor R1 is the surge protection circuit's terminal voltage V. z The second terminal of resistor R2 is the driving voltage V. gs I ds To discharge current. Because the bus voltage V in the simulation... BUS With surge protection circuit terminal voltage V z When directly connected, the surge protection circuit's terminal voltage V z Always equal to bus voltage V BUS The surge protection circuit cannot display the actual terminal voltage, therefore the bus voltage V... BUS An internal resistance R of the power supply is added between the surge protection circuit and the surge protection circuit. i In the simulation, it was set to a fixed value of 2 ohms.

[0035] Simulation verification was performed using LTSPICE software. Figure 4 This is a comparison of simulation waveforms between a traditional surge protection circuit and a surge protection circuit of the present invention. BUS V is the bus voltage. z_before To improve the terminal voltage of traditional surge protection circuits, I ds_ before To improve the discharge current of transistor Q2 in the traditional surge protection circuit, V gs_ before To improve the drive voltage of transistor Q2 in the traditional surge protection circuit; V z_after To improve the terminal voltage of the surge protection circuit of the present invention, I ds_ after To improve the discharge current of transistor Q3 in the surge protection circuit of the present invention, V gs_ after To improve the surge protection circuit of the present invention, the driving voltage of transistor Q3 is improved, wherein V BUS The rise rate is set to 28V / 30ns. It can be seen that before the improvement measures were implemented, the surge protection circuit activated prematurely, V z_before Below V for an extended period of time BUS For a long time, I ds_ before The value is not zero, indicating that the surge protection circuit has been subjected to power for an extended period due to accidental activation. After implementing improvement measures, the accidental activation phenomenon has been significantly reduced. z_after rate of ascent and V BUS Almost identical, I ds_ afterThe duration and peak size of V were both significantly reduced. gs From the waveform, V gs_ after Compared to V gs_ before With a slower rise time and amplitude, transistor Q3 has a lower turn-on degree. Simulation results show that this method can effectively suppress the false turn-on problem caused by hot-plugging in surge protection circuits.

[0036] In summary, when the bus voltage V BUS When the voltage drops below the sum of the breakdown voltages of Zener diodes D1 and D2, the surge protection circuit of this invention does not operate. In this operating mode, transistor Q3 remains normally open. When the bus voltage V... BUS When the voltage rises above the sum of the breakdown voltages of Zener diodes D1 and D2, transistor Q3 changes from its normally open state to its off state without affecting the normal operation of the surge protection circuit. At this time, transistor Q2 conducts, discharging the bus current and providing surge protection. When the bus voltage V... BUS When a fast rising edge is present, transistor Q3 is in a normally on state, which can effectively prevent transistor Q2 from being mistakenly turned on under low bus voltage and prevent transistor Q2 from being damaged by overpower. This invention can significantly solve problems such as electrostatic discharge, electrical fast transient bursts, lightning strikes, surge voltages, and transient voltages generated during hot-plugging.

[0037] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A surge protection circuit, characterized by, The first end of the first resistor is connected to a bus voltage, the first end of the first transistor and the second end of the second transistor, the second end of the first resistor is connected to the third end of the first transistor and the cathode of the first zener diode, the anode of the first zener diode is connected to the cathode of the second zener diode and the third end of the third transistor, the anode of the second zener diode is connected to the second end of the third resistor, the second end of the third transistor, the first end of the second transistor and ground, the second end of the first transistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the third resistor, the first end of the third transistor and the third end of the second transistor; When the bus voltage is lower than the sum of the breakdown voltages of the first and second zener diodes, the first and second zener diodes are off, the first transistor is off, the second transistor is off, and the third transistor is on; When the bus voltage is higher than the sum of the breakdown voltages of the first and second zener diodes, the first and second zener diodes are on, the first transistor is on, the second transistor is on, and the third transistor is off; When there is a fast rising edge in the bus voltage, the first and second zener diodes are off, the first transistor is on, the second transistor is off, and the third transistor is on.

2. A surge protection circuit as claimed in claim 1, characterized in that The third transistor has a working characteristic that when V GS_Q3 <V GS(th)_Q3 , the third transistor is always on; when V GS_Q3 ≥V GS(th)_Q3 , the third transistor is off, wherein V GS(th)_Q3 >0, V GS_Q3 is a gate-source voltage of the third transistor, and V GS(th)_Q3 is a gate-source threshold voltage of the third transistor.

3. A surge protection circuit as claimed in claim 2, wherein the first and second voltage clamping devices are connected in series between the input and the output of the surge protection circuit. The first and second transistors are MOSFETs.

4. A surge protection circuit as claimed in claim 3, wherein the voltage divider comprises a first resistor and a second resistor connected in series, the first resistor having a resistance value of 1.5 times the resistance value of the second resistor. The first transistor is a P-type MOSFET and the second transistor is an N-type MOSFET.

5. A surge protection circuit as claimed in claim 4, wherein the voltage divider comprises a first resistor and a second resistor connected in series, the first resistor having a resistance value of 1.5 times the resistance value of the second resistor. The third transistor is a JFET.

6. A surge protection circuit as claimed in claim 5, wherein the voltage divider comprises a first resistor and a second resistor connected in series, the first resistor having a resistance value of 1.5 times the resistance value of the second resistor. The third transistor is a P-type JFET.

7. A surge protection circuit as claimed in claim 6, wherein the voltage divider comprises a first resistor and a second resistor connected in series, the first resistor having a resistance value of 1.5 times the resistance value of the second resistor. The first end of each transistor is its source, the second end of each transistor is its drain, and the third end of each transistor is its gate.

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