Electrostatic discharge protection circuit and electronic device

Abstract

The invention provides an electrostatic discharge protection circuit and an electronic device. The electrostatic discharge protection circuit includes: a current discharge transistor; the current discharge transistor is connected between a first node and a second node; wherein the current discharge transistor is used for discharging electrostatic pulses between a first node and a second node in a conducting state; a mirror current module; the mirror image current module is used for generating a mirror image driving current based on the electrostatic pulse; a voltage generation module; and the voltage generation module is used for generating a driving voltage signal based on the mirror image driving current so as to drive the current discharge transistor to be conducted.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to an electrostatic discharge protection circuit and an electronic device. Background Art

[0002] Electrostatic discharge (ESD) is the primary cause of electrical overstress damage to most electronic components. For example, gallium nitride high electron mobility transistors (GaN HEMTs) are particularly susceptible to ESD damage due to their device structure, and therefore generally require ESD protection circuits.

[0003] Therefore, how to provide ESD protection for electronic components is an urgent problem to be solved. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an electrostatic discharge protection circuit and an electronic device.

[0005] According to a first aspect of an embodiment of the present disclosure, an electrostatic discharge protection circuit is provided, the electrostatic discharge protection circuit comprising:

[0006] A current discharge transistor; the current discharge transistor is connected between the first node and the second node; wherein the current discharge transistor is used to discharge electrostatic pulses between the first node and the second node in a conductive state;

[0007] A mirror current module; the mirror current module is used to generate a mirror drive current based on the electrostatic pulse;

[0008] A voltage generating module; the voltage generating module is used to generate a driving voltage signal based on the mirror driving current to drive the current discharge transistor to turn on.

[0009] In some embodiments, the voltage generating module includes a fourth resistor, and the current mirroring module includes a first transistor, a second transistor, a second resistor, a third resistor, and a first resistor, wherein:

[0010] The first end of the first resistor, the first end of the second resistor and the first node are connected;

[0011] The gate of the first transistor, the drain of the first transistor and the gate of the second transistor are connected as a third node;

[0012] The second end of the second resistor is connected to the third node;

[0013] The second end of the first resistor is connected to the drain of the second transistor;

[0014] A first end of the third resistor is connected to the source of the first transistor;

[0015] The source of the second transistor is connected to the control terminal of the current discharge transistor as a fourth node;

[0016] The first end of the fourth resistor is connected to the fourth node;

[0017] The second end of the third resistor, the second end of the fourth resistor, and the second node are connected.

[0018] In some embodiments, the electrostatic discharge protection circuit further includes at least one first diode sequence, wherein the first diode sequence includes at least one diode connected in series in the same direction; wherein the first diode sequence is provided in at least one of the following:

[0019] connected in series with the second resistor between the first node and the third node, wherein the forward conduction direction of the first diode sequence is toward the third node;

[0020] connected in series with the first resistor between the first node and the drain of the second transistor, wherein the forward conduction direction of the first diode sequence is toward the drain of the second transistor;

[0021] connected in series with the third resistor between the source of the first transistor and the second node, wherein the forward conduction direction of the first diode sequence is toward the second node;

[0022] The first diode sequence is connected in series with the fourth resistor between the fourth node and the second node, wherein the forward conduction direction of the first diode sequence is toward the second node.

[0023] In some embodiments, the mirror current module includes a first mirror current module and a second mirror current module; the voltage generating module includes a first voltage generating module and a second voltage generating module; wherein,

[0024] The first mirror current module is used to generate a first mirror driving current based on a first electrostatic pulse on the first node;

[0025] The first voltage generating module is configured to generate a first driving voltage signal based on the first mirror driving current to drive the current discharge transistor to turn on;

[0026] The second mirror current module is used to generate a second mirror driving current based on a second electrostatic pulse on the second node;

[0027] The second voltage generating module is configured to generate a second driving voltage signal based on the second mirror driving current to drive the current discharge transistor to be turned on.

[0028] In some embodiments, the first voltage generating module includes an eighth resistor;

[0029] The first current mirror module includes a third transistor, a fourth transistor, a seventh resistor, a ninth resistor, a second diode sequence, and a third diode sequence, wherein the second diode sequence includes at least one diode connected in series in the same direction, and the third diode sequence includes at least one diode connected in series in the same direction; wherein,

[0030] The drain of the fourth transistor, the first end of the seventh resistor and the first node are connected;

[0031] The gate of the third transistor, the drain of the third transistor and the gate of the fourth transistor are connected as a fifth node;

[0032] The second end of the seventh resistor is connected to the fifth node;

[0033] The source of the fourth transistor is connected to the control terminal of the current discharge transistor as a sixth node;

[0034] The ninth resistor and the third diode sequence are connected in series between the source of the third transistor and the second node, wherein the forward conduction direction of the third diode sequence is toward the second node;

[0035] The eighth resistor and the second diode sequence are connected in series between the sixth node and the second node, wherein the forward conduction direction of the second diode sequence is toward the second node;

[0036] The second voltage generating module includes an eleventh resistor;

[0037] The second current mirror module includes a fifth transistor, a sixth transistor, a tenth resistor, a twelfth resistor, a fourth diode sequence and a fifth diode sequence, wherein the fourth diode sequence includes at least one diode connected in series in the same direction, and the fifth diode sequence includes at least one diode connected in series in the same direction; wherein,

[0038] The drain of the sixth transistor, the second end of the tenth resistor and the second node are connected;

[0039] The gate of the fifth transistor, the drain of the fifth transistor, and the gate of the sixth transistor are connected as a seventh node;

[0040] The first end of the tenth resistor is connected to the seventh node;

[0041] The source of the sixth transistor is connected to the sixth node;

[0042] The twelfth resistor and the fifth diode sequence are connected in series between the source of the fifth transistor and the first node, wherein the forward conduction direction of the fifth diode sequence is toward the first node;

[0043] The eleventh resistor and the fourth diode sequence are connected in series between the sixth node and the first node, wherein the forward conduction direction of the fourth diode sequence is toward the first node.

[0044] In some embodiments, the first current mirror module further includes a fifth resistor, and the fifth resistor is arranged between the first node and the drain of the fourth transistor; and / or

[0045] The second current mirror module further includes a sixth resistor, wherein the sixth resistor is arranged between the second node and the drain of the sixth transistor. In some embodiments, the electrostatic discharge protection circuit further includes: at least one sixth diode sequence, wherein the sixth diode sequence includes at least one diode connected in series in the same direction; wherein the sixth diode sequence is arranged in at least one of the following:

[0046] connected in series with the seventh resistor between the first node and the fifth node, wherein the forward conduction direction of the sixth diode sequence is toward the fifth node;

[0047] connected in series with the fifth resistor between the first node and the drain of the fourth transistor, wherein the forward conduction direction of the sixth diode sequence is toward the drain of the fourth transistor;

[0048] connected in series with the tenth resistor between the second node and the seventh node, wherein the forward conduction direction of the sixth diode sequence is toward the seventh node;

[0049] The sixth diode is connected in series with the sixth resistor between the second node and the drain of the sixth transistor, wherein the forward conduction direction of the sixth diode sequence is toward the drain of the sixth transistor.

[0050] In some embodiments, the forward conduction voltage of the second diode sequence is less than the conduction voltage of the control terminal of the current discharge transistor; and / or

[0051] The forward conduction voltage of the fourth diode sequence is less than the conduction voltage of the control terminal of the current discharge transistor.

[0052] In some embodiments, the current discharge transistor comprises a bidirectional conduction transistor.

[0053] According to a second aspect of the embodiments of the present disclosure, an electronic device is provided, comprising the electrostatic discharge protection circuit described in the first aspect.

[0054] According to an embodiment of the present disclosure, an electrostatic discharge protection circuit and an electronic device are disclosed. The electrostatic discharge protection circuit includes: a current discharge transistor; the current discharge transistor is connected between a first node and a second node; wherein the current discharge transistor is used to discharge electrostatic pulses between the first node and the second node in the on state; a mirror current module; the mirror current module is used to generate a mirror drive current based on the electrostatic pulse; a voltage generation module; the voltage generation module is used to generate a drive voltage signal based on the mirror drive current to drive the current discharge transistor to conduct. In this way, a mirror drive current with a relatively stable current value is generated based on the electrostatic pulse by the mirror current module, and a stable drive voltage signal is generated by the voltage generation module to control the conduction of the current discharge transistor. On the one hand, the discharge of static electricity can be achieved; on the other hand, since the drive voltage signal is relatively stable, the reliability of the current discharge transistor control can be improved, and the reliability and stability of the electrostatic discharge protection circuit control can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 This is one of the structural schematic diagrams of an electrostatic discharge protection circuit according to an embodiment;

[0056] Figure 2 FIG2 is a second structural diagram of an electrostatic discharge protection circuit according to an embodiment;

[0057] Figure 3 FIG3 is a third structural diagram of an electrostatic discharge protection circuit according to an embodiment;

[0058] Figure 4 is a schematic diagram of a diode sequence structure according to an embodiment;

[0059] Figure 5 FIG4 is a fourth structural diagram of an electrostatic discharge protection circuit according to an embodiment;

[0060] Figure 6 FIG5 is a fifth structural diagram of an electrostatic discharge protection circuit according to an embodiment;

[0061] Figure 7 FIG6 is a sixth structural diagram of an electrostatic discharge protection circuit according to an embodiment;

[0062] Figure 8 FIG7 is a seventh structural diagram of an electrostatic discharge protection circuit according to an embodiment;

[0063] Figure 9 is a schematic diagram showing the architecture of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0064] To make the technical solutions and beneficial effects of the present invention more clearly understood, the following detailed description is given by way of specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly illustrate the details of the local features. Unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0065] The embodiments of the present disclosure are not exhaustive and are merely illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present disclosure. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a certain embodiment can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementation methods in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined. For example, some or all steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0066] In each embodiment of the present disclosure, unless otherwise specified or provided for by logic, the terms and / or descriptions between the embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form a new embodiment based on their inherent logical relationships.

[0067] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0068] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular, such as "a", "an", "the", "above", "said", "the", "the", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun following the article may be understood as a singular expression or a plural expression.

[0069] In the embodiments of the present disclosure, “plurality” refers to two or more.

[0070] In some embodiments, the terms “at least one”, “one or more”, “a plurality of”, “multiple”, etc. can be used interchangeably.

[0071] In some embodiments, descriptions such as "at least one of A and B," "A and / or B," "in one case A, in another case B," or "in one case A, in another case B" may include the following technical solutions depending on the situation: in some embodiments, A (A is executed independently of B); in some embodiments, B (B is executed independently of A); in some embodiments, execution is selected from A and B (A and B are selectively executed); and in some embodiments, A and B (both A and B are executed). The same applies when there are more branches, such as A, B, and C.

[0072] In some embodiments, "A or B" and other expressions may include the following technical solutions, depending on the circumstances: in some embodiments, A (A is executed independently of B); in some embodiments, B (B is executed independently of A); in some embodiments, execution is selected from A and B (A and B are selectively executed). The above is also applicable when there are more branches, such as A, B, and C.

[0073] The prefixes such as "first" and "second" in the embodiments of the present disclosure are only used to distinguish different description objects and do not constitute any restriction on the position, order, priority, value or content of the description objects. For the statement of the description object, please refer to the description in the context of the claims or embodiments, and no unnecessary restriction should be constituted due to the use of prefixes. For example, if the description object is a "field", the ordinal number before the "field" in the "first field" and the "second field" does not limit the position or order between the "fields", and "first" and "second" do not limit whether the "fields" they modify are in the same message, nor do they limit the order of the "first field" and the "second field". For another example, if the description object is a "level", the ordinal number before the "level" in the "first level" and the "second level" does not limit the priority between the "levels". For another example, the value of the description object is not limited by the ordinal number and can be one or more. Taking "first device" as an example, the value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", then the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different; for another example, if the description object is "information", then the "first information" and the "second information" can be the same information or different information, and their contents can be the same or different.

[0074] In some embodiments, “including A,” “comprising A,” “used to indicate A,” and “carrying A” can be interpreted as directly carrying A or indirectly indicating A.

[0075] In some embodiments, terms such as "...", "determine...", "in the case of...", "at the time of...", "when...", "if...", "if...", etc. can be used interchangeably.

[0076] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not less than", and "above" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0077] In addition, each element, each row, or each column in the table of the embodiment of the present disclosure can be implemented as an independent embodiment, and the combination of any elements, any rows, and any columns can also be implemented as an independent embodiment.

[0078] It should be noted that, unless there is any contradiction, the transistors in the embodiments of the present application (such as the current discharge transistor and the driving transistor) may be N-type transistors, P-type transistors, enhancement-type transistors, depletion-type transistors, etc. For N-type transistors, enhancement-type transistors, or depletion-type transistors, the on-level is a high level, and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the first terminal and the second terminal thereof are connected, and when the gate of the N-type transistor is at a low level, the first terminal and the second terminal thereof are disconnected. For P-type transistors, the on-level is a low level, and the off-level is a high level. That is, when the control terminal of the P-type transistor is at a low level, the first terminal and the second terminal thereof are connected, and when the control terminal of the P-type transistor is at a high level, the first terminal and the second terminal thereof are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control terminal, and, depending on the signal of the gate of each transistor and its type, its first terminal can serve as the source and the second terminal as the drain (such as a P-type transistor), or its first terminal can serve as the drain and the second terminal as the source (such as an N-type transistor). In addition, the on-level and off-level in the embodiments of the present invention are general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / off the transistor. Here, transistor conduction may include transistor drain and source conduction.

[0079] like Figure 1 As shown, an embodiment of the present disclosure provides an electrostatic discharge protection circuit 100, and the electrostatic discharge protection circuit 100 includes:

[0080] A current discharge transistor S1; the current discharge transistor S1 is connected between the first node and the second node; wherein the current discharge transistor S1 is used to discharge electrostatic pulses between the first node and the second node when in a conducting state;

[0081] A mirror current module 110; the mirror current module 110 is used to generate a mirror driving current based on the electrostatic pulse;

[0082] Voltage generating module 120: The voltage generating module 120 is configured to generate a driving voltage signal based on the mirror driving current to drive the current discharge transistor S1 to turn on.

[0083] In a possible implementation, the first node is a node for electrostatic protection by the electrostatic discharge protection circuit 100, and the second node is a target node for electrostatic discharge. Figure 1 The first node shown is the gate of the transistor S0 that needs to be protected by the electrostatic discharge protection circuit 100 , and the second node may be a target node for gate electrostatic discharge, such as a power ground.

[0084] In a possible implementation, the second node is a node for electrostatic protection by the electrostatic discharge protection circuit 100 , and the first node is a target node for electrostatic discharge.

[0085] In a possible implementation, the first node and the second node are target nodes for each other's electrostatic discharge.

[0086] In a possible implementation, the electrostatic pulse may be an electrostatic pulse on the first node or an electrostatic pulse on the second node.

[0087] In one possible implementation, the mirror drive current may include the current generated by the mirror current module 110 under electrostatic pulse driving. The mirror current module 110 may generate a reference current based on the electrostatic pulse, and the mirror drive current may be obtained by the mirror current module 110 mirroring the reference current.

[0088] In a possible implementation, the current mirror module 110 may be implemented using a simple current mirror, a proportional current mirror, a cascode current mirror, or the like.

[0089] In one possible implementation, under certain conditions, the mirror drive current can remain within a predetermined range even when the voltage value of the electrostatic pulse changes. Therefore, the mirror current module 110 can maintain a stable output of the mirror drive current for the duration of the electrostatic pulse. The mirror current module 110 can reduce the variation of the mirror drive current during the duration of the electrostatic pulse.

[0090] In a possible implementation, the mirror driving current is positively correlated with the voltage value on the first node.

[0091] In a possible implementation, the mirror driving current is positively correlated with the voltage value on the second node.

[0092] In a possible implementation, the voltage generating module 120 generating the driving voltage signal based on the mirror driving current may include one of the following:

[0093] The voltage generating module 120 directly generates a driving voltage signal; for example, the voltage generating module 120 may directly generate a driving voltage signal by mirroring a driving current based on Ohm's law, etc.;

[0094] The voltage generating module 120 indirectly generates the driving voltage signal; for example, the voltage generating module 120 adjusts the driving voltage signal by mirroring the driving current.

[0095] Here, the voltage generating module 120 can be configured as follows: when an electrostatic pulse exists between the first node and the second node and the mirror current module 110 generates a mirror driving current, it can generate a driving voltage signal based on the mirror driving current to drive the current discharge transistor S1 to turn on to discharge the electrostatic current; when there is no electrostatic pulse between the first node and the second node, or the voltage difference between the first node and the second node is less than the discharge voltage difference threshold, the voltage generating module 120 can generate a voltage signal based on the mirror current of the mirror current module 110 to keep the current discharge transistor S1 in a cut-off state to reduce the impact on the first node and / or the second node.

[0096] In one possible implementation, the mirror drive current has a corresponding relationship with the drive voltage signal. For example, the current value of the mirror drive current is positively correlated with the voltage value of the drive voltage signal. The voltage value of the drive voltage signal can be set based on the on-voltage and / or off-voltage of the gate of the current discharge transistor S1. The voltage value of the drive voltage signal under the mirror drive current can be set to be greater than or equal to the on-voltage of the gate of the current discharge transistor S1. Then, when the electrostatic pulse arrives, the mirror current module 110 generates a mirror drive current, and the voltage generation module 120 generates a drive voltage signal based on the mirror drive current to turn on the current discharge transistor S1 to discharge the electrostatic current. When there is no electrostatic pulse, the mirror current generated by the mirror current module 110 is less than the mirror drive current, and the drive voltage signal generated by the voltage generation module 120 is less than the on-voltage of the gate of the current discharge transistor S1, so that the current discharge transistor S1 is in the off state.

[0097] In one possible implementation, the current discharge transistor S1 may be a Group III nitride transistor.

[0098] In one possible implementation, Figure 1 As shown, the gate of the current discharge transistor can be implemented by an N-type transistor.

[0099] In this way, the mirror current module 110 generates a mirror driving current with a relatively stable current value based on the electrostatic pulse, and the voltage generation module 120 generates a stable driving voltage signal for controlling the conduction of the current discharge transistor S1. On the one hand, the discharge of static electricity can be achieved; on the other hand, since the driving voltage signal is relatively stable, the reliability of the control of the current discharge transistor S1 can be improved, and the reliability and stability of the control of the electrostatic discharge protection circuit 100 can be improved.

[0100] In some embodiments, as Figure 2 As shown, the voltage generating module 120 includes a fourth resistor R4, and the current mirror module 110 includes a first transistor NM1, a second transistor NM2, a second resistor R2, a third resistor R3 and a first resistor R1, wherein,

[0101] The first end of the first resistor R1, the first end of the second resistor R2 and the first node are connected;

[0102] The gate of the first transistor NM1, the drain of the first transistor NM1 and the gate of the second transistor NM2 are connected as a third node;

[0103] The second end of the second resistor R2 is connected to the third node;

[0104] The second end of the first resistor R1 is connected to the drain of the second transistor NM2;

[0105] A first end of the third resistor R3 is connected to the source of the first transistor NM1;

[0106] The source of the second transistor NM2 is connected to the control terminal of the current discharge transistor S1 as a fourth node;

[0107] The first end of the fourth resistor R4 is connected to the fourth node;

[0108] The second end of the third resistor R3, the second end of the fourth resistor R4 and the second node are connected.

[0109] In one possible implementation, the first transistor NM1 , the second transistor NM2 , and the current discharge transistor S1 may all be implemented using Group III nitride transistors.

[0110] In a possible implementation, the first transistor NM1 and the second transistor NM2 may be transistors of the same type, for example, both the first transistor NM1 and the second transistor NM2 may be enhancement-mode transistors.

[0111] In one possible implementation, the current discharge transistor S1 may be implemented using a Group III nitride transistor.

[0112] In a possible implementation, the current discharge transistor S1 may be an N-type transistor.

[0113] In a possible implementation, the resistance of the third resistor R3 may be equal to the resistance of the fourth resistor R4.

[0114] like Figure 2 As shown, the electrostatic pulse can be located at the first node. The second node can be used to discharge the electrostatic current. For example, the second node can be a power ground.

[0115] Based on the voltage signal at the first node (such as an electrostatic pulse or a normal operating voltage signal), the current mirror module 110 generates a reference current along the second resistor R2, the drain-to-source connection of the first transistor NM1, and the third resistor R3. The second transistor NM2 can mirror the reference current to obtain a mirrored current, thereby generating a voltage signal at the fourth node. The resistance of the fourth resistor R4 is positively correlated with the voltage value at the control terminal (the fourth node) of the current discharge transistor S1. Here, the second transistor NM2 can mirror the reference current to obtain a mirrored current, which can include any of the following: the second transistor NM2 can copy the reference current to obtain the mirrored current; the second transistor NM2 can proportionally mirror the reference current to obtain the mirrored current.

[0116] When the voltage signal at the first node is an electrostatic pulse, the second transistor NM2 can mirror the reference current to obtain a mirrored drive current, generating a drive voltage signal at the fourth node. When the voltage value of the drive voltage signal is greater than or equal to the turn-on voltage of the control terminal of the current discharge transistor S1, the current discharge transistor S1 is turned on (e.g., the drain and source of the transistor are turned on) to discharge the electrostatic current.

[0117] When the voltage signal at the first node is a normal operating voltage (e.g., a 5V operating voltage), the second transistor NM2 can mirror the reference current to obtain a mirrored current, generating a voltage signal at the fourth node. The voltage value of the voltage signal is less than the turn-on voltage of the control terminal of the current bleeder transistor S1, and the current bleeder transistor S1 is turned off (e.g., the drain and source of the transistor are turned off). This reduces the impact of the ESD protection circuit 100 on the normal operating voltage.

[0118] Here, the fourth resistor R4 can be set based on adjusting the gate-on voltage of the current bleeding transistor S1 to adjust the voltage drop at the fourth node. The fourth resistor R4 can be adjusted so that when an electrostatic pulse is present at the first node, the voltage at the fourth node is greater than or equal to the gate-on voltage of the current bleeding transistor S1, and when no electrostatic pulse is present at the first node, the voltage at the fourth node is less than the gate-on voltage of the current bleeding transistor S1.

[0119] In this way, a mirror driving current with a relatively stable current value is generated by the mirror current module 110 based on the electrostatic pulse, and then a stable driving voltage signal is generated through the fourth resistor R4 to control the conduction of the current discharge transistor S1. On the one hand, the discharge of static electricity can be achieved; on the other hand, since the driving voltage signal is relatively stable, the reliability of the control of the current discharge transistor S1 can be improved, and the reliability and stability of the control of the electrostatic discharge protection circuit 100 can be improved.

[0120] In some embodiments, as Figure 3 As shown, the electrostatic discharge protection circuit 100 further includes at least one first diode sequence D1, wherein the first diode sequence D1 includes at least one diode connected in series in the same direction; wherein the first diode sequence D1 is provided in at least one of the following:

[0121] connected in series with the second resistor R2 between the first node and the third node, wherein the forward conduction direction of the first diode sequence D1 is toward the third node;

[0122] connected in series with the first resistor R1 between the first node and the drain of the second transistor NM2, wherein the forward conduction direction of the first diode array D1 is toward the drain of the second transistor NM2;

[0123] connected in series with the third resistor R3 between the source of the first transistor NM1 and the second node, wherein the forward conduction direction of the first diode array D1 is toward the second node;

[0124] The first diode array D1 is connected in series with the fourth resistor R4 between the fourth node and the second node, wherein the forward conduction direction of the first diode array D1 is toward the second node.

[0125] For example, Figure 4 As shown, the diode sequence includes n diodes from 1 to n, where n is an integer greater than or equal to 1. The anode of diode 1 is connected to the cathode of diode 2, and the anode of diode 2 is connected to the cathode of diode 3. The cathode of the diode sequence is the cathode of diode 1, and the anode of the diode sequence is the anode of diode n. Figure 4 The forward conduction direction of the diode sequence shown is the direction in which current flows from the anode of the nth diode to the cathode of the first diode.

[0126] In a possible implementation, the forward conduction voltage of the diode sequence is the sum of the forward conduction voltages of each diode in the diode sequence.

[0127] Here, the forward conduction direction of the diode sequence refers to the direction of current flow when the diode sequence is forward conducting. For example, the forward conduction direction of the first diode sequence D1 is toward the third node, which means that when the first diode sequence D1 is forward conducting, current flows toward the third node.

[0128] In this embodiment, when a diode array is connected in series with a resistor, the diode array can be placed before or after the resistor in the direction of current flow. For example, a first diode array D1 and a second resistor R2 connected in series between a first node and a third node may include at least one of the following: the first diode array D1 is placed between the first node and the second resistor R2; or the first diode array D1 is placed between the second resistor R2 and the third node. A detailed description of each diode array is omitted here.

[0129] like Figure 3 As shown, the diode sequence connected in series in the circuit can realize the voltage division of the circuit based on the semiconductor PN junction.

[0130] When the voltage difference between the first node and the second node is the voltage difference within the normal operating voltage, leakage current exists between the first node and the second node. For example, leakage current flows from the first node through the second resistor R2, the first transistor NM1, and the third resistor R3 to the second node. To reduce leakage current, the resistance of the second resistor R2 and / or the resistance of the third resistor R3 can be increased to limit the leakage current. The need to increase the resistance of the second resistor R2 and / or the resistance of the third resistor R3 reduces the flexibility of resistor selection. Here, voltage division can be achieved using a first diode array D1 connected in series with the second resistor R2 and / or a first diode array D1 connected in series with the third resistor R3, reducing the voltage drop across the resistors under the same leakage current. This allows the same leakage current limiting effect to be achieved using resistors with smaller resistance values ​​(the second resistor R2 and / or the third resistor R3). This improves the flexibility of resistor selection. The leakage current flowing from the first node through the first resistor R1, the second transistor NM2, and the fourth resistor R4 to the second node is similar to the leakage current flowing from the first node through the second resistor R2, the first transistor NM1, and the third resistor R3 to the second node. The voltage division operation of the diode array is similar and will not be repeated here.

[0131] like Figure 3 As shown, when a first electrostatic pulse occurs at the first node, a mirror drive current flows from the fourth node through the first diode array D1 and the fourth resistor R4 to the second node. The first mirror drive current generates a voltage drop across the fourth resistor R4. This, combined with the forward voltage of the first diode array D1, generates a drive voltage signal at the control terminal (gate) of the current discharge transistor S1, driving the current discharge transistor S1 to conduct and discharge the first electrostatic pulse to the second node.

[0132] On the one hand, the first diode array D1 can share the voltage of the driving voltage signal with the fourth resistor R4. The fourth resistor R4 can be flexibly adjusted based on the voltage divided by the first diode array D1, and is not limited to a fixed resistance value, thereby increasing the flexibility of selecting the fourth resistor R4. On the other hand, the first diode array D1 has a unidirectional conduction characteristic, which can reduce the interference of the reverse signal from the second node on the ESD protection circuit 100.

[0133] In some embodiments, as Figure 5 As shown, the mirror current module 110 includes a first mirror current module 111 and a second mirror current module 112; the voltage generating module 120 includes a first voltage generating module 121 and a second voltage generating module 122; wherein,

[0134] The first mirror current module 111 is configured to generate a first mirror driving current based on a first electrostatic pulse on the first node;

[0135] The first voltage generating module 121 is configured to generate a first driving voltage signal based on the first mirror driving current to drive the current discharge transistor S1 to turn on;

[0136] The second mirror current module 112 is configured to generate a second mirror driving current based on a second electrostatic pulse on the second node;

[0137] The second voltage generating module 122 is configured to generate a second driving voltage signal based on the second mirror driving current, so as to drive the current discharge transistor S1 to be turned on.

[0138] Here, the first node and the second node are mutually target nodes for electrostatic discharge. When a first electrostatic pulse occurs at the first node, the first mirror current module 111 can combine with the first voltage generation module 121 to generate a first drive voltage signal to drive the current discharge transistor S1 to turn on, discharging the first electrostatic pulse to the second node through the current discharge transistor S1. When a second electrostatic pulse occurs at the second node, the second mirror current module 112 can combine with the second voltage generation module 122 to generate a second drive voltage signal to drive the current discharge transistor S1 to turn on, discharging the second electrostatic pulse to the first node through the current discharge transistor S1.

[0139] The specific implementation of the first mirror current module 111 generating the first mirror drive current based on the first electrostatic pulse, and the first voltage generating module 121 generating the first drive voltage signal based on the first mirror drive current are similar to the implementation of any of the above embodiments in which the mirror current module 110 generates the mirror drive current based on the electrostatic pulse, and the voltage generating module 120 generates the drive voltage signal based on the mirror drive current, and will not be repeated here.

[0140] The specific implementation of the second mirror current module 112 generating the second mirror drive current based on the second electrostatic pulse, and the second voltage generating module 122 generating the second drive voltage signal based on the second mirror drive current are similar to the implementation of any of the above embodiments in which the mirror current module 110 generates the mirror drive current based on the electrostatic pulse, and the voltage generating module 120 generates the drive voltage signal based on the mirror drive current, and will not be repeated here.

[0141] In some embodiments, the current discharge transistor S1 includes a bidirectional conduction transistor.

[0142] In one possible implementation, the current discharge transistor S1 may be a Group III nitride transistor.

[0143] By adopting a bidirectional conductive transistor, when the voltage difference between the gate of the current discharge transistor S1 and the first node is greater than the threshold voltage, or when the voltage difference between the gate of the current discharge transistor S1 and the second node is greater than the threshold voltage, the bidirectional conductive transistor can be turned on to discharge the first electrostatic pulse or the second electrostatic pulse respectively.

[0144] In this way, the first driving voltage signal for the first electrostatic pulse is generated by the first mirror current module 111 and the first voltage generating module 121 to achieve the release of the first electrostatic pulse, and the second driving voltage signal for the second electrostatic pulse is generated by the second mirror current module 112 and the second voltage generating module 122 to achieve the release of the second electrostatic pulse, thereby realizing bidirectional electrostatic discharge protection for the first node and the second node.

[0145] In some embodiments, as Figure 6 As shown, the first voltage generating module 121 includes an eighth resistor R8;

[0146] The first current mirror module 111 includes a third transistor NM3, a fourth transistor NM4, a seventh resistor R7, a ninth resistor R9, a second diode sequence D2, and a third diode sequence D3. The second diode sequence D2 includes at least one diode connected in series in the same direction. The third diode sequence D3 includes at least one diode connected in series in the same direction.

[0147] The drain of the fourth transistor NM4, the first end of the seventh resistor R7 and the first node are connected;

[0148] The gate of the third transistor NM3, the drain of the third transistor NM3 and the gate of the fourth transistor NM4 are connected as a fifth node;

[0149] The second end of the seventh resistor R7 is connected to the fifth node;

[0150] The source of the fourth transistor NM4 is connected to the control terminal of the current discharge transistor S1 as a sixth node;

[0151] The ninth resistor R9 and the third diode sequence D3 are connected in series between the source of the third transistor NM3 and the second node, wherein the forward conduction direction of the third diode sequence D3 is toward the second node;

[0152] The eighth resistor R8 and the second diode sequence D2 are connected in series between the sixth node and the second node, wherein the forward conduction direction of the second diode sequence D2 is toward the second node;

[0153] The second voltage generating module 122 includes an eleventh resistor R11;

[0154] The second current mirror module 112 includes a fifth transistor NM5, a sixth transistor NM6, a tenth resistor R10, a twelfth resistor R12, a fourth diode sequence D4, and a fifth diode sequence D5. The fourth diode sequence D4 includes at least one diode connected in series in the same direction, and the fifth diode sequence D5 includes at least one diode connected in series in the same direction.

[0155] The drain of the sixth transistor NM6, the second end of the tenth resistor R10 and the second node are connected;

[0156] The gate of the fifth transistor NM5, the drain of the fifth transistor NM5 and the gate of the sixth transistor NM6 are connected as a seventh node;

[0157] The first end of the tenth resistor R10 is connected to the seventh node;

[0158] A source of the sixth transistor NM6 is connected to the sixth node;

[0159] The twelfth resistor R12 and the fifth diode array D5 are connected in series between the source of the fifth transistor NM5 and the first node, wherein the forward conduction direction of the fifth diode array D5 is toward the first node;

[0160] The eleventh resistor R11 and the fourth diode sequence D4 are connected in series between the sixth node and the first node, wherein the forward conduction direction of the fourth diode sequence D4 is toward the first node.

[0161] In some embodiments, as Figure 7 As shown, the first mirror current module 111 further includes a fifth resistor R5, and the fifth resistor R5 is arranged between the first node and the drain of the fourth transistor NM4; and / or

[0162] The second current mirror module 112 further includes a sixth resistor R6 , which is disposed between the second node and the drain of the sixth transistor NM6 .

[0163] Here, the fifth resistor R5 and the sixth resistor R6 can be used to adjust the first mirror driving current and the second mirror driving current respectively to adapt to different mirror driving current requirements.

[0164] In a possible implementation, the resistance of the fifth resistor R5 may be equal to the resistance of the seventh resistor R7, and / or the resistance of the sixth resistor R6 may be equal to the resistance of the tenth resistor R10.

[0165] In a possible implementation, the resistance of the fifth resistor R5 may be different from the resistance of the tenth resistor R10.

[0166] In one possible implementation, the third transistor NM3 , the fourth transistor NM4 , the fifth transistor NM5 , the sixth transistor NM6 , and the current discharge transistor S1 may all be implemented using Group III nitride transistors.

[0167] In a possible implementation, the third transistor NM3 , the fourth transistor NM4 , the fifth transistor NM5 and the sixth transistor NM6 may be transistors of the same type, for example, the third transistor NM3 , the fourth transistor NM4 , the fifth transistor NM5 and the sixth transistor NM6 may all be depletion-mode transistors.

[0168] In one possible implementation, the third transistor NM3 and the fourth transistor NM4 may have the same electrical parameters, or the fifth transistor NM5 and the sixth transistor NM6 may have the same electrical parameters, or the third transistor NM3, the fourth transistor NM4, the fifth transistor NM5, and the sixth transistor NM6 may have the same electrical parameters. Here, the electrical parameters may include electrical performance parameters of the transistors, such as threshold voltage Vth, on-resistance Rdson, gate-source capacitance (Cgs), etc.

[0169] In a possible implementation, the electrical parameters of the second diode sequence D2 and the third diode sequence D3 may be the same, and / or the electrical parameters of the fourth diode sequence D4 and the fifth diode sequence D5 may be the same.

[0170] like Figure 6As shown, when a first static electricity pulse occurs at the first node, the reference current of the first mirror current module 111 flows from the first node through the seventh resistor R7, the third transistor NM3, the third diode array D3, and the ninth resistor R9 to the second node. The first mirror current module 111 mirrors the reference current to generate a first mirrored drive current. The first mirrored drive current then flows from the first node through the fifth resistor R5, the fourth transistor NM4, the second diode array D2, and the eighth resistor R8 to the second node. The first mirrored drive current generates a voltage drop across the eighth resistor R8. This, combined with the forward voltage of the second diode array D2, generates a first drive voltage signal at the control terminal (gate) of the current discharge transistor S1, discharging the first static electricity pulse to the second node.

[0171] The second diode array D2 can share the voltage of the first driving voltage signal with the eighth resistor R8 , and can also reduce interference of the reverse signal from the second node on the ESD protection circuit 100 .

[0172] When a second static electricity pulse occurs at the second node, the reference current of the second mirror current module 112 flows from the second node through the tenth resistor R10, the fifth transistor NM5, the fifth diode array D5, and the twelfth resistor R12 to the first node. The second mirror current module 112 mirrors the reference current to generate a second mirrored drive current. The second mirrored drive current then flows from the second node through the sixth resistor R6, the sixth transistor NM6, the fourth diode array D4, and the eleventh resistor R11 to the first node. The second mirrored drive current generates a voltage drop across the eleventh resistor R11. This, combined with the forward voltage of the fourth diode array D4, generates a second drive voltage signal at the control terminal (gate) of the current discharge transistor S1, discharging the second static electricity pulse to the first node.

[0173] The fourth diode array D4 can share the voltage of the second driving voltage signal with the eleventh resistor R11 , and can also reduce interference of the reverse signal from the first node on the ESD protection circuit 100 .

[0174] In a possible implementation, the forward conduction voltage of the fourth diode array D4 is smaller than the conduction voltage of the control terminal of the current discharge transistor S1 .

[0175] In a possible implementation, the forward conduction voltage of the second diode array D2 is smaller than the conduction voltage of the control terminal of the current discharge transistor S1 .

[0176] The forward conduction voltage of the fourth diode sequence D4 is lower than the conduction voltage of the control terminal of the current bleeder transistor S1. The voltage of the control terminal of the current bleeder transistor S1 can be adjusted via the eleventh resistor R11 to reduce the possibility of the current bleeder transistor S1 being turned on when the voltage between the first node and the second node is at the normal operating voltage due to an excessively large forward conduction voltage of the fourth diode sequence D4. The forward conduction voltage of the second diode sequence D2 is lower than the conduction voltage of the control terminal of the current bleeder transistor S1. The voltage of the control terminal of the current bleeder transistor S1 can be adjusted via the eighth resistor R8 to reduce the possibility of the current bleeder transistor S1 being turned on when the voltage between the first node and the second node is at the normal operating voltage due to an excessively large forward conduction voltage of the fourth diode sequence D4.

[0177] In some embodiments, as Figure 8 As shown, the electrostatic discharge protection circuit 100 further includes at least one sixth diode sequence D6, wherein the sixth diode sequence D6 includes at least one diode connected in series in the same direction; wherein the sixth diode sequence D6 is provided in at least one of the following:

[0178] connected in series with the seventh resistor R7 between the first node and the fifth node, wherein the forward conduction direction of the sixth diode array D6 is toward the fifth node;

[0179] connected in series with the fifth resistor R5 between the first node and the drain of the fourth transistor NM4 , wherein the forward conduction direction of the sixth diode array D6 is toward the drain of the fourth transistor NM4 ;

[0180] connected in series with the tenth resistor R10 between the second node and the seventh node, wherein the forward conduction direction of the sixth diode array D6 is toward the seventh node;

[0181] The sixth diode array D6 is connected in series with the sixth resistor R6 between the second node and the drain of the sixth transistor NM6 , wherein the forward conduction direction of the sixth diode array D6 is toward the drain of the sixth transistor NM6 .

[0182] Diode sequence such as Figure 4 As shown, no further details are given here.

[0183] Here, the forward conduction direction of the diode sequence refers to the direction of current flow when the diode sequence is forward conducting. For example, the forward conduction direction of the sixth diode sequence D6 is toward the fifth node, which means that when the sixth diode sequence D6 is forward conducting, current flows toward the fifth node.

[0184] In this embodiment, when a diode array is connected in series with a resistor, the diode array can be placed before or after the resistor in the direction of current flow. For example, the sixth diode array D6 and the seventh resistor R7 can be connected in series between the first node and the fifth node, which can include at least one of the following: the sixth diode array D6 is placed between the first node and the seventh resistor R7; the sixth diode array D6 is placed between the seventh resistor R7 and the fifth node. A detailed description of each diode array is omitted here.

[0185] The sixth diode array D6 is used in the circuit as follows Figure 3 Similar to the first diode array D1 described in the embodiment, it can share the voltage of the driving voltage signal with the resistor. The resistor can be flexibly adjusted based on the voltage division of the sixth diode array D6, not limited to a fixed resistance value, thus increasing the flexibility of resistor selection. Furthermore, the sixth diode array D6 has a unidirectional conduction characteristic, which can reduce interference with the ESD protection circuit 100 from reverse signals from the second node. This will not be further described here.

[0186] In a possible implementation, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be N-type transistors.

[0187] In a possible implementation, the diodes in the diode sequence described in this embodiment may be group III nitride Schottky barrier diodes.

[0188] Figure 9 The electronic device 10 according to the embodiment of the present disclosure includes an electrostatic discharge protection circuit 100. Figures 1 to 8 The embodiments are shown and will not be described in detail here.

[0189] In some possible implementations, the electronic device 10 may include an independent electronic device, such as an integrated circuit chip.

[0190] In some possible implementations, the electronic device 10 may be composed of multiple electronic components, and the electrostatic discharge protection circuit 100 may be provided in the electronic device 10 in the form of discrete components.

[0191] Other embodiments of the present invention will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the invention that follow from the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

[0192] It should be understood that the present invention is not limited to the exact construction described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. An electrostatic discharge protection circuit, characterized in that: The electrostatic discharge protection circuit comprises: A current discharge transistor; the current discharge transistor is connected between the first node and the second node; wherein the current discharge transistor is used to discharge electrostatic pulses between the first node and the second node in a conductive state; A mirror current module; the mirror current module is used to generate a mirror drive current based on the electrostatic pulse; A voltage generating module; the voltage generating module is used to generate a driving voltage signal based on the mirror driving current to drive the current discharge transistor to turn on.

2. The electrostatic discharge protection circuit according to claim 1, wherein: The voltage generating module includes a fourth resistor, and the mirror current module includes a first transistor, a second transistor, a second resistor, a third resistor and a first resistor, wherein: The first end of the first resistor, the first end of the second resistor and the first node are connected; The gate of the first transistor, the drain of the first transistor and the gate of the second transistor are connected as a third node; The second end of the second resistor is connected to the third node; The second end of the first resistor is connected to the drain of the second transistor; A first end of the third resistor is connected to the source of the first transistor; The source of the second transistor is connected to the control terminal of the current discharge transistor as a fourth node; The first end of the fourth resistor is connected to the fourth node; The second end of the third resistor, the second end of the fourth resistor, and the second node are connected.

3. The electrostatic discharge protection circuit according to claim 2, wherein: The electrostatic discharge protection circuit further includes at least one first diode sequence, wherein the first diode sequence includes at least one diode connected in series in the same direction; wherein the first diode sequence is provided in at least one of the following: connected in series with the second resistor between the first node and the third node, wherein the forward conduction direction of the first diode sequence is toward the third node; connected in series with the first resistor between the first node and the drain of the second transistor, wherein the forward conduction direction of the first diode sequence is toward the drain of the second transistor; connected in series with the third resistor between the source of the first transistor and the second node, wherein the forward conduction direction of the first diode sequence is toward the second node; The first diode sequence is connected in series with the fourth resistor between the fourth node and the second node, wherein the forward conduction direction of the first diode sequence is toward the second node.

4. The electrostatic discharge protection circuit according to claim 1, wherein: The mirror current module includes a first mirror current module and a second mirror current module; the voltage generation module includes a first voltage generation module and a second voltage generation module; wherein, The first mirror current module is used to generate a first mirror driving current based on a first electrostatic pulse on the first node; The first voltage generating module is configured to generate a first driving voltage signal based on the first mirror driving current to drive the current discharge transistor to turn on; The second mirror current module is used to generate a second mirror driving current based on a second electrostatic pulse on the second node; The second voltage generating module is configured to generate a second driving voltage signal based on the second mirror driving current to drive the current discharge transistor to be turned on.

5. The electrostatic discharge protection circuit according to claim 4, characterized in that: The first voltage generating module includes an eighth resistor; The first current mirror module includes a third transistor, a fourth transistor, a seventh resistor, a ninth resistor, a second diode sequence, and a third diode sequence, wherein the second diode sequence includes at least one diode connected in series in the same direction, and the third diode sequence includes at least one diode connected in series in the same direction; wherein, The drain of the fourth transistor, the first end of the seventh resistor and the first node are connected; The gate of the third transistor, the drain of the third transistor and the gate of the fourth transistor are connected as a fifth node; The second end of the seventh resistor is connected to the fifth node; The source of the fourth transistor is connected to the control terminal of the current discharge transistor as a sixth node; The ninth resistor and the third diode sequence are connected in series between the source of the third transistor and the second node, wherein the forward conduction direction of the third diode sequence is toward the second node; The eighth resistor and the second diode sequence are connected in series between the sixth node and the second node, wherein the forward conduction direction of the second diode sequence is toward the second node; The second voltage generating module includes an eleventh resistor; The second current mirror module includes a fifth transistor, a sixth transistor, a tenth resistor, a twelfth resistor, a fourth diode sequence and a fifth diode sequence, wherein the fourth diode sequence includes at least one diode connected in series in the same direction, and the fifth diode sequence includes at least one diode connected in series in the same direction; wherein, The drain of the sixth transistor, the second end of the tenth resistor and the second node are connected; The gate of the fifth transistor, the drain of the fifth transistor, and the gate of the sixth transistor are connected as a seventh node; The first end of the tenth resistor is connected to the seventh node; The source of the sixth transistor is connected to the sixth node; The twelfth resistor and the fifth diode sequence are connected in series between the source of the fifth transistor and the first node, wherein the forward conduction direction of the fifth diode sequence is toward the first node; The eleventh resistor and the fourth diode sequence are connected in series between the sixth node and the first node, wherein the forward conduction direction of the fourth diode sequence is toward the first node.

6. The electrostatic discharge protection circuit according to claim 5, characterized in that: The first current mirror module further includes a fifth resistor, and the fifth resistor is arranged between the first node and the drain of the fourth transistor; and / or The second mirror current module further includes a sixth resistor, wherein the sixth resistor is arranged between the second node and the drain of the sixth transistor.

7. The electrostatic discharge protection circuit according to claim 6, wherein: The electrostatic discharge protection circuit further includes: at least one sixth diode sequence, wherein the sixth diode sequence includes at least one diode connected in series in the same direction; wherein the sixth diode sequence is provided in at least one of the following: connected in series with the seventh resistor between the first node and the fifth node, wherein the forward conduction direction of the sixth diode sequence is toward the fifth node; connected in series with the fifth resistor between the first node and the drain of the fourth transistor, wherein the forward conduction direction of the sixth diode sequence is toward the drain of the fourth transistor; connected in series with the tenth resistor between the second node and the seventh node, wherein the forward conduction direction of the sixth diode sequence is toward the seventh node; The sixth diode is connected in series with the sixth resistor between the second node and the drain of the sixth transistor, wherein the forward conduction direction of the sixth diode sequence is toward the drain of the sixth transistor.

8. The electrostatic discharge protection circuit according to claim 5, wherein: The forward conduction voltage of the second diode sequence is less than the conduction voltage of the control terminal of the current discharge transistor; and / or The forward conduction voltage of the fourth diode sequence is less than the conduction voltage of the control terminal of the current discharge transistor.

9. The electrostatic discharge protection circuit according to any one of claims 5 to 7, characterized in that: The current discharge transistor includes a bidirectional conducting transistor.

10. An electronic device, characterized in that: The electronic device comprises the electrostatic discharge protection circuit according to any one of claims 1 to 9.

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