Variable gate voltage drive for gate drive control

Abstract

The invention relates to variable gate voltage driving for gate drive control. A synchronous rectifier driver circuit is configured to drive a synchronous rectifier. The driver circuit drives a gate terminal of the synchronous rectifier switch with a gate drive voltage proportional to a current flowing through the synchronous rectifier switch during at least a portion of a conduction phase of the synchronous rectifier switch.

Description

Technical Field

[0001] The present disclosure relates to synchronous rectifier driver circuits. Background Art

[0002] A resonant converter is a broad category of switching converters that includes a resonant circuit that plays an active role in determining the input-output power flow. Considering the most common implementation, in these converters, a full-bridge (or half-bridge) consisting of four (or two) power switches (usually power field-effect transistors (FETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs)) (which are powered by a DC voltage) generates a voltage square wave that is applied to a resonant circuit tuned to a frequency close to the fundamental frequency of the aforementioned square wave. Therefore, due to its selective characteristics, the resonant circuit responds primarily to the fundamental component, while its response to the higher harmonics of the square wave is negligible.

[0003] As a result, the circulating power can be modulated by varying the frequency of the square wave while keeping the duty cycle constant at 50%.Furthermore, depending on the resonant circuit configuration, the current and / or voltage associated with the power flow has a sinusoidal or segmented sinusoidal shape.

[0004] These voltages are rectified and filtered to provide DC power to the load. In offline applications, to comply with safety regulations, the rectification and filtering systems that power the load are typically coupled to the resonant circuit via a transformer to provide isolation between the source and the load, as required by these regulations. As with all isolated network converters, in this case, a distinction is made between the primary side (associated with the primary winding of the transformer), which is connected to the input source, and the secondary side (associated with the secondary winding of the transformer), which supplies power to the load through the rectification and filtering system.

[0005] Currently, among many types of resonant converters, the so-called LLC resonant converter is widely used, especially in its half-bridge version. The name LLC comes from the resonant circuit using two inductors / inductors (L) and a capacitor (C). Summary of the Invention

[0006] Embodiments of the present disclosure provide a driver circuit for a synchronous rectifier of a resonant converter that effectively and efficiently drives a rectifier switch of the synchronous rectifier. In one embodiment, a synchronous rectifier includes a driver circuit that drives a gate terminal of the synchronous rectifier switch with a gate drive voltage proportional to a current flowing through the synchronous rectifier switch during at least a portion of a conduction phase of the synchronous rectifier switch.

[0007] In one embodiment, a synchronous rectifier includes a driver circuit that drives a gate terminal of a synchronous rectifier switch with a gate drive voltage based on a gate drive reference signal. The gate drive reference voltage is generated at least in part based on a voltage or current associated with the synchronous rectifier switch multiplied by a gain parameter. The driver circuit automatically and continuously updates the gain parameter to maintain efficient and effective drive of the rectifier switch.

[0008] Although the embodiments described herein may sometimes be described with respect to driving a single rectifier switch, particularly of a resonant converter, in practice, the embodiments of the present disclosure may also drive a second rectifier switch in the same or similar manner as the first rectifier switch.

[0009] In one embodiment, a method includes driving a rectifier switch of a synchronous rectifier with a gate drive signal during a cycle including an on-phase and an off-phase. The method includes estimating an output current of the rectifier switch during the on-phase to measure a voltage across the rectifier switch, and adjusting a voltage of the gate drive signal during at least a portion of the on-phase based on the output current.

[0010] In one embodiment, a device includes a synchronous rectifier driver circuit configured to drive a first rectifier switch. The driver circuit includes a shaping circuit configured to receive a drain voltage signal indicative of a voltage at a drain terminal of the rectifier switch and generate a gate drive reference voltage. The shaping circuit is configured as a voltage regulator configured to receive the gate drive reference voltage and a power supply voltage and generate a driver supply voltage based on the gate drive reference voltage. The shaping circuit is configured as a gate driver having a first input configured to receive the gate drive reference voltage, a power supply input configured to receive the driver supply voltage, and an output configured to output a gate drive signal to a gate terminal of the rectifier switch.

[0011] In one embodiment, a method includes driving a rectifier switch of a resonant converter using a driver circuit of the resonant converter, receiving a drain voltage of the rectifier switch using a shaping circuit of the driver circuit, and generating a gate drive reference voltage based on the drain voltage using the shaping circuit. The method includes generating a driver supply voltage based on the gate drive reference voltage using a voltage regulator of the driver circuit, and receiving the driver supply voltage at a supply voltage terminal of a gate driver of the driver circuit. The method includes receiving the gate drive reference voltage at an input terminal of the gate driver and outputting a gate drive signal from the gate driver to a gate terminal of the rectifier switch.

[0012] In one embodiment, a method includes, using a driver circuit of a resonant converter, driving a rectifier switch of the resonant converter with a gate drive signal based on a gate drive reference signal, and receiving a drain voltage of the rectifier switch using a shaping circuit of the driver circuit. The method includes generating, using the shaping circuit, the gate drive reference voltage based on the drain voltage and a gain parameter. The method includes performing, using the shaping circuit, a first comparison of the gate drive reference voltage with a first threshold value during a first cycle of the gate drive signal, and adjusting the gain parameter for a second cycle of the gate drive signal based at least in part on the first comparison.

[0013] In one embodiment, a device includes a synchronous rectifier driver circuit configured to drive a rectifier switch using a gate drive signal and includes a shaping circuit. The shaping circuit is configured to receive a drain voltage signal indicative of a voltage at a drain terminal of the rectifier switch and generate a gate drive reference voltage based on the drain voltage and a gain parameter. The shaping circuit is configured to perform a first comparison of the gate drive reference voltage with a first threshold during a first cycle of the gate drive signal and adjust the gain parameter for a second cycle of the gate drive signal based at least in part on the first comparison.

[0014] In one embodiment, a method includes driving a rectifier switch of a synchronous rectifier with a gate drive signal and generating a gate drive reference voltage based on a product of a drain voltage of the rectifier switch and a gain parameter. The method includes performing a first comparison of the gate drive reference voltage with a first threshold value and adjusting the gain parameter based at least in part on the first comparison. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided purely by way of non-limiting examples.

[0016] The characteristics and advantages of the present disclosure will become clear from the following detailed description of a practical embodiment of the disclosure illustrated by way of non-limiting example in the accompanying drawings, in which:

[0017] Figure 1 is a schematic diagram of a resonant converter according to one embodiment;

[0018] Figure 2A and Figure 2B A diagram including signals associated with a resonant converter according to one embodiment;

[0019] Figure 3 is a block diagram of a driver circuit of a synchronous rectifier of a resonant converter according to one embodiment;

[0020] Figure 4is a block diagram of a driver circuit of a synchronous rectifier of a resonant converter according to one embodiment;

[0021] Figure 5 is a schematic diagram of a voltage regulator of a driver circuit of a synchronous rectifier according to one embodiment;

[0022] Figure 6 is a schematic diagram of a portion of a shaping circuit of a synchronous rectifier driving circuit according to an embodiment;

[0023] Figure 7 is a schematic diagram of a portion of a shaping circuit of a synchronous rectifier driving circuit according to an embodiment;

[0024] Figure 8 including diagrams associated with a driver circuit for a synchronous rectifier according to one embodiment;

[0025] Figure 9 is a flow chart of a method for adjusting a gain factor associated with a driver circuit of a synchronous rectifier according to one embodiment;

[0026] Figure 10 is a flow chart of a method for operating a synchronous rectifier according to one embodiment;

[0027] Figure 11 is a flow chart of a method for operating a synchronous rectifier according to one embodiment;

[0028] Figure 12 is a flow chart of a method for operating a synchronous rectifier according to one embodiment; and

[0029] Figure 13 is a flow chart of a method for operating a synchronous rectifier according to one embodiment. DETAILED DESCRIPTION

[0030] In the following description, various specific details are shown to provide a deeper understanding of the embodiments. The embodiments may be provided without one or more of the specific details or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so that aspects of the embodiments are not obscured.

[0031] References to "an embodiment" or "one embodiment" within the framework of this specification mean that the particular configuration, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," and the like that may appear in various places in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, the particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0032] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, one skilled in the relevant art will recognize that the embodiments can be practiced without one or more of these specific details, or using other methods, components, materials, etc. In other instances, well-known algorithms related to facial recognition, facial detection, and facial authentication are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0033] Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and variations thereof (such as "comprises" and "comprising") should be interpreted in an open and inclusive sense, i.e., "including but not limited to." Furthermore, unless the context clearly dictates otherwise, "first," "second," and similar ordinal indicators should be interpreted as interchangeable.

[0034] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0035] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the word "or" is generally used in its broadest sense, meaning "and / or," unless the content clearly dictates otherwise.

[0036] Figure 1 is a schematic diagram of a resonant converter 100 according to one embodiment. The resonant converter 100 may be an LLC resonant converter. As will be described in more detail below, the components of the resonant converter cooperate to provide a gate drive voltage for the rectifier switches of the resonant converter, which enables more efficient operation in terms of power consumption while maintaining the effectiveness of the resonant converter 100. More details about the resonant converter can be found in U.S. patent application No. 17 / 490,793, filed on September 9, 2021, which was subsequently issued on November 14, 2023 as U.S. Patent No. 11,817,791. The entire contents of U.S. patent application No. 17 / 490,793 are incorporated herein.

[0037] As will be explained in more detail below, in one embodiment, the resonant converter 100 includes a synchronous rectifier including a driver circuit that drives a gate terminal of the synchronous rectifier switch with a gate drive voltage that is proportional to a current flowing through the synchronous rectifier switch during at least a portion of the conduction phase of the synchronous rectifier switch.

[0038] As will be described in greater detail below, in one embodiment, the resonant converter 100 includes a synchronous rectifier that includes a driver circuit. The driver circuit drives the gate terminal of the synchronous rectifier switch with a gate drive voltage based on a gate drive reference signal. The gate drive reference voltage is generated based at least in part on a voltage or current associated with the synchronous rectifier switch multiplied by a gain parameter. The driver circuit automatically and continuously updates the gain parameter to maintain efficient and effective drive of the rectifier switch.

[0039] The resonant converter 100 includes an input terminal that receives a high input voltage Vin and an input terminal coupled to a ground voltage GND1. In other words, the input voltage Vin is applied across the input terminals of the resonant converter 100. The input voltage Vin can be a DC voltage provided by a DC generator such as a battery or another DC voltage source. The input voltage Vin can also be generated by rectifying an AC voltage using a rectifier circuit (such as a bridge rectifier). The bridge rectifier can include a filter circuit, such as a capacitor.

[0040] The resonant converter 100 includes a high output terminal 102a and a low output terminal 102b. An output voltage Vout is output across the output terminals 102a and 102b. The output voltage Vout may be a DC output voltage. Alternatively or additionally, an output current Iout may be provided across the terminals 102a and 102b. The output voltage or output current may be used to drive a load.

[0041] In one embodiment, the resonant converter 100 includes a half-bridge circuit including two switches SW1 and SW2 . The switches SW1 and SW2 are coupled in series between input terminals of the resonant converter 100 .

[0042] In one embodiment, switches SW1 and SW2 are NMOS transistors. The drain terminal of SW1 is coupled to the high input voltage terminal. The source terminal of SW1 is coupled to the drain terminal of SW2. The source terminal of SW2 is coupled to ground.

[0043] In one embodiment, the resonant converter 100 includes a driver circuit 104 that drives switches SW1 and SW2 of the half-bridge circuit. Additional details regarding the driver circuit 104 are provided below.

[0044] The transformer T includes a primary winding T1 on the input side and a center-tapped secondary winding on the output side, which includes a first secondary winding T2a and a second secondary winding T2b connected in series. The input side of the resonant circuit block includes a first inductor Ls coupled between the output node of the half-bridge circuit and the primary winding T1. The input side of the resonant circuit block includes a second inductor Lp and a capacitor Cr. The second inductor Lp is coupled in parallel with the primary winding T1. The capacitor Cr is coupled between the second inductor Lp and the source terminal of the switch SW2. Other configurations of the resonant circuit block on the input side may be utilized without departing from the scope of the present disclosure. In practice, the two windings T1 and T2 may not be fully coupled. In addition, there may be leakage inductance and magnetizing inductance associated with the transformer. The leakage inductance can be modeled via an inductor connected in series with the primary winding T1. Conversely, the magnetizing inductance of the transformer T (used to model magnetic flux) can be modeled using an inductor connected in parallel with the primary winding T1. Therefore, the inductance Ls may correspond to the leakage inductance of the transformer T and may be implemented by an inductor connected in series with the primary winding T1, or may be generated by both the leakage inductance of the transformer T and such an inductor. Similarly, the inductance Lp may correspond to the magnetizing inductance of the transformer T and may be implemented by an inductor connected in parallel with the primary winding T1, or may be generated by both the magnetizing inductance of the transformer T and such an inductor. Therefore, in practice, the inductors Lp and Ls and the transformer T may be integrated into a single component.

[0045] As previously described, the secondary side of the transformer T includes a center-tapped arrangement, i.e., the secondary winding T2 includes a first terminal coupled to the drain terminal of the first rectifier switch SR1, a second terminal coupled to the drain of the second rectifier switch SR2, and a center-tapped terminal coupled to the output terminal 102a. In one embodiment, the rectifier switches SR1 and SR2 correspond to NMOS transistors. Without departing from the scope of this disclosure, the rectifier switches SR1 and SR2 may include other types of switches.

[0046] As will be explained in more detail below, switches SR1 and SR2 perform a rectification function. Thus, due to the rectification function of transistors SR1 and SR2, terminal 102a corresponds to a positive output terminal and terminal 102b corresponds to a negative output terminal, which generally corresponds to the second ground GND2.

[0047] In one embodiment, the resonant converter 100 may further include an output filter connected between the output terminals 102a and 102b. Figure 1 , capacitor Cout is connected (eg, directly) between output terminals 102a and 102b.

[0048] Returning to the input side of the resonant converter 100 , the gate terminals of the switches SW1 and SW2 are driven via a driver circuit 104 , which is configured to generate respective drive signals HSGD and LSGD for the electronic switches SW1 and SW2 .

[0049] In one embodiment, driver circuit 104 generally drives switches SW1 and SW2 in a selected manner to apply a square wave having a frequency close to the frequency of the resonant tank to switch node HB, i.e., the node to which the source of SW1 and the drain of SW2 are connected. In this manner, the resonant tank (Lp, Ls, and Cr) behaves as a tuned filter, and the current is formed by a single fundamental harmonic of the Fourier series expansion and is therefore effectively a sinusoidal curve.

[0050] In one embodiment, the driver circuit 104 is configured to generate the drive signals HSGD and LSGD so that the following four phases are repeated during each switching cycle: a first time interval or phase, which includes closing the first electronic switch SW1 and opening the second electronic switch SW2, thereby connecting the switch node HB to the positive input voltage Vin. A second time interval or phase, which includes opening both the first electronic switch SW1 and the second electronic switch SW2. A third time interval or phase, which includes opening the first electronic switch SW1 and closing the second electronic switch SW2, thereby connecting the switch node HB to the negative input node, such as ground GND1. A fourth time interval or phase, which includes opening both the first electronic switch SW1 and the second electronic switch SW2.

[0051] In order to realize soft switching using the resonance of the resonant circuit, the second time interval and the fourth time interval may be useful. Figure 1 The LLC topology shown allows ZVS (zero voltage switching) of switches SW1 and SW2 on the primary side and ZCS (zero current switching) of diodes D1 and D2 on the secondary side, thereby allowing efficient operation of the converter at high switching frequencies.

[0052] In one embodiment, the electronic converter provides a voltage Vout and a current Iout via output terminals 102a and 102b. Typically, a closed loop (often implemented using a negative feedback control system) maintains the converter's output voltage Vout or output current Iout constant as operating conditions change (e.g., changes in input voltage Vin and / or output load 30). As previously described, regulation of the converter's output voltage Vout or output current Iout is achieved by varying the switching frequency of the square wave at the input of the switching node HB / resonant tank.

[0053] Returning to the output side of the stationary circuit 100, in one embodiment, the resonant circuit 100 includes a synchronous rectifier driver 106. The synchronous rectifier driver 106 is configured to drive switches SR1 and SR2 to emulate ideal diodes. The core function of the synchronous rectifier driver 106 is to turn on each synchronous rectifier switch SR1 and SR2 whenever the corresponding transformer half-winding T2a or T2b begins conducting.

[0054] Each of the synchronous rectifier switches SR1 and SR2 has an associated body diode. Therefore, the synchronous rectifier driver 106 turns on a given synchronous rectifier switch SR1 or SR2 when the corresponding diode begins to conduct, and turns off the synchronous rectifier switch when the flowing current approaches zero. To achieve high efficiency, the rectifier driver 106 controls the channel conduction time to reduce the diode conduction time.

[0055] exist Figure 1 In the simplified view of FIG, driver 106 includes an input terminal coupled to the drain terminal of rectifier switch SR1. Driver 106 includes an input terminal coupled to the drain terminal of rectifier switch SR2. Driver 106 includes an output terminal coupled to the gate terminal of first rectifier switch SR1. Driver 106 includes an output terminal coupled to the gate terminal of second driver switch SR2. Driver 106 includes an input terminal for receiving a value k, an input terminal for receiving a value V1, and an input terminal for receiving a power supply voltage VCC. Although not shown, driver 106 may also include a terminal for receiving a ground reference voltage. Driver 106 may include other terminals or terminal combinations without departing from the scope of this disclosure.

[0056] In one embodiment, the driver 106 applies a first gate drive signal GD1 to the first rectifier switch SR1. The driver 106 applies a second gate drive signal GD2 to the second rectifier switch SR2. The gate drive signals turn the rectifier switches on and off. When the first rectifier switch SR1 is turned on, the first rectifier current I SR1 Flows through the first rectifier switch SR1. When the second rectifier switch SR2 is turned on, the second rectifier current I SR2 flows through the second rectifier switch SR2.

[0057] Driver 106 receives a drain voltage signal DVS1 corresponding to the drain voltage of switch SR1. Driver 106 receives a drain voltage signal DVS2 corresponding to the drain voltage of switch SR2. As will be explained in more detail below, driver 106 senses drain voltage signals DVS1 and DVS2 and generates gate drive signals GD1 and GD2 based in part on the sensed drain voltage signals DVS1 and DVS2.

[0058] In one embodiment, the driver 106 generates the gate drive signals GD1 and GD2 according to the following formula:

[0059] VGD=V1+k*DVS,

[0060] Where VGD is the voltage level of the gate drive signal GD. In one embodiment, the voltage value V1 and the gain factor k are received via a dedicated input terminal of the driver 106, such as Figure 1 However, the voltage value V1 and the gain parameter k can be based on external sensing parameters (such as I SR1 , I SR2 , DVS1, DVS2 or other sensed values) are generated internally within the driver 106.

[0061] In one embodiment, the received or generated values ​​V1 and k set the ratio between the gate drive voltage and DVS. This approach can selectively increase the internal on-resistance RDSON of the corresponding rectifier switch SR to improve the efficiency of the switch SR. The internal on-resistance RDSON corresponds to the effective resistance of the switch SR when the switch SR is conducting current. In one embodiment, when the current approaches zero, the driver 106 selectively increases the RDSON of the rectifier switch SR to amplify the DVS voltage signal, thereby better detecting the zero crossing of the rectifier switch current.

[0062] about Figure 2A and Figure 2B The function of the driver 106 may be better understood. Figure 2A Included is a graph 200 that provides a simplified illustration of signals and values ​​associated with operation of the rectifier switch SR by the driver 106 .

[0063] In simplified form, during the first phase, labeled PH1, gate drive signal GD1, represented by curve 208, goes high, thereby turning on rectifier switch SR1. Gate drive signal GD2, represented by curve 209, is low during the first phase. Curve 204 represents the current flowing through rectifier switch SR1 during the first phase. Dashed curve 206 represents drain voltage signal DVS1 of rectifier switch SR1. Curve 210 illustrates internal reference signal VGD_REF, as described in more detail below.

[0064] During the second phase, labeled PH2, GD1 is low and GD2 goes high, turning on the rectifier switch SR2. Curve 205 represents the current flowing through the rectifier switch SR2 during the second phase. Dashed curve 207 represents the drain voltage signal DVS2 of the rectifier switch SR2.

[0065] like Figure 2AAs shown, when the current IS is about to start flowing, the corresponding drain voltage signal DVS changes from a high voltage to a negative voltage. When the current flows through the body diode of the rectifier switch SR, the drain voltage signal DVS becomes negative. The rectifier circuit detects this situation and, in response thereto, turns on the gate drive signal GD. Therefore, after the current ISR starts to flow, the gate drive signal GD becomes high. When the gate drive signal GD becomes high, the drain voltage signal DVS becomes essentially 0V and then follows a shape that is essentially a mirror image of the shape of the current ISR. When GD becomes low and the switch SR is turned off and the current ISR is still flowing, the drain voltage signal DVS returns to a negative value. The drain voltage signal DVS becomes a high voltage only after the ISR current is zero. As previously described, Figure 2A The view is simplified. In practice, the gate drive signal GD and the drain voltage signal DVS have different shapes, such as Figure 2B shown.

[0066] exist Figure 2B In FIG2 , when current ISR (not shown) begins to flow, the corresponding DVS drops to a low voltage, as shown by curve 206. GD then goes high, as shown by curve 208. The conduction phase of switch SR then begins, and DVS rises to a voltage slightly below 0V. For the first half of this phase, gate drive signal GD has a substantially flat value. However, halfway through this phase, at time t1, driver 106 adjusts how it generates the gate drive signal. Specifically, as previously described, at or shortly after time t1, driver circuit 106 begins generating gate drive signal GD1 with a voltage level VGD equal to V1+k*DVS. In one embodiment, driver 106 utilizes a peak detector to detect a negative peak or a corresponding positive peak in DVS and ISR to identify the midpoint of the corresponding conduction phase, time t1.

[0067] After time t1, driver 106 is operating to discharge the gate capacitance of rectifier switch SR2 to a target voltage VGD_REF set by driver 106, as described in more detail below. The terms V1 and k can be programmed via external programming pins to accommodate different external loads of residential circuit 100. When gate drive signal GD reaches a value between times T1 and T2, gate drive signal GD decreases. At time T2, gate drive signal GD is very close to the threshold voltage Vth of the corresponding rectifier switch SR. When the gate drive signal approaches the threshold voltage of rectifier switch SR, the internal on-resistance RDSON of switch SR begins to increase significantly. This causes a change in the slope of DVS. In this case, rectifier switch SR operates with a high RDSON. At time T3, ISR (not shown) returns to zero, and DVS quickly crosses zero. The zero crossing of DVS is detected by driver 106. Driver 106 sets gate drive signal GD to 0 at time T3 to turn off rectifier switch SR. Driver 106 can utilize a zero-crossing detector to detect the zero crossing of DVS.

[0068] In one embodiment, the gate drive voltage of the rectifier switch SR is controlled in a manner proportional to the current flowing through the rectifier switch. This has the effect of shaping DVS to improve gate drive control.

[0069] Figure 3 is a block diagram of the driver circuit 106 according to one embodiment. Figure 3 The driver circuit 106 is Figure 1 1 . An example of a driver circuit 106 is shown in FIG. 1 . The driver circuit 106 includes a gate driver 110. The gate driver 110 generates a gate drive signal GD. The driver circuit 106 includes a shaping circuit 112 that generates a gate drive reference signal VGD_REF. As will be explained in more detail below, the gate drive reference signal VGD_REF is provided to the gate driver 110, and the gate driver 110 generates a gate drive signal based on the gate drive reference signal VGD_REF. The driver circuit 106 also includes a zero crossing detector 114. The zero crossing detector 114 may correspond to a comparator that receives a ground voltage on a non-inverting input and a drain voltage signal DVS on an inverting input. After DVS crosses ground, the comparator 114 generates a signal that causes the gate driver 110 to turn off the rectifier switch SR by setting the gate drive signal to 0.

[0070] The shaping circuit 112 is connected to an external pin (such as Figure 1 The external input shown receives the drain voltage signal DVS and the values ​​V1 and k. The shaping circuit 112 generates VGD_REF as follows:

[0071] VGD_REF=V1+k*DVS.

[0072] Although Figure 3 Only a single gate driver 110, a single shaping circuit 112, and a single comparator 114 are shown, but in practice, the driver circuit 106 includes a pair of each of these components. The first shaping circuit 112 can receive DVS1 and generate VGD_REF for the first gate driver 110. The first gate driver 110 can generate a first gate drive signal GD1 for the first rectifier switch SR1. The first comparator 114 can generate a shutdown signal for the first gate driver 110. The second shaping circuit 112 can receive DVS2 and generate VGD_REF for the second gate driver 110, which provides a second gate drive signal GD2 to the second rectifier switch SR2. The second comparator 114 can provide a shutdown signal to the second gate driver 110.

[0073] Figure 4 FIG. 1 is a schematic diagram of a driver circuit 106 according to one embodiment. The driver circuit 106 is Figure 1 or Figure 3 The driver circuit 106 includes a VDS shaping circuit 112 that generates a reference signal VGD_REF as previously described based on DVS, V1, and k, or in some other suitable manner.

[0074] The driver circuit 106 further includes a voltage regulator 115. The voltage regulator 115 receives VGD_REF from the shaping circuit 112. The voltage regulator 115 receives a power supply voltage VCC from an external input. The voltage regulator 115 generates a driver power supply voltage VDRV based on VGD_REF and VCC. The voltage regulator 115 provides the driver power supply voltage VDRV to the gate driver 110. The external capacitor C EXT is coupled to a terminal of the driver circuit 106 and is charged to a voltage VDRV to eliminate or reduce fluctuations in VDRV. Alternatively, capacitor C EXT May be an internal component of driver circuit 106. VDRV helps enable driver circuit 110 to generate gate drive signal GD to drive rectifier switch SR in a selected, efficient manner.

[0075] The gate driver 110 includes a first input that receives VGD_REF from the shaping circuit 112. The gate driver 110 also includes an input that receives an on signal for turning the driver signal on. The gate driver 110 also includes an input that receives an off signal for turning the driver signal off. In practice, a single terminal may receive the signal that turns the driver signal on and off. The high supply terminal of the driver 110 receives the voltage from the regulator 115 and the external capacitor C EXTReceives the driver supply voltage VDD RV.

[0076] In one embodiment, the drain voltage signal DVS is based on RDSON and ISR. Specifically:

[0077] DVS=RDSON*ISR.

[0078] Furthermore, RDSON is based on the gate-to-source voltage of the rectifier switch SR. When the source of SR is coupled to ground, RDSON can be controlled by controlling the voltage level VGD of the gate drive signal GD. As VGD decreases, ISR increases. Furthermore, the power loss of the rectifier switch SR is given by the following formula:

[0079] Ploss=RDSON*(ISR)^2+VDRV*VCC*fs*Cg, where fs is the switching frequency of the rectifier switch SR, and Cg is the gate capacitance of the rectifier switch SR.

[0080] In one example, VCC is 12 V and VDRV is approximately 10.5 V. In practice, VDRV may vary during use of the driver circuit 106. Figure 2A and Figure 2B , the voltage regulator 115 may generate VDRV based on the average peak value of VGD_REF over multiple cycles. For example, Figure 2A Periods n, n+1, and n+2 are shown. Voltage regulator 115 can measure and record the peak voltage level of VGD_REF over multiple periods and can generate VDRV, which is the average value of VGD_REF, across a selected number of periods. In one embodiment, VDRV varies between periods but does not vary during a period.

[0081] Continue to refer Figure 2B , before time t1, VGD is equal to VDRV. After time t1, VGD is equal to V1+k*DVS, as described above.

[0082] Back to Figure 4 As previously mentioned, the driver circuit 106 may generate a separate VGD_REF and gate driver signal GD for each rectifier switch SR. Therefore, the driver circuit 106 may include Figure 4 Two copies of each component shown.

[0083] Figure 5 is a schematic diagram of the voltage regulator 115 according to one embodiment. Figure 5 The voltage regulator 115 is Figure 41 and 2. The voltage regulator 115 is an example of a voltage regulator 115. The voltage regulator 115 receives VGD_REF from the shaping circuit 112. In one embodiment, the VGD_REF received at the input of the voltage regulator 115 is a multiplexed signal. In particular, as previously described, there are two shaping circuits 114. The first shaping circuit 112 outputs VGD_REF for the first rectifier switch SR1. The second shaping circuit 112 outputs VGD_REF for the second rectifier switch SR2. Thus, although not shown, a multiplexer can receive these two VGD_REF signals and can provide them to the voltage regulator 115 in a multiplexed manner. The voltage regulator 115 includes a node AV that stores VGD_REF or the average of both SR1 and SR2. The capacitor C 存储 It has a first terminal coupled to node AV and a second terminal coupled to ground.

[0084] Voltage regulator 115 includes a diode D0, a switch S1, and a switch S4 coupled between VGD_REF and node AV. Capacitor C1 has a first terminal coupled between switches S1 and S4 and a second terminal coupled to ground. Diode D3 and resistor R2 are coupled between VGD_REF and node AV. MIN and the first terminal of the capacitor C1. This corresponds to the circuit branch of VGD_REF of the first rectifier switch SR1.

[0085] When SR1 is initially turned on, switch S1 is closed. If VGD_REF1 is greater than the voltage stored on the first terminal of capacitor C1, current will flow through diode D0 and charge capacitor C1. When the DVS of rectifier switch SR1 reaches the peak voltage, switch S1 is opened and switch S4 is closed. This causes the charge to be distributed across C 存储 If the voltage on C1 is greater than C 存储 The voltage on C 存储 The voltage across will increase. If C 存储 The voltage on C1 is greater than the voltage on C2. 存储 The voltage across will decrease. The capacitance of capacitor C1 is equal to C 存储 When S1 or S4 is closed, switches S2, S3 and S5 are open.

[0086] Voltage regulator 115 includes a diode D1, a switch S2, and a switch S5 coupled between VGD_REF and node AV. Capacitor C2 has a first terminal coupled between switches S2 and S5 and a second terminal coupled to ground. Diode D2 and resistor R3 are coupled between VGD_REF and node AV. MIN Between the first terminal of the capacitor C2. This corresponds to the circuit branch of VGD_REF of the second rectifier switch SR2.

[0087] When SR2 is initially turned on, switch S2 is closed. If VGD_REF2 is greater than the voltage stored on the first terminal of capacitor C2, current will flow through diode D1 and charge capacitor C2. When the DVS of rectifier switch SR2 reaches the peak voltage, switch S2 is opened and switch S5 is closed. This causes the charge to be distributed across C 存储 If the voltage on C2 is greater than C 存储 The voltage on C 存储 The voltage across will increase. If C 存储 The voltage on C is greater than the voltage on C2, then C 存储 The voltage across will decrease. The capacitance of capacitor C2 is equal to C 存储 When S1 or S4 is closed, switches S1, S3 and S4 are open.

[0088] The voltage regulator 115 is also configured to selectively operate in a burst mode. In the burst mode, switches S1, S2, S4, and S5 are all open and switch S3 is closed. This results in a voltage supply to capacitor C 存储 Provides maximum voltage VGD_REF MAX This will cause the capacitor C 存储 Charge to the maximum voltage VGD_REF MAX .

[0089] Diode D4 and resistor R4 are also coupled to VGD_REF MIN With capacitor C 存储 Therefore, if the capacitor C 存储 The voltage on the MIN Below, the diode D4 becomes conductive, and C 存储 Charged to the minimum voltage VGD_REF MIN .

[0090] In one embodiment, voltage regulator 115 includes a switch S6 coupled in parallel with capacitor C1. Switch S6 can be used to selectively initialize or reset the voltage of capacitor C1 before closing switch S1. For example, by closing switch S6, the voltage on capacitor C1 can be initialized or reset to ground. After resetting the voltage on capacitor C1, switch S6 is opened. Then, switch S1 can be closed to perform the aforementioned functions.

[0091] In one embodiment, voltage regulator 115 includes a switch S7 coupled in parallel with capacitor C2. Switch S7 can be used to selectively initialize or reset the voltage of capacitor C2 before closing switch S2. For example, by closing switch S7, the voltage on capacitor C2 can be initialized or reset to ground. After resetting the voltage on capacitor C2, switch S7 is opened. Then, switch S2 can be closed to perform the above-described functions.

[0092] The voltage regulator 115 includes an operational amplifier 116. The operational amplifier includes a capacitor C coupled to 存储 An external capacitor Cext may also be coupled to the output of the operational amplifier 116 .

[0093] In one embodiment, resistor R1 has a value of 5 kΩ, resistor R2 has a value of 50 kΩ, resistor R3 has a value of 50 kΩ, and resistor R4 has a value of 5 kΩ. In one embodiment, C1 is equal to C2 and C 存储 / m, where m is the number of cycles over which the average value is calculated. Resistors R1-R4 and capacitors C1, C2, and C 存储 Other values ​​of .

[0094] use Figure 4 and Figure 5 The voltage regulator 115 and driver circuit 106 have various benefits. For example, during the rectifier switch turn-off phase (t>t1), the DVS shaping control always starts from the correct voltage level. The change in gate voltage level with output current improves conversion efficiency, especially for high-frequency applications, because the load is light and the gate switching losses are reduced. In one embodiment, under steady-state conditions when the converter is operating at medium / high load, the gate drive is set to the desired maximum value VGD_REF as the load decreases. MAX , the gate drive voltage also decreases.

[0095] Figure 6 is a simplified schematic diagram of the shaping circuit 112 according to one embodiment. The shaping circuit 112 is Figure 1 、 Figure 3 and Figure 4An example of a shaping circuit 112 is shown. Shaping circuit 112 includes a voltage-controlled current source that generates current I1 based on its internal resistance R7 and DVS. External resistor R5 is coupled to an external terminal coupled to the output of the first current source. Driver circuit 106 includes a second current source that generates current I2. External resistor R6 is coupled to an external terminal coupled to the output of the second current source. The voltage at the output of the first current source is VREFDVS. The voltage at the output of the second current source is VREFVTH. The adder outputs VGD_REF as the sum of VREFDVS and VREFVTH.

[0096] In one embodiment, VREFVTH equals I2*R6 and is a constant corresponding to V1. In one embodiment, VREFDVS equals I1*R5 (which equals DVS*R5 / R7). As a result, the gain factor k equals R5 / R7. Therefore, VREFDVS = k*DVS. This is a way to set the value k and V1 through external input via resistors R5 and R6.

[0097] Figure 7 FIG. 1 is a schematic diagram of a shaping circuit 112 according to an embodiment. The shaping circuit 112 is Figure 1 、 Figure 3 and Figure 4 An example of a shaping circuit 112 is shown. Shaping circuit 112 includes a first voltage-controlled current source that generates current I1 and includes an internal resistor R7 (not shown) and is controlled by DVS. Variable resistor R5 is coupled between the first current source and ground. The output node of the first current source provides voltage VREFDVS. Shaping circuit 112 includes a second current source that generates current I2. Resistor R6 is coupled between the second current source and ground. The output node of the second current source provides voltage VREFVTH. An adder generates VGD_REF by adding VREFDVS and VREFVTH.

[0098] The value of variable resistor R5 is set by the automatic gain calibration process. Setting the value of variable resistor R5 corresponds to setting the value of gain parameter k, since k = R5 / R7. As will be explained in more detail below, other calibration processes enable the gain parameter k to be configured for the selected rectifier switch. Other calibration processes may also be active. Therefore, if the characteristics of rectifier switch SR change, for example, if the temperature changes, the gain parameter k may change.

[0099] In one embodiment, VREFVTH is equal to I2*R6 and is a constant corresponding to V1. In one embodiment, VREFDVS is equal to I1*R2 (which is equal to DVS*R2 / R7). As a result, the gain factor k is equal to R5 / R7. Therefore, VREFDVS=k*DVS.

[0100] Figure 8 The diagram shows a method including Figure 1 800 of the signals associated with the rectifier switch SR. Graph 800 is similar in many respects to Figure 2B The graphs are basically similar. However, in Figure 8 Medium, value DVS TH FL The value VGD is shown as the threshold value of DVS. MAXTH Also shown is the threshold value of VGD_REF. As will be explained in more detail below, DVS TH FL and VGD MAXTH Used for automatic calibration process of gain parameter k.

[0101] In one embodiment, the gain parameter k is initially set to a minimum value. In one example, the starting value is 40. Each cycle, the signal VGD_REF is compared with VGD MAXTH In one example, VGD MAXTH is 10V.

[0102] After one cycle, if VGD_REF is less than VGD MAXTH , and DVS is less than DVS TH FL , then k increases. In one example, DVS TH FL After one cycle, if VGD_REF is greater than VGD MAXTH , then k is decremented. If the switching cycle is closed before time t1, then k is not updated.

[0103] If the rectifier switch SR is turned off prematurely after t1 but before 75% of the previous cycle duration, k is decremented. This may indicate circuit instability.

[0104] Under steady-state conditions, the VGD_REF peak can be MAXTH The jitter may depend on the increment / decrement step value selected (e.g., k is incremented or decremented by 1 or some other step value). k saturates to a maximum value. In one example, the maximum k value is 150.

[0105] In one embodiment, if VGD_REF is less than VGD MAXTHAnd DVS is smaller than DVS TH FL , and if k is less than the maximum k value, k can be updated every cycle. In one embodiment, when VGD_REF is greater than VGD MAXTH Thereafter, or if k=maximum, k may be updated every nth cycle. In one example, n=8. In one example, k ranges from 50 to 150. Other values ​​and parameters may be used without departing from the scope of the present disclosure.

[0106] Figure 9 is a flow chart of a method 900 for adjusting a gain parameter k used when writing a rectifier switch of a resonant converter according to one embodiment. Figures 1-8 The components, processes and systems described herein. Method 900 may correspond to an automatic calibration process for a gain parameter k. At 902, the gain parameter k is set to an initial value. In one embodiment, the initial value is the minimum value of k. At 904, VGD_REF is compared to VGD MAXTH Compare and contrast DVS with DVS TH FL At 906, if VGD_REF is less than VGD MAXTH And if DVS is less than DVS TH FL , then k is incremented by the selected step value. In one example, the selected step value is 10, but other values ​​may be used without departing from the scope of this disclosure. At 908, if VGD_REF is greater than VGD MAXTH , then k is decremented by the step value. Without departing from the scope of the present disclosure, the method 900 may utilize other steps or combinations of steps, such as Figure 8 The steps described.

[0107] Automatic calibration of the gain parameter k eliminates the tedious manual parameter configuration process and provides a simple solution for users of resonant converters. This saves costs because the additional external components required for manual configuration are not required. It also speeds up start-up time. Furthermore, there is no need to change the configuration every time the external rectifier switch MOSFET is changed. The DVS shaping control is correctly configured regardless of changes in the rectifier switch SR.

[0108] Figure 10 is a flow chart of a method 1000 for operating a synchronous rectifier according to one embodiment. The method 1000 may utilize Figures 1-9At 1002, method 1000 includes driving a rectifier switch of a synchronous rectifier with a gate drive signal during a cycle including an on-phase and an off-phase. At 1004, method 1000 includes estimating an output current of the rectifier switch during the on-phase to measure a voltage across the rectifier switch. At 1006, method 1000 includes adjusting a voltage of the gate drive signal during at least a portion of the on-phase based on the output current.

[0109] Figure 11 is a flow chart of a method 1100 for operating a synchronous rectifier according to one embodiment. The method 1100 may utilize Figures 1-9 The method 1100 includes, at 1102, driving a rectifier switch of a synchronous rectifier with a gate drive signal. At 1104, the method 1100 includes generating a gate drive reference voltage based on a product of a drain voltage of the rectifier switch and a gain parameter. At 1106, the method 1100 includes performing a first comparison of the gate drive reference voltage with a first threshold value. At 1108, the method 1100 includes adjusting the gain parameter based at least in part on the first comparison.

[0110] Figure 12 is a flow chart of a method 1200 for operating a synchronous rectifier according to one embodiment. The method 1200 may utilize Figures 1-9 The components, processes, and systems described herein are described herein. At 1202, method 1200 includes driving a rectifier switch of the resonant converter using a driver circuit of the resonant converter. At 1204, method 1200 includes receiving a drain voltage of the rectifier switch using a shaping circuit of the driver circuit. At 1206, method 1200 includes generating a gate drive reference voltage based on the drain voltage using the shaping circuit. At 1208, method 1200 includes generating a driver supply voltage based on the gate drive reference voltage using a voltage regulator of the driver circuit. At 1210, method 1200 includes receiving the driver supply voltage at a supply voltage terminal of a gate driver of the driver circuit. At 1212, method 1200 includes receiving the gate drive reference voltage at an input terminal of the gate driver. At 1214, method 1200 includes outputting a gate drive signal from the gate driver to a gate terminal of the rectifier switch.

[0111] Figure 13 is a flow chart of a method 1300 for operating a synchronous rectifier according to one embodiment. The method 1300 may utilize Figures 1-9The components, processes, and systems described herein. At 1302, method 1300 includes, using a driver circuit of the resonant converter, driving a rectifier switch of the resonant converter with a gate drive signal based on a gate drive reference signal. At 1304, method 1300 includes, using a shaping circuit of the driver circuit, receiving a drain voltage of the rectifier switch. At 1306, method 1300 includes, using the shaping circuit, generating a gate drive reference voltage based on the drain voltage and a gain parameter. At 1308, method 1300 includes, using the shaping circuit, performing a first comparison of the gate drive reference voltage with a first threshold value during a first cycle of the gate drive signal. At 1310, method 1300 includes adjusting a gain parameter for a second cycle of the gate drive signal based at least in part on the first comparison.

[0112] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to encompass all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A method comprising: driving a rectifier switch of the synchronous rectifier with a gate drive signal during a cycle including an on-phase and an off-phase; estimating an output current of the rectifier switch during the conduction phase; as well as During at least a portion of the conduction phase, a voltage of the gate drive signal is adjusted based on the output current. 2 . The method of claim 1 , wherein estimating the output current comprises measuring a drain voltage of the rectifier switch, and wherein adjusting the voltage of the gate drive signal comprises adjusting the voltage of the gate drive signal based on the drain voltage.

3. The method according to claim 1, comprising: maintaining the voltage of the gate drive signal at a maximum value during a first portion of the conduction phase; as well as During a second portion of the on-phase, the voltage of the gate drive signal is adjusted proportionally to the output current.

4. The method according to claim 3, comprising: generating a gate drive reference voltage based on a drain voltage of the rectifier switch; generating a gate driver supply voltage based on the gate drive reference voltage; receiving the driver supply voltage at a power supply terminal of the gate driver; receiving the gate drive reference voltage at an input terminal of the gate driver; as well as The gate driving signal is output from an output terminal of the gate driver.

5. A device comprising: A synchronous rectifier driver circuit configured to drive a first rectifier switch and comprising: a shaping circuit configured to receive a drain voltage signal indicative of a voltage at a drain terminal of the rectifier switch and generate a gate drive reference voltage; a voltage regulator configured to receive the gate drive reference voltage and a power supply voltage and generate a driver power supply voltage based on the gate drive reference voltage; and A gate driver has a first input configured to receive the gate drive reference voltage, a power input configured to receive the driver supply voltage, and an output configured to output a gate drive signal to a gate terminal of the rectifier switch.

6. The device of claim 5 , wherein the gate driver drives the gate terminal of the rectifier switch in cycles, wherein each cycle includes an on-phase and an off-phase, wherein the voltage regulator is configured to identify a peak value of the gate drive reference voltage in each cycle. 7 . The device of claim 5 , wherein the voltage regulator generates the gate driver supply voltage as an average value of the peak value of the gate drive reference voltage over n cycles, where n is an integer greater than 1. 8 . The device of claim 7 , wherein the voltage regulator comprises a node storing the average of the peak values.

9. The device of claim 8, wherein the voltage regulator comprises an operational amplifier comprising: A non-inverting input is coupled to the average value of the peak value, an output providing the driver supply voltage, and an inverting input is coupled to the output in a feedback configuration. 10 . The device of claim 8 , wherein the voltage regulator comprises a storage capacitor coupled to the node and configured to store the average of the peak values.

11. The device of claim 10, wherein the voltage regulator comprises: an input configured to receive the reference voltage; a first capacitor coupled to the input node; as well as A first switch is coupled between the first capacitor and the second capacitor. 12 . The device of claim 11 , wherein the first capacitor has a capacitance equal to a capacitance of the storage capacitor divided by n.

13. A method comprising: driving a rectifier switch of the resonant converter using a driver circuit of the resonant converter; receiving a drain voltage of the rectifier switch using a shaping circuit of the driver circuit; generating a gate drive reference voltage based on the drain voltage using the shaping circuit; generating a driver supply voltage based on the gate drive reference voltage using a voltage regulator of the driver circuit; receiving the driver supply voltage at a supply voltage terminal of a gate driver of the driver circuit; receiving the gate drive reference voltage at an input terminal of the gate driver; as well as A gate drive signal is output from the gate driver to a gate terminal of the rectifier switch.

14. The method according to claim 1, comprising: driving the gate terminal of the rectifier switch in cycles, wherein each cycle includes an on-phase and an off-phase; as well as The voltage regulator is used to identify the peak value of the gate driving reference voltage in each cycle. 15 . The method of claim 13 , comprising generating, using the voltage regulator, the gate driver supply voltage as an average of a peak value of the gate driver reference voltage over n cycles, where n is an integer greater than 1.

16. The method of claim 15, comprising storing the average of the peak values ​​at a storage node of the voltage regulator.

17. The method of claim 16, wherein the voltage regulator comprises an operational amplifier, the operational amplifier comprising: A non-inverting input is coupled to the average value of the peak value, an output providing the driver supply voltage, and an inverting input is coupled to the output in a feedback configuration.

18. The method of claim 16, comprising storing the average of the peak values ​​using a storage capacitor of the voltage regulator.

19. The method of claim 18, wherein the voltage regulator comprises: an input configured to receive the reference voltage; a first capacitor coupled to the input node; as well as A first switch is coupled between the first capacitor and the storage capacitor.

20. The method of claim 19, wherein the first capacitor has a capacitance equal to the capacitance of the storage capacitor divided by n.

21. A method comprising: using a driver circuit of a resonant converter to drive a rectifier switch of the resonant converter with a gate drive signal based on a gate drive reference signal; receiving a drain voltage of the rectifier switch using a shaping circuit of the driver circuit; generating the gate drive reference voltage based on the drain voltage and a gain parameter using the shaping circuit; performing a first comparison of the gate drive reference voltage with a first threshold using the shaping circuit during a first cycle of the gate drive signal; as well as The gain parameter for a second period of the gate drive signal is adjusted based at least in part on the first comparison.

22. The method of claim 21, comprising performing a second comparison of the drain voltage to a second threshold using the shaping circuit during the first cycle of the gate drive signal.

23. The method of claim 22, comprising incrementing the gain parameter if the gate drive reference voltage is less than the first threshold and the drain voltage is less than the second threshold.

24. The method of claim 21, comprising decrementing the gain parameter if the gate drive reference voltage is greater than the first threshold.

25. The method of claim 21, comprising: comparing the gate drive reference voltage with the first threshold during the second period; as well as If the rectifier switch is off during the first half of the second cycle, the gain parameter is maintained at the same value during a third cycle.

26. The method of claim 21, comprising: comparing the gate drive reference voltage with the first threshold during the second period; as well as If the rectifier switch is turned off before the last quarter of the second cycle, the gain parameter for a third cycle is decremented.

27. The method of claim 21, wherein adjusting the gain parameter comprises adjusting a variable resistor.

28. The method according to claim 27, comprising: The gate drive reference voltage is generated as a sum of a first voltage and a product of the gain parameter and the drain voltage.

29. The method according to claim 28, comprising: passing a first current from a first current source through a first resistor; as well as A second current from a second current source is passed through the variable resistor.

30. The method of claim 29, comprising: generating the first voltage as a product of the first current and a resistance of the first resistor; as well as The product of the gain parameter of the product of the second current and the resistance of the variable resistor and the drain voltage is generated.

31. A device comprising: A synchronous rectifier driver circuit is configured to drive a rectifier switch using a gate drive signal and includes a shaping circuit configured to: receiving a drain voltage signal indicative of a voltage at a drain terminal of the rectifier switch and generating a gate drive reference voltage based on the drain voltage and a gain parameter; performing a first comparison of the gate drive reference voltage with a first threshold during a first cycle of the gate drive signal; as well as The gain parameter is adjusted during a second period of the gate drive signal based at least in part on the first comparison.

32. The device of claim 31 , comprising a gate driver having an input configured to receive the gate drive reference voltage and an output configured to output the gate drive signal to a gate terminal of the rectifier switch.

33. The device of claim 31 , comprising a variable resistor, wherein the shaping circuit is configured to adjust the gain parameter by adjusting the variable resistor.

34. The device of claim 33, wherein the shaping circuit is configured to generate the gate drive reference voltage as a sum of a first voltage and a product of the gain parameter and the drain voltage.

35. The device of claim 33, comprising: a first current source coupled to the first resistor; as well as A second current source is coupled to the variable resistor.

36. The device of claim 35, wherein the shaping circuit is configured to: generating the first voltage as a product of the first current and a resistance of the first resistor; and The product of the gain parameter and the drain voltage is generated as a product of the second current and a resistance of the variable resistor.

37. The device of claim 31 , wherein the shaping circuit is configured to perform a second comparison of the drain voltage with a second threshold during the first period of the gate drive signal, and to increment the gain parameter if the gate drive reference voltage is less than the first threshold and the drain voltage is less than the second threshold.

38. The device of claim 31, wherein the shaping circuit is configured to decrement the gain parameter if the gate drive reference voltage is greater than the first threshold.

39. A method comprising: driving a rectifier switch of the synchronous rectifier with a gate drive signal; generating a gate drive reference voltage based on a product of a drain voltage of the rectifier switch and a gain parameter; performing a first comparison of the gate drive reference voltage with a first threshold; as well as The gain parameter is adjusted based at least in part on the first comparison.

40. The method of claim 39, comprising: performing a second comparison of the drain voltage with a second threshold; as well as The gain parameter is adjusted based at least in part on the second comparison.

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