Data converter integrated with voltage-capacitance-temperature conversion function

Abstract

The invention discloses a data converter integrated with a voltage-capacitance-temperature conversion function, and belongs to the field of data converters. The data converter integrated with the voltage-capacitance-temperature conversion function comprises a sampling and feedback module and a modulator. The sampling and feedback module collects a capacitance signal, a voltage signal and a temperature signal of the temperature sensing module, and transmits the signals to the modulator; the modulator converts a capacitance signal, a voltage signal and a temperature signal into digital signals based on a 24-bit Sigma-Delta kernel, thereby realizing multifunctional conversion of the capacitance signal, the voltage signal and the temperature signal.

Description

Technical Field

[0001] The present invention relates to the technical field of data converters, and in particular to a data converter with integrated voltage-capacitance-temperature conversion function. Background Art

[0002] With the advancement of the internet and the widespread use of information technology, human life is becoming increasingly connected to the data world, placing higher demands on the performance and accuracy of data converters. Traditional Nyquist ADCs often cannot achieve such high precision. However, Sigma-Delta, based on oversampling technology, can effectively push in-band noise out of the passband by using a sampling rate far higher than the Nyquist frequency. This, coupled with a digital half-band filter, produces high-precision data conversion results. When the input signal is a low-frequency or DC signal, it is an incremental Sigma-Delta modulator. A DC incremental ADC is characterized by periodic resetting of the modulator after a certain quantization period, called a conversion period. After each conversion period, a reset signal is added to the modulator system. The overall conversion accuracy of the modulator is positively correlated with the conversion period.

[0003] Different data converters often use different sampling modules to convert different external signals into signals that are easier for the core to process. Based on the Sigma-Delta core, different sampling conversion methods can also be used to oversample and process various different types of signals, saving power and area. Traditional data converters have a single function, and a system often requires integrating data converters with different functions, wasting a lot of area and power.

[0004] In this context, there is an urgent need for a data converter that integrates multiple functions to optimize or solve the above problems. Summary of the Invention

[0005] An object of the present invention is to provide a data converter integrating voltage-capacitance-temperature conversion function to solve the problems in the background art.

[0006] To solve the above technical problems, the present invention provides a data converter with integrated voltage-capacitance-temperature conversion function, comprising: a sampling and feedback module, a modulator; The sampling and feedback module is composed of three sampling modules with different functions: voltage, capacitance and temperature. Based on different functions, different sampling circuits are selected to collect capacitance signals, voltage signals and temperature signals of the temperature sensing module, and transmit them to the modulator; The modulator is based on the Sigma-Delta core, which converts capacitance signals, voltage signals and temperature signals into digital signals, realizing multifunctional conversion of capacitance, voltage and temperature signals; wherein, The sampling of the capacitance signal is driven by a four-phase clock, enabling it to complete two sampling and charge transfer cycles within one cycle of the subsequent two-phase non-overlapping clock. The digital code stream is obtained through integration by a two-stage integrator and compared with the voltage of the comparator, completing the conversion process from capacitance signal to digital signal. The voltage signal adopts double sampling, sampling and integration are performed twice in one cycle of two phases. The sampled voltage signal is added with the feedback signal of the comparator, and after two integrations in the modulator's Sigma-Delta core and compared with the standard level of the comparator, a digital code stream is obtained, completing the conversion process from voltage signal to digital signal. The temperature sensing module converts the temperature signal into VBE. A pair of capacitors samples the VBE through the upper and lower plates, and converts the VBE into a corresponding amount of charge under the drive of the clock signal, which is then transferred to the Sigma-Delta core of the modulator.

[0007] In one embodiment, when the modulator converts the capacitance signal, the sampling and feedback module includes a capacitance to be measured C SENSOR , positive terminal parasitic capacitance Cp_para, negative terminal parasitic capacitance Cn_para, a pair of capacitors CDACP, a pair of capacitors CDACN, capacitor CFB1, capacitor CFB2, capacitor CFB3, capacitor CFB4; Capacitor to be measured C SENSOR One end is grounded, and the other end is connected to the positive reference voltage VRP, the common mode voltage VCM, and the negative reference voltage VRN respectively through three switches, and is permanently connected to the upper plate of the Cp_para capacitor; the lower plate of the Cp_para capacitor is grounded, and the upper plate is connected to VRN, VRP, and the positive and negative input stages of the first-stage integrator respectively through four switches; the lower plate of the Cn_para capacitor is grounded, and the upper plate is connected to VRN, VRP, and the positive and negative input stages of the first-stage integrator respectively through four switches; A pair of accessible capacitors CDACP and a pair of accessible capacitors CDACN are provided to extend the measuring range. The upper plates of the pair of capacitors CDACP are connected to VRN and VRP respectively through two switches, and the lower plates are connected to the positive input terminal of the first-stage integrator through two switches. The upper plates of the pair of capacitors CDACN are connected to VRN and VRP respectively through two switches, and the lower plates are connected to the negative input terminal of the first-stage integrator through two switches. CDACP, CDACN and the capacitor to be measured C SENSOR The sampling and integration are driven by four-phase clocks Φ1, 2, 3, and 4: In the Φ1 stage, the capacitor C to be measured SENSOR In the negative sampling phase, the capacitor C SENSOR One end is grounded and the other end is connected to VRN to test the capacitor C SENSORCharging, after charging is completed, the capacitor C to be tested SENSOR The signal is sampled; Φ3 stage, the capacitor to be measured C SENSOR In the forward sampling phase, the capacitor C SENSOR One end is grounded and the other end is connected to VRP to the capacitor C to be measured. SENSOR Charging, after charging is completed, the capacitor C to be tested SENSOR The signal is sampled; In the Φ2 and Φ4 stages, the capacitor C to be measured SENSOR The upper plate of the capacitor is connected to the VCM voltage. The transfer voltages in the Φ2 and Φ4 stages are |VRN-VCM| and |VRP-VCM| respectively. The lower plate of the Cp_para capacitor is grounded. In the Φ1 stage, the upper plate of the Cp_para capacitor is connected to VRN to charge the Cp_para capacitor. In the Φ2 stage, the upper plate of the Cp_para capacitor is connected to the positive input terminal of the first-stage integrator. SENSOR The upper plate of the capacitor Cp_para is always connected to the upper plate of the capacitor Cp_para. SENSOR The charge on the capacitor is also transferred to the first positive integrating capacitor of the first stage integrator in this cycle; the upper plate of the Cp_para capacitor in the Φ3 stage is connected to VRP to charge the Cp_para capacitor; the upper plate of the Cp_para capacitor in the Φ4 stage is connected to the negative input terminal of the first stage integrator. SENSOR The upper plate of the capacitor Cp_para is always connected to the upper plate of the capacitor Cp_para. SENSOR The charge on is also transferred to the first negative integrating capacitor of the first stage integrator in this cycle; wherein the first positive integrating capacitor is connected in parallel to the positive input terminal and the positive output terminal of the first stage integrator, and the first negative integrating capacitor is connected in parallel to the negative input terminal and the negative output terminal of the first stage integrator; The lower plate of the Cn_para capacitor is grounded. The upper plate of the Cn_para capacitor in the Φ1 stage is connected to VRN to charge the Cn_para capacitor. The upper plate of the Cn_para capacitor in the Φ2 stage is connected to the positive input of the first-stage integrator. The upper plate of the Cn_para capacitor in the Φ3 stage is connected to VRP to charge the Cn_para capacitor. The upper plate of the Cn_para capacitor in the Φ4 stage is connected to the negative input of the first-stage integrator. The Cn_para capacitor and the Cp_para capacitor have differential inputs, which can effectively suppress the influence of parasitic capacitance on the first-stage integrator. In the Φ1,4 stage, the upper plates of a pair of capacitors CDACP are connected to VRN; in the Φ2,3 stage, the upper plates of a pair of capacitors CDACP are connected to VRP; in the Φ1,2 stage, the lower plates of a pair of capacitors CDACP are connected to the positive input terminal of the first-stage integrator; in the Φ3,4 stage, the lower plates of a pair of capacitors CDACP are connected to the negative input terminal of the first-stage integrator; in the Φ1,4 stage, the upper plates of a pair of capacitors CDACN are connected to VRP; in the Φ2,3 stage, the upper plates of a pair of capacitors CDACN are connected to VRN; in the Φ1,2 stage, the lower plates of a pair of capacitors CDACN are connected to the negative input terminal of the first-stage integrator; in the Φ3,4 stage, the upper plates of a pair of capacitors CDACN are connected to the positive input terminal of the first-stage integrator; the range of the entire circuit is controlled by controlling the size of the circuits connected to CDACN and CDACP; For the capacitor C to be measured SENSOR Using double sampling, the Φ1, 2, 3, 4 cycles are the same as the clocks CLK1 and CLK2, and the duty cycle is half of CLK1 and CLK2; in the Φ1 stage, VRN is used to stimulate the capacitor C to be tested. SENSOR Sampling; Φ2 stage, the capacitor to be measured C SENSOR When VCM is connected, the voltage difference between the upper plates in the two cycles transfers part of the charge charged in the Φ1 stage to the first positive integrating capacitor to complete the integration; Similarly, the VRP excitation is used to complete the test capacitor C in the Φ3 stage. SENSOR Sampling; Φ2 stage capacitor C to be measured SENSOR Connect to VCM, the voltage difference of the upper plate in two cycles transfers part of the charge charged in the Φ3 stage to the first negative integral capacitor to complete the integration; thus, in one cycle of CLK1 and CLK2, Φ1,2,3,4 completes two integrations of the capacitor C to be measured. SENSORThe rest of the circuit is controlled by two non-overlapping clocks CLK1, CLK1D, CLK2, and CLK2D. The upper plate of CFB1 is connected to VRP at CLK1D and to VRN at CLK2D. The lower plate of CFB1 is connected to VCOM at CLK1, and to the positive input of the first-stage integrator at CLK2 and when the output code stream BS is negative, and to the negative output of the first-stage integrator at CLK2 and when the output code stream BS is negative. The upper plate of CFB2 is connected to VRN at CLK1D and to VRP at CLK2D. The lower plate of CFB2 is connected to VCOM at CLK2, and to the positive input of the first-stage integrator at CLK1 and when the output code stream BS is negative, and to the negative output of the first-stage integrator at CLK2. K1 and output code stream BS is connected to the negative output terminal of the first-stage integrator; the upper plate of CFB3 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of CFB3 is connected to VCOM at CLK2, connected to the negative input terminal of the first-stage integrator when CLK1 and the output code stream BS is negative, and connected to the positive output terminal of the first-stage integrator when CLK1 and the output code stream BS is BS; the upper plate of CFB4 is connected to VRP at CLK2D and to VRN at CLK1D; the lower plate of CFB4 is connected to VCOM at CLK1, connected to the negative input terminal of the first-stage integrator when CLK2 and the output code stream BS is negative, and connected to the positive output terminal of the first-stage integrator when CLK1 and the output code stream BS is BS.

[0008] In one embodiment, when the modulator converts a voltage signal, the sampling and feedback module includes capacitor CFB1, capacitor CFB2, capacitor CFB3, capacitor CFB4, sampling capacitor Cs1n, and sampling capacitor Cs1p; Capacitors Cs1n and Cs1p serve as the first-stage sampling capacitors. The upper plate of capacitor Cs1n is connected to the MUX_IN0 terminal through two switches, and the lower plate is connected to the positive input terminal of the first-stage integrator through two switches. The upper plate of capacitor Cs1p is connected to the MUX_IN1 terminal through two switches, and the lower plate is connected to the negative input terminal of the first-stage integrator through two switches. Both MUX_IN0 and MUX_IN1 are voltage terminals to be measured. The upper plate of capacitor Cs1n is connected to the MUX_IN1 terminal at CLK1, and the upper plate of capacitor Cs1p is connected to the MUX_IN0 terminal at CLK1. At LK2, the upper plate of capacitor Cs1p is connected to MUX_IN1, and the upper plate of capacitor Cs1n is connected to MUX_IN0. At CLK1, the lower plate of capacitor Cs1n is connected to the negative input of the first-stage integrator, and the lower plate of capacitor Cs1p is connected to the positive input of the first-stage integrator. At CLK2, the two are swapped, and the lower plate of capacitor Cs1n is connected to the positive input of the first-stage integrator at CLK2, and the lower plate of capacitor Cs1p is connected to the negative input of the first-stage integrator at CLK2. In this way, double sampling completes sampling and integration simultaneously in one cycle to improve clock utilization. The upper plate of capacitor CFB1 is connected to VRP during CLK1D and to VRN during CLK2D; the lower plate of capacitor CFB1 is connected to VCOM during CLK1, connected to the positive input terminal of the first-stage integrator when CLK2 and the output code stream BS is negative, and connected to the negative output terminal of the first-stage integrator when CLK2 and the output code stream BS is negative; the upper plate of capacitor CFB2 is connected to VRN during CLK1D and to VRP during CLK2D; the lower plate of capacitor CFB2 is connected to VCOM during CLK2, connected to the positive input terminal of the first-stage integrator when CLK1 and the output code stream BS is negative, and connected to the negative output terminal of the first-stage integrator when CLK1 and the output code stream BS is negative; The upper plate of capacitor CFB3 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of capacitor CFB3 is connected to VCOM at CLK2, connected to the negative input terminal of the first-stage integrator at CLK1 and when the output code stream BS is negative, and connected to the positive output terminal of the first-stage integrator at CLK1 and when the output code stream BS is BS; the upper plate of capacitor CFB4 is connected to VRP at CLK2D and to VRN at CLK1D; the lower plate of capacitor CFB4 is connected to VCOM at CLK1, connected to the negative input terminal of the first-stage integrator at CLK2 and when the output code stream BS is negative, and connected to the positive output terminal of the first-stage integrator at CLK1 and when the output code stream BS is BS.

[0009] In one embodiment, when the modulator converts the temperature signal, the sampling and feedback module includes capacitor CFB1, capacitor CFB2, capacitor CFB3, capacitor CFB4, feedback capacitor CTEM1, feedback capacitor CTEM2, feedback capacitor CTEM3, and feedback capacitor CTEM4; The temperature sensing module is in internal temperature detection mode. The module generates a voltage difference VBE under different current working conditions and transmits it to the sampling and feedback module, which is then input to the modulator for digital conversion. Four capacitors CFB are grouped in pairs, and their upper plates are connected to the voltage VBE; the upper plate of capacitor CFB1 is connected to the high level of VBE, and the lower plate is connected to VCM and the positive and negative input terminals of the first-stage integrator through a three-way switch; the upper plate of capacitor CFB2 is connected to the low level of VBE, and the lower plate is connected to VCM and the positive and negative input terminals of the first-stage integrator through a three-way switch; the upper plate of capacitor CFB3 is connected to the high level of VBE, and the lower plate is connected to VCM and the positive and negative input terminals of the first-stage integrator through a three-way switch; the upper plate of capacitor CFB4 is connected to the low level of VBE, and the lower plate is connected to VCM and the positive and negative input terminals of the first-stage integrator through a three-way switch; Four capacitors CTEM are added as feedback, among which the upper plate of capacitor CTEM1 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of capacitor CTEM1 is connected to VCOM at CLK1, and is connected to the positive input of the first-stage integrator when CLK2 and the output code stream BS is negative, and is connected to the negative output of the first-stage integrator when CLK2 and the output code stream BS is positive; the upper plate of capacitor CTEM2 is connected to VRN at CLK1D and to VRP at CLK2D; the lower plate of capacitor CTEM2 is connected to VCOM at CLK2, and is connected to the positive input of the first-stage integrator when CLK1 and the output code stream BS is negative, and is connected to the first-stage integrator when CLK1 and the output code stream BS is positive. The negative output terminal of the integrator; the upper plate of capacitor CTEM3 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of capacitor CTEM3 is connected to VCOM at CLK2, and is connected to the negative input terminal of the first-stage integrator when CLK1 and the output code stream BS are negative, and is connected to the positive output terminal of the first-stage integrator when CLK1 and the output code stream BS are negative; the upper plate of capacitor CTEM4 is connected to VRP at CLK2D and to VRN at CLK1D; the lower plate of capacitor CTEM4 is connected to VCOM at CLK1, and is connected to the negative input terminal of the first-stage integrator when CLK2 and the output code stream BS are negative, and is connected to the positive output terminal of the first-stage integrator when CLK1 and the output code stream BS are negative.

[0010] In one embodiment, in the modulator, the first-stage amplifier is a chopper operational amplifier, and a capacitor and a switch are connected in parallel between the positive input terminal and the positive output terminal, and the negative input terminal and the negative output terminal of the chopper operational amplifier, respectively, to serve as an integrating capacitor and a reset switch. The modulator further includes: two summing circuit capacitors Csum1, the upper plates of which are respectively connected to the differential output of the first-stage integrator and VCOM through two switches; and the lower plates are respectively permanently connected to the positive input and negative input of the comparator; a second-stage integrator and two sampling capacitors Cs2, wherein the upper plate of one sampling capacitor Cs2 is connected to the positive output terminal of the first-stage integrator and VCM respectively through two switches, and the lower plate is connected to the positive input terminal of the second-stage integrator and VCM respectively through two switches; the upper plate of the other sampling capacitor Cs2 is connected to the negative output terminal of the first-stage integrator and VCM respectively through two switches, and the lower plate is connected to the negative input terminal of the second-stage integrator and VCM respectively through two switches; the second-stage integrator includes an operational amplifier, and capacitors and reset switches are connected in parallel between the positive input terminal and the positive output terminal, and the negative input terminal and the negative output terminal of the operational amplifier; Two adding circuit capacitors Csum2, wherein the upper plate of one adding circuit capacitor Csum2 is connected to the positive terminal of the differential output of the second-stage integrator and VCM respectively through two switches, and the lower plate is permanently connected to the positive input of the comparator; the upper plate of the other adding circuit capacitor Csum2 is connected to the negative terminal of the differential output of the second-stage integrator and VCM respectively through two switches, and the lower plate is permanently connected to the negative input of the comparator; The positive and negative input terminals of the comparator are connected to VCM via a switch, and the result output code stream BS of the comparator passes through a latch and a filter to obtain an output Dout.

[0011] The present invention provides a data converter with integrated voltage-capacitance-temperature conversion functions, comprising a sampling and feedback module and a modulator. The sampling and feedback module consists of three sampling modules with different functions: voltage, capacitance, and temperature. Based on the different functions, different sampling circuits are selected to collect capacitance signals, voltage signals, and temperature signals from a temperature sensing module, and transmit them to the modulator. The modulator, based on a 24-bit Sigma-Delta core, converts the capacitance, voltage, and temperature signals into digital signals, achieving multifunctional conversion of capacitance, voltage, and temperature signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a structural diagram of a capacitance, voltage, and temperature function data converter provided by the present invention; Figure 2 This is a schematic diagram of the structure of a capacitor sampling function down sampling and feedback module and a modulator core provided by the present invention; Figure 3 This is a schematic diagram of the structure of a voltage sampling function down sampling and feedback module and a modulator core provided by the present invention; Figure 4 This is a schematic diagram of the structure of a temperature sampling function down sampling and feedback module and a modulator core provided by the present invention. DETAILED DESCRIPTION

[0013] The following is a detailed description of a data converter with integrated voltage-capacitance-temperature conversion functionality, as proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0014] The present invention provides a data converter with integrated voltage-capacitance-temperature conversion function, such as Figure 1As shown, it includes a sampling and feedback module and a modulator. The sampling and feedback module consists of three sampling modules with different functions: voltage, capacitance, and temperature. Based on different functions, different sampling circuits are selected to collect capacitance signals, voltage signals, and temperature signals from the temperature sensing module, and transmit them to the modulator. The modulator, based on a 24-bit Sigma-Delta core, converts capacitance signals, voltage signals, and temperature signals into digital signals, realizing multifunctional conversion of capacitance, voltage, and temperature signals.

[0015] The sampling and feedback module is divided into three channels for sampling and feedback because the present invention can realize three different functions. The three modes have three different signal sampling and feedback circuits, but share a Sigma-Delta modulator core.

[0016] The signal sampling of the capacitance mode is driven by a four-phase clock, which enables it to complete two sampling and charge transfers in one cycle of the subsequent two-phase non-overlapping clock, including C SENSOR Sampling of two different reference voltages VRN and VRP and subsequent circuit C SENSOR ∙|VRN-VCM| and C SENSOR ∙ |VRP-VCM| charge transfer. Capacitive mode can extend the measurement range by controlling the number of CDACs connected. To match the sampling module, a four-phase clock drive is also used. The feedback connection is determined by the comparator result and two non-overlapping clocks, providing global feedback to the modulator core, achieving the Sigma-Delta modulator noise shaping effect for the entire modulator core. A digital bit stream is generated through integration in a two-stage integrator and compared with the comparator voltage, completing the conversion from capacitive signal to digital signal.

[0017] like Figure 2 As shown, the first stage of the circuit core is driven by a four-phase clock; the second stage and other parts are driven by a two-phase non-overlapping clock. SENSOROne end is grounded, while the other end is connected to VRP, VCM, and VRN via three switches. It is also permanently connected to the top plate of the Cp_para capacitor. The bottom plate of the Cp_para capacitor is grounded, while the top plate is connected to VRN, VRP, and the positive and negative inputs of the first-stage integrator via four switches. The bottom plate of the Cn_para capacitor is grounded, while the top plate is connected to VRN, VRP, and the positive and negative inputs of the first-stage integrator via four switches. A pair of two accessible capacitors, CDACN and CDACP, are also provided to extend the measurement range. The top plates of the two accessible capacitors, CDACP, are connected to VRN and VRP, respectively, via two switches, while the bottom plates are connected to the positive and negative inputs of the first-stage integrator via two switches. The modulator is based on a 24-bit Sigma-Delta core, the first-stage amplifier is a chopper operational amplifier, and capacitors and switches are connected in parallel between the positive input and positive output, and the negative input and negative output of the chopper operational amplifier to serve as integration capacitors and reset switches. The modulator also includes two summing circuit capacitors Csum1, a second-stage integrator and two sampling capacitors Cs2, and two summing circuit capacitors Csum2. The upper plates of the two adding circuit capacitors Csum1 are connected to the differential output of the first-stage integrator and VCOM respectively through two switches; the lower plates are permanently connected to the positive input and negative input of the comparator respectively; the upper plate of a sampling capacitor Cs2 is connected to the positive output terminal of the first-stage integrator and VCM respectively through two switches, and the lower plate is connected to the positive input terminal of the second-stage integrator and VCM respectively through two switches; the upper plate of another sampling capacitor Cs2 is connected to the negative output terminal of the first-stage integrator and VCM respectively through two switches, and the lower plate is connected to the negative input terminal of the second-stage integrator and VCM respectively through two switches; the second-stage integrator includes an operational amplifier, and the operational amplifier Capacitors and reset switches are connected in parallel between the positive input and positive output, and the negative input and negative output of the amplifier; the upper plate of an adding circuit capacitor Csum2 is connected to the positive terminal of the second-stage integrator differential output and VCM respectively through two switches, and the lower plate is permanently connected to the positive input of the comparator; the upper plate of another adding circuit capacitor Csum2 is connected to the negative terminal of the second-stage integrator differential output and VCM respectively through two switches, and the lower plate is permanently connected to the negative input of the comparator; the positive and negative input terminals of the comparator are connected to VCM through switches, and the result BS (Bitstream, output code stream) of the comparator is output Dout through a latch and a filter.

[0018] CDAC and C SENSOR The sampling and integration of the part are driven by the four-phase clock Φ1, 2, 3, 4. In the Φ1 phase, the capacitor C SENSOR In the negative sampling phase, the capacitor C SENSOR One end is grounded and the other end is connected to VRN to test the capacitor C SENSORCharging, after charging is completed, the capacitor C to be tested SENSOR The signal is sampled; in the Φ3 stage, the capacitor C SENSOR In the forward sampling phase, the capacitor C SENSOR One end is grounded and the other end is connected to VRP to the capacitor C to be measured. SENSOR Charging, after charging is completed, the capacitor C to be tested SENSOR The signal is sampled; in the Φ2 and Φ4 stages, the capacitor C SENSOR The upper plate of the capacitor is connected to the VCM voltage. The transfer voltages in the Φ2 and Φ4 stages are |VRN-VCM| and |VRP-VCM| respectively. The lower plate of the Cp_para capacitor is grounded. In the Φ1 stage, the upper plate of the Cp_para capacitor is connected to VRN to charge the Cp_para capacitor. In the Φ2 stage, the upper plate of the Cp_para capacitor is connected to the positive input terminal of the first-stage integrator. SENSOR The upper plate of the capacitor Cp_para is always connected to the upper plate of the capacitor Cp_para. SENSOR The charge on the capacitor is also transferred to the first positive integrating capacitor CI1 of the first stage integrator in this cycle; in the Φ3 stage, the upper plate of the Cp_para capacitor is connected to VRP to charge the Cp_para capacitor; in the Φ4 stage, the upper plate of the Cp_para capacitor is connected to the negative input terminal of the first stage integrator. SENSOR The upper plate of the capacitor Cp_para is always connected to the upper plate of the capacitor Cp_para. SENSORThe charge on the capacitor is also transferred to the first negative integrating capacitor CI1' of the first-stage integrator during this cycle. The first positive integrating capacitor CI1 is connected in parallel to the positive input and positive output of the first-stage integrator, while the first negative integrating capacitor CI1' is connected in parallel to the negative input and negative output of the first-stage integrator. The lower plate of the Cn_para capacitor is grounded. In the Φ1 stage, the upper plate of the Cn_para capacitor is connected to VRN to charge the Cn_para capacitor. In the Φ2 stage, the upper plate of the Cn_para capacitor is connected to the positive input of the first-stage integrator, and in the Φ3 stage, the upper plate of the Cn_para capacitor is connected to VRP to charge the Cn_para capacitor. In the Φ4 stage, the upper plate of the Cn_para capacitor is connected to the negative input of the first-stage integrator. The differential input of the Cn_para capacitor and the Cp_para capacitor effectively suppresses the impact of parasitic capacitance on the first-stage integrator. In the Φ1,4 stage, the upper plate of a pair of capacitors CDACP is connected to VRN, in the Φ2,3 stage, the upper plate of a pair of capacitors CDACP is connected to VRP; in the Φ1,2 stage, the lower plate of a pair of capacitors CDACP is connected to the positive input of the first-stage integrator, in the Φ3,4 stage, the lower plate of a pair of capacitors CDACP is connected to the negative input of the first-stage integrator; in the Φ1,4 stage, the upper plate of a pair of capacitors CDACN is connected to VRP, in the Φ2,3 stage, the upper plate of a pair of capacitors CDACN is connected to VRN; in the Φ1,2 stage, the lower plate of a pair of capacitors CDACN is connected to the negative input of the first-stage integrator, in the Φ3,4 stage, the upper plate of a pair of capacitors CDACN is connected to the positive input of the first-stage integrator. The size of the two DACs connected to the circuit can be controlled to control the range of the entire circuit. Since the capacitor C to be measured is SENSOR Using double sampling, the Φ1, 2, 3, 4 cycles are the same as the clocks CLK1 and CLK2, and the duty cycle is half of CLK1 and CLK2; in the Φ1 stage, VRN is used to stimulate the capacitor C to be tested. SENSOR Sampling; Φ2 stage, the capacitor to be measured C SENSOR Connect VCM, the voltage difference between the two cycles of the upper plate transfers part of the charge charged in the Φ1 stage to the first positive integration capacitor CI1 to complete the integration. Similarly, in the Φ3 stage, VRP excitation is used to complete the integration of the capacitor C SENSOR Sampling; Φ2 stage capacitor C to be measured SENSOR Connect to VCM, the voltage difference of the upper plate in two cycles transfers part of the charge charged in the Φ3 stage to the first negative integral capacitor CI1' to complete the integration; thus, in one cycle of CLK1 and CLK2, Φ1,2,3,4 completes two integrations of the capacitor C to be measured. SENSOR Two sampling and integration.

[0019] The rest of the circuit is controlled by two non-overlapping clocks CLK1, CLK1D, CLK2, and CLK2D. The upper plate of CFB1 is connected to VRP at CLK1D and to VRN at CLK2D. The lower plate of CFB1 is connected to VCOM at CLK1, to the positive input of the first-stage integrator at CLK2 and BSN (bitstream negative), and to the negative output of the first-stage integrator at CLK2 and BS. The upper plate of CFB2 is connected to VRN at CLK1D and to VRP at CLK2D. The lower plate of CFB2 is connected to VCOM at CLK2, to the positive input of the first-stage integrator at CLK1 and BSN, and to the negative output of the first-stage integrator at CLK1 and BS. The upper plate of CFB3 is connected to VRP at CLK1D and to VRN at CLK2D. The lower plate of CFB3 is connected to VCOM at CLK2, to the negative input of the first-stage integrator at CLK1 and BSN, and to the positive output of the first-stage integrator at CLK1 and BS; the upper plate of CFB4 is connected to VRP at CLK2D, and to VRN at CLK1D; the lower plate of CFB4 is connected to VCOM at CLK1, to the negative input of the first-stage integrator at CLK2 and BSN, and to the positive output of the first-stage integrator at CLK1 and BS.

[0020] Although CFB1, CFB, CFB3, and CFB4 are not driven by a four-phase clock, the first-stage integrator uses dual sampling, requiring integration and sampling to complete within a single cycle. CLK1D is a delayed version of CLK1, and CLK2D is a delayed version of CLK. This non-overlapping two-phase clock design effectively minimizes charge leakage. CFB1 and CFB2 are grouped together, while CFB3 and CFB4 are grouped together, ensuring simultaneous integration and sampling of the feedback capacitors. During the CLK1 phase, the top plates of CFB1 and CFB4 are connected to VRP and VRN, respectively, and the bottom plates to VCOM. This allows for sampling of the positive and negative VREF signals and accumulation of charge for the next clock cycle based on the positive or negative voltage level of BS. Simultaneously, the top plates of CFB2 and CFB3 are connected to VRN and VNP, respectively, while the bottom plates transfer charge to the positive and negative input integrating capacitors of the first-stage integrator based on the high and low voltage levels of BS. During CLK2, the functions of the two are swapped, enabling simultaneous sampling and integration.

[0021] The voltage mode employs double sampling, performing sampling and integration twice within a two-phase cycle. This not only effectively utilizes the clock, achieving higher accuracy within the same reset time, but also matches the four-phase sampling clock of the capacitor mode, further enabling the multiplexing of the Sigma-Delta modulator core. The sampled voltage signal is added to the comparator's feedback signal, integrated twice by the Sigma-Delta modulator core, and compared with the comparator's reference level to produce a digital bit stream, completing the conversion from voltage to digital.

[0022] like Figure 3 As shown, the voltage mode uses dual sampling, and the sampling loop uses dual sampling to sample the input signal. Unlike ordinary sampling, the dual sampling loop samples and integrates in both the original sampling phase and the original integration phase, improving work efficiency and SNR (signal-to-noise ratio). The first stage uses dual sampling and dual integration, while the second stage still uses single sampling and single integration. Unlike the circuit in capacitor mode, the four-phase capacitor drive CDAC and capacitor sampling module are not involved in the operation. Capacitors Cs1n and Cs1p are added to the circuit as the first-stage sampling capacitors. The upper plate of capacitor Cs1n is connected to MUX_IN0 through two switches, and the lower plate is connected to the positive input of the first-stage integrator through two switches. The upper plate of capacitor Cs1p is connected to MUX_IN1 through two switches, and the lower plate is connected to the negative input of the first-stage integrator through two switches. Both MUX_IN0 and MUX_IN1 are voltage terminals to be measured.

[0023] The core operating timing is identical to that of the capacitor mode, with only the sampling module differing. During CLK1, the top plate of capacitor Cs1n is connected to MUX_IN1, while the top plate of capacitor Cs1p is connected to MUX_IN0. During CLK2, the top plate of capacitor Cs1p is connected to MUX_IN1, while the top plate of capacitor Cs1n is connected to MUX_IN0. During CLK1, the bottom plate of capacitor Cs1n is connected to the negative input of the first-stage integrator, while the bottom plate of capacitor Cs1p is connected to the positive input of the first-stage integrator. During CLK2, the top plate of capacitor Cs1n is connected to the positive input of the first-stage integrator, while the bottom plate of capacitor Cs1p is connected to the negative input of the first-stage integrator. This dual sampling mechanism allows simultaneous sampling and integration within a single cycle, improving clock utilization.

[0024] The upper plate of capacitor CFB1 is connected to VRP during CLK1D and to VRN during CLK2D; the lower plate of capacitor CFB1 is connected to VCOM during CLK1, to the positive input of the first-stage integrator during CLK2 and BSN, and to the negative output of the first-stage integrator during CLK2 and BS; the upper plate of capacitor CFB2 is connected to VRN during CLK1D and to VRP during CLK2D; the lower plate of capacitor CFB2 is connected to VCOM during CLK2, to the positive input of the first-stage integrator during CLK1 and BSN, and to the negative output of the first-stage integrator during CLK1 and BS; The upper plate of capacitor CFB3 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of capacitor CFB3 is connected to VCOM at CLK2, connected to the negative input terminal of the first-stage integrator at CLK1 and BSN, and connected to the positive output terminal of the first-stage integrator at CLK1 and BS; the upper plate of capacitor CFB4 is connected to VRP at CLK2D and to VRN at CLK1D; the lower plate of capacitor CFB4 is connected to VCOM at CLK1, connected to the negative input terminal of the first-stage integrator at CLK2 and BSN, and connected to the positive output terminal of the first-stage integrator at CLK1 and BS.

[0025] Because temperature mode requires normalized parameters for processing and subsequent digital circuitry, the capacitors in the sampling and feedback modules differ from those in the previous two functions. The temperature sensing module converts the temperature signal into VBE. A pair of capacitors samples this VBE through upper and lower plates. Driven by a clock signal, this VBE is converted into a corresponding amount of charge for subsequent Sigma-Delta modulator core use.

[0026] like Figure 4As shown, the temperature sensing module operates in internal temperature detection mode. Under varying currents, it generates a voltage difference, VBE, which is transmitted to the sampling and feedback module and then fed into the modulator for digital conversion. Due to the need for normalization during the temperature mode sampling phase, a new set of capacitors is used as the core sampling and feedback capacitors, with no subsequent circuit changes. Four capacitors, CFB, are grouped in pairs, with their top plates connected to the voltage VBE. Capacitor CFB1's top plate is connected to VBE high, while its bottom plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. Capacitor CFB2's top plate is connected to VBE low, while its bottom plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. Capacitor CFB3's top plate is connected to VBE high, while its bottom plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. Capacitor CFB4's top plate is connected to VBE low, while its bottom plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. Four new capacitors CTEM are added as feedback, where the upper plate of capacitor CTEM1 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of capacitor CTEM1 is connected to VCOM at CLK1, to the positive input of the first-stage integrator at CLK2 and BSN, and to the negative output of the first-stage integrator at CLK2 and BS; the upper plate of capacitor CTEM2 is connected to VRN at CLK1D and to VRP at CLK2D; the lower plate of capacitor CTEM2 is connected to VCOM at CLK2, to the positive input of the first-stage integrator at CLK1 and BSN, and to the negative output of the first-stage integrator at CLK1 and BS. The negative output terminal of the integrator; the upper plate of capacitor CTEM3 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of capacitor CTEM3 is connected to VCOM at CLK2, to the negative input terminal of the first-stage integrator at CLK1 and BSN, and to the positive output terminal of the first-stage integrator at CLK1 and BS; the upper plate of capacitor CTEM4 is connected to VRP at CLK2D and to VRN at CLK1D; the lower plate of capacitor CTEM4 is connected to VCOM at CLK1, to the negative input terminal of the first-stage integrator at CLK2 and BSN, and to the positive output terminal of the first-stage integrator at CLK1 and BS.

[0027] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A data converter with integrated voltage-capacitance-temperature conversion function, characterized in that: include: Sampling and feedback module, modulator; The sampling and feedback module is composed of three sampling modules with different functions: voltage, capacitance and temperature. Based on different functions, different sampling circuits are selected to collect capacitance signals, voltage signals and temperature signals of the temperature sensing module, and transmit them to the modulator; The modulator is based on the Sigma-Delta core, which converts capacitance signals, voltage signals and temperature signals into digital signals, realizing multifunctional conversion of capacitance, voltage and temperature signals; wherein, The sampling of the capacitance signal is driven by a four-phase clock, enabling it to complete two sampling and charge transfer cycles within one cycle of the subsequent two-phase non-overlapping clock. The digital code stream is obtained through integration by a two-stage integrator and compared with the voltage of the comparator, completing the conversion process from capacitance signal to digital signal. The voltage signal adopts double sampling, sampling and integration are performed twice in one cycle of two phases. The sampled voltage signal is added with the feedback signal of the comparator, and after two integrations in the modulator's Sigma-Delta core and compared with the standard level of the comparator, a digital code stream is obtained, completing the conversion process from voltage signal to digital signal. The temperature sensing module converts the temperature signal into VBE. A pair of capacitors samples the VBE through the upper and lower plates, and converts the VBE into a corresponding amount of charge under the drive of the clock signal, which is then transferred to the Sigma-Delta core of the modulator.

2. The data converter with integrated voltage-capacitance-temperature conversion function according to claim 1, wherein: When the modulator converts the capacitance signal, the sampling and feedback module includes the capacitance to be measured C SENSOR , positive terminal parasitic capacitance Cp_para, negative terminal parasitic capacitance Cn_para, a pair of capacitors CDACP, a pair of capacitors CDACN, capacitor CFB1, capacitor CFB2, capacitor CFB3, capacitor CFB4; Capacitor to be measured C SENSOR One end is grounded, and the other end is connected to the positive reference voltage VRP, the common mode voltage VCM, and the negative reference voltage VRN respectively through three switches, and is permanently connected to the upper plate of the Cp_para capacitor; the lower plate of the Cp_para capacitor is grounded, and the upper plate is connected to VRN, VRP, and the positive and negative input stages of the first-stage integrator respectively through four switches; the lower plate of the Cn_para capacitor is grounded, and the upper plate is connected to VRN, VRP, and the positive and negative input stages of the first-stage integrator respectively through four switches; A pair of accessible capacitors CDACP and a pair of accessible capacitors CDACN are provided to extend the measuring range. The upper plates of the pair of capacitors CDACP are connected to VRN and VRP respectively through two switches, and the lower plates are connected to the positive input terminal of the first-stage integrator through two switches. The upper plates of the pair of capacitors CDACN are connected to VRN and VRP respectively through two switches, and the lower plates are connected to the negative input terminal of the first-stage integrator through two switches. CDACN, CADCP and the capacitor to be measured C SENSOR The sampling and integration are driven by four-phase clocks Φ1, 2, 3, and 4: In the Φ1 stage, the capacitor C to be measured SENSOR In the negative sampling phase, the capacitor C SENSOR One end is grounded and the other end is connected to VRN to test the capacitor C SENSOR Charging, after charging is completed, the capacitor C to be tested SENSOR The signal is sampled; Φ3 stage, the capacitor to be measured C SENSOR In the forward sampling phase, the capacitor C SENSOR One end is grounded and the other end is connected to VRP to the capacitor C to be measured. SENSOR Charging, after charging is completed, the capacitor C to be tested SENSOR The signal is sampled; In the Φ2 and Φ4 stages, the capacitor C to be measured SENSOR The upper plate of the capacitor is connected to the VCM voltage. The transfer voltages in the Φ2 and Φ4 stages are |VRN-VCM| and |VRP-VCM| respectively. The lower plate of the Cp_para capacitor is grounded. In the Φ1 stage, the upper plate of the Cp_para capacitor is connected to VRN to charge the Cp_para capacitor. In the Φ2 stage, the upper plate of the Cp_para capacitor is connected to the positive input terminal of the first-stage integrator. SENSOR The upper plate of the capacitor Cp_para is always connected to the upper plate of the capacitor Cp_para. SENSOR The charge on the capacitor is also transferred to the first positive integrating capacitor of the first stage integrator in this cycle; the upper plate of the Cp_para capacitor in the Φ3 stage is connected to VRP to charge the Cp_para capacitor; the upper plate of the Cp_para capacitor in the Φ4 stage is connected to the negative input terminal of the first stage integrator. SENSOR The upper plate of the capacitor Cp_para is always connected to the upper plate of the capacitor Cp_para. SENSOR The charge on is also transferred to the first negative integrating capacitor of the first stage integrator in this cycle; wherein the first positive integrating capacitor is connected in parallel to the positive input terminal and the positive output terminal of the first stage integrator, and the first negative integrating capacitor is connected in parallel to the negative input terminal and the negative output terminal of the first stage integrator; The lower plate of the Cn_para capacitor is grounded. The upper plate of the Cn_para capacitor in the Φ1 stage is connected to VRN to charge the Cn_para capacitor. The upper plate of the Cn_para capacitor in the Φ2 stage is connected to the positive input of the first-stage integrator. The upper plate of the Cn_para capacitor in the Φ3 stage is connected to VRP to charge the Cn_para capacitor. The upper plate of the Cn_para capacitor in the Φ4 stage is connected to the negative input of the first-stage integrator. The Cn_para capacitor and the Cp_para capacitor have differential inputs, which can effectively suppress the influence of parasitic capacitance on the first-stage integrator. In the Φ1,4 stage, the upper plates of a pair of capacitors CDACP are connected to VRN; in the Φ2,3 stage, the upper plates of a pair of capacitors CDACP are connected to VRP; in the Φ1,2 stage, the lower plates of a pair of capacitors CDACP are connected to the positive input terminal of the first-stage integrator; in the Φ3,4 stage, the lower plates of a pair of capacitors CDACP are connected to the negative input terminal of the first-stage integrator; in the Φ1,4 stage, the upper plates of a pair of capacitors CDACN are connected to VRP; in the Φ2,3 stage, the upper plates of a pair of capacitors CDACN are connected to VRN; in the Φ1,2 stage, the lower plates of a pair of capacitors CDACN are connected to the negative input terminal of the first-stage integrator; in the Φ3,4 stage, the upper plates of a pair of capacitors CDACN are connected to the positive input terminal of the first-stage integrator; the range of the entire circuit is controlled by controlling the size of the circuits connected to CDACP and CDACN; For the capacitor C to be measured SENSOR Using double sampling, the Φ1, 2, 3, 4 cycles are the same as the clocks CLK1 and CLK2, and the duty cycle is half of CLK1 and CLK2; in the Φ1 stage, VRN is used to stimulate the capacitor C to be tested. SENSOR Sampling; Φ2 stage, the capacitor to be measured C SENSOR When VCM is connected, the voltage difference between the upper plates in the two cycles transfers part of the charge charged in the Φ1 stage to the first positive integrating capacitor to complete the integration; Similarly, the VRP excitation is used to complete the test capacitor C in the Φ3 stage. SENSOR Sampling; Φ2 stage capacitor C to be measured SENSOR Connect to VCM, the voltage difference of the upper plate in two cycles transfers part of the charge charged in the Φ3 stage to the first negative integral capacitor to complete the integration; thus, in one cycle of CLK1 and CLK2, Φ1,2,3,4 completes two integrations of the capacitor C to be measured. SENSOR The rest of the circuit is controlled by two non-overlapping clocks CLK1, CLK1D, CLK2, and CLK2D. The upper plate of CFB1 is connected to VRP at CLK1D and to VRN at CLK2D. The lower plate of CFB1 is connected to VCOM at CLK1, and to the positive input of the first-stage integrator at CLK2 and when the output code stream BS is negative, and to the negative output of the first-stage integrator at CLK2 and when the output code stream BS is negative. The upper plate of CFB2 is connected to VRN at CLK1D and to VRP at CLK2D. The lower plate of CFB2 is connected to VCOM at CLK2, and to the positive input of the first-stage integrator at CLK1 and when the output code stream BS is negative, and to the negative output of the first-stage integrator at CLK2. K1 and output code stream BS is connected to the negative output terminal of the first-stage integrator; the upper plate of CFB3 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of CFB3 is connected to VCOM at CLK2, connected to the negative input terminal of the first-stage integrator when CLK1 and the output code stream BS is negative, and connected to the positive output terminal of the first-stage integrator when CLK1 and the output code stream BS is BS; the upper plate of CFB4 is connected to VRP at CLK2D and to VRN at CLK1D; the lower plate of CFB4 is connected to VCOM at CLK1, connected to the negative input terminal of the first-stage integrator when CLK2 and the output code stream BS is negative, and connected to the positive output terminal of the first-stage integrator when CLK1 and the output code stream BS is BS.

3. The data converter with integrated voltage-capacitance-temperature conversion function according to claim 2, wherein: When the modulator converts the voltage signal, the sampling and feedback module includes capacitor CFB1, capacitor CFB2, capacitor CFB3, capacitor CFB4, sampling capacitor Cs1n, and sampling capacitor Cs1p; Capacitors Cs1n and Cs1p serve as first-stage sampling capacitors. The upper plate of capacitor Cs1n is connected to the MUX_IN0 terminal through two switches, and the lower plate is connected to the positive input terminal of the first-stage integrator through two switches. The upper plate of capacitor Cs1p is connected to the MUX_IN1 terminal through two switches, and the lower plate is connected to the negative input terminal of the first-stage integrator through two switches. Both MUX_IN0 and MUX_IN1 are voltage terminals to be measured. The upper plate of capacitor Cs1n is connected to the MUX_IN1 terminal during CLK1, and the upper plate of capacitor Cs1p is connected to the MUX_IN0 terminal during CLK1. The two are swapped during CLK2, with the upper plate of capacitor Cs1p connected to the MUX_IN1 terminal and the upper plate of capacitor Cs1n connected to the MUX_IN0 terminal. The lower plate of capacitor Cs1n is connected to the negative input terminal of the first-stage integrator during CLK1, and the lower plate of capacitor Cs1p is connected to the positive input terminal of the first-stage integrator during CLK1. The two are swapped at CLK2. The lower plate of capacitor Cs1n is connected to the positive input terminal of the first-stage integrator at CLK2, and the lower plate of capacitor Cs1p is connected to the negative input terminal of the first-stage integrator at CLK2. In this way, double sampling completes sampling and integration simultaneously in one cycle to improve clock utilization. The upper plate of capacitor CFB1 is connected to VRP during CLK1D and to VRN during CLK2D; the lower plate of capacitor CFB1 is connected to VCOM during CLK1, connected to the positive input terminal of the first-stage integrator when CLK2 and the output code stream BS is negative, and connected to the negative output terminal of the first-stage integrator when CLK2 and the output code stream BS is negative; the upper plate of capacitor CFB2 is connected to VRN during CLK1D and to VRP during CLK2D; the lower plate of capacitor CFB2 is connected to VCOM during CLK2, connected to the positive input terminal of the first-stage integrator when CLK1 and the output code stream BS is negative, and connected to the negative output terminal of the first-stage integrator when CLK1 and the output code stream BS is negative; The upper plate of capacitor CFB3 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of capacitor CFB3 is connected to VCOM at CLK2, connected to the negative input terminal of the first-stage integrator at CLK1 and when the output code stream BS is negative, and connected to the positive output terminal of the first-stage integrator at CLK1 and when the output code stream BS is BS; the upper plate of capacitor CFB4 is connected to VRP at CLK2D and to VRN at CLK1D; the lower plate of capacitor CFB4 is connected to VCOM at CLK1, connected to the negative input terminal of the first-stage integrator at CLK2 and when the output code stream BS is negative, and connected to the positive output terminal of the first-stage integrator at CLK1 and when the output code stream BS is BS.

4. The data converter with integrated voltage-capacitance-temperature conversion function as claimed in claim 3, wherein: When the modulator converts the temperature signal, the sampling and feedback module includes capacitor CFB1, capacitor CFB2, capacitor CFB3, capacitor CFB4, feedback capacitor CTEM1, feedback capacitor CTEM2, feedback capacitor CTEM3, and feedback capacitor CTEM4; The temperature sensing module is in internal temperature detection mode. The module generates a voltage difference VBE under different current working conditions and transmits it to the sampling and feedback module, which is then input to the modulator for digital conversion. Four capacitors CFB are grouped in pairs, and their upper plates are connected to the voltage VBE; the upper plate of capacitor CFB1 is connected to the high level of VBE, and the lower plate is connected to VCM and the positive and negative input terminals of the first-stage integrator through a three-way switch; the upper plate of capacitor CFB2 is connected to the low level of VBE, and the lower plate is connected to VCM and the positive and negative input terminals of the first-stage integrator through a three-way switch; the upper plate of capacitor CFB3 is connected to the high level of VBE, and the lower plate is connected to VCM and the positive and negative input terminals of the first-stage integrator through a three-way switch; the upper plate of capacitor CFB4 is connected to the low level of VBE, and the lower plate is connected to VCM and the positive and negative input terminals of the first-stage integrator through a three-way switch; Four capacitors CTEM are added as feedback, among which the upper plate of capacitor CTEM1 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of capacitor CTEM1 is connected to VCOM at CLK1, and is connected to the positive input of the first-stage integrator when CLK2 and the output code stream BS is negative, and is connected to the negative output of the first-stage integrator when CLK2 and the output code stream BS is positive; the upper plate of capacitor CTEM2 is connected to VRN at CLK1D and to VRP at CLK2D; the lower plate of capacitor CTEM2 is connected to VCOM at CLK2, and is connected to the positive input of the first-stage integrator when CLK1 and the output code stream BS is negative, and is connected to the first-stage integrator when CLK1 and the output code stream BS is positive. The negative output terminal of the integrator; the upper plate of capacitor CTEM3 is connected to VRP at CLK1D and to VRN at CLK2D; the lower plate of capacitor CTEM3 is connected to VCOM at CLK2, and is connected to the negative input terminal of the first-stage integrator when CLK1 and the output code stream BS are negative, and is connected to the positive output terminal of the first-stage integrator when CLK1 and the output code stream BS are negative; the upper plate of capacitor CTEM4 is connected to VRP at CLK2D and to VRN at CLK1D; the lower plate of capacitor CTEM4 is connected to VCOM at CLK1, and is connected to the negative input terminal of the first-stage integrator when CLK2 and the output code stream BS are negative, and is connected to the positive output terminal of the first-stage integrator when CLK1 and the output code stream BS are negative.

5. The data converter with integrated voltage-capacitance-temperature conversion function as claimed in claim 4, characterized in that: In the modulator, the first-stage amplifier is a chopper operational amplifier, and capacitors and switches are connected in parallel between the positive input terminal and the positive output terminal, and the negative input terminal and the negative output terminal of the chopper operational amplifier to serve as an integrating capacitor and a reset switch. The modulator further includes: two summing circuit capacitors Csum1, the upper plates of which are respectively connected to the differential output of the first-stage integrator and VCOM through two switches; and the lower plates are respectively permanently connected to the positive input and negative input of the comparator; a second-stage integrator and two sampling capacitors Cs2, wherein the upper plate of one sampling capacitor Cs2 is connected to the positive output terminal of the first-stage integrator and VCM respectively through two switches, and the lower plate is connected to the positive input terminal of the second-stage integrator and VCM respectively through two switches; the upper plate of the other sampling capacitor Cs2 is connected to the negative output terminal of the first-stage integrator and VCM respectively through two switches, and the lower plate is connected to the negative input terminal of the second-stage integrator and VCM respectively through two switches; the second-stage integrator includes an operational amplifier, and capacitors and reset switches are connected in parallel between the positive input terminal and the positive output terminal, and the negative input terminal and the negative output terminal of the operational amplifier; Two adding circuit capacitors Csum2, wherein the upper plate of one adding circuit capacitor Csum2 is connected to the positive terminal of the differential output of the second-stage integrator and VCM respectively through two switches, and the lower plate is permanently connected to the positive input of the comparator; the upper plate of the other adding circuit capacitor Csum2 is connected to the negative terminal of the differential output of the second-stage integrator and VCM respectively through two switches, and the lower plate is permanently connected to the negative input of the comparator; The positive and negative input terminals of the comparator are connected to VCM via a switch, and the result output code stream BS of the comparator passes through a latch and a filter to obtain an output Dout.

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