Semiconductor structure, forming method thereof and electronic equipment

Abstract

The invention relates to the technical field of semiconductors, and relates to a semiconductor structure and a forming method thereof and electronic equipment, the semiconductor structure comprises an active column, a first insulating layer, a second insulating layer and a grid electrode, the active column extends along a first direction, and the active column comprises a first source drain region, a second source drain region and a channel region which are sequentially distributed along the first direction; the first insulating layer and the second insulating layer are at least respectively positioned on two sides of the channel region in the second direction; the second direction intersects with the first direction; the grid electrode surrounds the periphery of a structure formed by the active column, the first insulating layer and the second insulating layer, and the orthographic projection of the grid electrode on the active column is at least partially overlapped with the channel region. According to the semiconductor structure, the structure arrangement can be optimized, the read-write signal interference is reduced, the sensing margin of the sensitive amplifier is improved, and the data retention time of the storage structure is prolonged.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and an electronic device. Background Art

[0002] As the integration level of memory devices increases, the pattern of individual memory cells is becoming increasingly refined, allowing more cells to be placed within the same area. This means that as the integration level of memory devices increases, the spacing between adjacent memory cells becomes increasingly smaller, making the interference problem between adjacent memory cells more difficult to effectively solve. Therefore, it is necessary to change the layout structure of existing memory devices.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as an electronic device, which can optimize the structural arrangement, reduce interference, and improve the sensing margin of the sense amplifier and the data retention time of the storage structure.

[0005] According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:

[0006] An active pillar extending along a first direction, wherein the active pillar comprises a first source and drain region, a channel region, and a second source and drain region sequentially distributed along the first direction;

[0007] A first insulating layer and a second insulating layer are respectively located at least on two sides of the channel region in a second direction; the second direction intersects the first direction;

[0008] A gate surrounds the periphery of the structure formed by the active pillar, the first insulating layer and the second insulating layer, and an orthographic projection of the gate on the active pillar at least partially overlaps with the channel region.

[0009] In an exemplary embodiment of the present disclosure, in the second direction, the width of the channel region is 30% to 60% of the sum of the width of the channel region, the width of the first insulating layer, and the width of the second insulating layer.

[0010] In an exemplary embodiment of the present disclosure, in the second direction, the first insulating layer and the second insulating layer have different widths.

[0011] In an exemplary embodiment of the present disclosure, the first insulating layer and the second insulating layer have different dielectric constants.

[0012] In an exemplary embodiment of the present disclosure, there are multiple active pillars, and the multiple active pillars form multiple active groups spaced apart along a third direction, wherein the third direction is perpendicular to the first direction and the second direction; the active group includes multiple active pillars spaced apart along the second direction, and the gates surrounding the periphery of each active pillar in the same active group are connected together to form a word line.

[0013] In an exemplary embodiment of the present disclosure, there are a plurality of word lines, and a third insulating layer is provided between adjacent word lines.

[0014] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:

[0015] a bit line located at one side of the active pillar in the first direction and connected to the first source and drain regions of the active pillars distributed along the third direction;

[0016] The storage structure is located on a side of the active pillar away from the bit line in the first direction and is connected to the second source and drain region of the active pillar.

[0017] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0018] forming an active pillar, wherein the active pillar extends along a first direction and includes at least a channel region;

[0019] forming a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer are respectively located at least on two sides of the channel region in a second direction; the second direction intersects the first direction;

[0020] A gate is formed, the gate surrounding the periphery of the structure formed by the active pillar, the first insulating layer and the second insulating layer, and an orthographic projection of the gate on the active pillar at least partially overlaps with the channel region.

[0021] In an exemplary embodiment of the present disclosure, forming the active pillar, the first insulating layer, and the second insulating layer includes:

[0022] A stacked structure is formed on a substrate, the substrate including a transistor region, the transistor region including a first region, a second region, and a third region sequentially distributed along the first direction, the stacked structure including a plurality of first semiconductor layers and first sacrificial layers alternately distributed along a third direction, and a first isolation trench penetrating each of the first semiconductor layers and each of the first sacrificial layers, the first sacrificial layer being located at least in the first region and the second region, and the first isolation trench extending along the first direction; the third direction being perpendicular to the first direction and the second direction;

[0023] Laterally etching the first semiconductor layer through the first isolation trench to reduce the width of the first semiconductor layer in the second direction to form a first recess and a second recess, respectively; the remaining first semiconductor layer forms the active pillar;

[0024] Filling the first concave portion and the second concave portion with insulating materials, respectively, to form the first insulating layer and the second insulating layer in the first concave portion and the second concave portion, respectively;

[0025] The first sacrificial layer is removed.

[0026] In an exemplary embodiment of the present disclosure, in the second direction, the width of the channel region is 30% to 60% of the sum of the width of the channel region, the width of the first insulating layer, and the width of the second insulating layer.

[0027] In an exemplary embodiment of the present disclosure, in the second direction, the first recess and the second recess have different depths.

[0028] In an exemplary embodiment of the present disclosure, the insulating material in the first recess is a first insulating material, and the insulating material in the second recess is a second insulating material, and the first insulating material and the second insulating material have different dielectric constants.

[0029] In an exemplary embodiment of the present disclosure, there are a plurality of first isolation trenches, each of which divides the first semiconductor layer into a plurality of active pillars. The plurality of active pillars form a plurality of active groups spaced apart along the third direction. The active groups include a plurality of active pillars spaced apart along the second direction. The gates surrounding the periphery of each active pillar in the same active group are connected together to form a word line. The word line formation includes:

[0030] forming a gate oxide layer surrounding an outer periphery of a structure formed by the active pillar, the first insulating layer, and the second insulating layer;

[0031] forming a conductive material conformally covering a surface of each of the active pillars having the gate oxide layer, wherein the conductive material fills the first isolation trenches between the active pillars spaced apart along the second direction;

[0032] forming an insulating material to fill remaining gaps between the active pillars distributed along the third direction;

[0033] At least the conductive material is laterally etched to form the word lines.

[0034] In an exemplary embodiment of the present disclosure, the first sacrificial layer is located in the first region, the second region, and the third region; the substrate further includes a storage structure region; the first isolation trench further extends to the storage structure region; a plurality of second semiconductor layers are formed on the storage structure region; and in the third direction, the second semiconductor layers and the active pillars are alternately distributed; a portion of the active pillar located on the first region of the transistor region is a first region to be doped, a portion located on the second region is a channel region, and a portion located on the third region is a second region to be doped; before forming the gate oxide layer, the formation method further includes:

[0035] forming a first isolation layer covering the second to-be-doped region of each of the active pillars and filling a gap between the second to-be-doped regions of each of the active pillars adjacent in the third direction; the gate oxide layer covering the first to-be-doped region and the channel region;

[0036] After at least laterally etching the conductive material to expose the first region to be doped, the forming method further includes:

[0037] doping the first region to be doped to form a first source and drain region;

[0038] removing the second semiconductor layer to expose a portion of the active pillar located in the storage structure region;

[0039] doping the active pillar and the second region to be doped located in the storage structure region to form a second source and drain region in the second region to be doped;

[0040] Optionally, forming the second source and drain region includes: forming a doping material layer on the surface of the active column located in the storage structure area, heat treating the doping material layer so that the doping ions in the doping material layer diffuse into the active column located in the storage structure area and the second area to be doped, and using the doped second area to be doped as the second source and drain region.

[0041] In an exemplary embodiment of the present disclosure, the first sacrificial layer is located in the first region and the second region, the substrate further includes a storage structure region, the first isolation trench further extends to the storage structure region, a plurality of second semiconductor layers are formed on the third region and the storage structure region, and the second semiconductor layers and the active pillars are alternately distributed in the third direction; the portion of the active pillar located on the first region of the transistor region is a first region to be doped, the portion located on the second region is a channel region, and the portion located on the third region is a second region to be doped; the gate oxide layer covers the first region to be doped and the channel region; and the formation method further includes:

[0042] After at least laterally etching the conductive material to expose the first region to be doped, the forming method further includes:

[0043] doping the first region to be doped to form a first source and drain region;

[0044] removing the second semiconductor layer to expose the second to-be-doped region in the active pillar and a portion of the active pillar located in a storage structure forming region;

[0045] doping the second region to be doped to form a second source and drain region;

[0046] Optionally, forming the second source and drain region includes: forming a doping material layer on the surface of the second region to be doped, heat treating the doping material layer so that the doping ions in the doping material layer diffuse into the second region to be doped, and using the doped second region to be doped as the second source and drain region.

[0047] In an exemplary embodiment of the present disclosure, before removing the second semiconductor layer, the forming method further includes:

[0048] forming a bit line on one side of the active pillar in the first direction, wherein the bit line is connected to the first source and drain regions of the active pillars distributed along the third direction;

[0049] After forming the second source and drain regions, the forming method further includes:

[0050] A storage structure is formed on a side of the active pillar away from the bit line in the first direction, and the storage structure is connected to the second source and drain region of the active pillar.

[0051] According to one aspect of the present disclosure, an electronic device is provided, including a processing device; and a memory device electrically connected to the processing device, wherein the memory device includes any one of the semiconductor structures described above.

[0052] The semiconductor structure and its formation method, as well as the electronic device disclosed herein, are provided with a first insulating layer and a second insulating layer on either side of the channel region, respectively. The gate surrounds the periphery of the structure formed by the active pillar, the first insulating layer, and the second insulating layer. This allows the spacing between adjacent transistors to satisfy the requirement that the transmitted data does not interfere with each other during a read operation when both transistors are turned on simultaneously. This also reduces gate coupling noise, reduces the channel width of each transistor, thereby reducing transistor leakage noise, and improves the sensing margin of the sense amplifier connected to the transistor, thereby improving data reading accuracy. Furthermore, during a write operation when both transistors are turned on simultaneously, the data in each other's channels does not interfere with each other, reducing the voltage fluctuation of the written data and improving data retention time.

[0053] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0055] Figure 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0056] Figure 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0057] Figure 3 In one embodiment of the present disclosure Figure 1 Cross-sectional view taken along the aa' direction;

[0058] Figure 4 In one embodiment of the present disclosure, an active group, a first insulating layer, a second insulating layer and a gate oxide layer are formed. Figure 1 In the bb' direction or along Figure 2 Cross-sectional view taken along the bb' direction;

[0059] Figure 5 A method for forming a semiconductor structure in an embodiment of the present disclosure;

[0060] Figure 6 is a top view of the stacking structure in an embodiment of the present disclosure;

[0061] Figure 7 In the embodiment of the present disclosure Figure 6 Cross-sectional view taken along the cc' direction;

[0062] Figure 8 is a cross-sectional view after stacked film layers are formed in an embodiment of the present disclosure;

[0063] Figure 9 In the embodiment of the present disclosure, the first groove rear edge is formed Figure 6 Cross-sectional view taken along the cc' direction;

[0064] Figure 10 In the embodiment of the present disclosure, the second sacrificial layer is formed on the back edge Figure 6 Cross-sectional view taken along the cc' direction;

[0065] Figure 11 In the embodiment of the present disclosure, the rear edge of the second sacrificial layer is removed. Figure 6 Cross-sectional view taken along the cc' direction;

[0066] Figure 12 In the embodiment of the present disclosure, the rear edge of the second sacrificial layer is removed. Figure 2 Cross-sectional view taken along the aa' direction;

[0067] Figure 13 In the embodiment of the present disclosure, the first sacrificial layer is formed at the rear edge Figure 6 Cross-sectional view taken along the cc' direction;

[0068] Figure 14 In the embodiment of the present disclosure, the first concave portion and the second concave portion are formed at the rear edge. Figure 6 Cross-sectional view taken along the cc' direction;

[0069] Figure 15 In the embodiment of the present disclosure, the first insulating layer and the second insulating layer are formed at the rear edge. Figure 6 Cross-sectional view taken along the cc' direction;

[0070] Figure 16 In the embodiment of the present disclosure, the first sacrificial layer is removed from the back edge. Figure 6 Cross-sectional view taken along the cc' direction;

[0071] Figure 17 This is a top view of the first embodiment of the present disclosure after the first isolation layer is formed;

[0072] Figure 18 In the first embodiment of the present disclosure, Figure 17 Cross-sectional view taken along the dd' direction;

[0073] Figure 19 The word line trailing edge is formed in the first embodiment of the present disclosure. Figure 17 Cross-sectional view taken along the dd' direction;

[0074] Figure 20 In one embodiment of the present disclosure, a word line trailing edge is formed. Figure 17 Cross-section taken along the ee' direction;

[0075] Figure 21 After forming the third isolation layer and the bit line in the first embodiment of the present disclosure, Figure 17 Cross-sectional view taken along the dd' direction;

[0076] Figure 22 In one embodiment of the present disclosure, a storage structure is formed at the rear edge. Figure 17 Cross-sectional view taken along the dd' direction;

[0077] Figure 23 In the embodiment of the present disclosure, step S330 is completed. Figure 2 Cross-sectional view taken along the aa' direction;

[0078] Figure 24 The second embodiment of the present disclosure forms a bit line trailing edge. Figure 2 Cross-sectional view taken along the aa' direction;

[0079] Figure 25 This is a top view after the fourth isolation layer is formed in the second embodiment of the present disclosure.

[0080] Description of reference numerals:

[0081] 1. Active pillar; 11. First source / drain region; 12. Channel region; 13. Second source / drain region; 110. Active group; 2. First insulating layer; 3. Second insulating layer; 4. Gate; 41. Gate oxide layer; 42. Conductive layer; 420. Conductive material; 5. Word line; 6. Third insulating layer; 7. Bit line; 8. Memory structure; 81. Lower electrode layer; 82. Dielectric layer; 83. Upper electrode layer; 10. Stacked structure; 101. First semiconductor layer; 10 2. First sacrificial layer; 103. First isolation trench; 104. First recess; 105. Second recess; 106. First trench; 107. Second trench; 20. Second semiconductor layer; 30. Second sacrificial layer; 40. First isolation layer; 50. Second isolation layer; 60. Third isolation layer; 70. Insulating material; 80. Fourth isolation layer; x, first direction; y, second direction; z, third direction; A, transistor area; B, storage structure area. DETAILED DESCRIPTION

[0082] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0083] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0084] The terms "a", "an", "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0085] With the development of semiconductor technology, the size of existing memory cells is getting smaller and smaller, and the spacing between adjacent memory cells is also getting smaller and smaller, which is easy to cause interference. Problems caused by interference include: coupling between the channels of transistors in adjacent memory cells, and coupling between the bit lines connected to the transistors in adjacent memory cells. Currently, as planar process scaling approaches physical limits, various types of memories are moving towards a three-dimensional stacked architecture. In a three-dimensional memory using horizontal word lines and vertical bit line transistors, in order to connect the gate metals of adjacent transistors to form a coherent word line, the channel width of the transistor must be large enough, which can reduce the transistor spacing so that a small amount of gate metal filling can achieve conductive connection between adjacent gates. However, an excessively large channel width not only leads to coupling between adjacent channels, but also causes a significant increase in transistor leakage current, resulting in deteriorated data storage time and higher power consumption.

[0086] Based on this, the present disclosure provides a semiconductor structure, such as Figure 1-Figure 3 As shown, the semiconductor structure includes an active pillar 1, a first insulating layer 2, a second insulating layer 3 and a gate 4, wherein:

[0087] The active pillar 1 extends along a first direction x, and includes a first source and drain region 11, a channel region 12, and a second source and drain region 13 sequentially distributed along the first direction x;

[0088] The first insulating layer 2 and the second insulating layer 3 are respectively located at least on two sides of the channel region 12 in the second direction y; the second direction y intersects with the first direction x;

[0089] The gate 4 surrounds the periphery of the structure formed by the active pillar 1 , the first insulating layer 2 and the second insulating layer 3 , and the orthographic projection of the gate 4 on the active pillar 1 at least partially overlaps with the channel region 12 .

[0090] In an exemplary embodiment of the present disclosure, in the second direction y, the width of the channel region 12 is 30% to 60% of the sum of the widths of the channel region 12 , the first insulating layer 2 , and the second insulating layer 3 .

[0091] The semiconductor structure disclosed herein is characterized in that a channel region 12 and a first insulating layer 2 and a second insulating layer 3 are provided on either side of the channel region 12 in an area where the channel region 12 is originally provided, and a gate 4 surrounds the periphery of the structure formed by the active pillar 1, the first insulating layer 2 and the second insulating layer 3, so that the spacing between adjacent transistors satisfies the requirement that the transmitted data does not interfere with each other during the simultaneous open read operation, and can also reduce the gate 4 coupling noise, reduce the channel width of each transistor, thereby reducing the leakage noise of the transistor, and improve the sensing margin of the sensitive amplifier connected to the transistor, thereby improving the accuracy of data reading. For example, in the second direction y (i.e., the lateral dimension perpendicular to the carrier transmission path), the width of the channel region 12 can be 30% to 60% of the sum of the widths of the channel region 12, the first insulating layer 2 and the second insulating layer 3. When the proportion of the channel region 12 is less than 60%, the area of ​​the channel region 12 is small, the leakage current channel area between the first source and drain region 111 and the second source and drain region 13 in the transistor is small, the leakage current is small, the sensing margin of the sense amplifier is increased, and the accuracy of data reading is improved; when the proportion of the channel region 12 is higher than 30%, the sharp reduction in the effective conductive area of ​​the channel region 12 caused by the excessive width of the first insulating layer 2 or the second insulating layer 3 can be avoided, thereby preventing the abnormal increase in the resistance of the channel region 12 and the attenuation of the driving current. At the same time, when the proportion of the channel region 12 is higher than 60%, the cross-sectional area of ​​the channel region 12 is relatively large, and the effect of suppressing the leakage current is not obvious; when the proportion of the channel region 12 is lower than 30%, the cross-sectional area of ​​the channel region 12 is too small, resulting in a small on-state current, which in turn causes the storage structure to have a long charge and discharge time, which cannot meet the design requirements of the storage device. In the present disclosure, by controlling the channel region ratio, the leakage current can be greatly reduced while ensuring sufficient on-state driving current. In addition, since the gate 4 surrounds the periphery of the structure formed by the active column 1, the first insulating layer 2 and the second insulating layer 3, the traditional double-gate control function of the channel can be achieved through a full-surround gate, and compared with the double-gate structure, the gate 4 of the present disclosure has smaller resistance.

[0092] On the other hand, the first insulating layer 2 and the second insulating layer 3 can reduce the area of ​​the channel region 12, so that the data in each other's channels do not interfere with each other during the write operation when adjacent transistors are turned on at the same time, reducing the voltage fluctuation of the written data and improving the data retention time.

[0093] The following describes in detail the various parts of the semiconductor structure disclosed herein and their specific details:

[0094] The material of the active pillar 1 can be a semiconductor material, for example, silicon, germanium or a composite material, and the material of the active pillar 1 is not particularly limited here. Figure 1-Figure 3As shown, the active pillar 1 may be strip-shaped and may extend along a first direction x. The active pillar 1 may include a first source and drain region 11, a channel region 12, and a second source and drain region 13 sequentially distributed along the first direction x. For example, the first source and drain region 11, the channel region 12, and the second source and drain region 13 may be sequentially contacted and connected along the first direction x. The cross-section of the active pillar 1 may be rectangular, elliptical, circular, polygonal, or irregular, without particular limitation herein.

[0095] like Figure 4 As shown, the first insulating layer 2 and the second insulating layer 3 may be located at least on both sides of the channel region 12 in the second direction y, that is, the first insulating layer 2 and the second insulating layer 3 may be spaced apart in the second direction y. For example, the first insulating layer 2 and the second insulating layer 3 may be located on the two sidewalls of the channel region 12 in the second direction y; or, please continue to refer to Figure 1 and Figure 2 As shown, the first insulating layer 2 and the second insulating layer 3 can be respectively located on the two sidewalls of the channel region 12 in the second direction y, and can also be located on the two sidewalls of the first source and drain region 11 in the second direction y and the two sidewalls of the second source and drain region 13 in the second direction y. For example, the first insulating layer 2 and the second insulating layer 3 can both be strip-shaped, and the first insulating layer 2 and the second insulating layer 3 can both extend along the first direction x, and the two ends of the first insulating layer 2 (and / or the second insulating layer 3) are respectively flush with the end of the first source and drain region 11 away from the channel region 12 and the end of the second source and drain region 13 away from the channel region 12.

[0096] The second direction y intersects the first direction x. For example, the second direction y and the first direction x may be perpendicular to each other. It should be noted that perpendicularity can be absolutely perpendicular or approximately perpendicular. Deviations are inevitable during the manufacturing process. In the present disclosure, the angle deviation may be caused by manufacturing process limitations, resulting in a certain deviation in the angle between the second direction y and the first direction x. As long as the angular deviation between the second direction y and the first direction x is within a preset range, the second direction y can be considered perpendicular to the first direction x. For example, the preset range can be 10°, that is, when the angle between the second direction y and the first direction x is greater than or equal to 80° and less than or equal to 100°, the second direction y can be considered perpendicular to the first direction x.

[0097] In an exemplary embodiment of the present disclosure, in the second direction y, the width of the channel region 12 may be 30% to 60% of the sum of the width of the channel region 12, the width of the first insulating layer 2, and the width of the second insulating layer 3. Within this ratio range, the cross-sectional area of ​​the channel region 12 can be appropriately reduced while ensuring the on-state current, thereby reducing the leakage current path area from the second source and drain region 13 to the first source and drain region 11, thereby helping to reduce leakage current, improve the sensing margin of the sense amplifier connected to the transistor, and thereby improve data reading accuracy. For example, in the second direction y, the width of the channel region 12 may be 30%, 35%, 40%, 45%, 50%, 55%, or 60% of the sum of the width of the channel region 12, the width of the first insulating layer 2, and the width of the second insulating layer 3. Of course, other ratios are also possible and are not listed here.

[0098] The materials of the first insulating layer 2 and the second insulating layer 3 can both be insulating materials. For example, the materials of the first insulating layer 2 and the second insulating layer 3 can be silicon nitride, silicon oxide, silicon carbide, aluminum oxide, polysilicon, silicon oxynitride, silicon carbide or carbon.

[0099] In an exemplary embodiment of the present disclosure, in the second direction y, the widths of the first insulating layer 2 and the second insulating layer 3 are different, so as to facilitate the regulation of the stress of the first insulating layer 2 and the second insulating layer 3, thereby reducing the probability of active pillar 1 collapse after etching the film structure between adjacent active pillars 1 during the manufacturing process, thereby helping to improve product yield. For example, in the second direction y, the ratio of the widths of the first insulating layer 2 and the second insulating layer 3 can be 3:2 to 5:4; for example, in the second direction y, the ratio of the widths of the first insulating layer 2 and the second insulating layer 3 can be 3:2, 4:3, or 5:4; of course, in the second direction y, the widths of the first insulating layer 2 and the second insulating layer 3 can also be other ratios, as long as the stress in the structure is optimized and the probability of collapse of each active pillar 1 is reduced.

[0100] In an exemplary embodiment of the present disclosure, the dielectric constants of the first insulating layer 2 and the second insulating layer 3 are different. For example, the materials of the first insulating layer 2 and the second insulating layer 3 are different. By designing different dielectric constants, the stress of the first insulating layer 2 and the second insulating layer 3 can also be regulated, thereby reducing the probability of active pillars 1 collapsing after etching the film structure between adjacent active pillars 1 during the manufacturing process, which helps to improve product yield. For example, the material of the first insulating layer 2 can be silicon oxide, and the material of the second insulating layer 3 can be silicon nitride; or, the material of the first insulating layer 2 can be silicon carbide, and the material of the second insulating layer 3 can be aluminum oxide; or, the material of the first insulating layer 2 can be silicon oxynitride, and the material of the second insulating layer 3 can be silicon carbide; or, the material of the first insulating layer 2 can be polysilicon, and the material of the second insulating layer 3 can be silicon carbide.

[0101] Please continue to see Figure 1 and Figure 2 As shown, the gate 4 surrounds the periphery of the structure formed by the active pillar 1, the first insulating layer 2 and the second insulating layer 3, and the positive projection of the gate 4 on the active pillar 1 at least partially overlaps with the channel region 12. The control function of the traditional double gate on the channel can be achieved through the full-surround gate 4, and compared with the double-gate structure, the gate 4 disclosed in the present invention can reduce the resistance of the gate 4 while weakening the coupling between the upper and lower adjacent gate layers 4.

[0102] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 1 and Figure 2 As shown, the gate 4 may include a gate oxide layer 41 and a conductive layer 42, wherein the material of the gate oxide layer 41 may be silicon oxide. In some embodiments of the present disclosure, such as Figure 1 As shown, the gate oxide layer 41 can conformally surround the periphery of the structure formed by the active pillar 1, the first insulating layer 2 and the second insulating layer 3. The orthographic projection of the gate oxide layer 41 on the active pillar 1 at least partially overlaps with the channel region 12. For example, the gate oxide layer 41 can surround the area corresponding to the channel region 12 in the active pillar 1; or, the gate oxide layer 41 can surround the periphery of the sidewall area corresponding to the entire active pillar 1. In other embodiments of the present disclosure, such as Figure 2 As shown, the gate oxide layer 41 may cover the upper and lower surfaces of the structure composed of the active pillar 1, the first insulating layer 2 and the second insulating layer 3. For example, the gate oxide layer 41 may cover the upper and lower surfaces of the channel region 12 and the first insulating layer 2 and the second insulating layer 3 located on both sides of the channel region 12; or, the gate oxide layer 41 may cover the upper and lower surfaces of the structure composed of the entire active pillar 1 (including the first source and drain region 11, the channel region 12 and the second source and drain region 13) and the first insulating layer 2 and the second insulating layer 3 located on both sides of the active pillar 1. In some further embodiments of the present disclosure, the gate oxide layer 41 may cover the upper and lower surfaces of the active pillar 1. For example, the gate oxide layer 41 may cover the upper and lower surfaces of the channel region 12 in the active pillar 1; or, the gate oxide layer 41 may cover the upper and lower surfaces of the entire active pillar 1 (including the first source and drain region 11, the channel region 12 and the second source and drain region 13). The conductive layer 42 can be made of a material with strong electrical conductivity, such as tungsten, titanium nitride, molybdenum, or rubidium. The conductive layer 42 can be disposed on the gate oxide layer 41 and surround the periphery of the active pillar 1. The orthographic projection of the conductive layer 42 on the active pillar 1 at least partially overlaps with the channel region 12. In some embodiments of the present disclosure, the orthographic projection of the conductive layer 42 on the active pillar 1 overlaps with the channel region 12.

[0103] In an exemplary embodiment of the present disclosure, Figure 4As shown, there can be multiple active pillars 1, with the multiple active pillars 1 forming multiple active groups 110 spaced apart along the third direction z. The third direction z is perpendicular to the first direction x and the second direction y. For example, the third direction z is perpendicular to the plane defined by the first direction x and the second direction y. The active group 110 can be formed on a substrate. The third direction z is perpendicular to the surface of the substrate, and the first direction x and the second direction y are both parallel to the surface of the substrate. The active group 110 can include all active pillars 1 spaced apart along the second direction y in the same layer. The gates 4 surrounding the periphery of each active pillar 1 in the same active group 110 are connected together to form a word line 5. For example, the conductive layers 42 in the gates 4 surrounding each active pillar 1 spaced apart along the second direction y can be interconnected to form a word line 5, which can extend along the second direction y. It should be noted that when the active group 100 includes only one active pillar 1, the gate oxide layer 41 and the conductive layer 42 provided on the active pillar 1 can serve as the gate 4.

[0104] Please continue to see Figure 1 and Figure 2 As shown, when there are multiple active groups 110, there are also multiple word lines 5. Each active group 110 may correspond to one word line 5. The multiple word lines 5 may be spaced apart along the third direction z, and a third insulating layer 6 (such as ) is provided between adjacent word lines 5. Figure 3 The adjacent word lines 5 can be physically isolated by the third insulating layer 6 to prevent coupling between adjacent word lines 5.

[0105] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 1-Figure 3 As shown, the semiconductor structure of the present disclosure may further include a bit line 7 and a storage structure 8, wherein:

[0106] In the first direction x, the bit line 7 is located on one side of the active pillar 1 and can be connected to the first source and drain regions 11 of each active pillar 1 distributed along the third direction z in different active groups 110. For example, the bit line 7 can be in a strip shape and can extend along the third direction z, and the bit line 7 can be in contact with the first source and drain regions 11. When each active group 110 includes multiple active pillars 1, the number of bit lines 7 is also multiple, and the multiple bit lines 7 can be distributed at intervals along the second direction y, and each bit line 7 is respectively connected to each active pillar 1 located in a different column. In this disclosure, please continue to refer to Figure 1 and Figure 2 As shown, by respectively providing a first insulating layer 2 and a second insulating layer 3 on both sides of the active pillar 1 , the effective dielectric distance between adjacent bit lines 7 is increased, thereby reducing the capacitive coupling between adjacent bit lines 7 and lowering the crosstalk between adjacent bit lines 7 .

[0107] Please continue to see Figure 3As shown, in the first direction x, the storage structure 8 is located on the side of the active pillar 1 away from the bit line 7, and is connected to the first source and drain region 11 of the active pillar 1. The storage structure 8 may be strip-shaped and may extend along the first direction x. A storage structure 8 is provided at each end of each active pillar 1. In some embodiments of the present disclosure, the storage structure 8 may be a capacitor; the capacitor may include a lower electrode layer 81, a dielectric layer 82, and an upper electrode layer 83, wherein the lower electrode layer 81 is in contact with the second source and drain region 13 in the active pillar 1, and the dielectric layer 82 is located between the upper electrode layer 83 and the lower electrode layer 81. In other embodiments of the present disclosure, the capacitor may be replaced by other structures with charge storage functions.

[0108] The present disclosure also provides a method for forming a semiconductor structure, which is used to form the semiconductor structure in any of the above embodiments, such as Figure 5 As shown, the forming method includes steps S110 to S130, wherein:

[0109] Step S110, forming an active pillar, wherein the active pillar extends along a first direction and includes at least a channel region;

[0110] Step S120, forming a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer are respectively located at least on two sides of the channel region in a second direction; the second direction intersects the first direction;

[0111] In step S130 , a gate is formed. The gate surrounds the periphery of the structure formed by the active pillar, the first insulating layer, and the second insulating layer. The orthographic projection of the gate on the active pillar at least partially overlaps with the channel region.

[0112] Compared with the prior art, the beneficial effects of the method for forming a semiconductor structure provided by the present disclosure are the same as the beneficial effects of the semiconductor structure provided by the above-mentioned example embodiments, and are not described in detail here.

[0113] The following is a detailed description of the steps and details of the method for forming a semiconductor structure disclosed herein:

[0114] like Figure 5 As shown, in step S110 , an active pillar 1 is formed. The active pillar 1 extends along a first direction x and includes at least a channel region 12 .

[0115] The active pillar 1 can be made of a semiconductor material, such as silicon, germanium, or a composite material. The material of the active pillar 1 is not particularly limited herein. The active pillar 1 can be strip-shaped and extend along a first direction x. The active pillar 1 can include a first region to be doped, a channel region 12, and a second region to be doped, sequentially distributed along the first direction x. For example, the first region to be doped, the channel region 12, and the second region to be doped can be sequentially contacted and connected along the first direction x. The cross-section of the active pillar 1 can be rectangular, elliptical, circular, polygonal, or irregular, and is not particularly limited herein.

[0116] In an exemplary embodiment of the present disclosure, forming the active pillar 1 may include:

[0117] A stacked structure 10 is formed on a substrate (not shown). The substrate can be a flat plate structure that can be rectangular, circular, elliptical, polygonal, or irregularly shaped. The material can be a semiconductor material, such as silicon. The substrate can include a transistor region A and a memory structure region B. The transistor region A can include a first region, a second region, and a third region sequentially distributed along a first direction x, with the third region adjacent to the memory structure region B. The stacked structure 10 can include a plurality of first semiconductor layers 101 and first sacrificial layers 102 alternately distributed along a third direction z, and a plurality of first isolation trenches 103 extending through each of the first semiconductor layers 101 and first sacrificial layers 102. The first sacrificial layer 102 is located in at least the first and second regions of the transistor region A. For example, in a first exemplary embodiment of the present disclosure, the first sacrificial layer 102 is located in the first, second, and third regions of the transistor region A. In a second exemplary embodiment of the present disclosure, the first sacrificial layer 102 is located in the first and second regions of the transistor region A. Each first isolation trench 103 extends along the first direction x and can extend from the transistor area A to the storage structure area B; the third direction z is perpendicular to the first direction x and the second direction y (eg Figure 6 and Figure 7 shown).

[0118] In an exemplary embodiment of the present disclosure, the steps of forming the stack structure 10 are as follows:

[0119] like Figure 8 As shown, a plurality of first semiconductor layers 101 and second semiconductor layers 20 alternately distributed along a third direction z can be formed on a substrate (not shown) by an epitaxial growth process. The material of the first semiconductor layer 101 can be silicon, and the material of the second semiconductor layer 20 can be silicon germanium. The bottommost second semiconductor layer 20 can be formed directly on the surface of the substrate.

[0120] like Figure 9As shown, a stacked film layer consisting of a plurality of first semiconductor layers 101 and a plurality of second semiconductor layers 20 can be dry-etched to form a first trench 106 penetrating the stacked film layer along a third direction z. The first trench 106 can extend along a first direction x and penetrate each of the first semiconductor layers 101 and each of the second semiconductor layers 20 along the first direction x. In an exemplary embodiment of the present disclosure, there can be a plurality of first trenches 106, and the plurality of first trenches 106 can be spaced apart and arranged in parallel along the second direction y.

[0121] like Figure 10 As shown, a second sacrificial layer 30 can be formed in the first trench 106 by a deposition process, and the second sacrificial layer 30 can fill the first trench 106; the material of the second sacrificial layer 30 can be an insulating material, for example, the material of the second sacrificial layer 30 can be silicon oxide, silicon nitride, silicon carbide, aluminum oxide, polysilicon, silicon oxynitride, silicon carbide or carbon, etc.

[0122] like Figure 11 and Figure 12 As shown, after the second sacrificial layer 30 is formed, part of the second semiconductor layer 20 can be removed. For example, in the first exemplary embodiment of the present disclosure, the second semiconductor layer 20 located in the transistor area A (including the first region, the second region and the third region) can be removed, thereby retaining the second semiconductor layer 20 located in the storage structure area B. In the second embodiment of the present disclosure, the second semiconductor layer 20 located in the first region and the second region of the transistor area A can be removed, thereby retaining the second semiconductor layer 20 corresponding to the third region of the transistor area A and the storage structure area B. It should be noted that when the material of the second semiconductor layer 20 is silicon germanium, part of the second semiconductor layer 20 can be removed by wet etching. The removal of part of the second semiconductor layer 20 can be carried out by passing a wet etching solution through the bit line trench (not shown in the figure). The bit line trench passes through each first semiconductor layer 101 and each second semiconductor layer 20 and is perpendicular to the first trench 106.

[0123] After removing a portion of the second semiconductor layer 20, the exposed first semiconductor layer 101 can be thinned to leave more process space for the gate 4 to be formed subsequently. It should be noted that during the thinning process of the first semiconductor layer 101, the remaining second semiconductor layer 20 and the second sacrificial layer 30 can support the remaining first semiconductor layers 101, thereby preventing the remaining first semiconductor layers 101 from collapsing during the thinning process. Thinning the first semiconductor layer 101 made of silicon can be achieved by wet etching by passing a solution into the bit line trench.

[0124] like Figure 13As shown, after the first semiconductor layer 101 is thinned, a first sacrificial layer 102 may be formed between the remaining first semiconductor layers 101. The first sacrificial layer 102 may fill the gaps between adjacent first semiconductor layers 101. For example, in the first exemplary embodiment of the present disclosure, since the gaps between the first semiconductor layers 101 located in the memory structure region B and between the bottommost first semiconductor layer 101 and the substrate (not shown) are filled with the second semiconductor layer 20, the first sacrificial layer 102 is located between the first semiconductor layers 101 in the first, second, and third regions of the transistor region A and between the bottommost first semiconductor layer 101 and the substrate, that is, the first sacrificial layer 102 is located in the first, second, and third regions. In the second exemplary embodiment of the present disclosure, since the second semiconductor layer 20 is filled between each first semiconductor layer 101 located on the third region and the storage structure region B, and between the bottom first semiconductor layer 101 and the substrate (not shown), the first sacrificial layer 102 is located between each first semiconductor layer 101 on the first region and the second region in the transistor region A, and between the bottom first semiconductor layer 101 and the substrate (not shown), that is, the first sacrificial layer 102 is located in the first region and the second region.

[0125] The material of the first sacrificial layer 102 can be silicon oxide, silicon nitride, silicon carbide, aluminum oxide, polysilicon, silicon oxynitride, silicon carbide, or carbon. The process for forming the first sacrificial layer 102 can be a deposition process. It should be noted that the material of the first sacrificial layer 102 is different from the material of the second sacrificial layer 30 so that the first sacrificial layer 102 is retained during the subsequent selective etching of the second sacrificial layer 30.

[0126] In the first exemplary embodiment of the present disclosure, the second sacrificial layer 30 located in the first region, the second region, and the third region of the transistor region A may be removed after the first sacrificial layer 102 is formed (see Figure 7 As shown), the sidewalls of the remaining first semiconductor layers 101 are exposed. In the second exemplary embodiment of the present disclosure, the second sacrificial layer 30 located in the first and second regions of the transistor region A can be removed after the first sacrificial layer 102 is formed (see Figure 7 ), thereby exposing the remaining sidewalls of each first semiconductor layer 101. For example, the second sacrificial layer 30 can be etched and removed using a selective etching process. The space formed after removing the second sacrificial layer 30 (i.e., a portion of the area where the first trench 106 was originally located) can be used as the first isolation trench 103.

[0127] like Figure 14As shown, the first semiconductor layer 101 can be laterally etched through the first isolation trench 103 to reduce the width of the first semiconductor layer 101 in the second direction y to form a first recess 104 and a second recess 105 respectively; the retained first semiconductor layer 101 forms an active pillar 1.

[0128] For example, each first semiconductor layer 101 can be etched through a lateral etching process to reduce the width of each first semiconductor layer 101 in the second direction y. A first recess 104 and a second recess 105 are formed on both sides of the remaining first semiconductor layer 101 after the width reduction. It should be noted that the first recess 104 and the second recess 105 are both surrounded by two first sacrificial layers 102 adjacent to each other in the third direction z and the sidewalls of the active pillar 1 between the two first sacrificial layers 102. The first recess 104 and the second recess 105 can both be strip-shaped and extend along the first direction x. The first recess 104 and the second recess 105 are spaced apart along the second direction y.

[0129] In subsequent processes, the remaining first semiconductor layer 101 after the width reduction can be used as the active pillar 1, and the portion of the active pillar 1 located on the first region of the transistor area A can be defined as the first to-be-doped region, the portion located on the second region can be defined as the channel region 12, and the portion located on the third region can be defined as the second to-be-doped region. Subsequently, the first to-be-doped region and the second to-be-doped region in the active pillar 1 can be doped to form first source and drain regions 11 and second source and drain regions 13 spaced apart along the first direction x. The region of the active pillar 1 between the first source and drain regions 11 and the second source and drain regions 13 can be used as the channel region 12.

[0130] In the present disclosure, since the first semiconductor layer 101 is laterally etched, the width of the active pillar 1 in the second direction y is reduced, thereby reducing the width of the channel region 12 and the cross-sectional area of ​​the channel region 12, thereby reducing the leakage current channel area from the second source and drain region 13 to the first source and drain region 11, which helps to reduce the leakage current and improve the sensing margin of the sensitive amplifier connected to the transistor, thereby improving the accuracy of data reading.

[0131] In some embodiments of the present disclosure, in the second direction y, the width of the active column 1 may be 30% to 60% of the sum of the width of the active column 1, the width of the first recess 104 on one side of the active column 1, and the width of the second recess 105 on one side of the active column 1. For example, the width of the active column 1 is 30%, 35%, 40%, 45%, 50%, 55% or 60% of the sum of the width of the active column 1, the width of the first recess 104, and the width of the second recess 105.

[0132] In an exemplary embodiment of the present disclosure, the first recess 104 and the second recess 105 have different depths in the second direction y, thereby causing the first insulating layer 2 and the second insulating layer 3 subsequently formed in the first recess 104 and the second recess 105 to have different widths in the first direction x. For example, during the process of removing the second sacrificial layer 30, the second sacrificial layer 30 within the first trench 106 on one side of the first semiconductor layer 101 can be removed first, while retaining the second sacrificial layer 30 within the first trench 106 on the other side. The end portion of the first semiconductor layer 101 exposed after removal of the second sacrificial layer 30 is laterally etched to form the first recess 104. Subsequently, the remaining second sacrificial layer 30 is removed to expose the other end portion of the first semiconductor layer 101, which is laterally etched to form the second recess 105. The depths of the two etchings are different, resulting in different depths of the first recess 104 and the second recess 105.

[0133] like Figure 5 As shown, in step S120 , a first insulating layer 2 and a second insulating layer 3 are formed. The first insulating layer 2 and the second insulating layer 3 are respectively located at least on two sides of the channel region 12 in the second direction y; the second direction y intersects with the first direction x.

[0134] like Figure 4 As shown, the first insulating layer 2 and the second insulating layer 3 may be spaced apart in the second direction y. For example, the first insulating layer 2 and the second insulating layer 3 may be respectively located on the two sidewalls of the channel region 12 in the second direction y; or, please continue to refer to Figure 1 and Figure 2 As shown, the first insulating layer 2 and the second insulating layer 3 can be respectively located on the two sidewalls of the channel region 12 in the second direction y, and can also be located on the two sidewalls of the first source and drain region 11 in the second direction y and the two sidewalls of the second source and drain region 13 in the second direction y. For example, the first insulating layer 2 and the second insulating layer 3 can both be strip-shaped, and the first insulating layer 2 and the second insulating layer 3 can both extend along the first direction x, and the two ends of the first insulating layer 2 (and / or the second insulating layer 3) are respectively flush with the end of the first source and drain region 11 away from the channel region 12 and the end of the second source and drain region 13 away from the channel region 12.

[0135] For example, the first concave portion 104 and the second concave portion 105 may be filled with insulating materials, respectively, to form a first insulating layer 2 and a second insulating layer 3 in the first concave portion 104 and the second concave portion 105, respectively. Figure 15As shown; in the second direction y, the width of the channel region 12 is 30% to 60% of the sum of the width of the channel region 12, the width of the first insulating layer 2, and the width of the second insulating layer 3. Within this ratio range, the cross-sectional area of ​​the channel region 12 can be appropriately reduced while ensuring the on-state current, thereby reducing the leakage current path area from the second source and drain region 13 to the first source and drain region 11, which helps to reduce leakage current, improve the sensing margin of the sense amplifier connected to the transistor, and thus improve the accuracy of data reading. When the proportion of the channel region 12 is higher than 60%, the cross-sectional area of ​​the channel region 12 is relatively large, and the effect of suppressing the off-state current is not obvious; when the proportion of the channel region 12 is lower than 30%, the cross-sectional area of ​​the channel region 12 is too small, resulting in a small on-state current, which in turn leads to an excessively long charge and discharge time of the storage structure, which cannot meet the design requirements of the storage device.

[0136] In an exemplary embodiment of the present disclosure, an insulating material can be deposited on the surface of the structure formed by each active pillar 1 and each first sacrificial layer 102 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition until the insulating material fills the first recess 104 and the second recess 105. The insulating material on the sidewalls of the first isolation trench 103 can then be removed, leaving the remaining insulating material within the first recess 104 and the second recess 105. The remaining insulating material within the first recess 104 can be used as the first insulating layer 2, and the remaining insulating material within the second recess 105 can be used as the second insulating layer 3. It should be noted that when the depths of the first recess 104 and the second recess 105 are different, the widths of the first insulating layer 2 and the second insulating layer 3 in the second direction y are different, which helps to regulate the stress of the first insulating layer 2 and the second insulating layer 3, thereby reducing the probability of collapse of the active pillar 1 and the remaining second semiconductor layer 20 after etching the film structure between adjacent active pillars 1 during the manufacturing process, thereby helping to improve product yield.

[0137] In an exemplary embodiment of the present disclosure, the insulating material in the first recess 104 is a first insulating material, and the insulating material in the second recess 105 is a second insulating material. The first and second insulating materials have different dielectric constants. For example, the first insulating material can be formed in the first recess 104, and the second insulating material can be formed in the second recess 105, thereby resulting in different dielectric constants for the first and second insulating layers 2 and 3. By designing different dielectric constants, the stress of the first and second insulating layers 2 and 3 can be controlled, thereby reducing the probability of active pillar 1 collapse after etching the film structure between adjacent active pillars 1 during the manufacturing process, thereby helping to improve product yield. For example, the first insulating material can be silicon oxide, and the second insulating material can be silicon nitride; alternatively, the first insulating material can be silicon carbide nitride, and the second insulating material can be aluminum oxide; alternatively, the first insulating material can be silicon oxynitride, and the second insulating material can be silicon carbide; further alternatively, the first insulating material can be polycrystalline silicon or amorphous silicon, and the second insulating material can be silicon carbide.

[0138] like Figure 16 As shown, after forming the first insulating layer 2 and the second insulating layer 3 and before forming the gate 4, the first sacrificial layer 102 can be removed to form the second trench 107 between the active pillars 1 in the third direction z. The first sacrificial layer 102 can be removed through the first isolation trench 103.

[0139] like Figure 5 As shown, in step S130 , a gate 4 is formed. The gate 4 surrounds the periphery of the structure formed by the active pillar 1 , the first insulating layer 2 and the second insulating layer 3 , and the orthographic projection of the gate 4 on the active pillar 1 at least partially overlaps with the channel region 12 .

[0140] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 16 As shown, there are multiple first isolation trenches 103. The multiple first isolation trenches 103 and second trenches 107 divide each first semiconductor layer 101 into multiple active pillars 1. All active pillars 1 spaced apart along the second direction y in the same layer form an active group 110. The number of active groups 110 can be multiple, and the multiple active groups 110 are spaced apart along the third direction z. The active group 110 includes multiple active pillars 1 spaced apart along the second direction y. The gates 4 surrounding the periphery of each active pillar 1 in the same active group 110 are connected together to form a word line 5. When there are multiple active groups 110, there are also multiple word lines 5. Each active group 110 can correspond to one word line 5, and the multiple word lines 5 can be spaced apart along the third direction z.

[0141] In the first exemplary embodiment of the present disclosure, since the first sacrificial layer 102 is located in the first region, the second region, and the third region of the transistor region A, after removing the first sacrificial layer 102, the first region to be doped corresponding to the first region, the channel region 12 corresponding to the second region, and the second region to be doped corresponding to the third region of the active pillar 1 can be exposed. Before forming the word line 5, a first isolation material can be deposited on each active pillar 1, the first insulating layer 2, and the second insulating layer 3 located in the transistor region A. The first isolation material can fill the gaps between each active pillar 1 distributed along the third direction z. The first isolation material can then be laterally etched to form a first isolation layer 40 that covers the second region to be doped of each active pillar 1, the first insulating layer 2 and the second insulating layer 3 on both sides of the second doped region, and fills the gaps between the second region to be doped of each active pillar 1 adjacent to each other in the third direction z, and the first insulating layer 2 and the second insulating layer 3 on both sides of the second doped region, as shown in FIG. Figure 17 and Figure 18 As shown. Subsequently, a gate oxide layer 41 can be formed on the exposed area (including the first area to be doped and the channel area 12) in the active pillar 1 (when the first insulating layer 2 and the second insulating layer 3 are formed on both sides of the active pillar 1, the gate oxide layer 41 can conformally surround the periphery of the structure formed by the active pillar 1, the first insulating layer 2 and the second insulating layer 3), forming a conductive material 420 that conformally covers the surface of each active pillar 1, the first insulating layer 2 and the second insulating layer 3 having the gate oxide layer 41. During the deposition process, the conductive material 420 can fill the first isolation trenches 103 between the active pillars 1 spaced apart along the second direction y. After the conductive material 420 is formed, the remaining space between the active pillars 1 along the third direction z can be filled with insulating material. As shown Figure 19 As shown, the gate oxide layer 41, the conductive material 420 and the insulating material can be laterally etched to expose the upper and lower surfaces of the portion of the active column 1 away from the storage structure area B (i.e., the first area to be doped), and the remaining conductive material 420 can be used as the word line 5, and the remaining insulating material can be used as the second isolation layer 50. Alternatively, the gate oxide layer 41 and the conductive material 420 can be etched to expose the upper and lower surfaces of the first area to be doped. Alternatively, the conductive material 420 can be etched to expose the side surface of the first area to be doped. In the above-mentioned process of laterally etching the gate oxide layer 41, the conductive material 420, and the insulating material, or in the process of laterally etching only the gate oxide layer 41 and the conductive material 420, the first insulating layer 2 and the second insulating layer 3 of the first area to be doped can also be etched. In an exemplary embodiment of the present disclosure, the word line 5 is formed along the trailing edge. Figure 17 The structure cut in the ee' direction is as follows Figure 20 shown.

[0142] In the first exemplary embodiment of the present disclosure, after forming the word line 5, the active pillar 1 (i.e., the first region to be doped) exposed in the region of the transistor region A away from the storage structure region B can be doped to form the first source and drain region 11. For example, the exposed region in the active pillar 1 can be ion doped by an ion implantation process; or, a doping material layer can be formed on the exposed region (e.g., the first region to be doped) in the active pillar 1, and then the doping ions in the doping material layer can be transferred to the active pillar 1 by heat treatment, and then the doping material layer can be removed. The doped first region to be doped in the active pillar 1 can be used as the first source and drain region 11, and the region directly below the word line 5 in the active pillar 1 can be used as the channel region 12. For example, the material of the doping material layer can be doped polysilicon. And after removing the doping material layer, insulating material can be filled between the first source and drain regions 11 distributed along the third direction z to form a third isolation layer 60, as shown in FIG. Figure 21 shown.

[0143] In the first exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include step S210 and step S220, wherein:

[0144] In step S210 , a bit line 7 is formed on one side of the active pillar 1 in the first direction x, and the bit line 7 is connected to the first source and drain regions 11 of the active pillars 1 distributed along the third direction z.

[0145] Please continue to see Figure 1-Figure 3 and Figure 21 As shown, in the first direction x, the bit line 7 is located on one side of the active pillar 1 and can be connected to the first source and drain regions 11 of each active pillar 1 distributed along the third direction z in different active groups 110. For example, the bit line 7 can be strip-shaped and can extend along the third direction z, and the bit line 7 can be in contact with and connected to the first source and drain regions 11. When each active group 110 includes multiple active pillars 1, the number of bit lines 7 is also multiple. The multiple bit lines 7 can be distributed at intervals along the second direction y, and each bit line 7 is respectively connected to each active pillar 1 located in a different column.

[0146] After forming the bit lines 7, the remaining second semiconductor layer 20 in the storage structure region B can be removed through capacitor trenches (not shown), thereby exposing the surface of the portion of the active pillar 1 located in the storage structure region B. The capacitor trenches penetrate each first semiconductor layer 101 and extend in a direction perpendicular to the first trenches 106. During the process of removing the second semiconductor layer 20, the first isolation layer 40 can serve as an etch stop layer.

[0147] The exposed surface of the active column 1 can be thinned through an etching process, and a doping material layer is formed on the surface of the thinned active column 1 in the storage structure area B. The doping material layer is heat treated, so that the doping ions in the doping material layer are diffused into the active column 1 exposed in the storage structure area B. At the same time, the doping ions are also laterally diffused into the second area to be doped covered by the first isolation layer 40. The second area to be doped in the active column 1 after this doping can be used as the second source and drain area 13.

[0148] In step S220 , a storage structure 8 is formed on a side of the active pillar 1 away from the bit line 7 in the first direction x. The storage structure 8 is connected to the second source and drain region 13 of the active pillar 1 .

[0149] like Figure 22 As shown, in the first direction x, the storage structure 8 is located on the side of the active pillar 1 away from the bit line 7, and is in contact with the second source and drain region 13 of the active pillar 1. The storage structure 8 may be strip-shaped and may extend along the first direction x. A storage structure 8 is provided at each end of each active pillar 1. In some embodiments of the present disclosure, the storage structure 8 may be a capacitor; the capacitor may include a lower electrode layer 81, a dielectric layer 82 and an upper electrode layer 83, wherein the lower electrode layer 81 covers the active pillar 1 connected to the second source and drain region 13, the dielectric layer 82 covers the lower electrode layer 81 and the first isolation layer 40 exposed by the lower electrode layer 81, and the upper electrode layer 83 covers the dielectric layer 82. In other embodiments, the lower electrode layer 81 of the capacitor may also be a tubular capacitor connected to the second source and drain region 13.

[0150] In other embodiments of the present disclosure, the capacitor can be replaced by other structures having the function of storing charge or other forms of information, such as a ferroelectric storage structure, or at least one of a resistive random access memory structure (RRAM), a magnetic random access memory structure (MRAM), and a phase change random access memory structure (PCRAM).

[0151] In the second embodiment of the present disclosure, since the first sacrificial layer 102 is located in the first region and the second region of the transistor region A, after removing the first sacrificial layer 102, the first to-be-doped region corresponding to the first region and the channel region 12 corresponding to the second region of the active pillar 1 can be exposed. The word line 5 can be formed on the exposed region (e.g., the first to-be-doped region and the channel region 12) of the active pillar 1, specifically including steps S310 to S340, wherein:

[0152] In step S310 , a gate oxide layer 41 is formed around the first to-be-doped region of the active pillar 1 , the channel region 12 , the first insulating layer 2 , and the second insulating layer 3 .

[0153] The material of the gate oxide layer 41 can be silicon oxide, please continue to refer to Figure 4As shown, a gate oxide layer 41 can be formed around the first region to be doped of the active pillar 1 and the periphery of the structure composed of the channel region 12, the first insulating layer 2, and the second insulating layer 3 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. It should be noted that the gate oxide layer 41 can only cover the surface of the first region to be doped and the channel region 12.

[0154] In step S320, a conductive material 420 is formed to conformally cover the first to-be-doped region and the channel region 12 of each active pillar 1 having the gate oxide layer 41, and the surfaces of the first insulating layer 2 and the second insulating layer 3 on both sides of the first to-be-doped region and the channel region 12. The conductive material 420 fills the first isolation trenches 103 between the first to-be-doped region and the channel region 12 of each active pillar 1 spaced apart along the second direction y.

[0155] The conductive material 420 may be a material with strong conductive properties, for example, the material may include tungsten, titanium nitride, molybdenum or rubidium. Figure 20 and Figure 23 As shown, a conductive material 420 can be deposited on the surface of the gate oxide layer 41 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and during the deposition process, the conductive material 420 can fill the first isolation trenches 103 between the active groups 110 distributed along the second direction y.

[0156] Step S330: forming an insulating material 70 to fill the remaining gaps between the active pillars 1 distributed along the third direction z. Figure 23 The insulating material may be silicon oxide, silicon nitride, silicon carbide nitride, aluminum oxide, polysilicon, silicon oxynitride or silicon carbide.

[0157] In step S340 , at least the conductive material 420 is laterally etched to form word lines 5 .

[0158] like Figure 24 As shown, after at least the conductive material 420 is laterally etched, the area of ​​the active pillar 1 away from the storage structure area B can be exposed (that is, the upper and lower surfaces of the first area to be doped are exposed). In other embodiments, the conductive material 420 can be laterally etched to retain the gate oxide layer 41. The retained gate oxide layer 41 can be used as an isolation layer. The conductive material 420 remaining after etching can be used as the word line 5, and the portion of the active pillar 1 directly below the word line 5 can be used as the channel region 12. In the above-mentioned process of laterally etching the gate oxide layer 41, the conductive material 420, and the insulating material, or in the process of laterally etching only the gate oxide layer 41 and the conductive material 420, the first insulating layer 2 and the second insulating layer 3 of the first area to be doped can also be etched.

[0159] The first region to be doped in the active pillar 1 can be doped through the upper surface, lower surface or side surface of the first region to be doped to form a first source and drain region 11. The specific doping process is similar to the doping process in the first embodiment, so it is not repeated here. After the first source and drain regions 11 are formed, the remaining space between the active pillars 1 can continue to be filled with insulating material. This portion of insulating material and the insulating material located between the word lines 5 can be collectively defined as a third insulating layer 6. In the second embodiment of the present disclosure, a bit line 7 can be formed after the third insulating layer 6 is formed. The formation process of the bit line 7 is similar to the above-mentioned step S210, so it is not repeated here.

[0160] After forming the bit lines 7, a dry etching process can be used to etch the active pillars 1 and the second semiconductor layer 20 located in the first region of the storage structure region B and the transistor region A to have the same size in the second direction as the active pillars 1 and the second semiconductor layer 20 in the second and third regions of the transistor region A. Thereafter, the remaining second semiconductor layer 20 can be removed, thereby exposing the second to-be-doped region of the active pillar 1, which will be used to form the second source and drain region 13 of the transistor, and the portion located in the storage structure region B. Subsequently, the exposed portion of the active pillar 1 can be thinned, and the thinned active pillar 1 can be doped, thereby converting the thinned second to-be-doped region into the second source and drain region 13.

[0161] Before doping the active pillars 1 to form the second source and drain regions 13, a fourth isolation layer 80 may be formed between the second to-be-doped regions in the active pillars 1 distributed along the third direction z. The specific position of the fourth isolation layer 80 is as follows: Figure 25 As shown. The fourth isolation layer 80 can prevent dopant ions from diffusing into the channel region 12 in the second region when doping the active pillar 1. Subsequently, a storage structure 8 can be formed on the surface of the portion of the active pillar 1 located above the storage structure region B. The specific structure and formation process of the storage structure 8 are similar to step S220 in the first exemplary embodiment and are therefore not further described here.

[0162] The present disclosure also provides an electronic device, which may include a processing device and a memory device electrically connected to the processing device, wherein the memory device includes the semiconductor structure of any of the above-described embodiments. Compared with the prior art, the electronic device provided by the present disclosure has the same beneficial effects as the semiconductor structure provided by the above-described exemplary embodiments, and thus is not further described here.

[0163] For example, the memory device may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Of course, other storage devices are also possible, which are not listed here. The electronic device may be a mobile phone, a tablet computer, a computer, etc.

[0164] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0165] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: An active pillar extending along a first direction, wherein the active pillar comprises a first source and drain region, a channel region, and a second source and drain region sequentially distributed along the first direction; A first insulating layer and a second insulating layer are respectively located at least on two sides of the channel region in a second direction; the second direction intersects the first direction; A gate surrounds the periphery of the structure formed by the active pillar, the first insulating layer and the second insulating layer, and an orthographic projection of the gate on the active pillar at least partially overlaps with the channel region.

2. The semiconductor structure according to claim 1, wherein: In the second direction, the width of the channel region is 30% to 60% of the sum of the width of the channel region, the width of the first insulating layer, and the width of the second insulating layer; and / or In the second direction, the first insulating layer and the second insulating layer have different widths; and / or The first insulating layer and the second insulating layer have different dielectric constants.

3. The semiconductor structure according to any one of claims 1 to 2, characterized in that: There are multiple active pillars, and the multiple active pillars form multiple active groups spaced apart along a third direction, where the third direction is perpendicular to the first direction and the second direction; the active group includes multiple active pillars spaced apart along the second direction, and the gates surrounding the periphery of each active pillar in the same active group are connected together to form a word line.

4. The semiconductor structure according to claim 3, wherein: There are a plurality of word lines, and a third insulating layer is provided between adjacent word lines.

5. The semiconductor structure according to claim 4, wherein: The semiconductor structure further comprises: a bit line located at one side of the active pillar in the first direction and connected to the first source and drain regions of the active pillars distributed along the third direction; The storage structure is located on a side of the active pillar away from the bit line in the first direction and is connected to the second source and drain region of the active pillar.

6. A method for forming a semiconductor structure, characterized in that: The forming method comprises: forming an active pillar, wherein the active pillar extends along a first direction and includes at least a channel region; forming a first insulating layer and a second insulating layer, wherein the first insulating layer and the second insulating layer are respectively located at least on two sides of the channel region in a second direction; the second direction intersects the first direction; A gate is formed, the gate surrounding the periphery of the structure formed by the active pillar, the first insulating layer and the second insulating layer, and an orthographic projection of the gate on the active pillar at least partially overlaps with the channel region.

7. The forming method according to claim 6, wherein: Forming the active pillar, the first insulating layer, and the second insulating layer includes: A stacked structure is formed on a substrate, the substrate including a transistor region, the transistor region including a first region, a second region, and a third region sequentially distributed along the first direction, the stacked structure including a plurality of first semiconductor layers and first sacrificial layers alternately distributed along a third direction, and a first isolation trench penetrating each of the first semiconductor layers and each of the first sacrificial layers, the first sacrificial layer being located at least in the first region and the second region, and the first isolation trench extending along the first direction; the third direction being perpendicular to the first direction and the second direction; Laterally etching the first semiconductor layer through the first isolation trench to reduce the width of the first semiconductor layer in the second direction to form a first recess and a second recess, respectively; the remaining first semiconductor layer forms the active pillar; Filling the first concave portion and the second concave portion with insulating materials, respectively, to form the first insulating layer and the second insulating layer in the first concave portion and the second concave portion, respectively; The first sacrificial layer is removed.

8. The forming method according to claim 6, wherein: In the second direction, the width of the channel region is 30% to 60% of the sum of the width of the channel region, the width of the first insulating layer, and the width of the second insulating layer.

9. The forming method according to claim 7, wherein: In the second direction, the first recess and the second recess have different depths; and / or The insulating material in the first recess is a first insulating material, and the insulating material in the second recess is a second insulating material. The first insulating material and the second insulating material have different dielectric constants.

10. The forming method according to claim 7, wherein: There are a plurality of first isolation trenches, each of which divides the first semiconductor layer into a plurality of active pillars. The plurality of active pillars form a plurality of active groups spaced apart along the third direction. The active groups include a plurality of active pillars spaced apart along the second direction. The gates surrounding the periphery of each active pillar in the same active group are connected together to form a word line. The forming of the word line comprises: forming a gate oxide layer surrounding an outer periphery of a structure formed by the active pillar, the first insulating layer, and the second insulating layer; forming a conductive material conformally covering a surface of each of the active pillars having the gate oxide layer, wherein the conductive material fills the first isolation trenches between the active pillars spaced apart along the second direction; forming an insulating material to fill remaining gaps between the active pillars distributed along the third direction; At least the conductive material is laterally etched to form the word lines.

11. The forming method according to claim 10, wherein: The first sacrificial layer is located in the first region, the second region, and the third region. The substrate further includes a storage structure region. The first isolation trench further extends to the storage structure region. A plurality of second semiconductor layers are formed on the storage structure region. In the third direction, the second semiconductor layers and the active pillars are alternately distributed. The portion of the active pillar located on the first region of the transistor region is a first region to be doped, the portion located on the second region is a channel region, and the portion located on the third region is a second region to be doped. Before forming the gate oxide layer, the forming method further includes: forming a first isolation layer covering the second to-be-doped region of each of the active pillars and filling a gap between the second to-be-doped regions of each of the active pillars adjacent in the third direction; the gate oxide layer covering the first to-be-doped region and the channel region; After at least laterally etching the conductive material to expose the first region to be doped, the forming method further includes: doping the first region to be doped to form a first source and drain region; removing the second semiconductor layer to expose a portion of the active pillar located in the storage structure region; doping the active pillar and the second region to be doped located in the storage structure region to form a second source and drain region in the second region to be doped; Optionally, forming the second source and drain region includes: forming a doping material layer on the surface of the active column located in the storage structure area, heat treating the doping material layer so that the doping ions in the doping material layer diffuse into the active column located in the storage structure area and the second area to be doped, and using the doped second area to be doped as the second source and drain region.

12. The forming method according to claim 10, wherein: The first sacrificial layer is located in the first region and the second region. The substrate further includes a storage structure region. The first isolation trench also extends to the storage structure region. A plurality of second semiconductor layers are formed on the third region and the storage structure region. In the third direction, the second semiconductor layers and the active pillars are alternately distributed. The portion of the active pillar located on the first region of the transistor region is a first region to be doped, the portion located on the second region is a channel region, and the portion located on the third region is a second region to be doped. The gate oxide layer covers the first region to be doped and the channel region; The forming method further comprises: After at least laterally etching the conductive material to expose the first region to be doped, the forming method further includes: doping the first region to be doped to form a first source and drain region; removing the second semiconductor layer to expose the second to-be-doped region in the active pillar and a portion of the active pillar located in a storage structure forming region; doping the second region to be doped to form a second source and drain region; Optionally, forming the second source and drain region includes: forming a doping material layer on the surface of the second region to be doped, heat treating the doping material layer so that the doping ions in the doping material layer diffuse into the second region to be doped, and using the doped second region to be doped as the second source and drain region.

13. The forming method according to claim 11 or 12, characterized in that: Before removing the second semiconductor layer, the forming method further includes: forming a bit line on one side of the active pillar in the first direction, wherein the bit line is connected to the first source and drain regions of the active pillars distributed along the third direction; After forming the second source and drain regions, the forming method further includes: A storage structure is formed on a side of the active pillar away from the bit line in the first direction, and the storage structure is connected to the second source and drain region of the active pillar.

14. An electronic device, characterized in that: A processing device is provided; and a memory device electrically connected to the processing device, wherein the memory device comprises the semiconductor structure according to any one of claims 1 to 5.

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