Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first region and a second region which are adjacent to each other; the floating gate structure is positioned on the substrate in the first region; the control gate structure is located on the floating gate structure, and the control gate structure and the floating gate structure are insulated from each other; the first dielectric layer is located on the surface of one side, facing the second region, of the floating gate structure and the control gate structure, and the width of the first dielectric layer located at the top of the floating gate structure is smaller than that of the first dielectric layer located at the bottom of the floating gate structure in the direction perpendicular to the side wall of the floating gate structure; and the erasing gate structure is positioned on the substrate in the second region. According to the embodiment of the invention, when voltage is applied to the erasure gate structure, leakage current is not easy to generate, and electrons in the floating gate structure can enter the erasure gate structure through the first dielectric layer close to the top position of the floating gate structure, so that the erasure efficiency of the semiconductor structure is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be primarily categorized into three main types: logic devices, memory devices, and analog circuits. Memory devices account for a significant proportion of integrated circuit products. With the advancement of semiconductor technology, the wider application of memory devices requires integrating these devices with other device areas on a single chip to form an embedded semiconductor memory device. For example, if a memory device is embedded within a central processing unit (CPU), it is necessary to ensure compatibility with the CPU platform and maintain the original memory device specifications and corresponding electrical performance.

[0003] Non-volatile memory (NVM) is a type of memory that retains on-chip information even after power is turned off. This includes electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory. NVM offers advantages such as system electrical erasability, reprogrammability, low operating voltage, and low cost, making it widely used in various fields, such as embedded systems (including PCs, network interconnect devices, and instrumentation) and emerging voice, image, and data storage products. Currently, flash memory has become the mainstream NVM.

[0004] However, the performance of flash memory still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region adjacently arranged; a floating gate structure located on the substrate in the first region; a control gate structure located on the floating gate structure, the control gate structure and the floating gate structure being insulated from each other; a first dielectric layer located on a surface of the floating gate structure and the control gate structure facing the second region, wherein the width of the first dielectric layer at the top of the floating gate structure is smaller than the width of the first dielectric layer at the bottom of the floating gate structure along a direction perpendicular to the sidewalls of the floating gate structure; and an erase gate structure located on the substrate in the second region.

[0007] Accordingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region adjacently arranged, a floating gate structure being formed on the substrate in the first region, a control gate structure being formed on the floating gate structure, and the control gate structure being insulated from the floating gate structure; forming a first dielectric layer on the surface of the floating gate structure and the control gate structure facing the second region, wherein the width of the first dielectric layer at the top of the floating gate structure is smaller than the width of the first dielectric layer at the bottom of the floating gate structure in a direction perpendicular to the sidewalls of the floating gate structure; and forming an erase gate structure on the substrate in the second region.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] A semiconductor structure provided by an embodiment of the present invention includes a first dielectric layer located on a surface of the floating gate structure and the control gate structure facing the second region. In a direction perpendicular to the sidewalls of the floating gate structure, the width of the first dielectric layer at the top of the floating gate structure is smaller than the width of the first dielectric layer at the bottom of the floating gate structure. Specifically, the width of the first dielectric layer near the top of the floating gate structure is smaller, while the width of the first dielectric layer near the bottom of the floating gate structure is larger. Because the width of the first dielectric layer near the bottom of the floating gate structure is larger, when a voltage is applied to the erase gate structure, electrons or electron holes trapped by defects in the substrate due to various factors are less likely to move from the substrate into the erase gate structure through electrical motion, thereby reducing leakage current and improving the performance of the semiconductor structure. Furthermore, the width of the first dielectric layer near the top of the floating gate structure is smaller. When a voltage is applied to the erase gate structure, electrons in the floating gate structure are more likely to enter the erase gate structure through the first dielectric layer near the top of the floating gate structure, thereby improving the erase efficiency of the semiconductor structure and further improving the performance of the semiconductor structure.

[0010] In a method for forming a semiconductor structure provided by an embodiment of the present invention, a first dielectric layer is formed on the surface of the floating gate structure and the control gate structure facing the second region. In a direction perpendicular to the sidewalls of the floating gate structure, the width of the first dielectric layer at the top of the floating gate structure is smaller than the width of the first dielectric layer at the bottom of the floating gate structure. That is, the width of the first dielectric layer near the top of the floating gate structure is smaller, while the width of the first dielectric layer near the bottom of the floating gate structure is larger. Because the width of the first dielectric layer near the bottom of the floating gate structure is larger, when a voltage is applied to the erase gate structure, electrons or electron holes trapped by defects in the substrate due to various factors are less likely to move from the substrate into the erase gate structure through electrical motion, thereby reducing the generation of leakage current and improving the performance of the semiconductor structure. Furthermore, the width of the first dielectric layer near the top of the floating gate structure is smaller. When a voltage is applied to the erase gate structure, electrons in the floating gate structure are more likely to enter the erase gate structure through the first dielectric layer near the top of the floating gate structure, thereby improving the erase efficiency of the semiconductor structure and further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural diagram of a semiconductor structure;

[0012] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figures 3 to 12 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0014] Currently, the performance of semiconductor structures still needs to be improved. This article analyzes the reasons why the performance of semiconductor structures needs to be improved by combining a semiconductor structure. Figure 1 It is a structural diagram of a semiconductor structure.

[0015] refer to Figure 1 The semiconductor structure includes: a substrate 10, the substrate 10 including a first region i′ and a second region ii′ arranged adjacent to each other; a floating gate structure 11 located on the substrate 10 in the first region i′; a control gate structure 12 located on the floating gate structure 11, and the control gate structure 12 is insulated from the floating gate structure 11; a first dielectric layer 13 located on the surface of the floating gate structure 11 and the control gate structure 12 facing the second region ii′; and an erase gate structure 14 located on the substrate 10 in the second region ii′.

[0016] Research has found that due to various factors (such as material properties, manufacturing process, etc.), there are usually certain defects in the substrate 10, and these defects often capture some electrons or electron holes. When voltage is applied to the erase gate structure 14, these electrons or electron holes captured by the defects will generate electrical movement and enter the erase gate structure 14 from the substrate 10 through the first dielectric layer 13, thereby generating leakage current, which in turn affects the performance of the semiconductor structure; however, increasing the width of the first dielectric layer 13 will affect the speed at which electrons enter the erase gate structure 14 from the floating gate structure 11, thereby affecting the erase efficiency of the semiconductor structure, and thus easily affecting the performance of the semiconductor structure.

[0017] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region adjacently arranged; a floating gate structure located on the substrate in the first region; a control gate structure located on the floating gate structure, the control gate structure and the floating gate structure being insulated from each other; a first dielectric layer located on a surface of the floating gate structure and the control gate structure facing the second region, wherein a width of the first dielectric layer at a top position of the floating gate structure, along a direction perpendicular to a sidewall of the floating gate structure, is smaller than a width of the first dielectric layer at a bottom position of the floating gate structure; and an erase gate structure located on the substrate in the second region.

[0018] A semiconductor structure provided by an embodiment of the present invention includes a first dielectric layer located on a surface of the floating gate structure and the control gate structure facing the second region. In a direction perpendicular to the sidewalls of the floating gate structure, the width of the first dielectric layer at the top of the floating gate structure is smaller than the width of the first dielectric layer at the bottom of the floating gate structure. Specifically, the width of the first dielectric layer near the top of the floating gate structure is smaller, while the width of the first dielectric layer near the bottom of the floating gate structure is larger. Because the width of the first dielectric layer near the bottom of the floating gate structure is larger, when a voltage is applied to the erase gate structure, electrons or electron holes trapped by defects in the substrate due to various factors are less likely to move from the substrate into the erase gate structure through electrical motion, thereby reducing leakage current and improving the performance of the semiconductor structure. Furthermore, the width of the first dielectric layer near the top of the floating gate structure is smaller. When a voltage is applied to the erase gate structure, electrons in the floating gate structure are more likely to enter the erase gate structure through the first dielectric layer near the top of the floating gate structure, thereby improving the erase efficiency of the semiconductor structure and further improving the performance of the semiconductor structure.

[0019] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0020] Figure 2 FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

[0021] refer to Figure 2 In this embodiment, the semiconductor structure includes: a substrate 100, wherein the substrate 100 includes a first region i and a second region ii arranged adjacent to each other; a floating gate structure 110, located on the substrate 100 in the first region i; a control gate structure 120, located on the floating gate structure 110, and the control gate structure 120 is insulated from the floating gate structure 110; a first dielectric layer 140, located on the surface of the floating gate structure 110 and the control gate structure 120 facing the second region ii, along a direction perpendicular to the sidewall of the floating gate structure 110, a width w1 of the first dielectric layer 140 at the top position of the floating gate structure 110 is smaller than a width w2 of the first dielectric layer 140 at the bottom position of the floating gate structure 110; and an erase gate structure 170, located on the substrate 100 in the second region ii.

[0022] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0023] In this embodiment, the substrate 100 is used to form a MOS transistor and constitute a non-volatile memory.

[0024] Specifically, the non-volatile memory includes an electrically programmable read-only memory, an electrically erasable programmable read-only memory, a flash memory, etc. In this embodiment, the non-volatile memory is described as a flash memory.

[0025] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0026] As an example, the substrate 100 is a planar substrate. In other embodiments, the substrate may also be a substrate having a channel-convex structure.

[0027] In this embodiment, the substrate 100 further includes a third region iii disposed adjacent to the first region i. The third region iii is located on a side of the first region i facing away from the second region ii.

[0028] The first region i, the second region ii and the third region iii constitute a storage cell region (not labeled). The storage cell region refers to the portion of the substrate 100 used to store data, usually used to form a storage cell. The storage cell region usually has a specific storage cell structure and circuit design to meet data storage requirements.

[0029] As an example, in the same memory cell area, the number of the first area i and the number of the third area iii are both 2, and the number of the second area ii is 1. In other embodiments, the number of the first area, the second area, and the third area can all be 1, or can all be multiple.

[0030] The floating gate structure 110 can capture and store electrons, and after power is lost, the electrons stored in the floating gate structure 110 will not be lost, thereby achieving information storage.

[0031] In this embodiment, the floating gate structure 110 includes a gate dielectric layer 111 located on the first region i-substrate 100 , and a floating gate layer 112 located on the gate dielectric layer 111 .

[0032] The gate dielectric layer 111 serves as a tunnel oxide layer of the flash memory, and is used to achieve electrical isolation between the floating gate layer 112 and the substrate 100 , thereby allowing electrons to enter the floating gate layer 112 through the gate dielectric layer 111 by utilizing the tunneling effect.

[0033] It should be noted that the gate dielectric layer 111 is made of silicon oxide. In other embodiments, the gate dielectric layer may also be made of other dielectric materials.

[0034] It should also be noted that the material of the floating gate layer 112 includes polysilicon.

[0035] In this embodiment, the sidewall of the floating gate structure 110 facing the second region ii protrudes from the control gate structure 120 , so that the floating gate structure 110 has a protruding portion 115 .

[0036] The side wall of the floating gate structure 110 toward the second region ii protrudes from the control gate structure 120, so that the floating gate structure 110 has a protrusion 115. When erasing, under the condition of the same voltage, the electric field strength at the top corner of the protrusion 115 is larger, and electrons can more easily enter the erase gate structure 170 from the floating gate structure 110, which is beneficial to improving the erasing speed and correspondingly improving the erasing performance.

[0037] It should be noted that the width w3 of the protrusion 115, along a direction perpendicular to the sidewalls of the floating gate structure 110, should not be too small or too large. If the width w3 of the protrusion 115 is too small, it will increase the difficulty of forming the control gate structure 120. If the width w3 of the protrusion 115 is too large, the overall size of the floating gate structure 110 will be too large, thereby affecting the development of high-integration semiconductor structures. Therefore, in this embodiment, the width w3 of the protrusion 115, along a direction perpendicular to the sidewalls of the floating gate structure 110, ranges from 300 angstroms to 500 angstroms.

[0038] The control gate structure 120 is used to allow electrons to enter the floating gate structure 110 during data writing. When reading data, an operating voltage is applied to the control gate structure 120, and the charged state of the floating gate structure 110 is used to control the on / off state of the channel region at the bottom of the floating gate structure 110.

[0039] In this embodiment, the control gate structure 120 includes an inter-gate dielectric layer 121 located on the floating gate structure 110 , and a control gate electrode layer 122 located on the inter-gate dielectric layer 121 .

[0040] The inter-gate dielectric layer 121 is used to isolate the floating gate structure 110 from the control gate electrode layer 122 , and accordingly insulates the control gate structure 120 from the floating gate structure 110 .

[0041] It should be noted that the material of the inter-gate dielectric layer 121 is a dielectric material. As an example, the inter-gate dielectric layer 121 has an ONO (Oxide-Nitride-Oxide) structure, that is, the inter-gate dielectric layer 121 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence from bottom to top.

[0042] It should also be noted that the material of the control gate electrode layer 122 includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide. As an example, the material of the control gate electrode layer 122 is polysilicon.

[0043] In this embodiment, the semiconductor structure further includes a spacer layer 130 located on the sidewall of the control gate structure 120 .

[0044] The spacer layer 130 is used to protect the sidewalls of the control gate structure 120 and can also be used to define the position of the drain region.

[0045] It should be noted that the material of the spacer layer 130 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.

[0046] Specifically, the spacer layer 130 is a stacked structure, including a first sub-spacer layer 131 located on the sidewall of the control gate structure 120, and a second sub-spacer layer 132 covering the first sub-spacer layer 131. As an example, the material of the first sub-spacer layer 131 is silicon nitride, and the material of the second sub-spacer layer 132 is silicon oxide.

[0047] In other embodiments, the sidewall spacer may also be a single-layer structure.

[0048] In this embodiment, the semiconductor structure further includes: a drain region (not shown), located in the substrate 100 in the third region iii; and a source region, located in the substrate 100 in the second region ii.

[0049] The drain region and the source region are used to provide a carrier source when the MOS transistor is working.

[0050] As an example, in the same memory cell region, the number of the first region i and the number of the third region iii are both 2, and the number of the second region ii is 1, that is, the source region is shared in the same memory cell region.

[0051] The first dielectric layer 140 is located on the surface of the floating gate structure 110 and the control gate structure 120 facing the second region ii. Along the direction perpendicular to the sidewall of the floating gate structure 110, the width w1 of the first dielectric layer 140 located at the top of the floating gate structure 110 is smaller than the width w2 of the first dielectric layer 140 located at the bottom of the floating gate structure 110. That is, the width of the first dielectric layer 140 near the top of the floating gate structure 110 is smaller, and the width of the first dielectric layer 140 near the bottom of the floating gate structure 110 is larger. Since the width of the first dielectric layer 140 near the bottom of the floating gate structure 110 is relatively large, when a voltage is applied to the erase gate structure 170, it is difficult for electrons or electron holes captured by defects in the substrate 100 due to various factors to enter the erase gate structure 170 from the substrate 100 through electrical movement, so leakage current is not easily generated, thereby improving the performance of the semiconductor structure; moreover, the width of the first dielectric layer 140 near the top of the floating gate structure 110 is relatively small. When a voltage is applied to the erase gate structure 170, it is easy for electrons in the floating gate structure 110 to enter the erase gate structure 170 through the first dielectric layer 140 near the top of the floating gate structure 110, thereby improving the erase efficiency of the semiconductor structure and further improving the performance of the semiconductor structure.

[0052] It should be noted that the width w1 of the first dielectric layer 140 at the top of the floating gate structure 110, along a direction perpendicular to the sidewalls of the floating gate structure 110, should not be too small or too large. If the width w1 of the first dielectric layer 140 at the top of the floating gate structure 110 is too small, it will easily increase the difficulty of forming the first dielectric layer 140; if the width w1 of the first dielectric layer 140 at the top of the floating gate structure 110 is too large, it will easily lead to poor results in improving erase efficiency. Therefore, in this embodiment, the width w1 of the first dielectric layer 140 at the top of the floating gate structure 110, along a direction perpendicular to the sidewalls of the floating gate structure 110, is in a range of 60 angstroms to 100 angstroms.

[0053] It should also be noted that the width w2 of the first dielectric layer 140 at the bottom of the floating gate structure 110, along a direction perpendicular to the sidewalls of the floating gate structure 110, should not be too small or too large. If the width w2 of the first dielectric layer 140 at the bottom of the floating gate structure 110 is too small, it may be less effective in reducing the amount of electrons or electron holes that enter the erase gate structure 170 from the substrate 100 through electrical motion. If the width w2 of the first dielectric layer 140 at the bottom of the floating gate structure 110 is too large, it may affect the quality of the erase gate structure 170. Therefore, in this embodiment, the width w2 of the first dielectric layer 140 at the bottom of the floating gate structure 110, along a direction perpendicular to the sidewalls of the floating gate structure 110, ranges from 140 angstroms to 230 angstroms.

[0054] In this embodiment, the interface between the first dielectric layer 140 covering the sidewalls of the floating gate structure 110 and the erase gate structure 170 is in a stepped or sloped shape.

[0055] The steps for forming the first dielectric layer 140 generally include: forming a first dielectric material layer (not shown) on the substrate 100 in the second region ii, the first dielectric material layer covering the surface of the floating gate structure 110 and the control gate structure 120 facing the second region ii; forming a top recess (not shown) in the first dielectric material layer located above the top of the floating gate structure 110, and forming a bottom recess (not shown) in the first dielectric material layer located on the side of the floating gate structure 110 in the second region ii, wherein the sidewalls of the bottom recess are stepped or sloped, and the remaining first dielectric material layer exposed by the bottom recess and the top recess serves as the first dielectric layer 140. Since the top recess is located above the top of the floating gate structure 110 and the bottom recess is located on the side of the floating gate structure 110, it can be understood that the top recess and the bottom recess are interconnected and together constitute a recess (not shown), which serves as the first recess. Since the sidewalls of the bottom groove are stepped or sloped, the groove surface is stepped or sloped accordingly, that is, the interface between the first dielectric layer 140 covering the sidewalls of the floating gate structure 110 and the erase gate structure 170 is stepped or sloped.

[0056] Specifically, the steps of forming the groove generally include: forming a top groove in the first dielectric material layer in the second region ii, located above the top of the floating gate structure 110; and forming a bottom groove in the first dielectric material layer, via the top groove, located on the side of the floating gate structure 110. In other words, a bottom groove having stepped or sloped sidewalls is formed via the top groove.

[0057] In other embodiments, when the floating gate structure does not have a protrusion, that is, the side wall of the floating gate structure facing the second region is flush with the side wall of the control gate structure facing the second region, the bottom of the top groove can be flush with the top of the floating gate structure, or lower than the top of the floating gate structure.

[0058] In this embodiment, a chemical vapor deposition process is typically used to form the first dielectric material layer, which is a high-temperature oxide (HTO) material. HTO has the characteristics of high film quality and good quality uniformity, which helps improve the quality of the first dielectric layer 140. Accordingly, the first dielectric layer 140 is also a high-temperature oxide material.

[0059] In a specific embodiment, the interface between the first dielectric layer 140 covering the sidewalls of the floating gate structure 110 and the erase gate structure 170 is stepped, including a first sidewall layer 147 covering a portion of the sidewalls at the bottom of the floating gate structure 110, and a second sidewall layer 146 covering the remaining sidewalls of the floating gate structure 110.

[0060] The interface between the first dielectric layer 140 covering the sidewalls of the floating gate structure 110 and the erase gate structure 170 is stepped, i.e., the surface of the groove is stepped. It is generally necessary to etch back the first dielectric material layer in a portion of the second region ii to form a groove located in the first dielectric material layer and having a stepped surface. The step of etching back the first dielectric material layer in a portion of the second region ii includes: etching back the first dielectric material layer multiple times from top to bottom along the thickness direction of the first dielectric material layer, and when etching the first dielectric material layer located on the side of the floating gate structure 110 in the second region ii, the etched area of ​​the subsequent etch back is located within the etched area of ​​the previous etch back. This facilitates the stepped surface of the groove, thereby further reducing the difficulty of forming the first dielectric layer 140.

[0061] It should be noted that, along the normal direction of the top surface of the substrate 100, the ratio of the height h2 of the first sidewall layer 147 to the height h1 of the second sidewall layer 146 should not be too small or too large. If the ratio of the height h2 of the first sidewall layer 147 to the height h1 of the second sidewall layer 146 is too small, it is easy to increase the difficulty of forming the first sidewall layer 147 and it is also easy to reduce the effect of electrons or electron holes entering the erase gate structure 170 from the substrate 100 through electrical movement. If the ratio of the height h2 of the first sidewall layer 147 to the height h1 of the second sidewall layer 146 is too large, it is easy to increase the difficulty of forming the second sidewall layer 146. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 100, the ratio of the height h2 of the first sidewall layer 147 to the height h1 of the second sidewall layer 146 ranges from 1.2:1 to 1:1.2.

[0062] As an example, the first dielectric layer 140 covering the sidewalls of the floating gate structure 110 includes a first sidewall layer 147 covering a portion of the sidewall at the bottom of the floating gate structure 510, and a second sidewall layer 146 covering the remaining sidewalls of the floating gate structure. The width of the second sidewall layer 146 is smaller than the width of the first sidewall layer 147. The width of the second sidewall layer 516 is the same at all locations, and the width of the first sidewall layer 147 is the same at all locations. In other embodiments, the width of the second sidewall layer 146 may also be different at all locations.

[0063] In this embodiment, the first dielectric layer 140 is also located on the substrate 100 in the second region ii; the erase gate structure 170 also covers the first dielectric layer 140 located on the substrate 100 in the second region ii.

[0064] The first dielectric layer 140 is also located on the substrate 100 in the second region ii, so that the erase gate structure 170 also covers the first dielectric layer 140 located on the substrate 100 in the second region ii. The first dielectric layer 140 located on the substrate 100 in the second region ii can isolate the erase gate structure 170 from the substrate 100, thereby simplifying the process steps for forming the erase gate structure 170.

[0065] In this embodiment, the substrate 100 further includes a third region iii adjacent to the first region i, the third region iii being located on the side of the first region i facing away from the second region ii. Accordingly, the first dielectric layer 140 is also located on the substrate 100 in the third region iii.

[0066] In this embodiment, the second dielectric layer 160 is located on the sidewall of the floating gate structure 110 facing away from the second region ii.

[0067] It should be noted that the second dielectric layer 160 is made of a high temperature oxide material.

[0068] Specifically, the second dielectric layer 160 also covers the first dielectric layer 140 and the spacer layer 130 .

[0069] As an example, the thickness of the second dielectric layer 160 on the substrate 100 in the third region iii is less than that on the substrate 100 in the second region ii. In other embodiments, the thickness of the second dielectric layer on the substrate in the third region may be equal to that on the substrate in the second region.

[0070] The erase gate structure 170 is used to apply a high voltage to the erase gate structure 170 during data erasure, so that there is a potential difference between the erase gate structure 170 and the floating gate structure 110, so that electrons in the floating gate structure 110 can be pulled into the erase gate structure 170 through the tunneling effect, thereby achieving data erasure.

[0071] As an example, the material of the erase gate structure 170 includes polysilicon.

[0072] Accordingly, the erase gate structure 170 is also located on the protrusion 115 .

[0073] In this embodiment, the semiconductor structure further includes a word line structure 180 located on the substrate 100 in the third region iii.

[0074] The word line structure 180 is used to determine the memory cells to be edited.

[0075] The word line structure 180 can be formed in the same step as the erase gate structure 170. As an example, the material of the erase gate structure 170 includes polysilicon, and accordingly, the material of the word line structure 180 also includes polysilicon.

[0076] Correspondingly, the word line structure 180 also covers the first dielectric layer 140 located on the third region iii of the substrate 100 .

[0077] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 12 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0078] refer to Figure 3 A substrate 500 is provided, the substrate 500 includes a first region I and a second region II arranged adjacent to each other, a floating gate structure 510 is formed on the substrate 500 in the first region I, a control gate structure 520 is formed on the floating gate structure 510, and the control gate structure 520 is insulated from the floating gate structure 510.

[0079] The substrate 500 is used to provide a process platform for subsequent process steps.

[0080] In this embodiment, the substrate 500 is used to form MOS transistors and constitute a non-volatile memory.

[0081] Specifically, the non-volatile memory includes an electrically programmable read-only memory, an electrically erasable programmable read-only memory, a flash memory, etc. In this embodiment, the non-volatile memory is described as a flash memory.

[0082] In this embodiment, the material of the substrate 500 is silicon. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0083] As an example, the substrate 500 is a planar substrate. In other embodiments, the substrate may also be a substrate having a channel-convex structure.

[0084] In this embodiment, in the step of providing the substrate 500 , the substrate 500 further includes a third region III disposed adjacent to the first region I, and the third region III is located on a side of the first region I facing away from the second region II.

[0085] The first region I, the second region II and the third region III constitute a storage cell region (not labeled). The storage cell region refers to the portion of the substrate 500 used to store data, usually used to form a storage cell. The storage cell region usually has a specific storage cell structure and circuit design to meet data storage requirements.

[0086] As an example, in the same memory cell area, the number of the first area I and the number of the third area III are both 2, and the number of the second area II is 1. In other embodiments, the number of the first area, the second area, and the third area can all be 1, or can all be multiple.

[0087] The floating gate structure 510 can capture and store electrons, and after power is lost, the electrons stored in the floating gate structure 510 will not be lost, thereby achieving information storage.

[0088] In this embodiment, the floating gate structure 510 includes a gate dielectric layer 511 located on the substrate 500 in the first region I, and a floating gate layer 512 located on the gate dielectric layer 511 .

[0089] The gate dielectric layer 511 serves as a tunneling oxide layer of the flash memory, and is used to achieve electrical isolation between the floating gate layer 512 and the substrate 500 , thereby utilizing the tunneling effect to allow electrons to enter the floating gate layer 512 through the gate dielectric layer 511 .

[0090] It should be noted that the gate dielectric layer 511 is made of silicon oxide. In other embodiments, the gate dielectric layer may also be made of other dielectric materials.

[0091] It should also be noted that the material of the floating gate layer 512 includes polysilicon.

[0092] In this embodiment, in the step of providing the substrate 500 , the sidewall of the floating gate structure 510 toward the second region II protrudes from the control gate structure 520 , so that the floating gate structure 510 has a protruding portion 515 .

[0093] The side wall of the floating gate structure 510 toward the second region II protrudes from the control gate structure 520, so that the floating gate structure 510 has a protrusion 515. When erasing, under the condition of the same voltage, the electric field strength at the top corner of the protrusion 515 is larger, and electrons can more easily enter the subsequently formed erase gate structure from the floating gate structure 510, which is beneficial to improving the erase speed and correspondingly improving the erase performance.

[0094] It should be noted that the width W3 of the protrusion 515, along a direction perpendicular to the sidewalls of the floating gate structure 510, should not be too small or too large. If the width W3 of the protrusion 515 is too small, it will increase the difficulty of forming the control gate structure 520. If the width W3 of the protrusion 515 is too large, the overall size of the floating gate structure 510 will be too large, thereby affecting the development of high-integration semiconductor structures. Therefore, in this embodiment, the width W3 of the protrusion 515, along a direction perpendicular to the sidewalls of the floating gate structure 510, ranges from 300 angstroms to 500 angstroms.

[0095] The control gate structure 520 is used to allow electrons to enter the floating gate structure 510 during the data writing process. When reading data, an operating voltage is applied to the control gate structure 520, and the charged state of the floating gate structure 510 is used to control the on / off state of the channel region at the bottom of the floating gate structure 510.

[0096] In this embodiment, the control gate structure 520 includes an inter-gate dielectric layer 521 located on the floating gate structure 510 and a control gate electrode layer 522 located on the inter-gate dielectric layer 521 .

[0097] The inter-gate dielectric layer 521 is used to isolate the floating gate structure 510 from the control gate electrode layer 522 , and accordingly insulates the control gate structure 520 from the floating gate structure 510 .

[0098] It should be noted that the material of the inter-gate dielectric layer 521 is a dielectric material. As an example, the inter-gate dielectric layer 521 has an ONO (Oxide-Nitride-Oxide) structure, that is, the inter-gate dielectric layer 521 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence from bottom to top.

[0099] It should also be noted that the material of the control gate electrode layer 522 includes one or more of polysilicon, titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide. As an example, the material of the control gate electrode layer 522 is polysilicon.

[0100] In this embodiment, in the step of providing the substrate 500 , a buffer layer 524 and a gate mask layer 525 stacked vertically in sequence are further formed on the top of the control gate structure 520 .

[0101] Here, the longitudinal direction refers to the normal direction along the top surface of the substrate 500.

[0102] The buffer layer 524 has good adhesion to the gate mask layer 525, and also has good adhesion to the control gate structure 520. Furthermore, the buffer layer 524 is used to provide a stress buffering effect when forming the gate mask layer 525, thereby improving the problem of dislocations generated when forming the gate mask layer 525.

[0103] The gate mask layer 525 is used as an etching mask for forming the control gate structure 520 and is also used to protect the top of the control gate structure 520 .

[0104] As an example, the material of the buffer layer 524 includes silicon oxide, and the material of the gate mask layer 525 includes silicon nitride. In other embodiments, the material of the buffer layer may also include other materials with good adhesion and stress buffering properties; the gate mask layer may also include silicon oxynitride, silicon carbide, or boron nitride.

[0105] In this embodiment, in the step of providing the substrate 500 , a spacer layer 530 is formed on the sidewall of the control gate structure 520 .

[0106] The spacer layer 530 is used to protect the sidewalls of the control gate structure 520 and can also be used to define the position of the drain region.

[0107] It should be noted that the material of the spacer layer 530 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.

[0108] Specifically, the spacer layer 530 is a stacked structure, including a first sub-spacer layer 531 located on the sidewall of the control gate structure 520, and a second sub-spacer layer 532 covering the first sub-spacer layer 531. As an example, the material of the first sub-spacer layer 531 is silicon nitride, and the material of the second sub-spacer layer 532 is silicon oxide.

[0109] In other embodiments, the sidewall spacer may also be a single-layer structure.

[0110] In this embodiment, in the step of providing the substrate 500 , a drain region (not shown) is further formed in the substrate 500 in the third region III.

[0111] The drain region and the subsequently formed source region are used to provide a carrier source when the MOS transistor is working.

[0112] refer to Figures 4 to 9 A first dielectric layer 540 is formed on the surface of the floating gate structure 510 and the control gate structure 520 facing the second region II. In a direction perpendicular to the sidewall of the floating gate structure 510, the width W1 of the first dielectric layer 540 at the top of the floating gate structure 510 is smaller than the width W2 of the first dielectric layer 540 at the bottom of the floating gate structure 510 (e.g., Figures 8 and 9 shown).

[0113] in, Figure 9 for Figure 8 A partial enlarged view of area A.

[0114] A first dielectric layer 540 is formed on the surface of the floating gate structure 510 and the control gate structure 520 facing the second region II. Along the direction perpendicular to the sidewall of the floating gate structure 510, the width W1 of the first dielectric layer 540 located at the top of the floating gate structure 510 is smaller than the width W2 of the first dielectric layer 540 located at the bottom of the floating gate structure 510. That is, the width of the first dielectric layer 540 near the top of the floating gate structure 510 is smaller, and the width of the first dielectric layer 540 near the bottom of the floating gate structure 510 is larger. Since the width of the first dielectric layer 540 near the bottom of the floating gate structure 510 is relatively large, when a voltage is applied to the erase gate structure, electrons or electron holes captured by defects in the substrate 500 due to various factors are difficult to enter the erase gate structure from the substrate 500 through electrical movement, so leakage current is not easily generated, thereby improving the performance of the semiconductor structure; moreover, the width of the first dielectric layer 540 near the top of the floating gate structure 510 is relatively small. When a voltage is applied to the erase gate structure, it is easy for electrons in the floating gate structure 510 to enter the erase gate structure through the first dielectric layer 540 near the top of the floating gate structure 510, thereby improving the erase efficiency of the semiconductor structure and further improving the performance of the semiconductor structure.

[0115] It should be noted that the width W1 of the first dielectric layer 540 at the top of the floating gate structure 510, along a direction perpendicular to the sidewalls of the floating gate structure 510, should not be too small or too large. If the width W1 of the first dielectric layer 540 at the top of the floating gate structure 510 is too small, it will easily increase the difficulty of forming the first dielectric layer 540; if the width W1 of the first dielectric layer 540 at the top of the floating gate structure 510 is too large, it will easily lead to poor results in improving erase efficiency. Therefore, in this embodiment, the width W1 of the first dielectric layer 540 at the top of the floating gate structure 510, along a direction perpendicular to the sidewalls of the floating gate structure 510, ranges from 60 angstroms to 100 angstroms.

[0116] It should also be noted that the width W2 of the first dielectric layer 540 at the bottom of the floating gate structure 510, along a direction perpendicular to the sidewalls of the floating gate structure 510, should not be too small or too large. If the width W2 of the first dielectric layer 540 at the bottom of the floating gate structure 510 is too small, it may be less effective in reducing the amount of electrons or electron holes that enter the erase gate structure from the substrate 500 through electrical motion. If the width W2 of the first dielectric layer 540 at the bottom of the floating gate structure 510 is too large, it may affect the quality of the erase gate structure subsequently formed. Therefore, in this embodiment, the width W2 of the first dielectric layer 540 at the bottom of the floating gate structure 510, along a direction perpendicular to the sidewalls of the floating gate structure 510, ranges from 140 angstroms to 230 angstroms.

[0117] In this embodiment, the steps of forming the first dielectric layer 540 include: Figure 4 As shown, a first dielectric material layer 545 is formed on the substrate 500 in the second region II. The first dielectric material layer 545 covers the surface of the floating gate structure 510 and the control gate structure 520 facing the second region II. Figures 5 to 9 As shown, in the second region II, a top groove 541 is formed in the first dielectric material layer 545 and is located above the top of the floating gate structure 510, and a bottom groove 542 is formed in the first dielectric material layer 545 and is located on the side of the floating gate structure 510. The sidewall of the bottom groove 542 is stepped or sloped, and the remaining first dielectric material layer 545 exposed by the bottom groove 542 and the top groove 541 serves as the first dielectric layer 540.

[0118] First, a first dielectric material layer 545 is formed on the substrate 500 in the second region II, covering the surface of the floating gate structure 510 and the control gate structure 520 facing the second region II. Then, a top groove 541 located above the top of the floating gate structure 510 and a bottom groove 542 located on the side of the floating gate structure 510 are formed in the first dielectric material layer 545. The remaining first dielectric material layer 545 exposed by the bottom groove 542 and the top groove 541 serves as the first dielectric layer 540, which helps to reduce the difficulty of forming the first dielectric layer 540.

[0119] Since the top groove 541 is located above the top of the floating gate structure 510 and the bottom groove 542 is located on the side of the floating gate structure 510, it can be understood that the top groove 541 and the bottom groove 542 are interconnected and together form a groove 543, which serves as a first groove. Since the sidewall of the bottom groove 542 is stepped or sloped, the surface of the groove 543 is correspondingly stepped or sloped.

[0120] Specifically, the step of forming the groove 543 includes: forming a top groove 541 (eg, a groove 542) located above the top of the floating gate structure 510 in the first dielectric material layer 545 in the second region II; Figure 6 via the top groove 541 (as shown); Figure 7 As shown), a bottom groove 542 (as shown) located at the side of the floating gate structure 510 is formed in the first dielectric material layer 545. Figure 8 and Figure 9 That is, the top groove 541 forms a bottom groove 542 with a stepped or sloped sidewall.

[0121] In other embodiments, when the floating gate structure does not have a protrusion, that is, the side wall of the floating gate structure facing the second region is flush with the side wall of the control gate structure facing the second region, the bottom of the top groove can be flush with the top of the floating gate structure, or lower than the top of the floating gate structure.

[0122] In this embodiment, the process for forming the first dielectric material layer 545 includes a chemical vapor deposition process. The first dielectric material layer 545 is a high temperature oxide material. HTO has the characteristics of high film quality and good quality uniformity, which is conducive to improving the quality of the first dielectric layer 540.

[0123] In a specific embodiment, the surface of the groove 543 is stepped; the first dielectric material layer 545 in a portion of the second region II is etched back to form a groove 543 located in the first dielectric material layer 545. The step of etching back the first dielectric material layer 545 in a portion of the second region II includes: etching back the first dielectric material layer 545 from top to bottom multiple times along the thickness direction of the first dielectric material layer 545, and when etching the first dielectric material layer 545 located on the side of the floating gate structure 510 in the second region II, the etched area of ​​the latter etched back is located inside the etched area of ​​the previous etched back.

[0124] The first dielectric material layer 545 is etched back multiple times from top to bottom along the thickness direction of the first dielectric material layer 545. That is, each etch back is only used to remove a portion of the thickness of the first dielectric material layer 545. When etching the first dielectric material layer 545 located on the side of the floating gate structure 510 in the second region II, the etched area of ​​the latter etch back is located inside the etched area of ​​the previous etch back, which makes it easier to make the surface of the groove 543 step-shaped, thereby further reducing the difficulty of forming the first dielectric layer 540.

[0125] As an example, the sidewall of the bottom groove 542 is stepped, that is, the first dielectric layer 540 covering the sidewall of the floating gate structure 510 is stepped, including a first sidewall layer 547 covering part of the sidewall at the bottom position of the floating gate structure 510, and a second sidewall layer 546 covering the remaining sidewall of the floating gate structure.

[0126] It should be noted that, along the normal direction of the top surface of the substrate 500, the ratio of the first sidewall layer 547 height H2 to the second sidewall layer 546 height H1 should not be too small or too large. If the ratio of the first sidewall layer 547 height H2 to the second sidewall layer 546 height H1 is too small, it is likely to increase the difficulty of forming the first sidewall layer 547 and also reduce the effect of reducing the entry of electrons or electron holes from the substrate 500 into the erase gate structure through electrical motion. If the ratio of the first sidewall layer 547 height H2 to the second sidewall layer 546 height H1 is too large, it is likely to increase the difficulty of forming the second sidewall layer 546. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 500, the ratio of the first sidewall layer 547 height H2 to the second sidewall layer 546 height H1 ranges from 1.2:1 to 1:1.2.

[0127] In this embodiment, each back etching step includes: forming a mask layer 550 on the floating gate structure 510 and the control gate structure 520, the mask layer 550 partially extending to the second region II, and the area not covered by the mask layer 550 is used as the etching area (such as Figure 5 using the mask layer 550 as a mask, etching a portion of the thickness of the first dielectric material layer 545; and removing the mask layer 550.

[0128] A mask layer 550 is formed on the floating gate structure 510 and the control gate structure 520. The mask layer 550 partially extends to the second region II. The area not covered by the mask layer 550 serves as an etching area. Using the mask layer 550 as a mask, a portion of the first dielectric material layer 545 is etched. This helps reduce the probability of damage to areas other than the etched area during each back etching process, thereby improving the morphological accuracy, dimensional accuracy, and positional accuracy of the first dielectric layer 540.

[0129] Specifically, in the multiple back etchings, the first dielectric material layer 545 on the side of the control gate structure 520 is back-etched for the first time, and the remaining thickness of the first dielectric material layer 545 that has not been etched covers the floating gate structure 510; after the first back etching, the remaining first dielectric material layer 545 on the side of the floating gate structure 510 is back-etched for the remaining times.

[0130] The first dielectric material layer 545 on the side of the control gate structure 520 is etched back for the first time, and the remaining thickness of the first dielectric material layer 545 that has not been etched covers the floating gate structure 510. After the first etch back, the remaining first dielectric material layer 545 on the side of the floating gate structure 510 is etched back for the remaining times. That is, the first etch back forms a top recess 541 located above the top of the floating gate structure 510 in the first dielectric material layer 545, and the remaining etch back forms a bottom recess 542 located on the side of the floating gate structure 510 in the first dielectric material layer 545. This allows the top recess 541 to be formed through a single etch back process, thereby reducing the number of process steps for forming the top recess 541 and correspondingly reducing the number of process steps for forming the recess 543, thereby simplifying the process flow.

[0131] As an example, after the first etch-back, the remaining first dielectric material layer 545 on the side of the floating gate structure 510 is etched back twice. That is, the bottom recess 542 is formed by the two etch-backs. The first dielectric layer 540 covering the sidewalls of the floating gate structure 510 includes a first sidewall layer 547 covering a portion of the sidewall at the bottom of the floating gate structure 510, and a second sidewall layer 546 covering the remaining sidewalls of the floating gate structure. The width of the second sidewall layer 546 is smaller than the width of the first sidewall layer 547, and the width of the second sidewall layer 546 is the same at all locations. The width of the first sidewall layer 547 is the same at all locations. In other embodiments, after the first etch-back, the remaining first dielectric material layer on the side of the floating gate structure is etched back more than twice, and the width of the second sidewall layer at all locations may also be different.

[0132] In this embodiment, in the first back etching of the first dielectric material layer 545 on the side of the control gate structure 520, the back etching process includes an anisotropic dry etching process, and the parameters of the dry etching process include: etching gases include Ar, O2, CH3F, CF4 and He, the gas flow rate of Ar is 500sccm to 600sccm, the gas flow rate of O2 is 100sccm to 150sccm, the gas flow rate of CHF3 is 10sccm to 15sccm, the gas flow rate of CF4 is 10sccm to 15sccm, the gas flow rate of He is 200sccm to 300sccm, the chamber pressure is 80mTorr to 120mTorr, and the bias power is 80W to 120W.

[0133] The anisotropic dry etching process has higher etching accuracy and better cross-section controllability, which is beneficial to further improve the morphology accuracy, size accuracy and position accuracy of the first dielectric layer 540 .

[0134] Ar, O2, CH3F, CF4 and He are commonly used etching gases in dry etching processes and have high process compatibility.

[0135] It should be noted that the gas flow rate of the etching gas should not be too small or too large. If the gas flow rate of the etching gas is too small, it is easy to reduce the etching rate, thereby reducing the production efficiency; if the gas flow rate of the etching gas is too large, it is easy to reduce the process stability, produce side effects, and easily increase the process cost. Therefore, in this embodiment, the gas flow rate of Ar is 500 sccm to 600 sccm, the gas flow rate of O2 is 100 sccm to 150 sccm, the gas flow rate of CHF3 is 10 sccm to 15 sccm, the gas flow rate of CF4 is 10 sccm to 15 sccm, and the gas flow rate of He is 200 sccm to 300 sccm.

[0136] It should also be noted that the chamber pressure should not be too low or too high. If the chamber pressure is too low, it can easily reduce the etching rate, thereby reducing production efficiency. If the chamber pressure is too high, it can easily reduce the process controllability and reaction rate uniformity of the etching process, resulting in poor process stability. Therefore, in this embodiment, the chamber pressure is 80mTorr to 120mTorr.

[0137] It is also important to note that the bias power should not be too low or too high. If the bias power is too low, the etching rate may be reduced; if the bias power is too high, the first dielectric material layer 545 may be overetched, making it difficult for the formed first dielectric layer 540 to meet process requirements. Therefore, in this embodiment, the bias power is 80W to 120W.

[0138] Therefore, by setting the gas flow rate, bias power and process pressure of the dry etching process within a reasonable range and coordinating them with each other, the process efficiency and stability can be improved while reducing process costs and side effects.

[0139] In this embodiment, in the remaining number of back etchings of the remaining first dielectric material layer 545 on the side of the floating gate structure 510, the back etching process includes an anisotropic dry etching process, and the parameters of the dry etching process include: etching gases include Ar, O2, CHF3, CF4 and He, the gas flow rate of Ar is 300 sccm to 550 sccm, the gas flow rate of O2 is 180 sccm to 2200 sccm, the gas flow rate of CHF3 is 10 sccm to 20 sccm, the gas flow rate of CF4 is 10 sccm to 20 sccm, the gas flow rate of He is 150 sccm to 200 sccm, the chamber pressure is 60 mTorr to 100 mTorr, and the bias power is 80 W to 120 W.

[0140] The reason why the etching gas includes Ar, O2, CHF3, CF4 and He is similar to the reason why the etching gas includes Ar, O2, CHF3, CF4 and He in the first back etching of the first dielectric material layer 545 on the side of the control gate structure 520, and will not be repeated here.

[0141] It should be noted that the reason why the gas flow rate of the etching gas should not be too small or too large is similar to the reason why the gas flow rate of the etching gas should not be too small or too large during the first back etching of the first dielectric material layer 545 on the side of the control gate structure 520, and will not be repeated here.

[0142] It should also be noted that the reason why the chamber pressure should not be too small or too large is similar to the reason why the chamber pressure should not be too small or too large during the first back etching of the first dielectric material layer 545 on the side of the control gate structure 520, and will not be repeated here.

[0143] It is also necessary to explain that the reason why the bias power should not be too small or too large is similar to the reason why the bias power should not be too small or too large during the first back etching of the first dielectric material layer 545 on the side of the control gate structure 520, and will not be repeated here.

[0144] As an example, after the first back etching, the remaining first dielectric material layer 545 on the side of the floating gate structure 510 is back-etched twice using a dry etching process, so that the first dielectric layer 540 covering the side wall of the floating gate structure 510 includes a first sidewall layer 547 covering part of the sidewall at the bottom position of the floating gate structure 510, and a second sidewall layer 546 covering the remaining sidewall of the floating gate structure.

[0145] It should be noted that the process parameters of the dry etching process for forming the second sidewall layer 546 include: the etching gases include Ar, O2, CHF3, CF4 and He, the gas flow rate of Ar is 300sccm to 500sccm, the gas flow rate of O2 is 180sccm to 220sccm, the gas flow rate of CHF3 is 15sccm to 20sccm, the gas flow rate of CF4 is 15sccm to 20sccm, the gas flow rate of He is 150sccm to 200sccm, the chamber pressure is 60mTorr to 100mTorr, and the bias power is 80W to 120W.

[0146] It should also be noted that the process parameters of the dry etching process for forming the first sidewall layer 547 include: the etching gases include Ar, O2, CHF3, CF4 and He, the gas flow rate of Ar is 350sccm to 550ccm, the gas flow rate of O2 is 180sccm to 220sccm, the gas flow rate of CHF3 is 10sccm to 15sccm, the gas flow rate of CF4 is 10sccm to 15sccm, the gas flow rate of He is 150sccm to 200sccm, the chamber pressure is 60mTorr to 100mTorr, and the bias power is 80W to 120W.

[0147] In this embodiment, in the step of providing the substrate 500, the substrate 500 further includes a third region III disposed adjacent to the first region I, and the third region III is located on the side of the first region I facing away from the second region II. Accordingly, in the step of forming the first dielectric material layer 545, the first dielectric material layer 545 is further formed on the substrate 500 in the third region III. In the step of forming the groove 543, a second groove 544 is further formed in the first dielectric material layer 545 in the third region III.

[0148] In other embodiments, the step of forming the first dielectric layer includes: forming a first dielectric material layer on the substrate in the second region, the first dielectric material layer covering the surface of the floating gate structure facing the second region; forming a groove in the first dielectric material layer in the second region, the bottom of the groove exposing the substrate in the second region or the remaining first dielectric material layer; filling the groove with a sacrificial layer; and performing multiple thinning processes on the sidewalls of the groove, the thinning process including: removing a portion of the height of the sacrificial layer to expose the sidewalls of the first dielectric material layer; removing a portion of the width of the first dielectric material layer through the exposed sidewalls of the first dielectric material layer; wherein, after the final thinning process is completed, the remaining first dielectric material layer serves as the first dielectric layer.

[0149] In this embodiment, during the step of forming the groove 543 in the first dielectric material layer 545 , some remaining first dielectric material layer 545 remains at the bottom of the groove 543 .

[0150] In the step of forming the groove 543 in the first dielectric material layer 545, the remaining first dielectric material layer 545 remains at the bottom of the groove 543, so that in the subsequent step of forming the erase gate structure, the erase gate structure also covers the first dielectric layer 540 located on the second region II substrate 500. The first dielectric layer 540 located on the second region II substrate 500 can isolate the erase gate structure from the substrate 500, which is conducive to simplifying the subsequent process steps of forming the erase gate structure.

[0151] In this embodiment, during the step of forming the groove 543, a second groove 544 is also formed in the first dielectric material layer 545 in the third region III. Accordingly, during the step of forming the groove 543 in the first dielectric material layer 545, some of the first dielectric material layer 545 remains at the bottom of the second groove 544.

[0152] refer to Figures 10 and 11 In this embodiment, after forming the first dielectric layer 540 and before forming the erase gate structure, the process further includes forming a second dielectric layer 560 (eg, Figure 10 shown).

[0153] It should be noted that the process of forming the second dielectric layer 560 includes a chemical vapor deposition process, and the second dielectric layer 560 is a high temperature oxide material.

[0154] Specifically, the second dielectric layer 560 also covers the first dielectric layer 540 and the spacer layer 530 .

[0155] As an example, after forming the second dielectric layer 560, in the third region III, the second dielectric layer 560 located on a portion of the first dielectric layer 540 is thinned (eg, Figure 11In other embodiments, the thinning process may not be performed.

[0156] In this embodiment, after forming the first dielectric layer 540 and before forming the erase gate structure, the process further includes: forming a source region (not shown) in the substrate 500 in the second region II.

[0157] As an example, in the same memory cell area, the number of the first area I and the number of the third area III are both 2, and the number of the second area II is 1, that is, the source area is shared in the same memory cell area.

[0158] It should be noted that the source region may be formed first and then the second dielectric layer 560 is formed; or the second dielectric layer 560 may be formed first and then the source region is formed.

[0159] refer to Figure 12 , an erase gate structure 570 is formed on the substrate 500 in the second region II.

[0160] The erase gate structure 570 is used to apply a high voltage to the erase gate structure 570 during data erasure, so that there is a potential difference between the erase gate structure 570 and the floating gate structure 510, so that electrons in the floating gate structure 510 can be pulled into the erase gate structure 570 through the tunneling effect, thereby achieving data erasure.

[0161] As an example, the material of the erase gate structure 570 includes polysilicon.

[0162] In this embodiment, the process of forming the erase gate structure 570 includes a chemical vapor deposition process and a chemical mechanical polishing process.

[0163] Accordingly, in the step of forming the erase gate structure 570 , the erase gate structure 570 is also located on the protrusion 515 .

[0164] Accordingly, in the step of forming the erase gate structure 570 , the erase gate structure 570 also covers the first dielectric layer 540 located on the second region II of the substrate 500 .

[0165] In this embodiment, during the step of forming the erase gate structure 570 , a word line structure 580 is further formed on the substrate 500 in the third region III.

[0166] The word line structure 580 is used to determine the memory cells to be edited.

[0167] As an example, the material of the erase gate structure 570 includes polysilicon, and correspondingly, the material of the word line structure 580 also includes polysilicon.

[0168] Correspondingly, the word line structure 580 also covers the first dielectric layer 540 located on the third region III of the substrate 500 .

[0169] It should be noted that the semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0170] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first region and a second region adjacently disposed; a floating gate structure located on the substrate in the first region; a control gate structure, located on the floating gate structure, wherein the control gate structure and the floating gate structure are insulated from each other; a first dielectric layer located on a surface of the floating gate structure and the control gate structure facing the second region, wherein a width of the first dielectric layer at a top position of the floating gate structure is smaller than a width of the first dielectric layer at a bottom position of the floating gate structure in a direction perpendicular to a sidewall of the floating gate structure; The erase gate structure is located on the substrate in the second region.

2. The semiconductor structure according to claim 1, wherein The sidewall of the floating gate structure facing the second region protrudes from the control gate structure, so that the floating gate structure has a protruding portion; The erase gate structure is also located on the protrusion.

3. The semiconductor structure according to claim 2, wherein: Along a direction perpendicular to the sidewall of the floating gate structure, the width of the protrusion ranges from 300 angstroms to 500 angstroms.

4. The semiconductor structure according to claim 1 or 2, wherein: The interface between the first dielectric layer covering the sidewall of the floating gate structure and the erase gate structure is in a step-like or slope-like shape.

5. The semiconductor structure according to claim 4, wherein: The interface between the first dielectric layer covering the sidewall of the floating gate structure and the erase gate structure is stepped, including a first sidewall layer covering part of the sidewall at the bottom of the floating gate structure and a second sidewall layer covering the remaining sidewall of the floating gate structure.

6. The semiconductor structure according to claim 5, wherein: Along a normal direction of the top surface of the substrate, a ratio of the first sidewall layer height to the second sidewall layer height ranges from 1.2:1 to 1:1.

2.

7. The semiconductor structure according to claim 1, wherein Along a direction perpendicular to the sidewall of the floating gate structure, the width of the first dielectric layer at the top of the floating gate structure ranges from 60 angstroms to 100 angstroms.

8. The semiconductor structure according to claim 1, wherein: Along a direction perpendicular to the sidewall of the floating gate structure, the width of the first dielectric layer at the bottom of the floating gate structure ranges from 140 angstroms to 230 angstroms.

9. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region adjacently disposed, a floating gate structure formed on the substrate of the first region, a control gate structure formed on the floating gate structure, and the control gate structure and the floating gate structure being insulated; forming a first dielectric layer on the surface of the floating gate structure and the control gate structure facing the second region, wherein a width of the first dielectric layer at a top position of the floating gate structure is smaller than a width of the first dielectric layer at a bottom position of the floating gate structure in a direction perpendicular to a sidewall of the floating gate structure; An erase gate structure is formed on the substrate in the second region.

10. The method for forming a semiconductor structure according to claim 9, wherein: In the step of providing the substrate, the sidewall of the floating gate structure facing the second region protrudes from the control gate structure, so that the floating gate structure has a protruding portion; In the step of forming the erase gate structure, the erase gate structure is also located on the protrusion.

11. The method for forming a semiconductor structure according to claim 9 or 10, wherein: The step of forming the first dielectric layer includes: forming a first dielectric material layer on the substrate in the second region, wherein the first dielectric material layer covers the surface of the floating gate structure and the control gate structure facing the second region; In the second region, a top groove located above the top of the floating gate structure and a bottom groove located on the side of the floating gate structure are formed in the first dielectric material layer. The sidewalls of the bottom groove are stepped or sloped, and the remaining first dielectric material layer exposed by the bottom groove and the top groove serves as the first dielectric layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming a groove in the first dielectric material layer, the first dielectric material layer remains at the bottom of the groove; In the step of forming the erase gate structure, the erase gate structure also covers the first dielectric layer located on the substrate in the second region.

13. The method for forming a semiconductor structure according to claim 11, wherein: The surface of the groove is stepped; Etching back the first dielectric material layer in a portion of the second region to form a groove in the first dielectric material layer, wherein the step of etching back the first dielectric material layer in a portion of the second region includes: The first dielectric material layer is etched back multiple times from top to bottom along the thickness direction of the first dielectric material layer, and when the first dielectric material layer located on the side of the floating gate structure is etched in the second area, the etched area of ​​the latter etched back is located inside the etched area of ​​the previous etched back.

14. The method for forming a semiconductor structure according to claim 13, wherein: Each back etching step includes: forming a mask layer on the floating gate structure and the control gate structure, wherein the mask layer partially extends toward the second region, and an area not covered by the mask layer serves as an etching area; Using the mask layer as a mask, etching a portion of the thickness of the first dielectric material layer; The mask layer is removed.

15. The method for forming a semiconductor structure according to claim 13, wherein: In the multiple etching backs, the first dielectric material layer on the side of the control gate structure is etched back for the first time, and the remaining thickness of the first dielectric material layer that has not been etched covers the floating gate structure; After the first etch-back is performed, the remaining first dielectric material layer on the side of the floating gate structure is etched back for the remaining times.

16. The method for forming a semiconductor structure according to claim 15, wherein: In the first back-etching of the first dielectric material layer on the side of the control gate structure, the back-etching process includes an anisotropic dry etching process, and the parameters of the dry etching process include: etching gases include Ar, O2, CHF3, CF4 and He, the gas flow rate of Ar is 500sccm to 600sccm, the gas flow rate of O2 is 100sccm to 150sccm, the gas flow rate of CHF3 is 10sccm to 15sccm, the gas flow rate of CF4 is 10sccm to 15sccm, the gas flow rate of He is 200sccm to 300sccm, the chamber pressure is 80mTorr to 120mTorr, and the bias power is 80W to 120W.

17. The method for forming a semiconductor structure according to claim 15, wherein: In the remaining number of back etchings of the remaining first dielectric material layer on the side of the floating gate structure, the back etching process includes an anisotropic dry etching process, and the parameters of the dry etching process include: etching gases include Ar, O2, CHF3, CF4 and He, the gas flow rate of Ar is 300sccm to 550sccm, the gas flow rate of O2 is 180sccm to 220sccm, the gas flow rate of CHF3 is 10sccm to 20sccm, the gas flow rate of CF4 is 10sccm to 20sccm, the gas flow rate of He is 150sccm to 200sccm, the chamber pressure is 60mTorr to 100mTorr, and the bias power is 80W to 120W.

18. The method for forming a semiconductor structure according to claim 9 or 10, wherein: The step of forming the first dielectric layer includes: forming a first dielectric material layer on the substrate in the second region, wherein the first dielectric material layer covers a surface of the floating gate structure facing the second region; In the second region, a groove is formed in the first dielectric material layer, wherein the bottom of the groove exposes the substrate of the second region or the remaining first dielectric material layer; filling a sacrificial layer in the groove; The first dielectric material layer on the sidewall of the groove is thinned multiple times, wherein the thinning process includes: removing a portion of the height of the sacrificial layer to expose the sidewall of the first dielectric material layer; and removing a portion of the width of the first dielectric material layer through the exposed sidewall of the first dielectric material layer; After the final thinning process is completed, the remaining first dielectric material layer serves as the first dielectric layer.

Images