Semiconductor device and preparation method thereof

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, an oxide layer, two metal gates, two floating gates and a common gate. The substrate includes a plurality of active regions including a first active region, a second active region, a central active region, a third active region and a fourth active region in sequence. The oxide layer is arranged on the substrate, and the two metal gates are arranged on the oxide layer and located between the first active region and the second active region and between the third active region and the fourth active region respectively. The two floating gates are disposed on the oxide layer and located between the second and central active regions and between the central and third active regions, respectively, and each metal gate is coplanar with the top surface of each floating gate. The common gate is located above the central active region and a part of the floating gates, and is isolated from the floating gates. The invention further provides a method for manufacturing the semiconductor device, so that the high-dielectric-constant metal gate with the gate height smaller than 600 angstroms and compatible with the 28-nanometer process is achieved.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device with an embedded memory and a manufacturing method thereof. Background Art

[0002] Current electronic devices all have memory, which can be categorized as either volatile or non-volatile. Volatile memory loses its data when power is lost, while non-volatile memory retains data even when power is lost. As technology evolves, shrinking transistor size allows for an increase in the amount of memory on a chip.

[0003] However, the reduction in memory size also increases the difficulty in manufacturing. Therefore, the existing technology still needs to be improved. Summary of the Invention

[0004] One embodiment of the present disclosure provides a semiconductor device comprising a substrate, an oxide layer, two metal gates, two floating gates, and a common gate. The substrate comprises a main body and a plurality of active regions disposed on top of the main body, wherein the active regions sequentially comprise a first active region, a second active region, a central active region, a third active region, and a fourth active region. The oxide layer is disposed above the substrate and between the active regions. Two metal gates are disposed on the oxide layer and are respectively located between the first active region and the second active region, and between the third active region and the fourth active region. Two floating gates are disposed on the oxide layer and are respectively located between the second active region and the central active region, and between the central active region and the third active region, wherein the top surface of each metal gate is coplanar with the top surface of each floating gate. The common gate is located above the central active region and above a portion of each floating gate, and the common gate is isolated from the floating gates.

[0005] In some embodiments, the oxide layer includes a thin oxide layer disposed above the substrate and between the first active region and the second active region, and between the third active region and the fourth active region.

[0006] In some embodiments, the oxide layer further includes a thick oxide layer disposed above the substrate and between the second active region and the central active region, and between the central active region and the third active region.

[0007] In some embodiments, the common gate includes: a body located above the central active region; and two extensions extending from the top of the body toward the floating gates and isolated from the floating gates.

[0008] In some embodiments, the distance between the common gate and each floating gate is 80 angstroms to 100 angstroms.

[0009] In some embodiments, an area of ​​each floating gate perpendicularly projected onto the bottom surface of the substrate body partially overlaps an area of ​​the central active region perpendicularly projected onto the bottom surface of the substrate body.

[0010] Another embodiment of the present disclosure provides a semiconductor device comprising a substrate, an oxide layer, two metal gates, two floating gates, and a common gate. The substrate comprises a main body and a plurality of active regions disposed on top of the main body, wherein the active regions sequentially comprise a first active region, a second active region, a central active region, a third active region, and a fourth active region. The oxide layer is disposed above the substrate and between the active regions. Two metal gates are disposed on the oxide layer and are respectively located between the first active region and the second active region, and between the third active region and the fourth active region. Two floating gates are disposed on the oxide layer and are respectively located between the second active region and the central active region, and between the central active region and the third active region. The common gate comprises a main body disposed above the central active region, and two extensions extending from the top of the main body toward each floating gate, and respectively located above a portion of each floating gate.

[0011] In some embodiments, top surfaces of the metal gates are coplanar with top surfaces of the floating gates.

[0012] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate comprising a body and a plurality of active regions disposed on top of the body, wherein the active regions sequentially comprise a first active region, a second active region, a third active region, and a fourth active region; forming an oxide layer above the substrate and between the active regions; forming a floating gate layer on the oxide layer, and patterning the floating gate layer to obtain two dummy floating gates respectively disposed between the first active region and the second active region and between the third active region and the fourth active region, and two floating gates disposed between the second active region and the third active region; forming a first interlayer dielectric layer; The invention relates to a method for fabricating a first interlayer dielectric layer on a substrate and a floating gate layer, wherein a top surface of a first interlayer dielectric layer is coplanar with a top surface of the floating gate layer; removing the dummy floating gates and forming two metal gates respectively, wherein a top surface of each metal gate is coplanar with a top surface of each floating gate; forming a second interlayer dielectric layer on a top surface of the first interlayer dielectric layer, a top surface of each metal gate and a top surface of each floating gate; forming a central active region on a top portion of the substrate and between the second active region and the third active region; and forming a common gate above the central active region and above a portion of each floating gate, wherein the common gate is isolated from the floating gates.

[0013] In some embodiments, the step of forming an oxide layer includes: forming an oxide layer above the substrate; and patterning the oxide layer to form a thin oxide layer and a thick oxide layer, wherein the thin oxide layer is between the first active region and the second active region, and between the third active region and the fourth active region, and the thick oxide layer is between the second active region and the third active region. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The various aspects of the present disclosure will be most easily understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard operating procedures, various features may not be drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. To make the above and other objects, features, advantages, and embodiments of the present disclosure more readily apparent, the accompanying drawings are described as follows:

[0015] Figures 1 to 7 The figures are cross-sectional views of one embodiment of the semiconductor device fabricated according to the present disclosure at different fabrication stages. DETAILED DESCRIPTION

[0016] To provide a more complete and detailed description of the present disclosure, the following provides illustrative descriptions of embodiments and examples of the present disclosure. However, these descriptions are not intended to be the only ways to implement or use the present disclosure. The embodiments disclosed below may be combined or substituted with one another where beneficial, and other embodiments may be added to one embodiment without further description or explanation. In the following description, numerous specific details are detailed to facilitate a thorough understanding of the following embodiments. However, the present disclosure may be practiced without these specific details.

[0017] Additionally, spatially relative terms, such as "lower" and "upper," are used to conveniently describe the relative relationship of one element or feature to other elements or features in the accompanying drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

[0018] As used herein, unless the context specifically limits the use of the articles, "a," "an," and "the" may refer to one or more. It will be further understood that the use of "comprises," "includes," "has," and similar words herein specify the stated features, regions, integers, steps, operations, elements, and / or components, but does not exclude the stated or additional one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0019] Furthermore, when a number or a range of numbers is described using the words "about," "approximately," and the like, the terms are intended to encompass numbers within a reasonable range that takes into account variations that inherently occur during manufacturing, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with the number, the number or range of numbers encompasses a reasonable range that includes the described number, such as within + / - 10% of the described number. Furthermore, the present disclosure may repeatedly reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0020] The high-k metal gate (HKMG) in the current 28nm process requires a gate height less than Otherwise, it is difficult to achieve the characteristics of 28 nanometers. However, the third generation of embedded flash memory (Embedded However, the gate height of ESF3 is greater than 1000 angstroms, making it incompatible with the high-k metal gate in the 28nm process. Furthermore, the third-generation embedded flash memory is complex to manufacture and requires high voltages, such as greater than 10 volts, to operate.

[0021] In view of this, some embodiments disclosed herein provide a semiconductor device with embedded memory and a method for fabricating the same, with a high-k metal gate having a gate height less than 600 angstroms and compatible with 28nm process, a simplified process with less than 13 mask steps, and the device can be driven with a voltage less than 5 volts without the need for high voltage.

[0022] Several embodiments and experimental examples are listed below to further illustrate the method for manufacturing a semiconductor device and the semiconductor device disclosed herein. However, these are for illustration purposes only and are not intended to limit the disclosure. The scope of protection of the disclosure shall be determined by the appended claims.

[0023] Although the methods disclosed herein are described below using a series of operations or steps, the order in which these operations or steps are presented should not be construed as limiting the present disclosure. For example, certain operations or steps may be performed in a different order and / or concurrently with other steps. Furthermore, not all illustrated operations, steps, and / or features must be performed to implement the presently disclosed embodiments. Furthermore, each operation or step described herein may include multiple sub-steps or actions.

[0024] For the sake of clarity, features and elements that are known in the art and are not necessary for understanding the described principles may be omitted.

[0025] Figures 1 to 7The cross-sectional views of an embodiment of the present disclosure of manufacturing a semiconductor device 100 at different manufacturing stages are shown. The method of manufacturing the semiconductor device 100 includes steps S11 to S18.

[0026] In step S11, a substrate 110 is provided, such as Figure 1 As shown, substrate 110 is a silicon substrate. In some embodiments, substrate 110 is a semiconductor-on-insulator substrate, such as silicon, a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate, and can be made of any suitable material. Substrate 110 includes a body 112 and a plurality of active regions 114 disposed on top of body 112. Active regions 114 include a first active region 114A, a second active region 114B, a third active region 114C, and a fourth active region 114D. In some embodiments, the first active region 114A on the leftmost side and the fourth active region 114D on the rightmost side serve as drains. The second active region 114B and the third active region 114C are not electrically connected to the outside world. That is, no conductive line is electrically connected to the second active region 114B, and no conductive line is electrically connected to the third active region 114C. In some embodiments, the body 112 of the substrate 110 is doped with a P-type doping method and the active regions 114 are doped with an N-type doping method; or the body 112 is doped with an N-type doping method and the active regions 114 are doped with a P-type doping method.

[0027] In step S12, an oxide layer 120 is formed on the substrate 110. Figure 1 Specifically, an oxide layer 120 is deposited over the substrate 110, for example, by chemical vapor deposition, physical vapor deposition, sputtering, or some other suitable deposition process, wherein the oxide layer 120 may be or otherwise include, for example, silicon oxide or some other suitable dielectric. Next, the oxide layer 120 is patterned to form a thin oxide layer 122 (core oxide) and a thick oxide layer 124 (IO oxide, input / output oxide), wherein the thin oxide layer 122 is located between the first active region 114A and the second active region 114B, and between the third active region 114C and the fourth active region 114D, and the thick oxide layer 124 is located between the second active region 114B and the third active region 114C. In some embodiments, the thin oxide layer 122 has a thickness D1 of approximately 20 angstroms or less, and the thick oxide layer 124 has a thickness D2 of approximately 50 angstroms or less, and the thickness D1 is less than the thickness D2. In some embodiments, the oxide layer 120 is made of silicon oxide or other suitable dielectric materials.

[0028] In step S13, a floating gate layer 130 is formed on the oxide layer 120. Figure 1 As shown. A floating gate layer 130 is deposited on the oxide layer 120, for example, by chemical vapor deposition, physical vapor deposition, sputtering, or some other suitable deposition process. The floating gate layer 130 is then patterned to provide two dummy floating gates 132 disposed between the first active region 114A and the second active region 114B, and between the third active region 114C and the fourth active region 114D, respectively, and two floating gates 134 disposed between the second active region 114B and the third active region 114C. Specifically, the dummy floating gate 132 is disposed on the thin oxide layer 122, and the floating gate 134 is disposed on the thick oxide layer 124. In some embodiments, the floating gate layer 130 may be or otherwise include, for example, doped polysilicon, a metal, or some other suitable conductive material.

[0029] In step S14, a first interlayer dielectric layer 140 is formed on the substrate 110 and the floating gate layer 130. Figure 1 Next, the first interlayer dielectric layer 140 is planarized, for example, by chemical mechanical polishing (CMP) or some other suitable planarization process, so that the top surface 142 of the first interlayer dielectric layer 140 is coplanar with the top surface 136 of the floating gate layer 130. The first interlayer dielectric layer 140 can be or otherwise include, for example, silicon nitride, silicon oxide, some other suitable dielectric material, or any combination thereof.

[0030] Then, if Figure 2 As shown, a first mask layer 150 is formed on a portion of the first interlayer dielectric layer 140 and the two floating gates 134. Specifically, the areas covered by the first mask layer 150 include: (1) a portion of the first interlayer dielectric layer 140 between the dummy floating gate 132 on the left and the floating gate 134 on the left is covered, while the remaining portion of the first interlayer dielectric layer 140 is exposed and uncovered; (2) the top surfaces 136 of the two floating gates 134 are covered; (3) the first interlayer dielectric layer 140 between the floating gates 134 is covered; and (4) a portion of the first interlayer dielectric layer 140 between the dummy floating gate 132 on the right and the floating gate 134 on the right is covered, while the remaining portion of the first interlayer dielectric layer 140 is exposed and uncovered. In other embodiments, the first mask layer 150 covers the two floating gates 134 but exposes the two dummy floating gates 132 to facilitate the subsequent removal of the two dummy floating gates 132. In some embodiments, the first mask layer 150 includes silicon oxide, silicon nitride, some other appropriate dielectric material, or any combination thereof. The first mask layer 150 can be formed, for example, by chemical vapor deposition, physical vapor deposition, some other appropriate deposition process, or any combination thereof.

[0031] In step S15, the dummy floating gates 132 are removed and two metal gates 162 are formed respectively. Figure 2 and Figure 3 As shown. First, Figure 2 As shown, the dummy floating gates 132 are removed. Specifically, the dummy floating gates 132 are etched until the thin oxide layer 122 is exposed, forming two holes 126. Figure 3 As shown, the first mask layer 150 is removed to expose the two floating gates 134 and the first interlayer dielectric layer 140. Next, a metal gate layer 160 is filled into the two holes 126 to form two metal gates 162, each disposed on the thin oxide layer 122. In some embodiments, the metal gate layer 160 is filled into the two holes 126 and then subjected to chemical mechanical polishing or some other suitable planarization process to make the top surface 164 of the metal gate layer 160 coplanar with the top surface 136 of the floating gate layer 130 and the top surface 142 of the first interlayer dielectric layer 140. In some embodiments, the height H1 of each metal gate 162 plus the thin oxide layer 122 is the same as the height H2 of each floating gate 134 plus the thick oxide layer 124. For example, the heights H1 and H2 are less than 600 angstroms. In some embodiments, the metal gate layer 160 may be or otherwise include, for example, a metal or some other suitable conductive material.

[0032] In step S16, a second interlayer dielectric layer 170 is formed on the top surface 142 of the first interlayer dielectric layer 140, the top surface 164 of each metal gate 162, and the top surface 136 of each floating gate 134. Figure 4 Next, a second mask layer 180 is formed to cover each metal gate 162 and a portion of each floating gate 134. Figure 5 As shown, a portion of the first interlayer dielectric layer 140 and a portion of the second interlayer dielectric layer 170 are removed to form a T-shaped opening 172. Specifically, the first interlayer dielectric layer 140 located between the two floating gates 134 is removed, and the portion of the second interlayer dielectric layer 170 not covered by the second mask layer 180 is removed to form the T-shaped opening 172 and the remaining second interlayer dielectric layer 174. Next, the second mask layer 180 is removed.

[0033] In step S17, a central active region 114E is formed on the top of the main body 112 of the substrate 110, as shown in FIG. Figure 5As shown. A central active region 114E is doped on top of the main body 112 of the substrate 110. The central active region 114E has the same P-type or N-type doping as the first active region 114A, the second active region 114B, the third active region 114C, and the fourth active region 114D. Next, a conformal oxide layer 176 is formed on the central active region 114E, the sidewalls 138, and a portion of the top surface 136 of each floating gate 134. In some embodiments, the conformal oxide layer 176 is made of the same material as the remaining second interlayer dielectric layer 174. In some embodiments, the area of ​​each floating gate 134 perpendicularly projected onto the bottom surface of the main body 112 of the substrate 110 partially overlaps with the area of ​​the central active region 114E perpendicularly projected onto the bottom surface of the main body 112 of the substrate 110, enabling electrical conduction between the floating gate 134 and the central active region 114E.

[0034] In step S18, a common gate 192 is formed above the central active region 114E and above a portion of each floating gate 134, and the common gate 192 is isolated from these floating gates 134 (not shown). Specifically, a common gate layer 190 is deposited on the conformal oxide layer 176 (i.e., filling the opening 172) and the remaining second interlayer dielectric layer 174. Then, the common gate layer 190 is planarized, for example, by chemical mechanical polishing or some other appropriate planarization process, so that the top surface 194 of the common gate 192 is coplanar with the top surface 175 of the remaining second interlayer dielectric layer 174. Then, as shown in FIG. Figure 6As shown, a third interlayer dielectric layer 200 is deposited on the top surface 194 of the common gate 192 and the top surface 175 of the remaining second interlayer dielectric layer 174. In some embodiments, the common gate 192 includes a body 192A and two extensions 192B. The body 192A is located above the central active region 114E. The two extensions 192B extend from the top of the body 192A toward each floating gate 134 and are spaced apart from each floating gate 134. The extensions 192B have a height H3 of 100 angstroms to 400 angstroms, and the length of the extensions 192B covers at least half of the top surface 136 of the floating gate 134. When the common gate 192 is used for erase memory, the extensions 192B and the side portions 192A1 of the body 192A couple the voltage to the floating gate 134, while the lower portion 192A2 of the body 192A couples the voltage from the central active region 114E to the source. In some embodiments, the distance G between the common gate 192 and each floating gate 134 (the thickness of the conformal oxide layer 176) is 80 angstroms to 100 angstroms. If the distance G is too large, electron retention in the device is poor, and electrons are more likely to leak out. Conversely, if the distance G is too small, the coupling efficiency decreases. In some embodiments, the common gate 192 has a T-shape in cross-section. In some embodiments, the common gate layer 190 can be or otherwise include, for example, silicon nitride, silicon oxide, some other suitable dielectric, or any combination thereof.

[0035] Then as Figure 7 As shown, the first active region 114A and the fourth active region 114D are electrically connected to bit lines BL1 and BL2, respectively. The central active region 114E is electrically connected to a source line (not shown). The second active region 114B and the third active region 114C are electrically isolated from each other. The metal gates 162 are electrically connected to word lines WL1 and WL2, respectively. The common gate 192 is electrically connected to the page line PL.

[0036] Although the present disclosure has been disclosed above in the form of embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0037]

Explanation of symbols

[0038] 100: Semiconductor devices

[0039] 110: Substrate

[0040] 112: Main body

[0041] 114: Active Zone

[0042] 114A: First active zone

[0043] 114B: Second active zone

[0044] 114C: Third active zone

[0045] 114D: Fourth Active Zone

[0046] 114E: Central Active Zone

[0047] 120: Oxide layer

[0048] 122: Thin oxide layer

[0049] 124: Thick oxide layer

[0050] 126: Hole

[0051] 130: floating gate layer

[0052] 132: Dummy floating gate

[0053] 134: Floating Gate

[0054] 136: Top surface

[0055] 138: Sidewall

[0056] 140: First interlayer dielectric layer

[0057] 142: Top surface

[0058] 150: First mask layer

[0059] 160: Metal gate layer

[0060] 162: Metal Gate

[0061] 164: Top surface

[0062] 170: Second interlayer dielectric layer

[0063] 172: Opening

[0064] 174: Remaining second interlayer dielectric layer

[0065] 175: Top surface

[0066] 176: Conformal Oxide Layer

[0067] 180: Second mask layer

[0068] 190: Common gate layer

[0069] 192: Common Gate

[0070] 192A: Ontology

[0071] 192A1: Side

[0072] 192B: Extension

[0073] 194: Top surface

[0074] 200: Third interlayer dielectric layer

[0075] BL1: bit line

[0076] BL2: bit line

[0077] D1: Thickness

[0078] D2: Thickness

[0079] G: distance

[0080] H1: Height

[0081] H2: Height

[0082] H3: Height

[0083] PL: Page Line

[0084] S11~S18: Steps

[0085] WL1: character line

[0086] WL2: character line.

Claims

1. A semiconductor device, characterized in that: Include: A substrate comprising a main body and a plurality of active regions respectively disposed on top of the main body, wherein the plurality of active regions sequentially comprise a first active region, a second active region, a central active region, a third active region, and a fourth active region; an oxide layer disposed above the substrate and between the plurality of active regions; Two metal gates are disposed on the oxide layer and are respectively located between the first active region and the second active region, and between the third active region and the fourth active region; Two floating gates are disposed on the oxide layer and are located between the second active region and the central active region, and between the central active region and the third active region, respectively, wherein a top surface of each metal gate is coplanar with a top surface of each floating gate; as well as The common gate is located above the central active region and above a portion of each of the floating gates, and the common gate is isolated from the plurality of floating gates. 2 . The semiconductor device according to claim 1 , wherein the oxide layer comprises a thin oxide layer disposed above the substrate and between the first active region and the second active region, and between the third active region and the fourth active region. 3 . The semiconductor device according to claim 2 , wherein the oxide layer further comprises a thick oxide layer disposed above the substrate and between the second active region and the central active region, and between the central active region and the third active region.

4. The semiconductor device according to any one of claims 1 to 3, wherein the common gate comprises: a body located above the central active area; and The two extension parts respectively extend from the top of the body toward the floating gates and are respectively isolated from the floating gates. 5 . The semiconductor device according to claim 1 , wherein a distance between the common gate and each of the floating gates is 80 angstroms to 100 angstroms.

6. The semiconductor device according to any one of claims 1 to 3, wherein an area of ​​each floating gate perpendicularly projected onto the bottom surface of the main body of the substrate partially overlaps an area of ​​the central active region perpendicularly projected onto the bottom surface of the main body of the substrate.

7. A semiconductor device, characterized in that: Include: A substrate comprising a main body and a plurality of active regions respectively disposed on top of the main body, wherein the plurality of active regions sequentially comprise a first active region, a second active region, a central active region, a third active region, and a fourth active region; an oxide layer disposed above the substrate and between the plurality of active regions; Two metal gates are disposed on the oxide layer and are respectively located between the first active region and the second active region, and between the third active region and the fourth active region; two floating gates disposed on the oxide layer and respectively located between the second active region and the central active region, and between the central active region and the third active region; and Common gate, including: a body located above the central active area; and The two extension portions extend from the top of the body toward the floating gates, and are respectively located above a portion of the floating gates. 8 . The semiconductor device of claim 7 , wherein top surfaces of the plurality of metal gates are coplanar with top surfaces of the plurality of floating gates.

9. A method for preparing a semiconductor device, characterized in that: Include: Providing a substrate, the substrate comprising a main body and a plurality of active regions respectively disposed on top of the main body, wherein the plurality of active regions sequentially comprise a first active region, a second active region, a third active region, and a fourth active region; forming an oxide layer above the substrate and between the plurality of active regions; forming a floating gate layer on the oxide layer, and patterning the floating gate layer to obtain two dummy floating gates respectively located between the first active region and the second active region and between the third active region and the fourth active region, and two floating gates located between the second active region and the third active region; forming a first interlayer dielectric layer on the substrate and the floating gate layer, wherein a top surface of the first interlayer dielectric layer is coplanar with a top surface of the floating gate layer; removing the plurality of dummy floating gates and forming two metal gates respectively, wherein a top surface of each metal gate is coplanar with a top surface of each floating gate; forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer, the top surface of each metal gate, and the top surface of each floating gate; forming a central active region on the top of the main body of the substrate and between the second active region and the third active region; as well as A common gate is formed above the central active region and above a portion of each of the floating gates, and the common gate is isolated from the plurality of floating gates.

10. The method according to claim 9, wherein the step of forming the oxide layer comprises: forming the oxide layer above the substrate; and The oxide layer is patterned to form a thin oxide layer and a thick oxide layer, wherein the thin oxide layer is located between the first active region and the second active region and between the third active region and the fourth active region, and the thick oxide layer is located between the second active region and the third active region.

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