A SiC MOSFET device and a manufacturing method thereof

Abstract

The application relates to a SiC MOSFET device and a manufacturing method thereof, a cell of the SiC MOSFET device comprising an N+ SiC substrate, an N-drift region, an N+ source region, a P body region, a P+ region, a gate dielectric layer, a gate, a field passivation layer, a source electrode and a drain electrode, further comprising a P bottom region and a hole absorption region, the high-doped P bottom region inhibiting the opening of a parasitic transistor. The hole absorption region is provided in a three-section structure, can realize the optimization of the potential distribution near the gate dielectric layer under the premise of not greatly increasing the resistance of a JFET region, further reduces the accumulation of local holes through the interconnection between the hole absorption regions, provides additional paths for the rapid export of the accumulated holes, further relieves the single particle effect, and reduces the occurrence probability of single particle gate penetration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a SiC MOSFET device and its fabrication method. Background Technology

[0002] MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a semiconductor device widely used for switching purposes and amplification of electronic signals in electronic devices.

[0003] Early semiconductor devices primarily used silicon-based substrates, but due to the inherent characteristics of silicon (such as narrow bandgap), their high-temperature, high-pressure, and radiation resistance properties were significantly limited. With the rise and gradual commercialization of wide-bandgap materials (such as silicon carbide (SiC) and gallium nitride (GaN)), the performance bottleneck of silicon-based devices was successfully overcome, and their application range was significantly broadened.

[0004] An existing SiC MOSFET structure is as follows: Figure 1 As shown, the device includes an N+SiC substrate 101, an N-drift region 102, a P-body region 103, a P+ region 104, an N+ source region 105, a gate dielectric layer 106, a gate electrode 107, a field passivation layer 108, a source electrode 109, and a drain electrode 110. The N+SiC substrate 101 is heavily N-type doped; the N-drift region 102 is located within the epitaxial layer of the N+SiC substrate 101 and is lightly N-type doped. The P-body region 103, P+ region 104, and N+ source region 105 are symmetrically distributed within the epitaxial layer of the N+SiC substrate 101 below the gate electrode 107. The N+ source region 105 is surrounded by the P-body region 103. The portion of the N-drift region 102 between the two symmetrically arranged N+ source regions 105 constitutes the JFET region of the SiC MOSFET device, with a width equal to the distance between the two P-body regions 103 and a depth equal to the doping depth of the P-body region 103. The gate dielectric layer 106 is a silicon dioxide layer disposed on the surface of the epitaxial layer of the N+SiC substrate 101, and the gate 107 is generally polysilicon.

[0005] In existing SiC MOSFET devices used in space applications, when high-energy particles bombard the device, under the influence of a reverse bias electric field, charge carriers undergo directional drift, forming transient peak currents. Holes migrate and accumulate in the JFET region, while electrons accumulate at the bottom of the N-drift region, leading to distortion of the depletion region boundary and reconstructing the internal electric field distribution. This process causes a doubling of the local electric field intensity (typically >3MV / cm), especially within the gate dielectric layer above the JFET region of the SiC MOSFET, further inducing single-event gate breakdown (SEGR), resulting in conductive paths within the gate dielectric layer and ultimately burning out the SiC MOSFET device. Therefore, it is urgent to optimize the electric field distribution in the JFET region through radiation-hardened design to mitigate the risk of gate dielectric layer failure. Summary of the Invention

[0006] Therefore, it is necessary to provide a SiC MOSFET device and its fabrication method to address the above problems, thereby reducing the probability of single-event gate breakdown by optimizing the electric field distribution in the JFET region.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A SiC MOSFET device, wherein the cell of the SiC MOSFET device comprises: an N+ SiC substrate, an N- drift region, an N+ source region, a P- body region, a P+ region, a gate dielectric layer, a gate electrode, a field passivation layer, a source electrode, and a drain electrode, and further comprises:

[0009] The P-bottom region is located below the P-body region and is P-type doped. The doping concentration of the P-bottom region is greater than the doping concentration of the P-body region and less than the doping concentration of the P+ region.

[0010] The hole absorption region is P-type doped, columnar in shape, located within the JFET region of the SiC MOSFET device and extending into the N-drift region below the JFET region. The width of the hole absorption region is smaller than the width of the JFET region. The top of the hole absorption region is located below the gate. The bottom depth of the hole absorption region is greater than the depth of the P-bottom region and less than the depth of the P+ region. The hole absorption region includes a first absorption region, a second absorption region, and a third absorption region. The first absorption region corresponds to the N-drift region below the JFET region, the second absorption region corresponds to the P-bottom region, and the third absorption region corresponds to the P-body region. The doping concentration of the first absorption region is greater than the doping concentration of the third absorption region, and the doping concentration of the third absorption region is greater than the doping concentration of the second absorption region.

[0011] The SiC MOSFET device disclosed in this invention adds a P-bottom region, which increases the potential below the P-body region and forms a "potential buffer layer" nearby. This reduces the potential difference near the gate dielectric layer, alleviates the problem of hole accumulation caused by high-energy particle bombardment, and reduces the single-event gate breakdown probability. Simultaneously, the SiC MOSFET device adds a hole absorption region. The hole absorption region further optimizes the potential distribution near the gate dielectric layer, reduces the electric field strength near the gate dielectric layer, and provides an additional path for the accumulated holes to exit. The three-segment hole absorption region corresponds to the P-body region, the P-bottom region, and the N-drift region below the JFET region, respectively. Furthermore, the hole absorption region is configured with different doping concentrations in different parts: the doping concentration of the first absorption region is greater than that of the third absorption region, and the doping concentration of the third absorption region is greater than that of the second absorption region. This reduces lateral diffusion, thereby lowering the resistance of the JFET region. Ultimately, it optimizes the potential distribution near the gate dielectric layer without excessively increasing the resistance of the JFET region, reduces the accumulation of local holes, and provides additional outlet paths for accumulated holes, further mitigating single-event effects and reducing the probability of single-event gate breakdown.

[0012] In one embodiment, the depth of the JFET region is H, the doping depth of the first absorption region is H1, the doping depth of the second absorption region is H2, and the doping depth of the third absorption region is H3, wherein H1>H2>H>H3.

[0013] In one embodiment, the doping concentration of the P-bottom region ranges from 1×10⁻⁶. 18 cm -3 above.

[0014] In one embodiment, the doping depth of the P-bottom region is less than the doping depth of the P+ region.

[0015] In one embodiment, the longitudinal section of the gate dielectric layer corresponding to the JFET region along a third direction is a cap-shaped trapezoid, wherein the width of the JFET region is L; the width of the bottom of the cap-shaped trapezoid of the gate dielectric layer is JL1, and JL1 = 0.6L~0.8L; the width of the top of the cap-shaped trapezoid of the gate dielectric layer is JL2, and JL2 = 0.2L~0.6L; the maximum thickness of the cap-shaped trapezoid of the gate dielectric layer is T1, and the thickness of the gate dielectric layer outside the cap-shaped trapezoid is T2, and T1 ≥ 3T2.

[0016] The JFET region corresponds to a thicker gate dielectric layer, which can reduce the potential distribution in the JFET region and further mitigate single-event effects from the perspective of the gate dielectric layer, reducing the probability of single-event gate breakdown. Moreover, the longitudinal section of the gate dielectric layer corresponding to the JFET region along the third direction is a cap-shaped trapezoid, which can further optimize the potential distribution in the JFET region, making it more gradual.

[0017] In one embodiment, the SiC MOSFET device further includes:

[0018] A transition region, which is P-type doped and surrounds multiple cells of the SiC MOSFET device;

[0019] The hole connection region, which is P-type doped, is located within the N-drift region and is used to connect the hole absorption regions of different cells and to connect the hole absorption regions with the transition region.

[0020] In one embodiment, the hole absorption regions of the plurality of cells extend along a first direction and are interconnected or independent of each other, and the hole absorption regions of the plurality of cells are interconnected in a second direction through the hole connection region.

[0021] The interconnection of multiple cell hole absorption regions can further increase the outlet paths of accumulated holes, especially enabling multiple cells to share the accumulated holes of a single or local cell, thereby improving the overall radiation resistance stability of the SiC MOSFET device. When the multiple cell hole absorption regions along the first direction are independent of each other, the disconnected region lacks a P-type hole absorption region. The region without a hole absorption region can protect the top gate dielectric layer and reduce its electric field through the depletion of the hole absorption regions on both sides. This method can reduce the proportion of P-regions within the JFET region, optimizing and reducing the on-resistance of the device without compromising its radiation performance.

[0022] Another embodiment discloses a method for fabricating a SiC MOSFET device, wherein the cell of the SiC MOSFET device is the cell of the SiC MOSFET device described in any of the above embodiments, and the P-bottom region and the hole absorption are formed by an ion implantation process.

[0023] In one embodiment, the fabrication process of the gate dielectric layer includes:

[0024] A SiO2 layer is deposited on the surface of the N+SiC substrate;

[0025] A portion of the SiO2 material on both sides of the JFET region was removed using a dry etching process.

[0026] The remaining SiO2 material is etched using a wet etching process to form a gate dielectric layer with a cap-shaped trapezoidal longitudinal section in the central region. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a typical SiC MOSFET device structure;

[0028] Figure 2 This is a schematic diagram of a SiC MOSFET device structure provided in Embodiment 1 of the present invention;

[0029] Figure 3 This is a schematic diagram of a SiC MOSFET device structure provided in Embodiment 2 of the present invention;

[0030] Figure 4 This is a schematic diagram of another SiC MOSFET device structure provided in Embodiment 2 of the present invention;

[0031] Figure 5 This is a schematic diagram of a SiC MOSFET device structure provided in Embodiment 3 of the present invention (a cross-sectional view along the third direction at B-B').

[0032] Figure 6 This is a cross-sectional view of a SiC MOSFET device along the third direction at point A-A', provided in Embodiment 4 of the present invention.

[0033] Figure 7 This is a top view of a SiC MOSFET device provided in Embodiment 4 of the present invention;

[0034] Figure 8 This is a perspective view of a SiC MOSFET device provided in Embodiment 4 of the present invention;

[0035] Figure 9 A top view of a SiC MOSFET device in the first embodiment of the present invention (Embodiment 5);

[0036] Figure 10 A perspective view of a SiC MOSFET device according to the first embodiment of the present invention (V).

[0037] Figure 11 This is a top view of a SiC MOSFET device according to the second embodiment of the present invention (V).

[0038] Figure 12 A perspective view of a SiC MOSFET device according to the second embodiment of the present invention (V5);

[0039] Figure 13A cross-sectional view of a SiC MOSFET device along a third direction at C-C' in the second embodiment of the present invention;

[0040] Figure 14 This is a top view of another SiC MOSFET device in the second embodiment of the present invention;

[0041] Figure 15 A top view of yet another SiC MOSFET device in the second embodiment of the present invention;

[0042] Figure 16 A top view of a SiC MOSFET device in the third embodiment of the present invention;

[0043] Figure 17 A top view of a SiC MOSFET device according to the fourth embodiment of the present invention;

[0044] Figure 18 This is a schematic diagram of the fabrication steps of a SiC MOSFET device provided in Embodiment 7 of the present invention.

[0045] In the figure: 101, N+SiC substrate; 102, N-drift region; 103, P-body region; 104, P+ region; 105, N+ source region; 106, gate dielectric layer; 107, gate electrode; 108, field passivation layer; 109, source electrode; 110, drain electrode; 111, P-bottom region; 112, hole absorption region; 113, gradient buffer layer; 114, transition region; 115, hole connection region; 1121, first absorption region; 1122, second absorption region; 1123, third absorption region. Detailed Implementation

[0046] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional scope of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0048] Example 1

[0049] Example 1 discloses a SiC MOSFET device, such as Figure 2 As shown, the cell of the SiC MOSFET device includes: an N+ SiC substrate 101, an N- drift region 102, an N+ source region 105, a P- body region 103, a P+ region 104, a gate dielectric layer 106, a gate electrode 107, a field passivation layer 108, a source electrode 109, and a drain electrode 110. It also includes a P-bottom region 111 and a hole absorption region 112.

[0050] The N+SiC substrate 101 is N-type heavily doped and includes an epitaxial layer. In addition to SiC, it is also suitable for silicon-based substrates, GaAs substrates, GaN substrates, silicon-on-insulator (SOI) substrates, and other emerging substrates (such as Al2O3, graphene, MoS2, etc.).

[0051] The N-drift region 102 is located within the epitaxial layer of the N+SiC substrate 101 and is lightly doped with N-type.

[0052] The N-drift region 102 contains an N+ source region 105, a P-body region 103, and a P+ region 104. The N+ source region 105 is heavily N-type doped and plays a crucial role in the device's turn-on, conduction, and turn-off processes. The P-body region 103 is moderately P-type doped and is located between the N+ source region 105 and the N+SiC substrate 101, serving as a key region connecting the N+ source region 105, the JFET region, and the N+SiC substrate 101. The P+ region 104 is heavily P-type doped with a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 Located on both sides of the N+ source region 105, serving as the contact area or isolation area of ​​the device.

[0053] A gate dielectric layer 106 and a gate electrode 107 are disposed on the surface of the epitaxial layer (N-drift region 102) of the N+SiC substrate 101. The gate dielectric layer 106 is an insulating film located between the gate electrode 107 and the JFET region. Through electrical isolation and electric field modulation, it controls whether charge carriers can enter the JFET region, thereby determining the conduction state of the device. The gate electrode 107 is the control electrode of the device, and is activated by applying a voltage (V). G An electric field is induced below the gate dielectric layer 106, which modulates the carrier concentration in the JFET region, thereby determining whether the device is turned on. It is the "master switch" for the device operation.

[0054] The field passivation layer 108 is an insulating film (such as SiO2, SiN) covering the surface of the SiC MOSFET device. x Its core function is to protect devices from external environmental factors (such as moisture and ions), while optimizing the surface electric field distribution and suppressing leakage current and reliability failure.

[0055] The source electrode 109 is located on the outermost layer of the SiC MOSFET device and is electrically connected to the N+ source region 105. The drain electrode 110 is located on the back side of the N+ SiC substrate 101.

[0056] The P-bottom region 111 is located below the P-body region 103 and is P-type doped. The doping concentration of the P-bottom region 111 is greater than that of the P-body region 103 but less than that of the P+ region 104. The higher doping concentration of the P-bottom region 111 increases the potential below the P-body region 103, forming a "potential buffer layer" nearby. This suppresses the potential difference caused by hole accumulation, reduces the probability of parasitic transistor activation, alleviates the problem of hole accumulation caused by high-energy particle bombardment in space, and reduces the single-event gate breakdown probability.

[0057] The hole absorption region 112 is P-type doped, columnar in shape, located within the JFET region and extending into the N-drift region 102 below the JFET region. The width of the hole absorption region 112 is smaller than the width of the JFET region. The top of the hole absorption region 112 is located below the gate 107. The bottom depth of the hole absorption region 112 is greater than the depth of the P-bottom region 111 and less than the depth of the P+ region 104. The hole absorption region 112 includes a first absorption region 1121, a second absorption region 1122, and a third absorption region 1123. The first absorption region 1121 corresponds to the N-drift region 102 below the JFET region, the second absorption region 1122 corresponds to the P-bottom region 111, and the third absorption region 1123 corresponds to the P-body region 103. The doping concentration of the first absorption region 1121 is greater than the doping concentration of the third absorption region 1123, and the doping concentration of the third absorption region 1123 is greater than the doping concentration of the second absorption region 1122.

[0058] Wherein, the doping depth is the vertical distance between the bottom of the doped region and the surface of the epitaxial layer of the N+SiC substrate 101. Preferably, the JFET region is specifically the area between the symmetrically distributed P-body region 103 and P-bottom region 111. Figure 2 As shown, the depth of the JFET region is H, the doping depth of the first absorption region 1121 is H1, the doping depth of the second absorption region 1122 is H2, and the doping depth of the third absorption region 1123 is H3, wherein H1>H2>H>H3.

[0059] Furthermore, the first absorption region 1121 of the SiC MOSFET device has a doping depth H1 of 0.7μm~1.4μm; the second absorption region 1122 has a doping depth H2 of 0.5μm~0.8μm; the third absorption region 1123 has a doping depth H3 of 0.2μm~0.6μm, and the depth H of the JFET region is between H2 and H3. Furthermore, the doping depth H1 of the first absorption region 1121 of the SiC MOSFET device is 0.7μm, 0.8μm, 0.9μm, 1.0μm, 1.1μm, 1.2μm, 1.3μm, or 1.4μm, etc.; the doping depth H2 of the second absorption region 1122 is 0.5μm, 0.6μm, 0.7μm, or 0.8μm, etc.; and the doping depth H3 of the third absorption region 1123 is 0.2μm, 0.3μm, 0.4μm, 0.5μm, or 0.6μm, etc.

[0060] The doping concentration of the first absorption region 1121 of the SiC MOSFET device is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm-3 The doping concentration of the second absorption region 1122 is 5 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The doping concentration of the third absorption region 1123 is 7 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 Preferably, the doping concentration of the first absorption region 1121 of the SiC MOSFET device is 1×10⁻⁶. 17 cm -3 3×10 17 cm -3 5×10 17 cm -3 7×10 17 cm -3 9×10 17 cm -3 Or 1×10 18 cm -3 etc.; the doping concentration of the second absorption region 1122 is 5×10⁻⁶. 16 cm -3 6×10 16 cm -3 7×10 16 cm -3 8×10 16 cm -3 9×10 16 cm -3 Or 1×10 17 cm -3 etc.; the doping concentration of the third absorption region 1123 is 7×10⁻⁶. 16 cm -3 8×10 16 cm -3 9×10 16 cm -3 1×10 17 cm -3 2×10 17 cm -3 3×10 17 cm -3 4×10 17 cm -3 Or 5×10 17 cm -3 wait.

[0061] The hole absorption region 112 further optimizes the potential distribution near the gate dielectric layer 106 and reduces the electric field strength near the gate dielectric layer 106. It also provides an additional path for the extraction of accumulated holes. The three-segment hole absorption regions 112 with different doping concentrations also reduce the resistance of the JFET region. Specifically, since the doping concentration of the P-bottom region 111 is greater than that of the P-body region 103, and the doping concentration of the P-body region 103 is greater than that of the N-drift region 102, the doping concentration of the first absorption region 1121 (corresponding to the N-drift region 102 below the JFET region) is greater than that of the third absorption region 1123 (corresponding to the P-body region 103), and the doping concentration of the third absorption region 1123 is greater than that of the second absorption region 1122 (corresponding to the P-bottom region 111). Specifically, a second absorption region 1122 with a lower doping concentration is set for the region with a high doping concentration (P bottom region 111). This can reduce lateral diffusion, thereby optimizing the potential distribution near the gate dielectric layer 106 without excessively increasing the resistance of the JFET region, reducing the accumulation of local holes, and providing additional outlet paths for the accumulated holes, further mitigating the single-event effect and reducing the probability of single-event gate breakdown.

[0062] The doping concentration of the P-bottom region 111 ranges from 1×10⁻⁶. 18 cm -3 The above is specifically 3×10 18 cm -3 ~8×10 18 cm -3 Preferably, the doping concentration of the P-bottom region 111 ranges from 3 × 10⁻⁶. 18 cm -3 4×10 18 cm -3 5×10 18 cm -3 6×10 18 cm -3 7×10 18 cm -3 8×10 18 cm -3 wait.

[0063] The doping depth of the P-bottom region 111 is less than the doping depth of the P+ region 104, with a difference of 0.1 μm to 0.4 μm. Preferably, the difference between the doping depth of the P-bottom region and the doping depth of the P+ region is 0.1 μm, 0.2 μm, 0.3 μm, or 0.4 μm, etc.

[0064] The setting of the bottom region 111 of P can increase the potential of the lower part of the body region 103, form a "potential buffer layer" in the vicinity, reduce the potential difference near the gate dielectric layer 106, alleviate the problem of hole accumulation caused by high-energy particle bombardment in space, and reduce the single-particle gate penetration probability.

[0065] Example 2

[0066] Example 2 discloses another SiC MOSFET device, such as Figure 3 As shown, the thickness of the gate dielectric layer 106 of the SiC MOSFET device cell at the center of the JFET region is greater than the thickness at other locations. That is, the longitudinal section of the gate dielectric layer 106 along the third direction has a structure that is raised in the middle and flat on both sides.

[0067] This embodiment adopts a gate dielectric layer 106 structure with a raised center and gentle sides, which can reduce the potential distribution in the JFET region, further alleviate the single-event effect, and reduce the probability of single-event gate breakdown.

[0068] Preferred, such as Figure 4 As shown, the longitudinal section of the gate dielectric layer 106 corresponding to the JFET region along the third direction is a cap-shaped trapezoid. This cap-shaped trapezoid can be considered as consisting of an isosceles trapezoid plus a rectangle at its apex. This gate dielectric layer 106 can be implemented using a dry etching + wet etching process. The cap-shaped trapezoid design further optimizes the potential distribution in the JFET region, making it more gradual.

[0069] Preferably, the width of the JFET region is L, where L = 2μm~4μm; the width of the bottom of the trapezoidal top of the gate dielectric layer 106 is JL1, and JL1 = 0.6L~0.8L; the width of the top of the trapezoidal top of the gate dielectric layer 106 is JL2, and JL2 = 0.2L~0.6L; the maximum thickness of the trapezoidal top of the gate dielectric layer 106 is T1, and the thickness of the non-trapezoidal top of the gate dielectric layer 106 is T2, and T1 ≥ 3T2.

[0070] Specifically, the maximum thickness T1 at the top trapezoidal portion of the gate dielectric layer 106 is 100nm~300nm, and the thickness T2 at the non-top trapezoidal portion of the gate dielectric layer 106 is 30nm~70nm. Preferably, the maximum thickness T1 at the top trapezoidal portion of the gate dielectric layer 106 is 100nm, 120nm, 160nm, 200nm, 240nm, 280nm, or 300nm, etc., and the thickness T2 at the non-top trapezoidal portion of the gate dielectric layer 106 is 30nm, 40nm, 50nm, 60nm, or 70nm, etc.

[0071] Example 3

[0072] Example 3 discloses another SiC MOSFET device, such as Figure 5 As shown, the SiC MOSFET device further includes a gradient buffer layer 113, which is located between the N+SiC substrate 101 and the N-drift region 102, and the doping concentration of the gradient buffer layer 113 varies from the N-drift region 102 to the N+SiC substrate 101.

[0073] Specifically, the SiC MOSFET device employs a thick epitaxial layer and a non-penetrating N-drift region structure. The doping concentration of the gradient buffer layer gradually transitions from the N-drift region (same doping concentration as the N-drift region) to the N+SiC substrate (same doping concentration as the N+SiC substrate). For example, according to the standard for 1200V devices, the doping concentration of the N-drift region is 8 × 10⁻⁶. 15 cm -3 The depth is 12 μm; the doping concentration of the gradient buffer layer is 8 × 10⁻⁶. 15 cm -3 The doping concentration transitions to the N+SiC substrate, and the thickness of the gradient buffer layer is 1μm~3μm.

[0074] The design of the gradient buffer layer enables a smooth transition of the lattice constant, suppression of impurity diffusion, optimization of the interface electric field, and suppression of electric field spikes at the substrate and epitaxial layer under high electric field and single-particle recombination effect, thereby reducing the probability of single-event burnout (SEB).

[0075] Example 4

[0076] Example 4 discloses another SiC MOSFET device, such as Figure 6 , Figure 7 and Figure 8 As shown, the SiC MOSFET device further includes:

[0077] Transition region 114, which is P-type doped and surrounds multiple cells of the SiC MOSFET device, is used to shield the electric field of the surrounding devices (for ease of observation). Figure 8 (Transition area not shown in the text)

[0078] Hole connection region 115, located within the N-drift region, is used to connect hole absorption regions 112 of different cells and to connect the hole absorption regions 112 with the transition region 114.

[0079] In this embodiment, the hole connection region connects the hole absorption region and the transition region, enabling the entire SiC MOSFET device to handle the conduction of locally accumulated holes. This alleviates the problem of hole accumulation caused by high-energy particle bombardment in space and reduces the single-event gate breakdown probability.

[0080] Specifically, the hole-connecting region can be the same as the first absorption region, and / or the same as the second absorption region, and / or the same as the third absorption region. That is, the hole-connecting region can be integrally formed with the first absorption region. Alternatively, the hole-connecting region can be integrally formed with the first and second absorption regions. Alternatively, the hole-connecting region can be integrally formed with the first, second, and third absorption regions. Furthermore, the hole-connecting region can also be connected through the P-body region and / or the P+ region.

[0081] It should be noted that, in this embodiment of the invention, the hole absorption region structure below the gate is the hole absorption region of the SiCMOSFET device, while the structures at other locations used to connect the hole absorption region are hole connection regions. Even if the hole connection region has the same or similar structure as the hole absorption region, it can still absorb and conduct holes, but the function of the hole connection region is still mainly to connect, and its location is not below the gate.

[0082] Preferred, such as Figure 6 , Figure 7 and Figure 8 As shown, the hole connection region 115 is identical to and integrally formed with the first absorption region 1121. In this way, charge carriers can be extracted from both sides of the hole connection region 115, further reducing the on-resistance of the JFET region.

[0083] Example 5

[0084] Example 5 discloses another SiC MOSFET device, wherein the hole absorption regions of the plurality of cells extend along a first direction and are interconnected or independent of each other, and the hole absorption regions of the plurality of cells are interconnected in a second direction through the hole connection region.

[0085] In the first method, the hole absorption regions of multiple cells extend along a first direction and are interconnected, and the hole absorption regions of the multiple cells are interconnected in a second direction through the hole connection region, and finally the hole absorption regions and the hole connection region are distributed in a network.

[0086] Specifically, such as Figure 6 (Cross-section view) Figure 7 (Top view) and Figure 8As shown in the (stereoscopic view), the multiple cell hole absorption regions 112 below the same gate are a single structure, extending along a first direction as multiple parallel straight lines; along a second direction, the hole absorption regions 112 are connected by the hole connection region 115, passing through the P+ region 104, and are connected in multiple parallel straight lines. The cross-section along the third direction at A-A' is shown below. Figure 7 As shown.

[0087] Or, such as Figure 9 (Top view) and Figure 10 As shown in the (stereoscopic view), along the first direction, multiple cell hole absorption regions 112 below the same gate are an integral structure and are arranged in multiple parallel straight lines along the first direction; along the second direction, the hole absorption regions 112 are connected by the hole connection regions 115 and are connected in multiple parallel straight lines through the N-drift regions 102 between the P+ regions 104. The cross-section along the third direction at B-B' is shown below. Figure 5 As shown.

[0088] The second method: the hole absorption regions of the plurality of cells extend along the first direction and are independent of each other, and the hole absorption regions of the plurality of cells are interconnected in the second direction through the hole connection region.

[0089] Specifically, such as Figure 11 (Top view) Figure 12 (3D diagram) and Figure 13 As shown in the cross-sectional view, multiple cell hole absorption regions 112 below the same gate are arranged in pairs as an integral structure, and each group of hole absorption regions 112 is independent of each other; hole connection regions 115 (integrated with the hole absorption regions 112) are distributed in multiple "I" shapes along the first direction, and connect the multiple hole absorption regions 112 in the second direction through the P-body region 103 and the P+ region 104. The longitudinal section along the third direction at C-C' is shown below. Figure 13 As shown.

[0090] Or, such as Figure 14 As shown, along the first direction, multiple cell hole absorption regions 112 below the same gate are independent of each other, and the hole connection region 115 along the second direction passes through the P+ region 104 and is connected to the hole absorption regions 112 distributed in the second direction by multiple parallel straight lines.

[0091] Or, such as Figure 15 As shown, along the first direction, multiple cell hole absorption regions 112 below the same gate are independent of each other, and the hole connection region 115 connects the hole absorption regions 112 distributed in the second direction through the N-drift region between the P+ regions 104 in multiple parallel straight lines along the second direction.

[0092] Furthermore, the connection methods of the hole absorption region may also include the following:

[0093] The third method: the hole absorption regions of multiple cells are interconnected only along the first direction.

[0094] Specifically, such as Figure 16 As shown, along the first direction, the hole absorption regions 112 below the same gate are an integral structure and interconnected, and together with the gate, they form multiple straight lines parallel to each other along the first direction. The two ends of the hole absorption region 112 are connected to the transition region 114 (the device of this type does not have a hole connection region structure).

[0095] The fourth method: The hole absorption regions of multiple cells are interconnected along the first direction and also along the direction between the second direction, and finally the hole absorption regions and hole connection regions are distributed in a network.

[0096] Specifically, such as Figure 17 As shown, the multiple cell hole absorption regions 112 below the same gate are an integral structure and are arranged in multiple parallel straight lines along the first direction; multiple parallel hole connection regions 115 are provided between the first direction and the second direction (e.g., at an angle of 30°, 45°, or 60° to the second direction).

[0097] In this embodiment, when multiple cell hole absorption regions below the same gate (along the first direction) are independent of each other, the disconnected region has no P-type hole absorption region. The region without a hole absorption region can protect the top gate dielectric layer and reduce its electric field through the depletion of hole absorption regions on both sides. This method can reduce the proportion of P-regions within the JFET region, optimizing and reducing the on-resistance of the device without compromising its irradiation performance.

[0098] It should be noted that the arrangement of the hole-connecting region is not limited to the direction along the second direction, the direction between the second and first directions, or parallel straight lines, line segments, U-shapes, and S-shapes. It can be arranged differently according to different cell distributions. Furthermore, whether the hole-connecting region passes through the P-body region and / or the P+ region depends on the structure and location of the hole-connecting region. That is, when the hole-connecting region is the same as the first absorption region, such as... Figure 6 , Figure 7 and Figure 8 As shown, the hole connection region 115 is connected via the P+ region 104. When the hole connection region is the same as the first absorption region, the second absorption region, and the third absorption region, as... Figure 11 , Figure 12 and Figure 13As shown, the cavity connection region 115 is connected in the second direction via the P+ region 104 and the P-body region 103.

[0099] It should be noted that the first direction is the direction of the gate finger (pointing along the gate); the second direction is parallel to the N+SiC substrate and perpendicular to the first direction; and the third direction is perpendicular to the N+SiC substrate. Furthermore, for ease of understanding, some structures of the SiC MOSFET device (e.g., gate, N+ source region, and transition region) are not explicitly shown in some embodiment drawings (especially top views and perspective views), but some structures well-known to those skilled in the art are present in the SiC MOSFET devices disclosed in the embodiments of this invention.

[0100] Example 6

[0101] Example 6 discloses a method for fabricating a SiC MOSFET device. The cell of the SiC MOSFET device fabricated using this method is the same as the cell of the SiC MOSFET device disclosed in any of the above examples. The P-bottom region and hole absorption of the SiC MOSFET device are formed by ion implantation.

[0102] The fabrication process of the gate dielectric layer includes:

[0103] A SiO2 layer is deposited on the surface of the N+SiC substrate;

[0104] A portion of the SiO2 material on both sides of the JFET region was removed using a dry etching process.

[0105] The remaining SiO2 material is etched using a wet etching process to form a gate dielectric layer with a cap-shaped trapezoidal longitudinal section in the central region.

[0106] Example 7

[0107] Example 7 discloses a specific method for fabricating a SiC MOSFET device, such as... Figure 18 As shown, the method includes:

[0108] Step S1: As Figure 18 In section 18a, an N+SiC substrate 101 with an epitaxial layer is prepared. The N+SiC substrate 101 is made of silicon carbide, and the doping concentration of its epitaxial layer is 8 × 10⁻⁶. 15 cm -3The epitaxial layer has a thickness of 10 μm. A gradient buffer layer 113 with a thickness of 2 μm is provided between the epitaxial layer and the N+SiC substrate 101. After the epitaxial layer growth is completed, RCA cleaning is performed to remove contaminants and particles from the wafer surface. The epitaxial layer that is not subsequently doped is the N-drift region 102 of the SiC MOSFET device.

[0109] Step S2: As Figure 18 In the 18b region, P-body region 103 and P-bottom region 111 are formed. Specifically, the first mask growth etching is performed, with an oxide mask thickness of 2 μm. Photolithography is then performed, followed by implantation of the intermediate-doped P-body region 103 and P-bottom region 111. The implantation type is P-type, and Al is implanted. The doping concentration of P-body region 103 is 4 × 10⁻⁶. 17 cm -3 The doping concentration of the bottom region 111 is 4 × 10⁻⁶. 18 cm -3 .

[0110] Step S3: Cleaning, performing a second mask growth, with an oxide mask thickness of 1 μm, photolithography, N+ source region implantation, implantation type N-type, doping concentration 1×10⁻⁶ 19 cm -3 This forms an N+ source region of 105 (e.g.) Figure 18 18c in the middle.

[0111] Step S4: Cleaning, performing the third mask growth, with an oxide mask thickness of 2 μm, photolithography, hole absorption region implantation, implantation type P-type, implantation Al, using six high-energy implantations from D1 to D6 to form the hole absorption region 112 (e.g., Figure 18 (18d in the middle).

[0112] Among them, D1 (20keV~40keV) and D2 (40keV~200keV) form the third absorption region 1123, with a doping concentration range of 7×10⁻⁶. 16 cm -3 ~5×10 17 cm -3 The depth is 0.2μm~0.6μm. D3 (200keV~300keV) and D4 (400keV~500keV) form the second absorption region 1122, with a doping concentration range of 5×10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The depth is 0.5μm~0.8μm. D5 (500keV~600keV) and D6 (600keV~900keV) form the first absorption region 1121, with a doping concentration range of 1×10⁻⁶. 17 cm -3 ~1×10 18cm -3 The depth is 0.7μm to 1.4μm. In this step, the hole connection region can be integrally formed with the hole absorption region 112 mentioned above.

[0113] Step S5: Cleaning, performing the fourth mask growth, with an oxide mask thickness of 2 μm, photolithography, P+ region implantation, P-type implantation, and a doping concentration of 1 × 10⁻⁶. 20 cm -3 Forming P+ region 104 (e.g.) Figure 18 (18e in the text). The transition region can be formed in the same injection step as the P+ region.

[0114] Step S6: Perform activation annealing on all injections at a temperature of 1500℃~1850℃ for 30min~60min.

[0115] Step S7: After sacrificial oxidation and cleaning, a gate dielectric layer 106 (e.g., ...) is formed on the surface of the epitaxial layer of the N+SiC substrate. Figure 18 (18f in the text). Specifically, a 200±2nm SiO2 layer is deposited using low-pressure chemical vapor deposition (LPCVD). Dry etching is then used to etch away a portion of the SiO2 material on both sides of the JFET region, achieving a thickness of 100±5nm. Next, a wet BOE (Buffered Oxide Etch) etching process is employed, using a 6:1 ratio of hydrofluoric acid (HF) to ammonium fluoride (NH4F) to achieve a thickness of 100±5nm, etching beveled edges on both sides of the thick SiO2 layer above the JFET region. This forms a gate dielectric layer 106 with a cap-shaped trapezoidal cross-section in the central region. The gate dielectric layer 106 is then annealed with N2O at a temperature of 1200℃ for 30 minutes.

[0116] Step S8: Deposit polysilicon and anneal the polysilicon with POCL3 to dope P element into the polysilicon to form gate 107 (e.g. Figure 18 (18g in the sample).

[0117] Step S9: Low-pressure chemical vapor deposition is used to deposit a field passivation layer 108 (e.g., for the gate and N+ source regions) to form the gate and N+ source regions. Figure 18 (18h in the middle).

[0118] Step S10: Photolithography, to set the opening of the gate.

[0119] Step S11: Magnetron sputtering is used to sputter metallic nickel, followed by annealing in a rapid annealing apparatus to form an ohmic contact in the N+ source region. A thick Al deposition is then performed on the front side to form the source electrode 109 (e.g., ...). Figure 18 (18i in the middle).

[0120] Step S12: Using magnetron sputtering, metallic nickel is sputtered onto the back side, followed by laser annealing, and then a thick TiNiAg metal deposition is performed on the back side to form the drain electrode 110 (e.g., Figure 18 (18j in the middle).

[0121] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The terms "first" and "second" used in this document are for distinction only and are not intended to limit the content of this invention.

[0122] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A SiC MOSFET device, wherein the cell of the SiC MOSFET device comprises: The N+SiC substrate, N- drift region, N+ source region, P- body region, P+ region, gate dielectric layer, gate electrode, field passivation layer, source electrode, and drain electrode are characterized by further comprising: The P-bottom region is located below the P-body region and is P-type doped. The doping concentration of the P-bottom region is greater than the doping concentration of the P-body region and less than the doping concentration of the P+ region. The hole absorption region is P-type doped, columnar in shape, located within the JFET region of the SiC MOSFET device and extending into the N-drift region below the JFET region. The width of the hole absorption region is smaller than the width of the JFET region. The top of the hole absorption region is located below the gate. The bottom depth of the hole absorption region is greater than the depth of the P-bottom region and less than the depth of the P+ region. The hole absorption region includes a first absorption region, a second absorption region, and a third absorption region. The first absorption region corresponds to the N-drift region below the JFET region, the second absorption region corresponds to the P-bottom region, and the third absorption region corresponds to the P-body region. The doping concentration of the first absorption region is greater than the doping concentration of the third absorption region, and the doping concentration of the third absorption region is greater than the doping concentration of the second absorption region.

2. The SiC MOSFET device according to claim 1, characterized in that, The depth of the JFET region is H, the doping depth of the first absorption region is H1, the doping depth of the second absorption region is H2, and the doping depth of the third absorption region is H3, wherein H1>H2>H>H3.

3. The SiC MOSFET device according to claim 1, characterized in that, The doping concentration range of the P-bottom region is 1×10⁻⁶. 18 cm -3 above.

4. The SiC MOSFET device according to claim 1, characterized in that, The doping depth of the bottom P region is less than the doping depth of the P+ region.

5. The SiC MOSFET device according to claim 1, characterized in that, The longitudinal section of the gate dielectric layer corresponding to the JFET region along the third direction is a cap-shaped trapezoid, wherein the third direction is perpendicular to the N+SiC substrate; the width of the JFET region is L; the width of the bottom of the cap-shaped trapezoid is JL1, and JL1 = 0.6L~0.8L; the width of the top of the cap-shaped trapezoid is JL2, and JL2 = 0.2L~0.6L; the maximum thickness of the gate dielectric layer corresponding to the cap-shaped trapezoid is T1, and the thickness of the gate dielectric layer corresponding to the non-cap-shaped trapezoid is T2, and T1 ≥ 3T2.

6. The SiC MOSFET device according to claim 1, characterized in that, Also includes: A transition region, which is P-type doped and surrounds multiple cells of the SiC MOSFET device; The hole connection region, which is P-type doped, is located within the N-drift region and is used to connect the hole absorption regions of different cells and to connect the hole absorption regions with the transition region.

7. The SiC MOSFET device according to claim 6, characterized in that, The hole absorption regions of the plurality of cells extend along a first direction and are interconnected or independent of each other, and the hole absorption regions of the plurality of cells are interconnected in a second direction through the hole connection region; the first direction is the direction of the gate finger; the second direction is parallel to the N+SiC substrate and perpendicular to the first direction.

8. The SiC MOSFET device according to claim 6, characterized in that, The hole connection region is integrally formed with the first absorption region.

9. A method for fabricating a SiC MOSFET device, characterized in that, The cell of the SiC MOSFET device is the cell of the SiC MOSFET device according to any one of claims 1 to 8, and the P-bottom region and the hole absorption region are formed by ion implantation.

10. The method for fabricating the SiC MOSFET device according to claim 9, characterized in that, The fabrication process of the gate dielectric layer includes: A SiO2 layer is deposited on the surface of an N+SiC substrate; A portion of the SiO2 material on both sides of the JFET region was removed using a dry etching process. The remaining SiO2 material is etched using a wet etching process to form a gate dielectric layer with a cap-shaped trapezoidal longitudinal section in the central region.

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