Back contact cell and method of manufacturing the same, photovoltaic module

Abstract

The embodiment of the present application relates to the field of photovoltaics, and provides a back contact cell, a manufacturing method thereof and a photovoltaic module, the back contact cell comprising: a substrate having a first surface and a second surface opposite to each other along a first direction, the second surface having first regions and second regions arranged alternately along a second direction; a first dielectric layer and a first doped layer stacked on the first regions, the first doped layer having P-type doping elements; a second dielectric layer and a second doped layer stacked on the second regions, the second doped layer having N-type doping elements; wherein the first doped layer comprises N layers of first doped films stacked, and along a direction away from the substrate, a crystallization rate of an (N-1)th layer of the first doped films is higher than that of an Nth layer of the first doped films, N being a positive integer greater than or equal to 2. The embodiment of the present application is at least beneficial to improving the photoelectric conversion efficiency of the back contact cell.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaics, and in particular to a back contact cell, a manufacturing method thereof, and a photovoltaic module. BACKGROUND

[0002] Solar cells are increasingly used as a sustainable clean energy source. A solar cell is a device that uses the photovoltaic principle to generate carriers to convert the light energy of the sun into electrical energy. Grid lines are usually used in solar cells to lead out the carriers, so as to effectively utilize the electrical energy. The mainstream types of current solar cells include BC cells (Back Contact), TOPCON (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and real cell), and heterojunction cells, etc.

[0003] In order to further avoid the shading of the grid lines on the front surface of the solar cell, the research on BC cells (Back Contact) is increasingly in-depth. By designing film layers with different characteristics on different regions of the back surface of the BC cell, the optical loss is reduced and the recombination of the photo-generated carriers is lowered, so as to improve the photoelectric conversion efficiency of the BC cell.

[0004] However, the cell efficiency of the current BC cell still needs to be further improved. SUMMARY

[0005] The present application provides a back contact cell and a manufacturing method thereof, a photovoltaic module, and a manufacturing method of a back contact cell of a photovoltaic module, which at least helps to improve the photoelectric conversion efficiency of the back contact cell.

[0006] According to some embodiments of the present application, the present application provides a back contact cell, which includes: a substrate having a first surface and a second surface opposite to each other along a first direction, the second surface having first regions and second regions arranged alternately along a second direction; a first dielectric layer and a first doped layer stacked on the first regions, the first doped layer having P-type doped elements; a second dielectric layer and a second doped layer stacked on the second regions, the second doped layer having N-type doped elements; wherein the first doped layer includes N layers of first doped films stacked, and along a direction away from the substrate, the crystallization rate of the (N-1)th first doped film is higher than that of the Nth first doped film, N being a positive integer greater than or equal to 2.

[0007] In some embodiments, the grain size of the (N-1)th first doped film is smaller than that of the Nth first doped film.

[0008] In some embodiments, N is 2, the crystallization rate of the first doped film of the (N-1)th layer is greater than or equal to 99%, and the crystallization rate of the first doped film of the Nth layer is less than 95%.

[0009] In some embodiments, N is 2, the grain size of the first doped film of the (N-1)th layer is 100 nm to 180 nm, and the grain size of the first doped film of the Nth layer is 190 nm to 300 nm.

[0010] In some embodiments, along the first direction, the thickness of the first doped film of the (N-1)th layer is less than the thickness of the first doped film of the Nth layer.

[0011] In some embodiments, along the first direction, N is 2, the thickness of the first doped film of the (N-1)th layer is 10 nm to 60 nm, and the thickness of the first doped film of the Nth layer is 10 nm to 500 nm.

[0012] In some embodiments, the second doped layer includes M layers of second doped films stacked, along the direction away from the substrate, the crystallization rate of the second doped film of the (M-1)th layer is higher than the crystallization rate of the second doped film of the Mth layer, and M is a positive integer greater than or equal to 2.

[0013] In some embodiments, the grain size of the second doped film of the (M-1)th layer is less than the grain size of the second doped film of the Mth layer.

[0014] In some embodiments, along the first direction, the thickness of the first doped layer is greater than the thickness of the second doped layer.

[0015] In some embodiments, at least one of the first doped layer and the second doped layer is polycrystalline silicon further doped with carbon elements or nitrogen elements; or, the material of the second doped layer includes amorphous silicon.

[0016] In some embodiments, the material of at least one of the first dielectric layer and the second dielectric layer includes aluminum oxide or silicon nitride; or, the material of at least one of the first dielectric layer and the second dielectric layer includes at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; or, the material of the second dielectric layer includes at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0017] In some embodiments, the doping concentration of the P-type doping elements in the first doped layer is 5×10 18 atom / cm 3 ~8×10 20 atom / cm 3; and / or, the doping concentration of the N-type doping element in the second doped layer is 5x10 19 atom / cm 3 ~9x10 20 atom / cm 3 .

[0018] In some embodiments, the back contact cell further comprises: a first passivation layer located on the first surface and at least on the surfaces of the first doped layer and the second doped layer away from the substrate; a second passivation layer located on the surface of the first passivation layer away from the substrate; wherein the thickness of the first passivation layer is 3nm-10nm along the first direction; and / or, the thickness of the second passivation layer is 70nm-90nm along the first direction.

[0019] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a manufacturing method of a back contact cell, comprising: providing a substrate, the substrate having a first surface and a second surface opposite along a first direction, the second surface having first regions and second regions arranged alternately along a second direction; forming a first doped layer and a first dielectric layer stacked on the first regions, the first doped layer having P-type doping elements; forming a second doped layer and a second dielectric layer stacked on the second regions, the second doped layer having N-type doping elements; wherein the step of forming the first doped layer comprises: forming a first semiconductor layer on the second surface by using a first deposition process, the first deposition process comprising N deposition stages connected in sequence, the deposition temperature of the (N-1)th deposition stage being lower than the deposition temperature of the Nth deposition stage, N being a positive integer greater than or equal to 2; performing a first doping treatment on the first semiconductor layer, so that the first semiconductor layer is converted into an initial first doped layer doped with P-type doping elements; performing a first patterning treatment on the initial first doped layer, only the initial first doped layer located on the first regions being reserved as the first doped layer, and the first doped layer comprising N first doped films stacked, the crystallization rate of the (N-1)th first doped film being higher than the crystallization rate of the Nth first doped film along the direction away from the substrate.

[0020] In some embodiments, the step of forming the second doped layer comprises: forming a second semiconductor layer on the second surface by using a second deposition process, the second deposition process comprising M temperature control stages connected in sequence, a process temperature of an (M-1)-th temperature control stage being lower than a process temperature of an M-th temperature control stage, M being a positive integer greater than or equal to 2; performing a second doping treatment on the second semiconductor layer, so that the second semiconductor layer is converted into an initial second doped layer doped with an N-type doping element; performing a second patterning treatment on the initial second doped layer, only the initial second doped layer located on the second region being reserved as the second doped layer, and the second doped layer comprising M layers of second doped films stacked, a crystallization rate of an (M-1)-th layer of the second doped films being higher than a crystallization rate of an M-th layer of the second doped films in a direction away from the substrate.

[0021] In some embodiments, M is 2, the second deposition process comprises a first temperature control stage and a second temperature control stage connected in sequence, the process temperature of the first temperature control stage being 520-570℃, and the process temperature of the second temperature control stage being 580-650℃.

[0022] In some embodiments, before forming the second semiconductor layer, a semi-finished back contact cell to be formed into the second semiconductor layer is placed into a reaction chamber; during the process of forming the second semiconductor layer by using the second deposition process, a carbon-containing gas or a nitrogen-containing gas is introduced into the reaction chamber, so that the second semiconductor layer formed is doped with carbon elements or nitrogen elements.

[0023] In some embodiments, in the step of performing the second doping treatment on the second semiconductor layer, a second protective layer is also formed on a side of the initial second doped layer away from the substrate; the second protective layer located on the first region is removed by using a second laser; the initial second doped layer located on the first region is removed by using a second etching process, and the remaining initial second doped layer is the second doped layer; wherein the second laser is a purple skin laser or a green skin laser, and the power of a laser generating the second laser is 5-80W.

[0024] In some embodiments, N is 2, the first deposition process comprises a first deposition stage and a second deposition stage connected in sequence, the deposition temperature of the first deposition stage being 520-570℃, and the deposition temperature of the second deposition stage being 580-650℃.

[0025] In some embodiments, before forming the first semiconductor layer, a semi-finished back contact cell to be formed into the first semiconductor layer is put into a reaction chamber; during the forming of the first semiconductor layer by using the first deposition process, a carbon-containing gas or a nitrogen-containing gas is introduced into the reaction chamber, so that the first semiconductor layer formed is doped with carbon elements or nitrogen elements.

[0026] In some embodiments, in the step of performing the first doping treatment on the first semiconductor layer, a first protective layer is further formed on a side of the initial first doped layer away from the substrate; the first protective layer on the second region is removed by using a first laser; the initial first doped layer on the second region is removed by using a first etching process, and the remaining initial first doped layer is the first doped layer; wherein the first laser is a purple skin laser or a green skin laser, and the power of the laser generating the first laser is 5W-80W.

[0027] According to some embodiments of the present application, a further aspect of the embodiments of the present application further provides a photovoltaic module, comprising: a cell string connected by a plurality of back contact cells according to any one of the above embodiments or formed by the manufacturing method of the back contact cells according to any one of the above embodiments; an encapsulation adhesive film used for covering a surface of the cell string; and a cover plate used for covering a surface of the encapsulation adhesive film away from the cell string.

[0028] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0029] The first doped layer is designed as a laminated structure including multiple first doped films with different crystallization rates. On one hand, the first doped film close to the substrate with a high crystallization rate can improve the uniformity of the film itself, which helps to avoid the grain of the first doped film close to the substrate from damaging other film layers, such as the first dielectric layer and the substrate, so as to ensure the stability of the performance of other film layers close to the first doped layer, improve the passivation effect of other film layers close to the first doped layer on the substrate, and thus reduce the recombination probability of photo-generated carriers. On the other hand, the first doped film far from the substrate has a low crystallization rate, which helps to improve the surface roughness of the first doped film far from the substrate, such as making the surface of the first doped film far from the substrate have large grains. Thus, when designing the electrode on the side of the first doped layer far from the substrate, the low crystallization rate of the first doped film can be used to improve the contact performance between the first doped layer and the electrode, so as to improve the collection efficiency of the electrode on photo-generated carriers, and thus improve the fill factor of the back contact cell. In this way, the passivation effect on the substrate can be improved by the cooperation of the first doped layer and the first dielectric layer, and the migration of photo-generated carriers in the first doped layer can be reduced, so as to further improve the photoelectric conversion efficiency of the back contact cell. BRIEF DESCRIPTION OF DRAWINGS

[0030] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which are shown by way of illustration in the drawings and are not necessarily drawn to scale. Unless otherwise noted, the drawings provided herein are not to scale. The embodiments herein will be described with frequent reference to the drawings, wherein like references indicate to like elements. As will be realized, the embodiments are capable of modifications in various obvious aspects, all without departing from the spirit and scope of the present disclosure. Accordingly, while the specific embodiments have been illustrated and described, such are by way of example only.

[0031] Figure 1 A first partial cross-sectional schematic view of a back contact cell according to an embodiment of the present application;

[0032] Figure 2 A second partial cross-sectional schematic view of a back contact cell according to an embodiment of the present application;

[0033] Figure 3 A third partial cross-sectional schematic view of a back contact cell according to an embodiment of the present application;

[0034] Figure 4 A process flow diagram corresponding to a manufacturing method of a back contact cell according to another embodiment of the present application;

[0035] Figure 5 A partial cross-sectional view of a back contact cell after forming a first semiconductor layer in a method of manufacturing a back contact cell according to another embodiment of the present application;

[0036] Figure 6 A partial cross-sectional view of a back contact cell after performing a first doping process in a method of manufacturing a back contact cell according to another embodiment of the present application;

[0037] Figure 7 A partial cross-sectional view of a back contact cell after performing a first laser process in a method of manufacturing a back contact cell according to another embodiment of the present application;

[0038] Figure 8 A partial cross-sectional view of a back contact cell after performing a first etching process in a method of manufacturing a back contact cell according to another embodiment of the present application;

[0039] Figure 9 A partial cross-sectional view of a back contact cell after forming a second semiconductor layer in a method of manufacturing a back contact cell according to another embodiment of the present application;

[0040] Figure 10 A partial cross-sectional view of a back contact cell after performing a second doping process in a method of manufacturing a back contact cell according to another embodiment of the present application;

[0041] Figure 11 A partial cross-sectional view of a back contact cell after performing a second laser process in a method of manufacturing a back contact cell according to another embodiment of the present application;

[0042] Figure 12 A partial perspective view of a cell string in a photovoltaic module according to yet another embodiment of the present application;

[0043] Figure 13 A partial cross-sectional view of a photovoltaic module according to yet another embodiment of the present application.

[0044] BRIEF DESCRIPTION OF DRAWINGS

[0045] 100, substrate; 110, first surface; 120, second surface; 1201, first region; 1202, second region; 1203, isolation region; 101, first dielectric layer; 111, initial first dielectric layer; 102, first doped layer; 112, first doped film; 1121, first inner doped film; 1122, first outer doped film; 122, initial first doped layer; 1221, initial first inner doped layer; 1222, initial first outer doped layer; 103, second dielectric layer; 113, initial second dielectric layer; 104, second doped layer; 114, second doped film; 1141, second inner doped film; 1142, second outer doped film; 124, initial second doped layer; 1241, initial second inner doped layer; 1242, initial second outer doped layer; 105, first semiconductor layer; 115, first semiconductor film; 116, first protective layer; 126, second protective layer; 107, second semiconductor layer; 117, second semiconductor film; 118, first passivation layer; 128, second passivation layer; 119, first electrode; 129, second electrode; 40, back contact cell; 41, encapsulation film; 42, cover plate; 43, conductive ribbon. DETAILED DESCRIPTION

[0046] As known from the background, the cell efficiency of BC cells still needs to be further improved.

[0047] It is found through analysis that, in BC cells, when the doped layer is used as a field passivation layer and a transport layer of photo-generated carriers, the crystallization rate of the doped layer is in a single numerical range, which makes it difficult to achieve a good balance between improving the passivation effect on BC cells and reducing the migration resistance of photo-generated carriers in the doped layer.

[0048] The embodiment of the present application provides a back contact cell, a manufacturing method thereof and a photovoltaic module. In the back contact cell, the first doped layer is designed as a laminated structure including a plurality of first doped films with different crystallization rates. On one hand, the first doped film close to the substrate with a high crystallization rate can improve the uniformity of the film layer itself, which helps to make the surface of the first doped film close to the substrate with a high crystallization rate free of grain precipitation, so that the first doped film close to the substrate can be designed with a high crystallization rate to avoid damage to other film layers, such as the first dielectric layer and the substrate, which are close to the first doped layer, so as to ensure the stability of the performance of other film layers close to the first doped layer, improve the passivation effect of other film layers close to the first doped layer on the substrate, and further reduce the recombination probability of photo-generated carriers. On the other hand, the first doped film away from the substrate has a low crystallization rate, which helps to improve the surface roughness of the first doped film away from the substrate, such as making the surface of the first doped film away from the substrate have large grains, so that when the electrode is designed on the side of the first doped layer away from the substrate, the contact performance between the first doped layer and the electrode can be improved by means of the first doped film with a low crystallization rate, so as to improve the collection efficiency of the electrode on the photo-generated carriers, and further improve the fill factor of the back contact cell. Such multi-aspect effects can not only improve the passivation effect on the substrate by the cooperation of the first doped layer and the first dielectric layer, but also reduce the migration hindrance of the photo-generated carriers in the first doped layer, so as to further improve the photoelectric conversion efficiency of the back contact cell.

[0049] In the description of the embodiments of the present application, the technical terms "first", "second", and the like are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0050] In this document, the term "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor is it independent or alternative to other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0051] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent: A exists, A and B exist, and B exists. In addition, the character " / " in this document generally represents a "or" relationship between the front and rear associated objects.

[0052] In the description of the embodiments of the present application, the term "a plurality of" refers to two or more (including two), and similarly, "a plurality of groups" refers to two or more groups (including two groups), and "a plurality of pieces" refers to two or more pieces (including two pieces).

[0053] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0054] In the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the technical terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0055] In the corresponding drawings of the embodiments of the present application, the thickness and area of the layers are exaggerated for better understanding and ease of description. When describing that a component (such as a layer, a film, a region or a substrate) is on or on the surface of another component, the component can be "directly" on the surface of the other component, or there can be a third component between the two components. On the contrary, when describing that a component is on the surface of another component or that a component surface forms or is provided with another component, it means that there is no third component between the two components. In addition, when describing that a component is "formed substantially" on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a part of the edge of the entire surface.

[0056] In the description of the embodiments of the present application, when a certain component "includes" another component, unless otherwise specified, other components are not excluded and can be further included. In addition, when a layer, film, region, plate or the like component is referred to as "on" another component, it can be "directly on" the other component (i.e. between the other component surface and the layer, film, region, plate or the like component, there is no other component), or there can be another component present therebetween. In addition, when a layer, film, region, plate or the like component is "directly on" another component, or when a layer, film, region, plate or the like component is on the surface of another component, it means that there is no other component therebetween.

[0057] The terms used in the description of various described embodiments herein are only for describing specific embodiments, and are not intended to be limiting. As used in the description of various embodiments described and the appended claims, "the component" is also intended to include the plural form, unless the context clearly indicates otherwise. Among them, the components include layers, films, regions or plates and the like components.

[0058] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present application, many technical details are presented in order to enable the reader to better understand the embodiments of the present application. However, the technical solutions claimed by the embodiments of the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0059] An embodiment of the present application provides a back contact battery, which will be described in detail below with reference to the accompanying drawings.

[0060] Reference Figure 1 , Figure 2 or Figure 3 , the back contact battery comprises: a substrate 100, the substrate 100 has a first surface 110 and a second surface 120 opposite along a first direction X, the second surface 120 has a first area 1201 and a second area 1202 arranged alternately along a second direction Y; a first dielectric layer 101 and a first doped layer 102 are stacked on the first area 1201, the first doped layer 102 has P-type doping elements; a second dielectric layer 103 and a second doped layer 104 are stacked on the second area 1202, the second doped layer 104 has N-type doping elements; wherein the first doped layer 102 comprises N stacked first doped films 112, along the direction away from the substrate 100, the crystallization rate of the (N-1)th first doped film 112 is higher than that of the Nth first doped film 112, N is a positive integer greater than or equal to 2.

[0061] wherein, Figure 1 is a first partial cross-sectional schematic view of the back contact battery provided by an embodiment of the present application; Figure 2A second partial cross-sectional schematic view of the back contact battery according to an embodiment of the present application is provided; Figure 3 A third partial cross-sectional schematic view of the back contact battery according to an embodiment of the present application is provided. It should be noted that, Figures 1 to 3 In the above embodiments, N is 2, i.e., the first doped layer 102 includes two layers of the first doped film 112 arranged in a stack. In actual applications, N can be designed to be 3, 4, 5, or the like according to specific requirements.

[0062] It should be noted that the first doped layer 102 is designed to be a stack structure including multiple layers of the first doped film 112 with different crystallization rates, i.e., different crystallization degrees. On the one hand, the first doped film 112 with a higher crystallization rate close to the substrate 100 can be regarded as a film layer structure with uniform internal grain distribution, so as to improve the film layer uniformity of the first doped film 112 with a higher crystallization rate close to the substrate 100, which helps to prevent the surface of the first doped film 112 with a higher crystallization rate close to the substrate 100 from grain precipitation, so that the first doped film 112 close to the substrate 100 can be designed to have a higher crystallization rate, so as to avoid damage to other film layers, such as the first dielectric layer 101 and the substrate 100, caused by the grains in the first doped layer 102, so as to ensure the stability of the performance of other film layers close to the first doped layer 102, so as to improve the passivation effect of other film layers close to the first doped layer 102 on the substrate 100, thereby reducing the recombination probability of photo-generated carriers. On the other hand, the first doped film 112 far from the substrate 100 has a lower crystallization rate, which helps to improve the surface roughness of the first doped film 112 far from the substrate 100, such as making the surface of the first doped film 112 far from the substrate 100 have larger grains, so that when the electrode is designed on the side of the first doped layer 102 far from the substrate 100, the lower crystallization rate of the first doped film 112 helps to improve the contact performance between the first doped layer 102 and the electrode, so as to improve the collection efficiency of the electrode on the photo-generated carriers, thereby improving the fill factor of the back contact battery. Such multiple effects can not only improve the passivation effect on the substrate 100 by the cooperation of the first doped layer 102 and the first dielectric layer 101, but also reduce the migration resistance of the photo-generated carriers in the first doped layer 102, so as to further improve the photoelectric conversion efficiency of the back contact battery.

[0063] It should be noted that the crystallization rate of the first doped film 112 in any layer of the first doped layer 102 can be obtained by Raman spectrum test. In the Raman spectrum test, the crystalline and amorphous parts in the first doped film 112 will present different intensity spectrum peaks, and the crystallization rate of the first doped film 112 can be estimated by observing the intensity of the spectrum peaks in different regions of the first doped film 112.

[0064] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0065] In some embodiments, the N-type doping element can be at least one of a phosphorus (P) element, a bismuth (Bi) element, an antimony (Sb) element, or an arsenic (As) element, etc. a V group element; the P-type semiconductor substrate is doped with a P-type element, and the P-type doping element can be at least one of a boron (B) element, an aluminum (Al) element, a gallium (Ga) element, or an indium (In) element, etc. a III group element.

[0066] The specific structure in the first doping layer 102 is described in detail below.

[0067] In some embodiments, referring to Figures 1 to 3 , the grain size in the (N-1)th first doping film 112 can be smaller than the grain size of the Nth first doping film 112. It is worth noting that the size distribution between the multiple grains contained in the first doping film 112 with a higher crystallization rate is more uniform, in other words, the difference in size between different grains in the first doping film 112 with a higher crystallization rate will not be large, for example, it is not easy to appear dendritic grains, so as not to cause damage to the film layer close to the first doping film 112, i.e. the first dielectric layer 101 and the substrate 100; unlike this, it is easier to appear different grains with a larger size difference in the first doping film 112 with a lower crystallization rate, so that when part of the material in the subsequent electrode penetrates into the first doping film 112, the electrode can have more contact area with the grains in the first doping film 112, thereby improving the contact performance between the electrode and the first doping film 112. Based on this, the grain size in the (N-1)th first doping film 112 is designed to be smaller than the grain size of the Nth first doping film 112, which is beneficial to both improving the passivation effect of the first doping layer 102 and the first dielectric layer 101 on the substrate 100, and improving the contact performance between the first doping layer 102 and the electrode.

[0068] It should be noted that in some cases, the grain size in the (N-1)th first doping film 112 being smaller than the grain size of the Nth first doping film 112 can represent that the average value of the size of the multiple grains in the Nth first doping film 112 is larger than the average value of the size of the multiple grains in the (N-1)th first doping film 112; in other cases, the grain size in the (N-1)th first doping film 112 being smaller than the grain size of the Nth first doping film 112 can represent that the size of the majority of the grains (e.g. more than 80% of the grains) in the Nth first doping film 112 is larger than the size of the majority of the grains (e.g. more than 80% of the grains) in the (N-1)th first doping film 112.

[0069] It is worth noting that the grain size in the first doping film 112 can be tested by SEM (Scanning Electron Microscope).

[0070] In some embodiments, referring to Figures 1 to 3 , N is 2, the crystallization rate of the (N-1)th layer of the first doped film 112 can be greater than or equal to 99%, and the crystallization rate of the Nth layer of the first doped film 112 can be less than 95%. In other words, the first doped layer 102 can include two layers of the first doped film 112, the first layer of the first doped film 112 being a first inner doped film 1121 closer to the first dielectric layer 101, and the second layer of the first doped film 112 being a first outer doped film 1122.

[0071] Based on this, the crystallization rate of the first inner doped film 1121 is greater than or equal to 99%, and the crystallization rate of the first outer doped film 1122 is less than 95%, so that the crystallization rates of the two layers of the first doped film 112 are both high, which is beneficial to ensure that both layers of the first doped film 112 have high film uniformity, so as to ensure that both layers of the first doped film 112 have high film quality and have a better field passivation effect on the substrate 100. Further, the crystallization rate of the first inner doped film 1121 is close to 100%, which is beneficial to further ensure that the first inner doped film 1121 contains a plurality of crystal grains of similar size, so as to avoid damage to the first dielectric layer 101 or the substrate 100 caused by the crystal grains in the first inner doped film 1121, thereby ensuring that the first dielectric layer 101 has a better chemical passivation effect on the substrate 100, and appropriately reducing the crystallization rate of the first outer doped film 1122 is beneficial to increase the contact area of the first outer doped film 1122 and the electrode by means of the crystal grains of larger size in the first outer doped film 1122.

[0072] In some embodiments, referring to Figures 1 to 3 , N is 2, the grain size of the (N-1)th layer of the first doped film 112 can be 100nm-180nm, for example, can be 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm, 165nm, 170nm or 175nm, etc.; the grain size of the Nth layer of the first doped film 112 can be 190nm-300nm, for example, can be 195nm, 200nm, 205nm, 210nm, 215nm, 220nm, 225nm, 230nm, 235nm, 240nm, 245nm, 250nm, 255nm, 260nm, 265nm, 270nm, 275nm, 280nm, 285nm, 290nm or 295nm, etc.

[0073] In some embodiments, referring to Figures 1 to 3, along the first direction X, the thickness of the (N-1)th layer of the first doped film 112 is less than the thickness of the Nth layer of the first doped film 112. In this way, after the electrodes are designed on the side of the first doped layer 102 away from the substrate 100, the thickness of the first doped film 112 closest to the electrodes in the first doped layer 102, i.e., the thickness of the outermost first doped film, is the largest, thereby facilitating the use of the large thickness of the outermost first doped film and the large-size crystal grains in the outermost first doped film to improve the blocking effect of the outermost first doped film on the material constituting the electrodes, so as to reduce the risk of the electrodes burning through the first doped layer 102 during the preparation of the electrodes.

[0074] In some embodiments, with reference to Figures 1 to 3 , N is 2, along the first direction X, the thickness of the (N-1)th layer of the first doped film 112, i.e., the thickness of the first inner doped film 1121, can be 10 nm to 60 nm, for example, can be 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, or 55 nm, etc.; the thickness of the Nth layer of the first doped film 112, i.e., the thickness of the first outer doped film 1122, can be 10 nm to 500 nm, for example, can be 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, 370 nm, 380 nm, 390 nm, 400 nm, 410 nm, 420 nm, 430 nm, 440 nm, 450 nm, 460 nm, 470 nm, 480 nm, or 490 nm, etc.

[0075] In some examples, the thickness of the first inner doped film 1121 can be 20 nm, and the thickness of the first outer doped film 1122 can be 330 nm.

[0076] The specific structure in the second doped layer 104 is described in detail below.

[0077] In some embodiments, with reference to Figure 2 or Figure 3 , the second doped layer 104 can include M layers of second doped films 114 stacked, along the direction away from the substrate 100, the crystallization rate of the (M-1)th layer of the second doped film 114 is higher than the crystallization rate of the Mth layer of the second doped film 114, and M is a positive integer greater than or equal to 2.

[0078] It should be noted that Figure 2 and Figure 3 In actual applications, M can be designed to be 3, 4, or 5, etc. according to specific needs.

[0079] It should be noted that, similar to the first doped layer 102, the second doped layer 104 is also designed to include a plurality of second doped films 114 with different crystallization rates, i.e., a stacked structure of second doped films 114 with different crystallization degrees. On the one hand, the second doped film 114 with a higher crystallization rate close to the substrate 100 can be regarded as a film layer structure with uniform internal grain distribution, so as to improve the film layer uniformity of the second doped film 114 with a higher crystallization rate close to the substrate 100, which helps to make the surface of the second doped film 114 with a higher crystallization rate close to the substrate 100 free of grain precipitation, so that the second doped film 114 close to the substrate 100 can be designed to have a higher crystallization rate, so as to avoid damage to other film layers, such as the second dielectric layer 103 and the substrate 100, etc., caused by the grains in the second doped film 114, so as to ensure the stability of the performance of other film layers close to the second doped layer 104, so as to improve the passivation effect of other film layers close to the second doped layer 104 on the substrate 100, thereby reducing the recombination probability of photo-generated carriers. On the other hand, the second doped film 114 far from the substrate 100 has a lower crystallization rate, which helps to improve the surface roughness of the second doped film 114 far from the substrate 100, such as making the surface of the second doped film 114 far from the substrate 100 have larger grains, so that when designing an electrode on the side of the second doped layer 104 far from the substrate 100, it is beneficial to improve the contact performance between the second doped layer 104 and the electrode by means of the second doped film 114 with a lower crystallization rate, so as to improve the collection efficiency of the electrode on photo-generated carriers, thereby improving the fill factor of the back contact cell. Such multi-aspect effects not only improve the passivation effect on the substrate 100 in cooperation with the second dielectric layer 103, but also reduce the migration hindrance of photo-generated carriers in the second doped layer 104, so as to further improve the photoelectric conversion efficiency of the back contact cell.

[0080] It should be noted that the crystallization rate of the second doped film 114 of any layer in the second doped layer 104 can also be obtained by Raman spectrum test.

[0081] In some cases, with reference to Figure 2 or Figure 3The grain size of the second doped film 114 in the (M-1)th layer can be smaller than the grain size of the second doped film 114 in the Mth layer. It is worth noting that the difference in size between different grains in the second doped film 114 with a higher crystallization rate is not large, for example, it is not easy to form dendritic grains, so as not to cause damage to the film layers close to the second doped film 114, i.e., the second dielectric layer 103 and the substrate 100; in contrast, the second doped film 114 with a lower crystallization rate is more likely to form different grains with a larger size difference, so that when part of the material in the subsequent electrode penetrates into the second doped film 114, the electrode can have more contact area with the grains in the second doped film 114, thereby improving the contact performance between the electrode and the second doped film 114. Based on this, the grain size of the second doped film 114 in the (M-1)th layer is designed to be smaller than the grain size of the second doped film 114 in the Mth layer, which is beneficial to both improving the passivation effect of the second doped layer 104 and the second dielectric layer 103 on the substrate 100 and improving the contact performance between the second doped layer 104 and the electrode.

[0082] It should be noted that in some cases, the grain size of the second doped film 114 in the (M-1)th layer being smaller than the grain size of the second doped film 114 in the Mth layer can mean that the average size of the plurality of grains in the Mth layer is larger than the average size of the plurality of grains in the (M-1)th layer; in other cases, the grain size of the second doped film 114 in the (M-1)th layer being smaller than the grain size of the second doped film 114 in the Mth layer can mean that the size of the majority of the grains (e.g., more than 80% of the grains) in the Mth layer is larger than the size of the majority of the grains (e.g., more than 80% of the grains) in the (M-1)th layer.

[0083] It is worth noting that the grain size of the second doped film 114 can be tested by SEM (Scanning Electron Microscope).

[0084] In some cases, with reference to Figure 2 or Figure 3 M is 2, the crystallization rate of the second doped film 114 in the (M-1)th layer can be greater than or equal to 99%, and the crystallization rate of the second doped film 114 in the Mth layer can be less than 95%. In other words, the second doped layer 104 can include two layers of second doped films 114, the first layer of second doped film 114 being a second inner doped film 1141 closer to the second dielectric layer 103, and the second layer of second doped film 114 being a second outer doped film 1142.

[0085] Therefore, the crystallization rate of the second inner doped film 1141 is greater than or equal to 99%, and the crystallization rate of the second outer doped film 1142 is less than 95%, so that the crystallization rates of the two layers of the second doped film 114 are both high, which is beneficial to ensure that the two layers of the second doped film 114 both have high film uniformity, so as to ensure that the two layers of the second doped film 114 both have high film quality and have a better field passivation effect on the substrate 100. Further, the crystallization rate of the second inner doped film 1141 is close to 100%, which is beneficial to further ensure that the second inner doped film 1141 contains a plurality of crystal grains with similar sizes, so as to avoid damage to the second dielectric layer 103 or the substrate 100 caused by the crystal grains in the second inner doped film 1141, thereby ensuring that the second dielectric layer 103 has a better chemical passivation effect on the substrate 100, and appropriately reducing the crystallization rate of the second outer doped film 1142 is beneficial to increase the contact area between the second outer doped film 1142 and the electrode by means of the crystal grains with large sizes in the second outer doped film 1142.

[0086] In some cases, with reference to Figure 2 or Figure 3 , M is 2, the size of the crystal grains in the (M-1)th layer of the second doped film 114 can be 100nm-180nm, and the size of the crystal grains in the Mth layer of the second doped film 114 can be 190nm-300nm.

[0087] In some cases, with reference to Figure 2 or Figure 3 , along the first direction X, the thickness of the (M-1)th layer of the second doped film 114 is less than the thickness of the Mth layer of the second doped film 114. In this way, after the electrode is designed on the side of the second doped layer 104 away from the substrate 100, the thickness of the outermost layer of the second doped film 114, which is the layer of the second doped film 114 closest to the electrode in the second doped layer 104, is the largest, thereby facilitating the use of the large thickness of the outermost layer of the second doped film and the large-size crystal grains in the outermost layer of the second doped film to improve the blocking effect of the outermost layer of the second doped film on the material constituting the electrode, so as to reduce the risk of the electrode burning through the second doped layer 104 during the preparation of the electrode.

[0088] In some cases, with reference to Figure 2 or Figure 3 , M is 2, along the first direction X, the thickness of the (M-1)th layer of the second doped film 114, i.e., the second inner doped film 1141, can be 10nm-60nm; and the thickness of the Mth layer of the second doped film 114, i.e., the second outer doped film 1142, can be 10nm-500nm.

[0089] In some examples, the thickness of the second inner doped film 1141 can be 20nm, and the thickness of the second outer doped film 1142 can be 180nm.

[0090] In another embodiment, with reference toFigure 1 In the direction away from the substrate 100, the second doped layer 104 can also be a single film layer structure based on the foundation of the first doped layer 102 including N layers of first doped films 112 with decreasing crystallization rate layer by layer. It is worth noting that the film layer performance of the doped layer, such as the crystallization rate, will also be affected by the doping elements contained in the doped layer. The first doped layer 102 is doped with P-type doping elements, and the second doped layer 104 is doped with N-type doping elements. Based on the difference of the doping elements contained in the two, the second doped layer 104 being a single film layer structure can also take into account the passivation performance of the second medium layer 103 to the substrate 100 and the contact performance of the second doped layer 104 to the electrode.

[0091] The materials of the first doped layer 102 and the second doped layer 104 are described in detail below.

[0092] In some embodiments, referring to Figures 1 to 3 , the materials of the first doped layer 102 and the second doped layer 104 both include polycrystalline silicon, and the back contact cell is a TBC cell (TOPCon Back Contact, referring to a cross passivation back contact cell).

[0093] In some cases, referring to Figure 2 or Figure 3 , similar to the first doped layer 102, the second doped layer 104 is a stacked structure including multiple layers of second doped films 114 with different crystallization rates. In other cases, referring to Figure 1 , unlike the first doped layer 102, the second doped layer 104 is a single layer of polycrystalline silicon.

[0094] In some cases, referring to Figures 1 to 3 , at least one of the first doped layer 102 and the second doped layer 104 is polycrystalline silicon also doped with carbon elements or nitrogen elements. It is worth noting that the first doped layer 102 and the second doped layer 104 are collectively referred to as doped layers. Whether it is the first doped layer 102 or the second doped layer 104, doping carbon elements or nitrogen elements in the film layer is beneficial to increase the band gap of the doped layer, thereby reducing the parasitic absorption of the doped layer to light, and thereby increasing the photogenerated carrier density generated by the substrate 100.

[0095] In some examples, based on the first doped layer 102 being polycrystalline silicon doped with both P-type doping elements and carbon elements or nitrogen elements, the second doped layer 104 can be polycrystalline silicon doped with N-type doping elements, or polycrystalline silicon doped with both N-type doping elements and carbon elements or nitrogen elements. In other examples, based on the first doped layer 102 being polycrystalline silicon doped with P-type doping elements, the second doped layer 104 can be polycrystalline silicon doped with N-type doping elements, or polycrystalline silicon doped with both N-type doping elements and carbon elements or nitrogen elements.

[0096] It should be noted that the case that the first doped layer 102 has P-type doping elements includes that each of the first doped films 112 in the first doped layer 102 has P-type doping elements; the case that the first doped layer 102 is doped with carbon elements or nitrogen elements includes that at least one of the first doped films 112 in the first doped layer 102 is doped with carbon elements or nitrogen elements; the case that the second doped layer 104 has N-type doping elements includes that each of the second doped films 114 in the second doped layer 104 has N-type doping elements; the case that the second doped layer 104 is doped with carbon elements or nitrogen elements includes that at least one of the second doped films 114 in the second doped layer 104 is doped with carbon elements or nitrogen elements.

[0097] In some embodiments, referring to Figure 1 , the material of the first doped layer 102 can include polycrystalline silicon, the material of the second doped layer 104 can include amorphous silicon, and the back contact cell is an HTBC cell. The HTBC cell is a heterojunction and tunnel oxide passivated contact hybrid passivated back contact photovoltaic cell (abbreviated as HTBC). It should be noted that in this case, unlike the first doped layer 102, the second doped layer 104 can be a single layer of amorphous silicon.

[0098] The thickness of the first doped layer 102 and the thickness of the second doped layer 104 are described in detail below. It should be noted that the thickness of the first doped layer 102 mentioned later refers to the total thickness of the N layers of first doped films 112 in the first doped layer 102, and the thickness of the second doped layer 104 refers to the thickness of the second doped layer 104 in a single film layer structure or the total thickness of the M layers of second doped films 114 in the second doped layer 104.

[0099] In some embodiments, along the first direction X, the thickness of the first doped layer 102 and the thickness of the second doped layer 104 can each be 50nm-500nm, for example, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm or 450nm, etc.

[0100] In some embodiments, referring to Figures 1 to 3 , along the first direction X, the thickness of the first doped layer 102 can be greater than the thickness of the second doped layer 104.

[0101] It is worth noting that the film layer performance of the doped layer, such as the burn-through resistance, can be affected by the doping elements contained in the doped layer. In the subsequent step of preparing the electrode, the first doped layer 102 doped with P-type doping elements is more likely to be burned through by the electrode than the second doped layer 104 doped with N-type doping elements. Therefore, the thickness of the first doped layer 102 is made thicker than that of the second doped layer 104, which is conducive to further reducing the risk of the electrode burning through the first doped layer 102 when the electrode is prepared.

[0102] In some embodiments, with reference to Figures 1 to 3 , the doping concentration of the P-type doping elements in the first doped layer 102 can be 5×10 18 atom / cm 3 , for example, 6×10 20 atom / cm 3 , 7×10 18 atom / cm 3 , 8×10 18 atom / cm 3 , 9×10 18 atom / cm 3 , 1×10 18 atom / cm 3 , 2×10 19 atom / cm 3 , 3×10 19 atom / cm 3 , 4×10 19 atom / cm 3 , 5×10 19 atom / cm 3 , 6×10 19 atom / cm 3 , 7×10 19 atom / cm 3 , 8×10 19 atom / cm 3 , 9×10 19 atom / cm 3 , 1×10 19 atom / cm 3 , 2×10 20 atom / cm 3 , 3×10 20 atom / cm 3 , 4×10 20 atom / cm 3 , 5×10 20 atom / cm 3 , 6×10 20 atom / cm3 6 x 10 20 atom / cm 3 or 7 x 10 20 atom / cm 3 etc.

[0103] In some embodiments, referring to Figures 1 to 3 , the doping concentration of the N-type doping element in the second doping layer 104 can be 5 x 10 19 atom / cm 3 ~ 9 x 10 20 atom / cm 3 For example, it can be 6 x 10 19 atom / cm 3 , 7 x 10 19 atom / cm 3 , 8 x 10 19 atom / cm 3 , 9 x 10 19 atom / cm 3 , 1 x 10 20 atom / cm 3 , 2 x 10 20 atom / cm 3 , 3 x 10 20 atom / cm 3 , 4 x 10 20 atom / cm 3 , 5 x 10 20 atom / cm 3 , 6 x 10 20 atom / cm 3 , 7 x 10 20 atom / cm 3 or 8 x 10 20 atom / cm 3 etc.

[0104] The materials of the first dielectric layer 101 and the second dielectric layer 103 are described in detail below. It should be noted that the materials of the first dielectric layer 101 and the second dielectric layer 103 can be the same or different in the same back contact cell.

[0105] In some embodiments, referring to Figures 1 to 3 , the material of at least one of the first dielectric layer 101 and the second dielectric layer 103 includes aluminum oxide or silicon nitride.

[0106] In some cases, the materials of the first dielectric layer 101 and the second dielectric layer 103 can both include aluminum oxide or silicon nitride, and the first dielectric layer 101 and the second dielectric layer 103 are both tunnel layers, and the back contact cell is a TBC cell.

[0107] It is worth noting that, compared with the tunneling layer whose material is silicon oxide, the material of the first dielectric layer 101 and the second dielectric layer 103 is designed as aluminum oxide or silicon nitride, which is conducive to further reducing the distortion of the first dielectric layer 101 and the second dielectric layer 103, thereby facilitating the improvement of the passivation effect of the first dielectric layer 101 and the second dielectric layer 103 on the substrate 100. Moreover, boron is easy to accumulate at the silicon oxide layer and further break the passivation performance of the silicon oxide. The material of the first dielectric layer 101 and the second dielectric layer 103 is designed as aluminum oxide or silicon nitride, which is conducive to avoiding the accumulation of boron at the first dielectric layer 101 and the second dielectric layer 103, thereby facilitating the guarantee of the higher passivation performance of the first dielectric layer 101 and the second dielectric layer 103.

[0108] In other cases, under the premise that the material of the first dielectric layer 101 includes aluminum oxide or silicon nitride, the material of the second dielectric layer 103 can include at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, and the first dielectric layer 101 and the second dielectric layer 103 are both tunneling layers, and the back contact cell is a TBC cell; or, the material of the second dielectric layer 103 can include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon, and the back contact cell is an HTBC cell.

[0109] In yet other cases, the material of the second dielectric layer 103 can include aluminum oxide or silicon nitride, and the material of the first dielectric layer 101 can include at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, and the first dielectric layer 101 and the second dielectric layer 103 are both tunneling layers, and the back contact cell is a TBC cell.

[0110] In other embodiments, referring to Figures 1 to 3 , the material of at least one of the first dielectric layer 101 and the second dielectric layer 103 can include at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride.

[0111] In some cases, the material of the first dielectric layer 101 and the material of the second dielectric layer 103 can both include at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, and the back contact cell is a TBC cell.

[0112] In other cases, the material of the first dielectric layer 101 can include at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride, and the material of the second dielectric layer 103 can include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon, and the back contact cell is an HTBC cell.

[0113] In some embodiments, the thickness of the first dielectric layer 101 and the second dielectric layer 103 can be 1 nm to 2 nm in the first direction X, for example, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, or 1.9 nm, etc.

[0114] In some embodiments, referring to Figure 3 , the back contact cell can further include: a first passivation layer 118 located on the first surface 110 and at least on the surface of the first doped layer 102 and the second doped layer 104 away from the substrate 100; and a second passivation layer 128 located on the surface of the first passivation layer 118 away from the substrate 100. It is worth noting that the first passivation layer 118 and the second passivation layer 128 can both serve as a passivation anti-reflection layer to reduce the reflectivity of the light of the back contact cell formed finally, thereby improving the absorption and utilization rate of the incident light of the back contact cell.

[0115] In some cases, the material of the first passivation layer 118 can be aluminum oxide, and the material of the second passivation layer 128 can be silicon nitride.

[0116] In some cases, the thickness of the first passivation layer 118 can be 3 nm to 10 nm in the first direction X, for example, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, or 9 nm, etc.

[0117] In some cases, the thickness of the second passivation layer 128 can be 70 nm to 90 nm in the first direction X, for example, 71 nm, 72 nm, 73 nm, 74 nm, 75 nm, 76 nm, 77 nm, 78 nm, 79 nm, 80 nm, 81 nm, 82 nm, 83 nm, 84 nm, 85 nm, 86 nm, 87 nm, 88 nm, or 89 nm, etc.

[0118] In some embodiments, referring to Figure 3 , the back contact cell can further include: a first electrode 119 at least in contact with the side of the first doped layer 102 away from the substrate 100; and a second electrode 129 at least in contact with the side of the second doped layer 104 away from the substrate 100. It is worth noting that the aforementioned "designing an electrode on the side of the first doped layer 102 away from the substrate 100" is the first electrode 119, and the aforementioned "designing an electrode on the side of the second doped layer 104 away from the substrate 100" is the second electrode 129.

[0119] In summary, the first doped layer 102 is designed as a stack structure including multiple first doped films 112 with different crystallization rates. On one hand, the first doped film 112 close to the substrate 100 with a high crystallization rate can improve the uniformity of the film layer itself, which helps to avoid the grain precipitation on the surface of the first doped film 112 close to the substrate 100, so that the first doped film 112 close to the substrate 100 can be designed with a high crystallization rate to avoid the damage of the grains in the first doped layer 102 to other film layers close to the first doped layer 102, such as the first dielectric layer 101 and the substrate 100, so as to ensure the stability of the performance of other film layers close to the first doped layer 102, improve the passivation effect of other film layers close to the first doped layer 102 on the substrate 100, and thus reduce the recombination probability of the photo-generated carriers. On the other hand, the first doped film 112 away from the substrate 100 has a low crystallization rate, which helps to improve the surface roughness of the first doped film 112 away from the substrate 100, such as making the surface of the first doped film 112 away from the substrate 100 have large grains, so that when the electrode is designed on the side of the first doped layer 102 away from the substrate 100, the low crystallization rate of the first doped film 112 can be used to improve the contact performance between the first doped layer 102 and the electrode, so as to improve the collection efficiency of the electrode on the photo-generated carriers, and thus improve the fill factor of the back contact cell. In this way, the passivation effect on the substrate 100 can be improved by the cooperation of the first doped layer 102 and the first dielectric layer 101, and the migration resistance of the photo-generated carriers in the first doped layer 102 can be reduced, so as to further improve the photoelectric conversion efficiency of the back contact cell.

[0120] Another embodiment of the present application also provides a manufacturing method of a back contact cell for forming the back contact cell provided in the foregoing embodiments. The manufacturing method of the back contact cell provided in another embodiment of the present application will be described in detail below with reference to the drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments will not be described herein.

[0121] Reference Figure 4 and Figures 5 to 11 , Figure 4 is a process flow chart corresponding to the manufacturing method of the back contact cell provided in another embodiment of the present application; Figures 5 to 11 is a partial cross-sectional schematic view corresponding to each step in the manufacturing method of the back contact cell provided in another embodiment of the present application. The manufacturing method of the back contact cell at least includes the following steps:

[0122] S1: Referring to Figure 5 , a substrate 100 is provided, the substrate 100 has a first surface 110 and a second surface 120 opposite to each other along a first direction X, and the second surface 120 has first regions 1201 and second regions 1202 arranged alternately along a second direction Y.

[0123] S2: refer to Figures 5 to 8 , a first doped layer 102 is formed on the first medium layer 101 and the first region 1201, and the first doped layer 102 has P-type doping elements.

[0124] In step S2, the step of forming the first doped layer 102 can include: referring to Figure 5 , a first semiconductor layer 105 is formed on the second surface 120 by using a first deposition process, the first deposition process includes N deposition stages connected in sequence, the deposition temperature of the (N-1)th deposition stage is lower than that of the Nth deposition stage, and N is a positive integer greater than or equal to 2; refer to Figure 5 and Figure 6 , the first semiconductor layer 105 is subjected to a first doping treatment, so that the first semiconductor layer 105 is converted into an initial first doped layer 122 doped with P-type doping elements; refer to Figures 6 to 8 , the initial first doped layer 122 is subjected to a first patterning treatment, only the initial first doped layer 122 located on the first region 1201 is reserved as the first doped layer 102, and the first doped layer 102 includes N layers of first doped films 112 stacked, and in the direction away from the substrate 100, the crystallization rate of the (N-1)th layer of first doped films 112 is higher than that of the Nth layer of first doped films 112.

[0125] S3: refer to Figures 9 to 11 , and Figure 2 , a second doped layer 104 is formed on the second medium layer 103 and the second region 1202, and the second doped layer 104 has N-type doping elements.

[0126] It is worth noting that before the first doping treatment, that is, before the P-type doping elements are doped, the first semiconductor layer 105 is formed by using a variable temperature deposition method, in other words, the first semiconductor layer 105 includes N layers of first semiconductor films 115 stacked, and after the first semiconductor layer 105 is subjected to the first doping treatment and the first patterning treatment, the N layers of first semiconductor films 115 are converted into N layers of first doped films 112 in sequence.

[0127] Therefore, in the step of forming the first semiconductor layer 105, the deposition temperature of the (N-1)th deposition stage is designed to be lower than that of the Nth deposition stage, in other words, the deposition temperature of the first deposition process is designed to be increased stage by stage. By means of the increase of the deposition temperature, on the one hand, the formation of large-sized crystal grains in the first semiconductor film 115 close to the substrate 100 is avoided, the surface of the first semiconductor film 115 close to the substrate 100 is prevented from precipitating crystal grains, and the damage to the first dielectric layer 101 and the substrate 100 is avoided, so as to ensure the good passivation effect of the first dielectric layer 101 on the substrate 100; on the other hand, the formation of large-sized crystal grains, such as dendritic crystal grains, in the first semiconductor film 115 far away from the substrate 100 is facilitated. In this way, the crystallization rate of the (N-1)th layer of the first doped film 112 is higher than that of the Nth layer of the first doped film 112, which is beneficial to the formation of the first doped layer 102.

[0128] The manufacturing method of the back contact battery provided by another embodiment of the present application will be described in detail below.

[0129] In some embodiments, with reference to Figure 5 Before the step of forming the first semiconductor layer 105 on the second surface 120, the manufacturing method of the back contact battery further comprises: forming an initial first dielectric layer 111 on the second surface 120; with reference to Figures 6 to 8 In the step of performing the first patterning treatment on the initial first doped layer 122, the initial first dielectric layer 111 is further subjected to the first patterning treatment, and only the initial first dielectric layer 111 located on the first region 1201 is reserved as the first dielectric layer 101.

[0130] The manufacturing method of the first doped layer 102 will be described in detail below.

[0131] In some embodiments, with reference to Figure 5 N is 2, the first deposition process comprises the first deposition stage and the second deposition stage connected in sequence, the deposition temperature of the first deposition stage can be 520-570°C, for example, can be 525°C, 530°C, 535°C, 540°C, 545°C, 550°C, 555°C, 560°C or 565°C, etc.; the deposition temperature of the second deposition stage is 580-650°C, for example, can be 585°C, 590°C, 595°C, 600°C, 605°C, 610°C, 615°C, 620°C, 625°C, 630°C, 635°C, 640°C or 645°C, etc. In this way, the crystallization rate of the first semiconductor film 115 formed in the first deposition stage is higher than that of the first semiconductor film 115 formed in the second deposition stage.

[0132] It should be noted that with reference to Figure 5 and Figure 6The first semiconductor layer 105 formed includes two first semiconductor films 115, and the initial first doped layer 122 formed after the first doped treatment of the first semiconductor layer 105 includes the initial first inner doped layer 1221 and the initial first outer doped layer 1222 stacked.

[0133] In some embodiments, before forming the first semiconductor layer 105, the semi-finished back contact cell to be formed into the first semiconductor layer 105 is placed in the reaction chamber; and during the process of forming the first semiconductor layer 105 by using the first deposition process, the carbon-containing gas or the nitrogen-containing gas is introduced into the reaction chamber, so that the first semiconductor layer 105 formed is doped with carbon elements or nitrogen elements. In this way, it is beneficial to dope the first doped layer 102 formed based on the first semiconductor layer 105 with carbon elements or nitrogen elements, so as to increase the band gap of the first doped layer 102, to reduce the parasitic absorption of the first doped layer 102 to light, and to further increase the photogenerated carrier density generated by the substrate 100.

[0134] It should be noted that since the first deposition process includes N deposition stages connected in sequence, the step of introducing the carbon-containing gas or the nitrogen-containing gas into the reaction chamber can be designed in at least one deposition stage, so that at least one of the first semiconductor films 115 is doped with carbon elements or nitrogen elements, and at least one of the first doped films 112 in the first doped layer 102 formed based on the first semiconductor layer 105 is doped with carbon elements or nitrogen elements.

[0135] In some examples, the carbon-containing gas can be methane, and the nitrogen-containing gas can be ammonia.

[0136] In some embodiments, in combination with reference to Figure 5 and Figure 6 In the step of performing the first doped treatment on the first semiconductor layer 105, a first protective layer 116 is also formed on the side of the initial first doped layer 122 away from the substrate 100; in combination with reference to Figure 6 and Figure 7 The first laser is used to remove the first protective layer 116 located on the second region 1202; in combination with reference to Figure 7 and Figure 8 The first etching process is used to remove the initial first doped layer 122 located on the second region 1202, and the remaining initial first doped layer 122 is the first doped layer 102.

[0137] In combination with reference to Figure 5 is a partial cross-sectional schematic view of a manufacturing method of a back contact cell according to another embodiment of the present application, after forming a first semiconductor layer; Figure 6 is a partial cross-sectional schematic view of a manufacturing method of a back contact cell according to another embodiment of the present application, after performing a first doped treatment; Figure 7A partial cross-sectional view of a back contact cell manufacturing method provided by another embodiment of the present application after processing by a first laser; Figure 8 A partial cross-sectional view of a back contact cell manufacturing method provided by another embodiment of the present application after processing by a first etching process.

[0138] In some cases, reference is made to Figures 6 to 8 A separation area 1203 is further designed between the first area 1201 and the second area 1202. In the step of removing the first protective layer 116 on the second area 1202 by the first laser, the first laser is also used to remove the first protective layer 116 on the separation area 1203. In the step of removing the initial first doped layer 122 on the second area 1202 by the first etching process, the first etching process is also used to remove the initial first doped layer 122 on the separation area 1203.

[0139] In some cases, the first laser can be a purple skin laser or a green skin laser. The power of the laser generating the first laser can be 5W-80W, for example, 10W, 15W, 20W, 25W, 30W, 35W, 40W, 45W, 50W, 55W, 60W, 65W, 70W or 75W, etc.

[0140] It is worth noting that both the purple skin laser and the green skin laser belong to the picosecond laser, which is an ultrashort pulse laser. The purple skin laser can also refer to the ultraviolet picosecond laser, and the green skin laser can also refer to the green picosecond laser. Compared with the green skin laser, the wavelength of the purple skin laser is smaller, the penetration depth of the film layer is smaller, and the energy of the purple skin laser is more concentrated on the surface of the film layer, which are all conducive to reducing the risk of causing greater laser damage to the initial first doped layer 122 by the first laser.

[0141] In some examples, the P-type doping element can be boron (B) element. Based on this, in the step of performing the first doping treatment on the first semiconductor layer 105, the first protective layer 116 formed on the side of the initial first doped layer 122 away from the substrate 100 can be boron-silicon glass (BSG). Moreover, both the initial first doped layer 122 and the first protective layer 116 will wrap around the partial area plated on the first surface 110.

[0142] In some examples, reference is made to Figure 7 and Figure 8The step of performing the first etching process includes: firstly removing a first protective layer (not shown in the figure) around the first surface 110 by using a chain acid washing process; and then removing the initial first doped layer 122 around the first surface 110 and on the second region 1202, and further removing the initial first dielectric layer 111 on the second region 1202 by using an alkali etching process. The remaining initial first dielectric layer 111 on the first region 1201 is the first dielectric layer 101.

[0143] In one example, in the step of performing the alkali etching process, after removing the initial first doped layer 122 and the initial first dielectric layer 111 on the second region 1202, a polishing process is further performed on the exposed second region 1202, so that the surface of the second region 1202 in the substrate 100 is further recessed towards the inside of the substrate 100 compared with the surface of the first region 1201 in the substrate 100. For example, the height difference between the surface of the first region 1201 and the surface of the second region 1202 is 3 μm to 8 μm, in other words, the etching depth of the second region 1202 in the substrate 100 is 3 μm to 8 μm.

[0144] In one example, a separation region 1203 is further designed between the first region 1201 and the second region 1202, and the alkali etching process further removes the initial first doped layer 122 and the initial first dielectric layer 111 on the separation region 1203.

[0145] The manufacturing method of the second doped layer 104 is described in detail as follows.

[0146] In some embodiments, the step of forming the second doped layer 104 can include: Figure 9 forming a second semiconductor layer 107 on the second surface 120 by using a second deposition process, the second deposition process including M temperature control stages connected in sequence, the process temperature of the (M-1)th temperature control stage being lower than the process temperature of the Mth temperature control stage, M being a positive integer greater than or equal to 2; in combination with reference to Figure 9 and Figure 10 performing a second doping treatment on the second semiconductor layer 107, so that the second semiconductor layer 107 is converted into an initial second doped layer 124 doped with an N-type doping element; in combination with reference to Figure 10 、 Figure 11 and Figure 2 performing a second patterning treatment on the initial second doped layer 124, only the initial second doped layer 124 on the second region 1202 is reserved as the second doped layer 104, and the second doped layer 104 includes M layers of second doped films 114 stacked, and the crystallization rate of the (M-1)th layer of second doped films 114 is higher than the crystallization rate of the Mth layer of second doped films 114 in the direction away from the substrate 100.

[0147] It is worth noting that before the second doping treatment, that is, before the N-type doping element is not doped, the second semiconductor layer 107 can also be formed by using the variable temperature deposition method, in other words, the second semiconductor layer 107 includes M layers of second semiconductor films 117 arranged in a stack, and after the second doping treatment and the second patterning treatment are performed on the second semiconductor layer 107, the M layers of second semiconductor films 117 are sequentially changed into M layers of second doped films 114.

[0148] Based on this, in the step of forming the second semiconductor layer 107, the process temperature of the (M-1)th temperature control stage is designed to be lower than the process temperature of the Mth temperature control stage, in other words, the process temperature of the second deposition process is designed to be gradually increased stage by stage. By means of the increase of the process temperature, on the one hand, it is avoided that the second semiconductor film 117 close to the substrate 100 forms a crystal grain with a large size, it is avoided that the surface of the second semiconductor film 117 close to the substrate 100 precipitates a crystal grain, and it is avoided that the second dielectric layer 103 and the substrate 100 are damaged, so as to ensure the good passivation effect of the second dielectric layer 103 on the substrate 100; on the other hand, it is facilitated that the second semiconductor film 117 far away from the substrate 100 is more likely to form a crystal grain with a large size, such as a dendritic crystal grain. In this way, through the multi-aspect action, it is beneficial to finally form the second doped layer 104 in which the crystallization rate of the (M-1)th layer of second doped film 114 is higher than the crystallization rate of the Mth layer of second doped film 114.

[0149] In some cases, referring to Figure 9 , before the second semiconductor layer 107 is formed on the second surface 120, the manufacturing method of the back contact cell further includes: forming an initial second dielectric layer 113 on the second surface 120; referring to Figure 10 , Figure 11 and Figure 2 , in the step of performing the second patterning treatment on the initial second doped layer 124, the initial second dielectric layer 113 is further subjected to the second patterning treatment, and only the initial second dielectric layer 113 located on the second region 1202 is reserved as the second dielectric layer 103.

[0150] In some cases, referring to Figure 9 , M is 2, and the second deposition process includes a first temperature control stage and a second temperature control stage connected in sequence, the process temperature of the first temperature control stage is 520°C-570°C, and the process temperature of the second temperature control stage is 580°C-650°C. In this way, it is beneficial to make the crystallization rate of the second semiconductor film 117 formed in the first temperature control stage higher than the crystallization rate of the second semiconductor film 117 formed in the second temperature control stage.

[0151] It should be noted that referring to Figure 9 and Figure 10The second semiconductor layer 107 formed includes two second semiconductor films 117, and the initial second doped layer 124 formed after the second doped treatment of the second semiconductor layer 107 includes the initial second inner doped layer 1241 and the initial second outer doped layer 1242 stacked.

[0152] In some cases, before forming the second semiconductor layer 107, the semi-finished back contact cell to be formed into the second semiconductor layer 107 is placed in the reaction chamber; and during the process of forming the second semiconductor layer 107 by using the second deposition process, the carbon-containing gas or the nitrogen-containing gas is introduced into the reaction chamber, so that the second semiconductor layer 107 formed is doped with carbon elements or nitrogen elements. In this way, it is beneficial to dope the second doped layer 104 formed based on the second semiconductor layer 107 with carbon elements or nitrogen elements, so as to increase the band gap of the second doped layer 104, to reduce the parasitic absorption of the second doped layer 104 to light, and to further increase the photogenerated carrier density generated by the substrate 100.

[0153] It should be noted that since the second deposition process includes M temperature control stages connected in sequence, the step of introducing the carbon-containing gas or the nitrogen-containing gas into the reaction chamber can be designed in at least one temperature control stage, so that at least one second semiconductor film 117 is doped with carbon elements or nitrogen elements, and at least one second doped film 114 in the second doped layer 104 formed based on the second semiconductor layer 107 is doped with carbon elements or nitrogen elements.

[0154] In some examples, the carbon-containing gas can be methane, and the nitrogen-containing gas can be ammonia.

[0155] In some cases, in combination with reference to Figure 9 and Figure 10 , in the step of performing the second doped treatment on the second semiconductor layer 107, a second protective layer 126 is also formed on the side of the initial second doped layer 124 away from the substrate 100; in combination with reference to Figure 10 and Figure 11 , the second laser is used to remove the second protective layer 126 located on the first region 1201; in combination with reference to Figure 11 and Figure 2 , the second etching process is used to remove the initial second doped layer 124 located on the first region 1201, and the remaining initial second doped layer 124 is the second doped layer 104.

[0156] wherein, Figure 9 is a partial cross-sectional view of a back contact cell provided by another embodiment of the present application after forming a second semiconductor layer in a manufacturing method of the back contact cell; Figure 10 is a partial cross-sectional view of a back contact cell provided by another embodiment of the present application after performing a second doped treatment in a manufacturing method of the back contact cell; Figure 11A partial sectional view of a back contact cell manufacturing method provided by another embodiment of the present application is shown in FIG. 12B.

[0157] In some cases, in combination with the reference of Figure 10 , Figure 11 and Figure 2 , an isolation region 1203 is designed between the first region 1201 and the second region 1202. In the step of removing the second protective layer 126 on the first region 1201 by the second laser, the second laser is also used to remove the second protective layer 126 on the isolation region 1203. In the step of removing the initial second doped layer 124 on the first region 1201 by the second etching process, the second etching process is also used to remove the initial second doped layer 124 on the isolation region 1203.

[0158] In some cases, the second laser can be a purple skin laser or a green skin laser, and the power of the laser generating the second laser can be 5W~80W.

[0159] In some examples, the N-type doping element can be a phosphorus (P) element. Based on this, in the step of performing the second doping treatment on the second semiconductor layer 107, the second protective layer 126 formed on the side of the initial second doped layer 124 away from the substrate 100 can be a phosphor silicon glass (PSG). Moreover, the initial second doped layer 124 and the second protective layer 126 are both around the partial region plated on the first surface 110.

[0160] In some examples, in combination with the reference of Figure 11 and Figure 2 , the step of performing the second etching process includes: first removing the second protective layer 126 plated on the first surface 110 (not shown in the figure) by a chain acid washing process; and then removing the initial second doped layer 124 plated on the first surface 110 and on the first region 1201 by an alkaline solution, and further removing the initial second dielectric layer 113 on the first region 1201, and the remaining initial second dielectric layer 113 on the second region 1202 is the second dielectric layer 103.

[0161] In one example, an isolation region 1203 is designed between the first region 1201 and the second region 1202. In the step of removing the initial second doped layer 124 and the initial second dielectric layer 113 on the first region 1201 by the alkaline solution, the initial second doped layer 124 and the initial second dielectric layer 113 on the isolation region 1203 are also removed.

[0162] It should be noted that Figure 11In the actual application, after the initial second doped layer and the initial second medium layer on the first region are removed, the exposed first surface and the isolation region are further subjected to texturing treatment, so that the first surface and the isolation region are both textured surfaces. For example, the textured surfaces of the first surface and the isolation region have a reflectivity of 7% to 10%, and the pyramids constituting the textured surfaces have a size of 1 μm to 2 μm.

[0163] In some embodiments, the step of providing the substrate includes: providing an initial substrate, and subjecting the initial substrate to double-sided polishing treatment to remove impurities on surfaces of the initial substrate and form a substrate with flat surfaces, thereby facilitating subsequent preparation of other film layers, for example, the initial first medium layer.

[0164] In some cases, the reflectivity of the first surface and the second surface of the substrate subjected to the double-sided polishing treatment can be 35% to 40%, and the depth of the initial substrate removed by the double-sided polishing treatment is about 3 μm to 8 μm.

[0165] In summary, at least in the step of forming the first semiconductor layer 105, the deposition temperature of the (N-1)th deposition stage is designed to be lower than that of the Nth deposition stage. On the one hand, this avoids the formation of large-sized crystal grains in the first semiconductor film 115 close to the substrate 100, the precipitation of crystal grains on the surface of the first semiconductor film 115 close to the substrate 100, and the damage to the first medium layer 101 and the substrate 100, thereby ensuring the good passivation effect of the first medium layer 101 on the substrate 100. On the other hand, this facilitates the formation of large-sized crystal grains, for example, dendritic crystal grains, in the first semiconductor film 115 away from the substrate 100. In this way, the crystallization rate of the first doped layer 102 of the (N-1)th layer of the first doped film 112 is higher than that of the Nth layer of the first doped film 112 in multiple aspects.

[0166] The following are specific embodiments of the manufacturing method of the back contact cell provided by an embodiment of the present application, as well as comparative examples related thereto:

[0167] Embodiment 1

[0168] The back contact cell 1 is prepared by the following steps:

[0169] (1) An N-type monocrystalline silicon wafer is selected, the resistivity of the N-type monocrystalline silicon wafer is about 0.5 ohmm to 10 ohmm, and the thickness of the N-type monocrystalline silicon wafer in the first direction X is about 150 μm. The N-type monocrystalline silicon wafer is subjected to double-sided polishing treatment, for example, the front surface and the back surface of the N-type monocrystalline silicon wafer are subjected to double-sided polishing by using a slot texturing device, to obtain the substrate 100.

[0170] Specifically, the damaged layer on the surface of the N-type monocrystalline silicon wafer is removed in a mixed solution containing potassium hydroxide and hydrogen peroxide, and then alkali etching is performed in a sodium hydroxide solution or a potassium hydroxide solution to form a base 100 including a flat tower base morphology, the size of the tower base is about 15 μm, the reflectivity of the tower base morphology is about 40%, and the etched depth of the N-type monocrystalline silicon wafer is about 5 μm, so that the damage to the N-type monocrystalline silicon wafer in the cutting process can be removed more thoroughly.

[0171] (2) An LPCVD process is used to prepare an aluminum oxide layer or a silicon nitride layer on the second surface as an initial first dielectric layer, wherein the thickness of the aluminum oxide layer or the silicon nitride layer can be 1 nm to 2 nm; further, an LPCVD process is used to form a carbon-doped or nitrogen-doped first semiconductor layer on the aluminum oxide layer or the silicon nitride layer, and the first semiconductor layer can be a silicon material mixed with internal crystalline and amorphous states. Specifically, a first deposition process is used to deposit a first semiconductor layer including two layers of first semiconductor films at different temperatures; wherein the deposition of the bottom layer of the first semiconductor film close to the base is at 555°C, and the thickness is 20 nm; and the deposition of the outer layer of the first semiconductor film away from the base is at 605°C, and the thickness is 330 nm.

[0172] (3) A high-temperature boron diffusion process is used to diffuse boron on the first semiconductor layer by using a tube diffusion device, so that the intrinsic amorphous silicon is converted into polycrystalline silicon, and the boron doping concentration in the polycrystalline silicon is 8×10 19 atom / cm 3 , so as to convert the first semiconductor layer into an initial first doped layer. The process temperature of the high-temperature boron diffusion process is 850°C to 1050°C. Moreover, a borosilicate glass (BSG) is formed on the side of the initial first doped layer away from the base after the high-temperature boron diffusion process.

[0173] (4) A first laser is used to perform laser processing on the BSG located on the second area to remove the BSG located on the second area. Specifically, a green laser is used, and the power of the laser device generating the green laser is controlled to be 50 W.

[0174] (5) A chain-type acid washing process is used to remove the BSG wrapped around the first surface; and then an alkali etching process is used to remove the initial first doped layer and the aluminum oxide layer or the silicon nitride layer wrapped around the first surface and located on the second area, and further to perform polishing processing on the exposed second area. The chain-type acid washing process can use a hydrofluoric acid solution with a concentration of 3% to 10%, the alkali etching process can use a sodium hydroxide solution or a potassium hydroxide solution, and the surface of the second area 1202 after the polishing processing presents a tower base with a size of 30 μm.

[0175] (6) LPCVD process is used to prepare an aluminum oxide layer or a silicon nitride layer on the second surface, which is used as an initial second medium layer, wherein the thickness of the aluminum oxide layer or the silicon nitride layer can be 1 nm to 2 nm; further, a carbon-doped or nitrogen-doped second semiconductor layer is formed on the aluminum oxide layer or the silicon nitride layer by using the LPCVD process, and the second semiconductor layer can be a silicon material with mixed internal crystalline and amorphous states. Specifically, a second deposition process is used to deposit a second semiconductor layer including two layers of second semiconductor films at different temperatures; wherein the deposition of the bottom layer of the second semiconductor film close to the substrate is at 555°C, and the thickness is 20 nm; the deposition of the outer layer of the second semiconductor film away from the substrate is at 605°C, and the thickness is 180 nm.

[0176] (7) High-temperature phosphorus diffusion is performed on the second semiconductor layer by using a tube diffusion device, and after the phosphorus diffusion, the intrinsic amorphous silicon is converted into polycrystalline silicon, and the doping concentration of phosphorus in the polycrystalline silicon is 4×10 20 atom / cm 3 , so as to convert the second semiconductor layer into an initial second doped layer. The process temperature of the high-temperature phosphorus diffusion is 850°C to 950°C. Moreover, after the high-temperature phosphorus diffusion, a phosphosilicate glass (PSG) is formed on the side of the initial second doped layer away from the substrate.

[0177] (8) The PSG located on the first area is subjected to laser treatment by using a second laser, so as to remove the PSG located on the first area. Specifically, a purple skin laser is used, and the power of the laser device generating the purple skin laser is controlled to be 10 W.

[0178] (9) The PSG circumferentially plated on the first surface is removed by using a chain-type acid washing process; then, the initial second doped layer and the aluminum oxide layer or the silicon nitride layer circumferentially plated on the first surface and located on the second area and the isolation area are removed by using a tank-type texturing device, and further, the first surface and the isolation area exposed are subjected to texturing treatment, for example, the surface reflectivity of the first surface and the isolation area is 8%, and the size of the pyramids constituting the textured surface is 2 μm.

[0179] (10) An ALD (Atomic Layer Deposition) process is used to deposit an aluminum oxide film, i.e., a first passivation layer, on the front surface and the back surface of the semi-finished back contact cell formed in step (9), and the thickness of the aluminum oxide film is 4 nm.

[0180] (11) An ALD (Atomic Layer Deposition) process is used to deposit a silicon nitride film, i.e., a second passivation layer, on the front surface and the back surface of the semi-finished back contact cell formed in step (10), and the thickness of the silicon nitride film is 80 nm.

[0181] (12) Depositing on the back surface of the semi-finished back contact cell formed in step (11) to perform screen printing to form an interdigital emitter, so as to finally form the back contact cell 1.

[0182] Comparative Example 1

[0183] The back contact cell 2 is prepared by the following steps:

[0184] Step (1) is the same as that in Example 1 and is not repeated here.

[0185] (2) A tunneling layer and an intrinsic amorphous silicon layer are prepared on the second surface by using an LPCVD process. The thickness of the tunneling layer is 1 nm to 2 nm, and the thickness of the intrinsic amorphous silicon layer is 350 nm.

[0186] (3) High-temperature boron diffusion is performed on the second surface by using a tube diffusion device to realize doping and crystallization of the intrinsic amorphous silicon layer, so as to convert the intrinsic amorphous silicon layer into a boron-doped polysilicon layer. The process temperature for high-temperature boron diffusion is 850°C to 1050°C, and the doping concentration of boron in the polysilicon layer is 8×10 19 atom / cm 3 .

[0187] Steps (4) and (5) are the same as those in Example 1 and are not repeated here.

[0188] (6) A tunneling layer and an intrinsic amorphous silicon layer are prepared again on the second surface by using an LPCVD process. The thickness of the tunneling layer is 1 nm to 2 nm, and the thickness of the intrinsic amorphous silicon layer is 350 nm.

[0189] (7) High-temperature phosphorus diffusion is performed on the second surface by using a tube diffusion device to realize doping and crystallization of the intrinsic amorphous silicon layer, so as to convert the intrinsic amorphous silicon layer into a phosphorus-doped polysilicon layer. The process temperature for high-temperature phosphorus diffusion is 850°C to 950°C, and the doping concentration of phosphorus in the polysilicon layer is 4×10 20 atom / cm 3 .

[0190] Steps (8) to (12) are the same as those in Example 1 and are not repeated here.

[0191] Table 1 is the photovoltaic index corresponding to the back contact cell 1 and the back contact cell 2.

[0192]

[0193] Note: VOC represents open-circuit voltage, Isc represents short-circuit current, FF represents fill factor, and EFF represents photoelectric conversion efficiency.

[0194] Based on the experimental results, compared with the direct formation of the tunneling layer and intrinsic amorphous silicon layer in Comparative Example 1, Example 1 uses the back contact battery manufacturing method provided in an embodiment of this application, which employs a variable temperature deposition process to form the first semiconductor layer and the second semiconductor layer. This ultimately increases the passivation effect on the first and second regions, improves the open-circuit voltage of the back contact battery, and reduces parasitic absorption of light by the first and second doped layers, thereby increasing the current density of the back contact battery. The higher roughness of the outer first doped film and the outer second doped film is beneficial for the contact between the electrode and the outer first doped film and the outer second doped film, thus improving the fill factor of the back contact battery. These factors combined result in the back contact battery 1 prepared in Example 1 having a higher conversion efficiency.

[0195] Another embodiment of this application provides a photovoltaic module for converting received light energy into electrical energy. The photovoltaic module provided in another embodiment of this application will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0196] Reference Figure 12 and Figure 13 ,as well as Figures 1 to 3 The photovoltaic module includes: a battery string, which is formed by connecting multiple back contact batteries 40 provided in the foregoing embodiments, or by connecting multiple back contact batteries 40 formed by the manufacturing method of the back contact batteries provided in the foregoing embodiments; an encapsulating film 41 for covering the surface of the battery string; and a cover plate 42 for covering the surface of the encapsulating film 41 away from the battery string.

[0197] in, Figure 12 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in another embodiment of this application; Figure 13 This is a partial cross-sectional schematic diagram of a photovoltaic module provided in another embodiment of this application.

[0198] In some embodiments, the back contact battery 40 is electrically connected in the form of a single sheet or multiple segments to form multiple battery strings, and the multiple battery strings are electrically connected in series and / or parallel. The back contact battery 40 can be a single sheet of battery or a slice of battery, where a slice of battery refers to a battery formed by cutting a single sheet of battery.

[0199] In some embodiments, in conjunction with reference Figure 12 and Figure 13 Multiple back-contact batteries 40 can be electrically connected to each other via conductive strips 43. Figure 12 and Figure 13Only the positional relationship between the back contact cells 40 is shown, that is, the side of each back contact cell 40 with the electrode is arranged towards the same side, so that the conductive strips 43 connect the same side of two adjacent back contact cells 40, respectively. In other embodiments, the back contact cells can also be arranged such that the electrodes of two adjacent back contact cells are located on different sides, and the conductive strips connect two adjacent back contact cells on different sides.

[0200] In some embodiments, the encapsulation film 41 includes a first encapsulation layer and a second encapsulation layer, the first encapsulation layer covers one of the front side or the back side of the back contact cell 40, and the second encapsulation layer covers the other of the front side or the back side of the back contact cell 40. Specifically, at least one of the first encapsulation layer or the second encapsulation layer can be an organic encapsulation film such as a polyvinyl butyral (PVB) film, an ethylene-vinyl acetate (EVA) film, a polyolefin elastomer (POE) film, or a polyethylene terephthalate (PET) film, or at least one of the first encapsulation layer or the second encapsulation layer can also be an EP film, an EPE film, or a PVP film. The EP film refers to a co-extrusion film formed by stacking an EVA film and a POE film, the EPE film refers to a co-extrusion film formed by stacking an EVA film, a POE film, and an EVA film in sequence, and the PVP film refers to a co-extrusion film formed by stacking a POE film, an EVA film, and a POE film in sequence. The co-extrusion film can be prepared by extruding one or more raw materials onto another film that has been prepared or by bonding different types of films to each other during the film processing process.

[0201] In some cases, the first encapsulation layer and the second encapsulation layer have a boundary before lamination, and after the lamination process, the photovoltaic module is formed without the concept of the first encapsulation layer and the second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0202] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or a cover plate with a light transmission function. Specifically, the surface of the cover plate 42 facing the encapsulation film 41 can be a concave-convex surface or a suede surface containing a plurality of convex structures, thereby increasing the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate, the first cover plate is opposite to the first encapsulation layer, and the second cover plate is opposite to the second encapsulation layer.

[0203] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, and therefore the protection scope of the embodiments of the present application should be subject to the scope defined by the claims.

Claims

1. A back-contact battery, characterized in that, include: A substrate having a first surface and a second surface opposite each other along a first direction, the second surface having a first region and a second region alternately arranged along a second direction; A first dielectric layer and a first doped layer are stacked on the first region, wherein the first doped layer is a P-type doped layer with P-type doping elements; A second dielectric layer and a second doped layer are stacked on the second region, wherein the second doped layer is an N-type doped layer with N-type doping elements; The P-type doped layer comprises N stacked first doped films. Along the direction away from the substrate, the crystallinity of the (N-1)th first doped film is higher than that of the Nth first doped film. The grain size in the (N-1)th first doped film is smaller than that in the Nth first doped film. The thickness of the (N-1)th first doped film is less than that of the Nth first doped film. N is a positive integer greater than or equal to 2. The N-type doped layer is a single-layer structure. Along the first direction, the thickness of the P-type doped layer is greater than the thickness of the N-type doped layer.

2. The back contact battery according to claim 1, characterized in that, When N is 2, the crystallinity of the first doped film in the (N-1)th layer is greater than or equal to 99%, and the crystallinity of the first doped film in the Nth layer is less than 95%.

3. The back contact battery according to claim 1, characterized in that, N is 2, the grain size in the first doped film of the (N-1)th layer is 100nm~180nm, and the grain size in the first doped film of the Nth layer is 190nm~300nm.

4. The back contact battery according to claim 1, characterized in that, N is 2. Along the first direction, the thickness of the first doped film in the (N-1)th layer is 10nm~60nm, and the thickness of the first doped film in the Nth layer is 10nm~500nm.

5. The back contact battery according to claim 1, characterized in that, At least one of the first doped layer and the second doped layer is polycrystalline silicon that is also doped with carbon or nitrogen; or, the material of the second doped layer includes amorphous silicon.

6. The back contact battery according to claim 1, characterized in that, The material of at least one of the first dielectric layer and the second dielectric layer includes alumina or silicon nitride; or, the material of at least one of the first dielectric layer and the second dielectric layer includes at least one of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride; or, the material of the second dielectric layer includes at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

7. The back contact battery according to claim 1, characterized in that, The doping concentration of the P-type dopant in the first doped layer is 5 × 10⁻⁶. 18 atom / cm 3 ~8×10 20 atom / cm 3 ; and / or, the doping concentration of the N-type dopant element in the second doped layer is 5 × 10⁻⁶. 19 atom / cm 3 ~9×10 20 atom / cm 3 .

8. The back contact battery according to claim 1, characterized in that, Also includes: A first passivation layer is located on the first surface and at least on the surfaces of both the first doped layer and the second doped layer that are away from the substrate; The second passivation layer is located on the surface of the first passivation layer away from the substrate; Wherein, along the first direction, the thickness of the first passivation layer is 3nm~10nm; and / or, along the first direction, the thickness of the second passivation layer is 70nm~90nm.

9. A method for manufacturing a back-contact battery, characterized in that, include: A substrate is provided, the substrate having a first surface and a second surface opposite each other along a first direction, the second surface having a first region and a second region alternately arranged along a second direction; A first dielectric layer and a first doped layer are stacked on the first region, wherein the first doped layer is a P-type doped layer with P-type doping elements; A second dielectric layer and a second doped layer are stacked on the second region, wherein the second doped layer is an N-type doped layer with N-type doping elements, and the N-type doped layer is a single film layer structure; Along the first direction, the thickness of the P-type doped layer is greater than the thickness of the N-type doped layer; The step of forming the P-type doped layer includes: forming a first semiconductor layer on the second surface using a first deposition process, the first deposition process including N deposition stages connected in sequence, the deposition temperature of the (N-1)th deposition stage being lower than the deposition temperature of the Nth deposition stage, and N being a positive integer greater than or equal to 2; performing a first doping treatment on the first semiconductor layer, so that the first semiconductor layer is transformed into an initial first doped layer doped with P-type doping elements; performing a first patterning treatment on the initial first doped layer, retaining only the initial first doped layer located on the first region as a P-type doped layer, and the P-type doped layer including N stacked first doped films, wherein along the direction away from the substrate, the crystallinity of the (N-1)th first doped film is higher than the crystallinity of the Nth first doped film, the grain size in the (N-1)th first doped film is smaller than the grain size in the Nth first doped film, and the thickness of the (N-1)th first doped film is smaller than the thickness of the Nth first doped film.

10. The method for manufacturing a back contact battery according to claim 9, characterized in that, The steps for forming the second doped layer include: A second semiconductor layer is formed on the second surface using a second deposition process; The second semiconductor layer is subjected to a second doping process, which transforms the second semiconductor layer into an initial second doped layer doped with N-type doping elements; the initial second doped layer is subjected to a second patterning process, and only the initial second doped layer located on the second region is retained as the second doped layer.

11. The method for manufacturing a back contact battery according to claim 10, characterized in that, Before forming the second semiconductor layer, the semi-finished back contact battery to which the second semiconductor layer is to be formed is placed in the reaction chamber; during the process of forming the second semiconductor layer using the second deposition process, carbon-containing gas or nitrogen-containing gas is introduced into the reaction chamber, so that the formed second semiconductor layer is doped with carbon or nitrogen elements.

12. The method for manufacturing a back contact battery according to claim 10, characterized in that, In the step of performing the second doping treatment on the second semiconductor layer, a second protective layer is also formed on the side of the initial second doped layer away from the substrate; The second protective layer located on the first region is removed using a second laser; The initial second doped layer located on the first region is removed by a second etching process, and the remaining initial second doped layer is the second doped layer. The second laser is either a purple laser or a green laser, and the power of the laser that generates the second laser is 5W to 80W.

13. The method for manufacturing a back contact battery according to claim 9, characterized in that, N is 2. The first deposition process includes a first deposition stage and a second deposition stage connected in sequence. The deposition temperature of the first deposition stage is 520℃~570℃, and the deposition temperature of the second deposition stage is 580℃~650℃.

14. The method for manufacturing a back contact battery according to claim 9, characterized in that, Before forming the first semiconductor layer, the semi-finished back contact battery to which the first semiconductor layer is to be formed is placed in the reaction chamber; during the process of forming the first semiconductor layer using the first deposition process, carbon-containing gas or nitrogen-containing gas is introduced into the reaction chamber, so that the first semiconductor layer formed is doped with carbon or nitrogen elements.

15. The method for manufacturing a back contact battery according to claim 9, characterized in that, In the step of performing the first doping treatment on the first semiconductor layer, a first protective layer is also formed on the side of the initial first doped layer away from the substrate; The first protective layer located on the second region is removed using a first laser. The initial first doped layer located on the second region is removed by a first etching process, and the remaining initial first doped layer is the first doped layer. The first laser is either a purple laser or a green laser, and the power of the laser that generates the first laser is 5W to 80W.

16. A photovoltaic module, characterized in that, include: A battery string is formed by connecting a plurality of back contact batteries as described in any one of claims 1 to 8, or by connecting a plurality of back contact batteries formed by the manufacturing method of the back contact batteries as described in any one of claims 9 to 15. An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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