An electrical impedance imaging apparatus

Abstract

The application discloses a kind of electrical impedance imaging devices, it is related to electrical impedance imaging technical field.Electrical impedance imaging device includes: electrode array, main control module, excitation signal buffer module, excitation signal amplification module, output control module and sampling module;Electrode array is used to contact with the target to be measured;Electrode array includes multiple electrodes;Main control module is used to provide excitation signal to excitation signal buffer module;Excitation signal buffer module is used to buffer excitation signal and provide to excitation signal amplification module;Excitation signal amplification module is used to amplify excitation signal and provide to output control module;Output control module is used to provide excitation signal to each electrode in time-sharing;Sampling module is used to collect the sampling signal fed back by each electrode;Main control module is also used to determine the electrical impedance distribution of the target to be measured according to the sampling signal of each electrode.The application improves the precision and stability of electrical impedance distribution measurement by using multi-stage buffer and amplification to process excitation signal.

Description

Technical Field

[0001] The present invention relates to the field of electrical impedance imaging technology, and in particular to an electrical impedance imaging device. Background Technology

[0002] Electrical Impedance Tomography (EIT) is a non-invasive, radiation-free functional imaging method with broad application prospects in clinical monitoring, industrial testing, and other fields. It achieves three-dimensional imaging of electrical impedance by measuring the electrical impedance distribution of a target object through an electrode array.

[0003] Existing electrical impedance tomography (EIT) systems typically generate excitation signals via a main control module, onboard amplifiers, and filter chips. These signals are then multiplexed and distributed to individual electrodes in an electrode array in a time-division manner to achieve impedance measurement. However, the signal chain of such EIT systems uses only a single-stage amplifier and lacks multi-stage buffering or conditioning capabilities. This makes it difficult to effectively suppress noise and distortion in the excitation signal, thus affecting the measurement accuracy of impedance distribution and limiting its application in high-precision EIT imaging scenarios. Summary of the Invention

[0004] This invention provides an electrical impedance imaging device that improves the accuracy and stability of electrical impedance distribution measurement by employing multi-stage buffering and amplification of the excitation signal.

[0005] The first aspect of the present invention provides an electrical impedance imaging device for measuring the electrical impedance distribution of a target under test. The electrical impedance imaging device includes: an electrode array, a main control module, an excitation signal buffer module, an excitation signal amplification module, an output control module, and a sampling module.

[0006] The electrode array is used to contact the target under test; the electrode array includes multiple electrodes;

[0007] The main control module is electrically connected to the excitation signal buffer module, and the main control module is used to provide excitation signals to the excitation signal buffer module;

[0008] The excitation signal buffer module is also electrically connected to the excitation signal amplification module. The excitation signal buffer module is used to buffer the excitation signal and provide it to the excitation signal amplification module.

[0009] The excitation signal amplification module is also electrically connected to the output control module. The excitation signal amplification module is used to amplify the excitation signal after it has been buffered by the excitation signal buffer module and provide it to the output control module.

[0010] The output control module is also electrically connected to each of the electrodes, and the output control module is used to provide the excitation signal amplified by the excitation signal amplification module to each of the electrodes in a time-division manner.

[0011] The sampling module is electrically connected to each of the electrodes, and the sampling module is used to collect the sampling signals fed back by each of the electrodes;

[0012] The main control module is also electrically connected to the sampling module. The main control module is also used to acquire the sampling signals of each electrode collected by the sampling module, and to determine the impedance distribution of the target under test based on the sampling signals of each electrode.

[0013] Optionally, the excitation signal buffer module includes a first operational amplifier unit, a second operational amplifier unit, and a first capacitor;

[0014] The main control module is electrically connected to the first operational amplifier unit, the first operational amplifier unit is electrically connected to the second operational amplifier unit through the first capacitor, and the second operational amplifier unit is electrically connected to the excitation signal amplification module.

[0015] Optionally, the first operational amplifier unit includes an LC oscillation circuit, a first operational amplifier, a first resistor, and a second resistor;

[0016] The main control module is electrically connected to the input terminal of the LC oscillation circuit, the output terminal of the LC oscillation circuit is electrically connected to the positive input terminal of the first operational amplifier, the inverting input terminal of the first operational amplifier is grounded through the first resistor, the inverting input terminal of the first operational amplifier is electrically connected to the output terminal of the first operational amplifier through the second resistor, and the output terminal of the first operational amplifier is electrically connected to the first terminal of the first capacitor.

[0017] Optionally, the second operational amplifier unit includes a second operational amplifier and a third resistor;

[0018] The second end of the first capacitor is electrically connected to the positive input terminal of the second operational amplifier. The positive input terminal of the second operational amplifier is grounded through the third resistor. The inverting input terminal and the output terminal of the second operational amplifier are both electrically connected to the excitation signal amplification module.

[0019] Optionally, the excitation signal amplification module includes a third operational amplifier, an instrumentation amplifier, a fourth resistor, a fifth resistor, a positive output terminal, and a negative output terminal;

[0020] The positive input terminal of the third operational amplifier is electrically connected to the excitation signal buffer module, the inverting input terminal of the third operational amplifier is grounded, and the output terminal of the third operational amplifier is electrically connected to the positive output terminal through the fourth resistor.

[0021] The inverting input terminal of the instrumentation amplifier is electrically connected to the output terminal of the instrumentation amplifier, and the non-inverting input terminal of the instrumentation amplifier is electrically connected to the non-inverting output terminal.

[0022] The negative output terminal is grounded through the fifth resistor;

[0023] Both the positive output terminal and the negative output terminal are electrically connected to the output control module.

[0024] Optionally, the output control module includes at least one output multiplexer group; the output multiplexer group includes a first multiplexer and a second multiplexer; the first multiplexer includes a first input terminal, multiple first output terminals and a first control terminal; the second multiplexer includes a second input terminal, multiple second output terminals and a second control terminal;

[0025] The excitation signal amplification module includes a positive output terminal and a negative output terminal; the first input terminal is electrically connected to the positive output terminal; the second input terminal is electrically connected to the negative output terminal;

[0026] Each of the first output terminals is electrically connected to each of the electrodes, and each of the second output terminals is electrically connected to each of the electrodes.

[0027] The first control signal output terminal of the main control module is electrically connected to the first control terminal, and the second control signal output terminal of the main control module is electrically connected to the second control terminal. The main control module is specifically used to control the first multiplexer to provide the excitation signal to each of the electrodes in a time-division manner, and at the same time, control the second multiplexer to provide the excitation signal to the electrode adjacent to the electrode that receives the excitation signal provided by the first multiplexer.

[0028] Optionally, the sampling module includes at least one sampling multiplexer group and a programmable gain amplifier;

[0029] The sampling multiplexer group includes a third multiplexer;

[0030] The third multiplexer includes multiple third input terminals, third output terminals, and third control terminals; each of the third input terminals is electrically connected to a corresponding electrode, the third control terminal is electrically connected to the third control signal output terminal of the main control module, and the third output terminal is electrically connected to the input terminal of the programmable gain amplifier.

[0031] The main control module is also used to control the third multiplexer to transmit the sampling signals fed back by each electrode to the programmable gain amplifier in a time-division manner;

[0032] The output of the programmable gain amplifier is electrically connected to the main control module. The programmable gain amplifier is used to amplify the sampling signal transmitted by the third multiplexer and then provide it to the main control module.

[0033] Optionally, the programmable gain amplifier includes a second capacitor, a fourth operational amplifier, and a differential amplifier;

[0034] The output terminal of the third multiplexer is electrically connected to the first terminal of the second capacitor, the second terminal of the second capacitor is electrically connected to the positive input terminal of the fourth operational amplifier, the inverting input terminal of the fourth operational amplifier is grounded, and the output terminal of the fourth operational amplifier is electrically connected to the inverting input terminal of the differential amplifier.

[0035] The non-inverting input terminal of the differential amplifier is grounded, the non-inverting output terminal of the differential amplifier is electrically connected to the main control module, and the inverting output terminal of the differential amplifier is grounded.

[0036] Optionally, the electrical impedance imaging device further includes: a host computer;

[0037] The main control module also includes a communication interface; the communication interface is connected to the host computer.

[0038] The main control module is also used to provide the sampling signal to the host computer through the communication interface.

[0039] Optionally, the electrical impedance imaging device further includes: a storage module;

[0040] The main control module is also electrically connected to the storage module, and the main control module is also used to store the sampled signal in the storage module.

[0041] Optionally, the electrical impedance imaging device further includes: a power supply module;

[0042] The power supply module is used to supply power to the main control module, the excitation signal buffer module, the excitation signal amplification module, the output control module, and the sampling module respectively.

[0043] The technical solution of this invention, by setting up an electrode array, a main control module, an excitation signal buffer module, an excitation signal amplification module, an output control module, and a sampling module in a power impedance imaging device, and by setting the electrode array, including multiple electrodes, to contact the target under test, lays the foundation for subsequent reconstruction of the electrical impedance distribution of the target under test through excitation electrodes. By electrically connecting the main control module to the excitation signal buffer module, the excitation signal buffer module to the excitation signal amplification module, and the excitation signal amplification module to the output control module, the main control module can provide an excitation signal to the excitation signal buffer module. The excitation signal buffer module can buffer the excitation signal and provide it to the excitation signal amplification module. The excitation signal amplification module can amplify the excitation signal buffered by the excitation signal buffer module and provide it to the output control module. Through the excitation signal buffer module and the excitation signal amplification module, multi-level buffering and amplification processing of the excitation signal is achieved, effectively improving the quality of the excitation signal provided by the excitation signal amplification module to the output control module. This enables the power impedance imaging device to cover various application scenarios and improves the accuracy and stability of electrical impedance distribution measurement. Simultaneously, by electrically connecting both the output control module and the sampling module to each electrode, the output control module can provide the amplified excitation signal (after excitation signal amplification) to each electrode in a time-division manner, and the sampling module can collect the sampling signals fed back by each electrode. Furthermore, by electrically connecting the main control module to the sampling module, the main control module can acquire the sampling signals collected by the sampling module from each electrode. The excitation signal applied to the electrodes creates a local electric field within the target under test, allowing the voltage difference between adjacent measurement electrode pairs collected by the sampling module to reflect the local changes in the internal impedance of the target under test. This enables the main control module to determine the impedance distribution of the target under test based on the sampling signals from each electrode.

[0044] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the structure of an electrical impedance imaging device provided in an embodiment of the present invention;

[0047] Figure 2This is a schematic diagram of the main control module in a power impedance imaging device provided in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the structure of an excitation signal buffer module in an electrical impedance imaging device provided in an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram of the structure of an excitation signal buffer module in an electrical impedance imaging device provided in an embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the structure of an excitation signal buffer module in an electrical impedance imaging device provided in an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of the sampling module in an electrical impedance imaging device provided in an embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram of the structure of a programmable gain amplifier in a resistive impedance imaging device provided in an embodiment of the present invention;

[0053] Figure 8 This is a schematic diagram of another electrical impedance imaging device provided in an embodiment of the present invention;

[0054] Figure 9 This is a schematic diagram of the communication interface in an electrical impedance imaging device provided in an embodiment of the present invention;

[0055] Figure 10 This is a schematic diagram of the power supply module in an electrical impedance imaging device provided in an embodiment of the present invention. Detailed Implementation

[0056] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0057] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0058] Figure 1 This is a schematic diagram of a power impedance imaging device provided in an embodiment of the present invention. The power impedance imaging device is used to measure the electrical impedance distribution of a target under test, such as... Figure 1 As shown, the electrical impedance imaging device includes: an electrode array 01, a main control module 1, an excitation signal buffer module 2, an excitation signal amplification module 3, an output control module 4, and a sampling module 5. The electrode array 01 is used to contact the target under test. The electrode array 01 includes multiple electrodes. The main control module 1 is electrically connected to the excitation signal buffer module 2 and is used to provide an excitation signal to the excitation signal buffer module 2. The excitation signal buffer module 2 is also electrically connected to the excitation signal amplification module 3 and is used to buffer the excitation signal and provide it to the excitation signal amplification module 3. The excitation signal amplification module 3 is also connected to the output control module 5. 4. Electrical connection: The excitation signal amplification module 3 is used to amplify the excitation signal buffered by the excitation signal buffer module 2 and provide it to the output control module 4; the output control module 4 is also electrically connected to each electrode, and is used to provide the excitation signal amplified by the excitation signal amplification module 3 to each electrode in a time-division manner; the sampling module 5 is electrically connected to each electrode, and is used to collect the sampling signals fed back by each electrode; the main control module 1 is also electrically connected to the sampling module 5, and is also used to acquire the sampling signals of each electrode collected by the sampling module 5, and determine the impedance distribution of the target under test based on the sampling signals of each electrode.

[0059] The electrode array 01 consists of multiple electrodes. For example, the electrodes can be made of silver or silver chloride material, and the multiple electrodes are uniformly distributed on the target to be tested, such as the surface of human tissue, so that a three-dimensional electric field covering the surface of the target to be tested can be formed by the electrode array 01. This lays the foundation for reconstructing the impedance distribution of the target to be tested by applying excitation signals to each electrode in the electrode array 01 and obtaining the sampling signals fed back by each electrode in the electrode array 01.

[0060] The main control module 1 can be specifically understood as a microcontroller. The microcontroller may have a built-in 12-bit digital-to-analog converter (DAC) and a 16-bit analog-to-digital converter (ADC), enabling the main control module 1 to generate excitation signals and acquire sampling signals via the DAC. For example, the main control module 1 may specifically include, as follows: Figure 2 The microcontroller U4 shown has pins 1-29 as output pins of the DAC and pins 1-18 as input pins of the ADC. Specifically, the main control module 1 is electrically connected to the excitation signal buffer module 2. The microcontroller's memory can pre-store discrete sampling point data of a sine wave, allowing the main control module 1 to directly read the pre-stored waveform data using a lookup table. It can also transfer the pre-stored waveform data from memory to the DAC's register via a Direct Memory Access (DMA) module, thereby providing the excitation signal to the excitation signal buffer module 2 through the DAC, significantly reducing the microcontroller's CPU utilization. For example, the excitation signal can be an adjustable sine wave excitation signal with a frequency of 1Hz-10kHz, laying the foundation for subsequent processing of the excitation signal by the excitation signal buffer module 2, the excitation signal amplification module 3, and the output control module 4, and providing it to each electrode in a time-division manner. This meets the dynamic excitation requirements of the electrical impedance imaging device for the electrodes.

[0061] After acquiring the excitation signal provided by the main control module 1, the excitation signal buffer module 2 buffers and performs preliminary filtering on the excitation signal. For example, the excitation signal buffer module 2 may include an LC oscillation circuit and an operational amplifier to eliminate high-frequency noise and distortion in the excitation signal provided by the main control module 1. Simultaneously, the excitation signal buffer module 2 is also electrically connected to the excitation signal amplification module 3. The excitation signal buffer module 2 can also provide low-impedance output and reduce attenuation during excitation signal transmission, enabling it to stably transmit the buffered and filtered excitation signal to the excitation signal amplification module 3.

[0062] After acquiring the excitation signal from the excitation signal buffer module 2, the excitation signal amplification module 3 further amplifies the excitation signal. For example, the excitation signal amplification module 3 may include an operational amplifier and an instrumentation amplifier to enable it to amplify the excitation signal with a fixed gain, such as 20dB. Simultaneously, the excitation signal amplification module 3 is electrically connected to the output control module 4. It can also condition the excitation signal through a differential input structure to stably provide the amplified excitation signal to the output control module 4, ensuring sufficient driving capability. Understandably, by using excitation signal buffer module 2 and excitation signal amplification module 3, multi-stage buffering and amplification of the excitation signal are achieved. This allows the excitation signal provided by excitation signal amplification module 3 to output control module 4 to have a frequency range of 50Hz-50kHz, an output impedance greater than 1MΩ, and errors, flatness, and stability all better than 1%, with the excitation current adjustable within 2mA. This effectively improves the quality of the excitation signal, enabling the electrical impedance imaging device to cover various application scenarios, thereby improving the accuracy and stability of electrical impedance distribution measurement. Furthermore, by using excitation signal buffer module 2 and excitation signal amplification module 3 to process the excitation signal, the use of filter chips and isolation chips in traditional single-stage amplification schemes is avoided, thus simplifying the circuit structure of the electrical impedance imaging device and reducing circuit manufacturing costs.

[0063] The output control module 4 is also electrically connected to each electrode in the electrode array 01, enabling it to provide the amplified excitation signal from the excitation signal amplification module 3 to each electrode in a time-division manner. Simultaneously, the sampling module 5 is electrically connected to each electrode in the electrode array 01, allowing it to acquire the sampling signals fed back from each electrode. It is understood that the electrodes in the electrode array 01 can be uniformly distributed in a ring shape on the surface of the target object, such as surrounding the surface of human tissue. This ring layout ensures that multiple electrodes can form a symmetrical electric field coverage in a two-dimensional plane, suitable for reconstructing three-dimensional impedance distributions. The output control module 4 may include a multiplexer, enabling it to selectively apply the amplified excitation signal from the excitation signal amplification module 3 to two adjacent electrodes in the electrode array 01 through the selective conduction of the multiplexer's output. These two electrodes can serve as excitation electrodes. The excitation signal applied to the excitation electrode can create a local electric field inside the target under test. The excitation current flows through the target under test along an approximately straight path. Due to the small distance between adjacent electrodes, the electric field is mainly concentrated in the region near the excitation electrode, thereby generating a voltage gradient related to the impedance distribution inside the target under test. The sampling module 5 may include a multiplexer so that the sampling module 5 can selectively conduct the output of the multiplexer to sequentially acquire the voltage signals generated by the excitation electrode driving multiple adjacent electrode pairs (excluding the excitation electrode). The voltage difference signal between adjacent measurement electrode pairs can reflect the voltage drop along the path of the excitation current inside the target under test. It can also be understood that the voltage difference signal measured by adjacent measurement electrode pairs reflects the local change in impedance along the path of the excitation current. Therefore, by providing the excitation signal to each electrode in a time-division manner through the output control module 4, adjacent electrode pairs in the electrode array 01 can be sequentially switched as excitation electrodes. This allows the sampling module 5 to sequentially acquire the voltage signals of all other adjacent measurement electrode pairs when different adjacent electrode pairs are used as excitation electrodes, laying the foundation for the subsequent determination of the impedance distribution of the target under test by the main control module 1.

[0064] The main control module 1 is also electrically connected to the sampling module 5, enabling it to acquire the sampling signals from each electrode collected by the sampling module 5 via an ADC. The main control module 1 can also increase the effective bit depth of the sampling signal to 14 bits to improve the resolution and reduce quantization noise. Simultaneously, the main control module 1 can determine the impedance distribution of the target under test based on the sampling signals from each electrode. For example, the main control module 1 can analyze the frequency domain characteristics of the sampling signal using a Fast Fourier Transform (FFT) to extract amplitude and phase information. This data can then be further processed using the Hough regularization algorithm to reconstruct the impedance distribution of the target under test, generating a three-dimensional image of the impedance distribution. This improves the accuracy of impedance distribution measurement, meeting the needs of primary healthcare and portable applications.

[0065] In this embodiment, an electrode array, a main control module, an excitation signal buffer module, an excitation signal amplification module, an output control module, and a sampling module are incorporated into the electrical impedance imaging device. The electrode array, comprising multiple electrodes, is placed in contact with the target under test, laying the foundation for subsequent reconstruction of the target's electrical impedance distribution using excitation electrodes. Electrical connections are established between the main control module and the excitation signal buffer module, the excitation signal buffer module and the excitation signal amplification module, and the excitation signal amplification module and the output control module. This allows the main control module to provide an excitation signal to the excitation signal buffer module, the excitation signal buffer module to buffer the excitation signal and provide it to the excitation signal amplification module, and the excitation signal amplification module to amplify the buffered excitation signal and provide it to the output control module. Through the excitation signal buffer module and the excitation signal amplification module, multi-stage buffering and amplification of the excitation signal are achieved, effectively improving the quality of the excitation signal provided to the output control module. This enables the electrical impedance imaging device to cover various application scenarios and improves the accuracy and stability of electrical impedance distribution measurement. Simultaneously, by electrically connecting both the output control module and the sampling module to each electrode, the output control module can provide the amplified excitation signal (after excitation signal amplification) to each electrode in a time-division manner, and the sampling module can collect the sampling signals fed back by each electrode. Furthermore, by electrically connecting the main control module to the sampling module, the main control module can acquire the sampling signals collected by the sampling module from each electrode. The excitation signal applied to the electrodes creates a local electric field within the target under test, allowing the voltage difference between adjacent measurement electrode pairs collected by the sampling module to reflect the local changes in the internal impedance of the target under test. This enables the main control module to determine the impedance distribution of the target under test based on the sampling signals from each electrode.

[0066] Optional, Figure 3 This is a schematic diagram of the excitation signal buffer module in an electrical impedance imaging device provided by an embodiment of the present invention, as shown below. Figure 3 As shown, the excitation signal buffer module 2 includes a first operational amplifier unit 21, a second operational amplifier unit 22, and a first capacitor C10; the main control module 1 is electrically connected to the first operational amplifier unit 21, the first operational amplifier unit 21 is electrically connected to the second operational amplifier unit 22 through the first capacitor C10, and the second operational amplifier unit 22 is electrically connected to the excitation signal amplification module 3.

[0067] Specifically, the main control module 1 is electrically connected to the first operational amplifier unit 21, enabling the first operational amplifier unit 21 to receive the excitation signal provided by the output pin of the DAC of the main control module 1. It can also perform preliminary buffering and amplification of the excitation signal to initially stabilize it and filter out some high-frequency noise, providing high-quality input for subsequent processing. The first capacitor C10 is used to connect the first operational amplifier unit 21 and the second operational amplifier unit 22 in series. The first capacitor C10 can filter out the DC component and low-frequency noise in the excitation signal output by the first operational amplifier unit 21, optimizing the quality of the excitation signal. The second operational amplifier unit 22 is electrically connected to the excitation signal amplification module 3, enabling it to further process the excitation signal output by the first operational amplifier unit 21. This ensures that the excitation signal can be stably transmitted to the excitation signal amplification module 3, thereby improving the accuracy and stability of the impedance distribution measurement.

[0068] Optional, continue to refer to Figure 3 The first operational amplifier unit 21 includes an LC oscillation circuit 201, a first operational amplifier U14.1, a first resistor R4, and a second resistor R3. The main control module 1 is electrically connected to the input terminal of the LC oscillation circuit 201, the output terminal of the LC oscillation circuit 201 is electrically connected to the non-inverting input terminal of the first operational amplifier U14.1, the inverting input terminal of the first operational amplifier U14.1 is grounded through the first resistor R4, the inverting input terminal of the first operational amplifier U14.1 is electrically connected to the output terminal of the first operational amplifier U14.1 through the second resistor R3, and the output terminal of the first operational amplifier U14.1 is electrically connected to the first terminal of the first capacitor C10.

[0069] Specifically, the main control module 1 is electrically connected to the input terminal of the LC oscillation circuit 201, and the output terminal of the LC oscillation circuit 201 is electrically connected to the positive input terminal of the first operational amplifier U14.1, so that the LC oscillation circuit 201 can receive the excitation signal provided by the output pin of the DAC of the main control module 1, and provide the excitation signal to the first operational amplifier U14.1 after filtering. The LC oscillation circuit 201 may specifically include a first inductor L2, a second inductor L3, a third inductor L4, a second capacitor C11, a third capacitor C12, a fourth capacitor C13, and a fifth capacitor C14. The first terminal of the first inductor L2 and the first terminal of the second capacitor C11 are both electrically connected to the output pin of the DAC of the main control module 1. The first terminal of the third capacitor C12 is electrically connected to the second terminal of the first inductor L2 and the first terminal of the second inductor L3, respectively. The first terminal of the fourth capacitor C13 is electrically connected to the second terminal of the second inductor L3 and the first terminal of the third inductor L4, respectively. The first terminal of the fifth capacitor C14 is electrically connected to the second terminal of the third inductor L4 and the positive input terminal of the first operational amplifier U14.1, respectively. The second terminals of the second capacitor C11, the third capacitor C12, the fourth capacitor C13, and the fifth capacitor C14 are all grounded. The inductance values ​​of the first inductor L2 are 6.8 μH, the second inductor L3 are 6.8 μH, the third inductor L4 are 8.2 μH, the second capacitor C11 is 33 pF, the third capacitor C12 is 56 pF, the fourth capacitor C13 is 68 pF, and the fifth capacitor C14 is 39 pF. This allows the LC oscillation circuit 201 to filter out high-frequency noise in the excitation signal and optimize the signal quality of the excitation signal by forming a preliminary filtering and tuning circuit.

[0070] The non-inverting input of the first operational amplifier U14.1 receives the excitation signal provided by the LC oscillation circuit 201. Simultaneously, the inverting input of the first operational amplifier U14.1 is grounded through a first resistor R4. The inverting input of the first operational amplifier U14.1 is electrically connected to its output through a second resistor R3. The resistance of the first resistor R4 is 12kΩ, and the resistance of the second resistor R3 is 1kΩ, configuring the first operational amplifier U14.1 as a non-inverting amplifier. The second resistor R3 and the first resistor R4 together determine the gain of the first operational amplifier U14.1, optimizing the amplitude of the excitation signal and further improving its stability and quality. The output of the first operational amplifier U14.1 is electrically connected to the first terminal of the first capacitor C10, enabling the first operational amplifier U14.1 to provide the excitation signal to subsequent circuits through the first capacitor C10.

[0071] Optional, continue to refer to Figure 3The second operational amplifier unit 22 includes a second operational amplifier U14.2 and a third resistor R5; the second end of the first capacitor C10 is electrically connected to the positive input terminal of the second operational amplifier U14.2, the positive input terminal of the second operational amplifier U14.2 is grounded through the third resistor R5, and the inverting input terminal and the output terminal of the second operational amplifier U14.2 are both electrically connected to the excitation signal amplification module 3.

[0072] Specifically, the positive input terminal of the second operational amplifier U14.2 can receive the excitation signal transmitted by the first capacitor C10, and the positive input terminal of the second operational amplifier U14.2 is grounded through the third resistor R5. The resistance value of the third resistor R5 is 100K. The third resistor R5 is used to prevent the positive input terminal of the second operational amplifier U14.2 from being floating and to filter out residual noise in the excitation signal. At the same time, the inverting input terminal and the output terminal of the second operational amplifier U14.2 are both electrically connected to the excitation signal amplification module 3, so that the second operational amplifier U14.2 can be configured as a voltage follower, enabling the second operational amplifier U14.2 to provide a low-impedance output, ensuring that the excitation signal can be stably transmitted to the excitation signal amplification module 3 through the output terminal SINE of the excitation signal buffer module 2.

[0073] Optional, Figure 4 This is a schematic diagram of the excitation signal buffer module in an electrical impedance imaging device provided by an embodiment of the present invention, as shown below. Figure 4 As shown, the excitation signal amplification module 3 includes a third operational amplifier U15.1, an instrumentation amplifier U3, a fourth resistor R6, a fifth resistor R7, a positive output terminal, and a negative output terminal. The positive input terminal of the third operational amplifier U15.1 is electrically connected to the excitation signal buffer module 2, the inverting input terminal of the third operational amplifier U15.1 is grounded, and the output terminal of the third operational amplifier U15.1 is electrically connected to the positive output terminal through the fourth resistor R6. The inverting input terminal of the instrumentation amplifier U3 is electrically connected to the output terminal of the instrumentation amplifier U3, and the non-inverting input terminal of the instrumentation amplifier U3 is electrically connected to the positive output terminal. The negative output terminal is grounded through the fifth resistor R7. Both the positive and negative output terminals are electrically connected to the output control module 4.

[0074] Specifically, the positive input terminal of the third operational amplifier U15.1 is electrically connected to the output terminal SINE of the excitation signal buffer module 2, so that the third operational amplifier U15.1 can receive the excitation signal provided by the excitation signal buffer module 2 through the positive input terminal. The inverting input terminal of the third operational amplifier U15.1 is grounded, and the output terminal of the third operational amplifier U15.1 is electrically connected to the positive output terminal through the fourth resistor R6. The resistance value of the fourth resistor R6 is 1KΩ, so that the third operational amplifier U15.1 is configured as a non-inverting amplifier. The fourth resistor R6 can adjust the amplitude and stability of the signal output, thereby enabling the third operational amplifier U15.1 to initially amplify the excitation signal and stably transmit it to the subsequent circuit.

[0075] The inverting input terminal of instrumentation amplifier U3, i.e., pin 2-2 of instrumentation amplifier U3, is electrically connected to the output terminal of instrumentation amplifier U3, i.e., pin 2-6 of instrumentation amplifier U3. The non-inverting input terminal of instrumentation amplifier U3, i.e., pin 2-3 of instrumentation amplifier U3, is electrically connected to the positive output terminal. This configures instrumentation amplifier U3 as a high-gain differential amplifier, enabling instrumentation amplifier U3 to receive the excitation signal provided by excitation signal buffer module 2 through the non-inverting input terminal. It can further perform differential processing, precise amplification, and impedance transformation on the excitation signal, making the excitation signal more suitable for the interface requirements of the subsequent positive output terminal. At the same time, it can suppress common-mode noise, improve the signal-to-noise ratio of the excitation signal, and ensure low distortion and high accuracy during the transmission of the excitation signal.

[0076] In addition, the excitation signal buffer module may also include a voltage reference chip U15.2. The reference voltage output terminal of the voltage reference chip U15.2, i.e., pin 3-1 of the voltage reference chip U15.2, is electrically connected to the inverting input terminal of the instrumentation amplifier U3. This allows the voltage reference chip U15.2 to provide a stable DC bias and reference level for the instrumentation amplifier U3, ensuring stable reference operation during signal amplification and conditioning, and preventing overall signal offset and accuracy degradation due to reference drift. Simultaneously, the sensing output terminal of the voltage reference chip U15.2, i.e., pins 3-5 of the voltage reference chip U15.2, is electrically connected to the output terminal of the third operational amplifier U15.1. This allows the voltage reference chip U15.2 to perform real-time sampling of the output voltage of the third operational amplifier U15.1, enabling real-time adjustment of the output reference voltage and ensuring high accuracy and stability of the output reference voltage.

[0077] The excitation signal is processed by the excitation signal buffer module 2 and the excitation signal amplification module 3, enabling the positive output terminal to provide an excitation signal to the output control module 4 with a frequency range of 50Hz-50kHz, an output impedance greater than 1MΩ, and error, flatness, and stability all better than 1%, while the excitation current is adjustable within 2mA. Simultaneously, the negative output terminal is grounded through the fifth resistor R7, which has a resistance of 0Ω, allowing the negative output terminal to connect to the reference ground, thus providing a stable reference ground potential for the positive output terminal. Both the positive and negative output terminals are electrically connected to the output control module 4, allowing them to form a differential signal pair and output to the output control module 4. This lays the foundation for the subsequent time-division provision of the excitation signal to each electrode through the output control module 4, and for reconstructing the impedance distribution of the target under test through the excitation electrodes.

[0078] Optional, Figure 5 This is a schematic diagram of the excitation signal buffer module in an electrical impedance imaging device provided by an embodiment of the present invention, as shown below. Figure 5 As shown, the output control module 4 includes at least one output multiplexer group 41; the output multiplexer group 41 includes a first multiplexer 401 and a second multiplexer 402; the first multiplexer 401 includes a first input terminal, multiple first output terminals and a first control terminal; the second multiplexer 402 includes a second input terminal, multiple second output terminals and a second control terminal; the excitation signal amplification module 3 includes a positive output terminal and a negative output terminal; the first input terminal is electrically connected to the positive output terminal; the second input terminal is electrically connected to the negative output terminal; Each first output terminal is electrically connected to each corresponding electrode, and each second output terminal is electrically connected to each corresponding electrode. The first control signal output terminal of the main control module 1 is electrically connected to the first control terminal, and the second control signal output terminal of the main control module 1 is electrically connected to the second control terminal. The main control module 1 is specifically used to control the first multiplexer 401 to provide the excitation signal to each electrode in a time-division manner, and at the same time, control the second multiplexer 402 to provide the excitation signal to the electrode adjacent to the electrode that receives the excitation signal provided by the first multiplexer 401.

[0079] Specifically, the output control module 4 includes one or more output multiplexer groups 41. The output multiplexer group 41 includes a first multiplexer 401 and a second multiplexer 402. The first input terminal of the first multiplexer 401, i.e., pins 4-28, is electrically connected to the positive output terminal. The second input terminal of the second multiplexer 402, i.e., pins 5-28, is electrically connected to the negative output terminal. The multiple first output terminals of the first multiplexer 401 and the multiple second output terminals of the second multiplexer 402 are respectively electrically connected to each electrode, so that the first multiplexer 401 and the second multiplexer 402 can respectively provide the signals provided by the positive output terminal and the negative output terminal of the excitation signal amplification module 3 to each electrode in a time-division manner. It is understood that the number of output multiplexer groups 41 in the output control module 4 can be determined based on the number of output terminals in the first multiplexer 401 and the second multiplexer 402 and the number of electrodes in the electrode array 01. For example, both the first multiplexer 401 and the second multiplexer 402 include 16 output terminals S1-S16. When the electrode array 01 includes 16 electrodes, only one output multiplexer group 41 needs to be set in the output control module 4 to realize that the multiple first output terminals of the first multiplexer 401 and the multiple second output terminals of the second multiplexer 402 are respectively electrically connected to each electrode. When the number of electrodes in the electrode array 01 is greater than 16, an additional output multiplexer group 41 can be added to the output control module 4. This invention does not specifically limit this.

[0080] Simultaneously, the first control signal output terminal of the main control module 1 is electrically connected to the first control terminal, and the second control signal output terminal of the main control module 1 is electrically connected to the second control terminal. This enables the main control module 1 to control the first multiplexer 401 to provide the excitation signal to each electrode in a time-division multiplexing manner, and at the same time, to control the second multiplexer 402 to provide the excitation signal to the electrode adjacent to the electrode that receives the excitation signal provided by the first multiplexer 401. This allows the output control module 4 to apply the excitation signal to two adjacent electrodes in the electrode array 01 through the first multiplexer 401 and the second multiplexer 402. These two electrodes can serve as excitation electrodes. The excitation signal applied to the excitation electrodes can form a local electric field inside the target under test. The excitation current flows through the target under test along an approximately straight path. Due to the small distance between adjacent electrodes, the electric field is mainly concentrated in the region near the excitation electrodes, thereby generating a voltage gradient related to the internal impedance distribution of the target under test. For example, continue to refer to... Figure 2 and Figure 5Pins 1-59 of the main control module 1 can be electrically connected to pins 4-18 of the first multiplexer 401 and pins 5-18 of the second multiplexer 402, respectively. Pins 1-81 to 1-84 of the main control module 1 are electrically connected to pins 4-17 to 4-14 of the first multiplexer 401, respectively. Pins 1-85 to 1-88 of the main control module 1 are electrically connected to pins 5-17 to 5-14 of the second multiplexer 402, respectively. This allows the main control module 1 to convert its control signals into control codes corresponding to the control terminals of the first multiplexer 401 and the second multiplexer 402 through an address decoder. This enables the main control module 1 to dynamically control the output terminals of the first multiplexer 401 and the second multiplexer 402 to be turned on.

[0081] The main control module 1 controls the first multiplexer 401 and the second multiplexer 402 to output positive and negative excitation signals to two adjacent electrodes in the electrode array 01 in sequence, so that the excitation electrode pair can be selected in the electrode array 01 in sequence, thereby realizing efficient electric field generation and impedance distribution measurement, while simplifying the circuit structure of the impedance imaging device and reducing the circuit manufacturing cost.

[0082] Optional, Figure 6 This is a schematic diagram of the sampling module in an electrical impedance imaging device provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the sampling module 5 includes at least one sampling multiplexer group 51 and a programmable gain amplifier 52; the sampling multiplexer group 51 includes a third multiplexer 501; the third multiplexer 501 includes multiple third input terminals, third output terminals, and third control terminals; each third input terminal is electrically connected to a corresponding electrode, the third control terminal is electrically connected to the third control signal output terminal of the main control module 1, and the third output terminal is electrically connected to the input terminal of the programmable gain amplifier 52; the main control module is also used to control the third multiplexer 501 to transmit the sampling signals fed back by each electrode to the programmable gain amplifier 52 in a time-division manner; the output terminal of the programmable gain amplifier 52 is electrically connected to the main control module 1, and the programmable gain amplifier 52 is used to amplify the sampling signals transmitted by the third multiplexer 501 and provide them to the main control module 1.

[0083] Specifically, the sampling module 5 includes one or more sampling multiplexer groups 51. The sampling multiplexer group 51 includes a third multiplexer 501, and the third multiplexer 501 includes multiple third input terminals and third output terminals. Each third input terminal is electrically connected to each corresponding electrode, and the third output terminal is electrically connected to the input terminal of the programmable gain amplifier 52, so that the third multiplexer 501 can transmit the sampling signals fed back by each electrode to the programmable gain amplifier 52 in a time-division multiplexing manner. It is understood that the number of sampling multiplexer groups 51 in sampling module 5 can be determined according to the number of third output terminals and the number of electrodes in electrode array 01. For example, the third multiplexer 501 includes 16 third output terminals S1-S16. When the electrode array 01 includes 16 electrodes, only one sampling multiplexer group 51 needs to be set in sampling module 5 to realize that the multiple third output terminals of the third multiplexer 501 are electrically connected to each corresponding electrode. When the number of electrodes in electrode array 01 is greater than 16, sampling multiplexer groups 51 can be added to sampling module 5 as appropriate. This invention does not make specific limitations on this.

[0084] Simultaneously, the third control signal output terminal of the main control module 1 is electrically connected to the third control terminal, enabling the main control module 1 to control the third input terminal of the third multiplexer 501 to be turned on in a time-division manner. This allows the third multiplexer 501 to sequentially acquire the sampling signals fed back from multiple adjacent electrode pairs in the electrode array 01, excluding the excitation electrode. The voltage difference signal fed back from the adjacent measurement electrode pairs can reflect the voltage drop along the path of the excitation current flowing inside the target under test. For example, when the output control module 4 applies the excitation signal to the first and second electrodes in the electrode array 01 under the control of the main control module 1, the first and second electrodes serve as excitation electrodes. Under the control of the main control module 1, the third multiplexer 501 can sequentially acquire the sampling signals fed back from the third and fourth electrodes, the fifth and sixth electrodes, and up to the fifteenth and sixteenth electrodes. It is understandable that the voltage difference signal detected by adjacent measuring electrode pairs reflects the local change in impedance along the path of the excitation current. Therefore, the output control module 4 provides the excitation signal to each electrode in a time-division manner so as to sequentially switch adjacent electrode pairs in the electrode array 01 as excitation electrodes. This allows the sampling module 5 to sequentially collect the voltage difference signal of all other adjacent measuring electrode pairs when different adjacent electrode pairs are used as excitation electrodes, laying the foundation for the subsequent determination of the impedance distribution of the target under test by the main control module 1.

[0085] It's understandable that we should continue to refer to this. Figure 2 and Figure 6Pins 1-59 of the main control module 1 can also be electrically connected to pins 6-18 of the third multiplexer 501. Pins 1-55 to 1-58 of the main control module 1 are respectively electrically connected to pins 6-17 to 6-14 of the third multiplexer 501, so that the main control module 1 can convert the control signal of the main control module 1 into the control code corresponding to the third control terminal of the third multiplexer 501 through the address decoder, thereby enabling the main control module 1 to dynamically control the output terminal of the third multiplexer 501 to be turned on.

[0086] The input of the programmable gain amplifier 52 can receive the sampling signals fed back from each electrode via time-division multiplexing from the third multiplexer 501. Simultaneously, the output of the programmable gain amplifier 52 is electrically connected to the main control module 1, enabling it to amplify the sampling signals transmitted from the third multiplexer 501 before providing them to the main control module 1. The programmable gain amplifier 52 can amplify the sampling signals through adjustable gain and enhance the signal-to-noise ratio of the sampling signals. This reduces quantization errors during subsequent digitization processing of the sampling signals by the main control module 1 and improves the accuracy of generating a three-dimensional image of the impedance distribution of the target under test using fast Fourier transform and Hough regularization algorithms. This enhances the efficiency and accuracy of impedance distribution measurement, meeting the needs of primary healthcare and portable applications. Furthermore, each first input terminal of the first multiplexer 401, each second input terminal of the second multiplexer 402, and each third input terminal of the third multiplexer 501 can be electrically connected to each corresponding electrode through the same connector, thereby simplifying the circuit structure of the electrical impedance imaging device and reducing the circuit manufacturing cost.

[0087] Optional, Figure 7 This is a schematic diagram of the structure of a programmable gain amplifier in a resistive impedance imaging device provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the programmable gain amplifier 52 includes a sixth capacitor C38, a fourth operational amplifier U17, and a differential amplifier U16; the output terminal of the third multiplexer 501 is electrically connected to the first terminal of the sixth capacitor C38, the second terminal of the sixth capacitor C38 is electrically connected to the non-inverting input terminal of the fourth operational amplifier U17, the inverting input terminal of the fourth operational amplifier U17 is grounded, and the output terminal of the fourth operational amplifier U17 is electrically connected to the inverting input terminal of the differential amplifier U16; the non-inverting input terminal of the differential amplifier U16 is grounded, the non-inverting output terminal of the differential amplifier U16 is electrically connected to the main control module 1, and the inverting output terminal of the differential amplifier U16 is grounded.

[0088] Specifically, the output of the third multiplexer 501 is electrically connected to the first terminal of the sixth capacitor C38, and the second terminal of the sixth capacitor C38 is electrically connected to the non-inverting input of the fourth operational amplifier U17. This allows the third multiplexer 501 to transmit the sampled signal to the fourth operational amplifier U17 via the sixth capacitor C38. The capacitance of the sixth capacitor C38 is 100nF, and it is used to block the DC component in the excitation signal. The inverting input of the fourth operational amplifier U17 is grounded, and the non-inverting input of the fourth operational amplifier U17 is grounded through the sixth resistor RG4. The fourth operational amplifier U17 is connected to the seventh resistor RG3, thus forming an external resistor network. The resistance of the sixth resistor RG4 is 2KΩ, and the resistance of the seventh resistor RG3 is 5KΩ. The sixth resistor RG4 and the seventh resistor RG3 are used to set the amplification gain of the fourth operational amplifier U17, for example, a gain of 20dB can be set, thereby enabling the fourth operational amplifier U17 to amplify the sampled signal and effectively suppress common-mode noise. Meanwhile, the output terminal of the fourth operational amplifier U17 is electrically connected to the first terminal of the eighth resistor R18, the second terminal of the eighth resistor R18 is electrically connected to the inverting input terminal of the differential amplifier U16, the first terminal of the seventh capacitor C41 is electrically connected to the second terminal of the eighth resistor R18 and the inverting input terminal of the differential amplifier U16 respectively, and the second terminal of the seventh capacitor C41 is grounded, so that the sampling signal output by the fourth operational amplifier U17 can be transmitted to the differential amplifier U16 after being current-limited by the eighth resistor R18 and filtered by the seventh capacitor C41 in sequence, so that the sampling signal can be further processed by the differential amplifier U16.

[0089] The non-inverting input of differential amplifier U16, i.e., pins 7-9, is grounded. The inverting output, i.e., pins 7-6, is grounded. The positive power supply port (pins 7-3 and 7-8) and negative power supply port (pins 7-8) of differential amplifier U16 are connected to a 3.3V power supply via the fourth inductor L5, which is used to suppress high-frequency power supply interference. The common-mode voltage input port, i.e., pins 7-4... The pin is connected to a reference level so that the differential amplifier U16 can scale the sampled signal at different ratios, such as 0.8X and 0.4X. This allows the differential amplifier U16 to output a sampled signal adapted to the ADC input port of the main control module 1 through its non-inverting output terminal, and to output a single-ended signal relative to the reference ground to the ADC port through its non-inverting output terminal. This satisfies the subsequent acquisition requirements of the ADC input port, improves the quality of the sampled signal input to the main control module 1, and lays the foundation for the subsequent determination of the impedance distribution of the target under test by the main control module 1.

[0090] Optional, Figure 8This is a schematic diagram of another electrical impedance imaging device provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the electrical impedance imaging device also includes: a host computer 6; the main control module 1 also includes a communication interface 11; the communication interface 11 is connected to the host computer 6; the main control module 1 is also used to provide the sampling signal to the host computer through the communication interface 11.

[0091] Specifically, after the main control module 1 acquires the sampling signals of each electrode collected by the sampling module 5 via the ADC, it can increase the effective bit depth of the sampling signal to 14 bits to improve the resolution of the sampling signal and reduce quantization noise. Simultaneously, the main control module 1 also includes a communication interface 11, which connects to the host computer 6, allowing the main control module 1 to provide the processed sampling signal to the host computer 6 via the communication interface 11. For example, the main control module 1 can acquire sampling curves with waveforms arranged in multiple sequential U-shapes through the sampling module 5. Each U-shape corresponds to the voltage difference signal of all other adjacent measurement electrode pairs when different adjacent electrode pairs are used as excitation electrodes; that is, the voltage difference of measurement electrode pairs closer to the excitation electrode is larger, and the voltage difference of measurement electrode pairs farther from the excitation electrode is smaller. After receiving the sampling signal, the host computer 6 can run a fast Fourier transform algorithm to analyze the frequency domain characteristics of the sampling signal, extract amplitude and phase information, and apply the Hough regularization algorithm to process the data to reconstruct a three-dimensional image of the impedance distribution of the target under test. The imaging software configured in the host computer 6 can further visualize the data into intuitive three-dimensional images, improving the accuracy of impedance distribution measurement to meet the needs of primary healthcare and portable applications. For example, the communication interface 11 may include a USB Type-C interface with a transmission rate of 12 Mbps to achieve high-speed data transmission, while hardware acceleration imaging in the host computer 6 can reduce the imaging latency of the impedance imaging device.

[0092] Optional, Figure 9 This is a schematic diagram of the communication interface in an electrical impedance imaging device provided in an embodiment of the present invention, as shown below. Figure 9 As shown, the USB Type-C interface U10 includes power pins, namely pins 8-11 and 8-2, and data signal pins, namely pins 8-5 to 8-8. (Continue to refer to...) Figure 2Pins 1-70 of the main control module 1 are electrically connected to pins 8-5 and 8-7 of the USB Type-C interface U10, respectively. Pin 71 of the main control module 1 is electrically connected to pins 8-6 and 8-8 of the USB Type-C interface U10, respectively, so that the main control module 1 can provide the processed sampling signal to the host computer 6 through the communication interface 11. At the same time, the power supply pins of the USB Type-C interface U10, namely pins 8-11 and 8-2, are connected to a +5V power supply. Pins 8-4 and 8-10 of the USB Type-C interface U10 are grounded through resistors R16 and R17, respectively. The resistance values ​​of resistors R16 and R17 are both 5.1KΩ, which ensures stable data signal transmission between the main control module 1 and the host computer 6, thereby improving the accuracy of impedance distribution measurement. In addition, pins 1-72 of the main control module 1 are SWD debugging interfaces, which are used to realize online firmware updates and improve the development efficiency of electrical impedance imaging devices.

[0093] Optional, continue to refer to Figure 8 The electrical impedance imaging device also includes: a storage module 7; the main control module 1 is also electrically connected to the storage module 7, and the main control module 1 is also used to store the sampled signal in the storage module.

[0094] Specifically, the main control module 1 is also electrically connected to the storage module 7, enabling the main control module 1 to store the sampling signals of each electrode acquired by the sampling module 5 in the storage module 7. For example, the storage module 7 may include off-chip Not OR Flash (NOR Flash), and the storage module may have a capacity of 32 Mbit and be able to cache 1 second of raw data. By storing the sampling signals in the storage module, offline analysis of the sampling signals is supported, data backup is provided to prevent the loss of critical information, the robustness of the electrical impedance imaging device is enhanced, the real-time processing pressure of the electrical impedance imaging device is reduced, and manufacturing costs are optimized.

[0095] Optional, continue to refer to Figure 8 The electrical impedance imaging device also includes a power supply module 8; the power supply module 8 is used to supply power to the main control module 1, the excitation signal buffer module 2, the excitation signal amplification module 3, the output control module 4 and the sampling module 5 respectively.

[0096] Specifically, the power supply module 8 is electrically connected to the main control module 1, the excitation signal buffer module 2, the excitation signal amplification module 3, the output control module 4, and the sampling module 5, respectively, so that the power supply module 8 can provide appropriate power supply voltage to the main control module 1, the excitation signal buffer module 2, the excitation signal amplification module 3, the output control module 4, and the sampling module 5, thereby ensuring the reliability and stability of the electrical impedance imaging device.

[0097] Optional, Figure 10 This is a schematic diagram of the power supply module in an electrical impedance imaging device provided by an embodiment of the present invention, as shown below. Figure 10As shown, the power supply module 8 includes an analog power supply unit 81, a digital power supply unit 82, and a reference power supply unit 83. Specifically, the analog power supply unit 81 includes a first low-dropout linear regulator U5. The input terminal of the first low-dropout linear regulator U5, namely pin 9-1, is electrically connected to a +5V voltage source, the first terminal of the eighth capacitor C24, and the first terminal of the ninth capacitor C25, respectively. The enable terminal of the first low-dropout linear regulator U5, namely pin 9-3, is electrically connected to the +5V voltage source. The output terminal of the first low-dropout linear regulator U5, namely pin 9-5, can output an analog voltage of 3.3V. The output terminal of the first low-dropout linear regulator U5 is also electrically connected to the first terminal of the tenth capacitor C26 and the first terminal of the eleventh capacitor C27. The ground terminal of the first low-dropout linear regulator U5, namely pin 9-2, the second terminal of the eighth capacitor C24, the second terminal of the ninth capacitor C25, the second terminal of the tenth capacitor C26, and the second terminal of the eleventh capacitor C27, is all grounded. The eighth capacitor C24 has a capacitance of 10μF, the ninth capacitor C25 has a capacitance of 100nF, the tenth capacitor C26 has a capacitance of 10μF, and the eleventh capacitor C27 has a capacitance of 100nF. This allows the eighth capacitor C24 and the ninth capacitor C25 to filter out high-frequency noise from the +5V voltage source, providing a stable power supply voltage for the analog power supply unit 81. The tenth capacitor C26 and the eleventh capacitor C27 can filter out high-frequency noise in the analog voltage output from the output terminal, ensuring that the analog power supply unit 81 can output a stable voltage. The output of the analog power supply unit 81 can be electrically connected to pins 1-21 of the main control module 1, the VEEA terminals of the first operational amplifier U14.1, the second operational amplifier U14.2, the third operational amplifier U15.1, the first multiplexer 401, the second multiplexer 402, the third multiplexer 501, and the fourth operational amplifier U17, respectively. This allows the analog power supply unit 81 to provide analog voltages to the main control module 1, the excitation signal buffer module 2, the excitation signal amplification module 3, the output control module 4, and the sampling module 5, respectively. Furthermore, a 100nF capacitor C40 is installed between the VEEA terminal of the fourth operational amplifier U17 and the reference ground to filter high-frequency noise and ensure stable power supply.

[0098] The digital power supply unit 82 includes a second low-dropout linear regulator U8. The input terminal of the second low-dropout linear regulator U8, specifically pin 10-1, is electrically connected to a +5V voltage source, the first terminal of the thirteenth capacitor C31, and the first terminal of the fourteenth capacitor C32, respectively. The enable terminal of the second low-dropout linear regulator U8, specifically pin 10-3, is electrically connected to the +5V voltage source. The output terminal of the second low-dropout linear regulator U8, specifically pin 10-5, outputs a digital voltage. The output terminal of the second low-dropout linear regulator U8 is also connected to the first terminal of the fifteenth capacitor C33, the first terminal of the sixteenth capacitor C17, and the first terminal of the seventeenth capacitor C18. The first terminal of capacitor 8, the first terminal of the eighteenth capacitor C19, the first terminal of the nineteenth capacitor C20, the first terminal of the twentieth capacitor C21, and the first terminal of the twenty-first capacitor C22 are electrically connected to the ground terminal of the second low-dropout linear regulator U8, that is, pin 10-2 of the second low-dropout linear regulator U8, the second terminal of the thirteenth capacitor C31, the second terminal of the fourteenth capacitor C32, the second terminal of the fifteenth capacitor C33, the second terminal of the sixteenth capacitor C17, the second terminal of the seventeenth capacitor C18, the second terminal of the eighteenth capacitor C19, the second terminal of the nineteenth capacitor C20, the second terminal of the twentieth capacitor C21, and the second terminal of the twenty-first capacitor C22 are all grounded. The thirteenth capacitor C31 has a capacitance of 47μF; the fourteenth capacitor C32, the seventeenth capacitor C18, the eighteenth capacitor C19, the nineteenth capacitor C20, the twentieth capacitor C21, and the twenty-first capacitor C22 all have a capacitance of 100nF; and the fifteenth capacitor C33 and the sixteenth capacitor C17 both have a capacitance of 10μF. This allows the thirteenth capacitor C31 and the fourteenth capacitor C32 to filter out high-frequency noise from the +5V voltage source, providing a stable power supply voltage for the digital power supply unit 82. The fifteenth capacitor C33, the sixteenth capacitor C17, the seventeenth capacitor C18, the eighteenth capacitor C19, the nineteenth capacitor C20, the twentieth capacitor C21, and the twenty-first capacitor C22 can filter out noise in the digital voltage output at the output terminal, ensuring that the digital power supply unit 82 can stably output digital voltage. The output terminals of the digital power supply unit 82 are electrically connected to pins 1-6, 1-11, 1-27, 1-50, 1-75, and 1-100 of the main control module 1, the VCCA terminal of the first operational amplifier U14.1, the VCCA terminal of the second operational amplifier U14.2, the VCCA terminal of the third operational amplifier U15.1, the VCCA terminal of the first multiplexer 401, the VCCA terminal of the second multiplexer 402, the VCCA terminal of the third multiplexer 501, and the VCCA terminal of the fourth operational amplifier U17, so that the analog power supply unit 81 can provide digital voltages to the main control module 1, the excitation signal buffer module 2, the excitation signal amplification module 3, the output control module 4, and the sampling module 5, respectively.In addition, a 22nd capacitor C39 is provided between the VCCA terminal of the fourth operational amplifier U17 and the reference ground. The capacitance value of the 22nd capacitor C39 is 100nF, which can filter high-frequency noise of the power supply and ensure stable power supply.

[0099] Reference power supply unit 83 includes a low-precision reference voltage source U6. The first terminal of the eleventh resistor R11 is electrically connected to a +5V voltage source. The second terminal of the eleventh resistor R11 is electrically connected to the first terminal of the twelfth resistor R12. The second terminal of the twelfth resistor R12 is electrically connected to the first terminal of the thirteenth resistor R13. The reference port of the low-precision reference voltage source U6 is electrically connected to the second terminal of the twelfth resistor R12 and the first terminal of the thirteenth resistor R13. The cathode port of the low-precision reference voltage source U6 is electrically connected to the second terminal of the eleventh resistor R11, the first terminal of the twelfth resistor R12, the first terminal of the twenty-third capacitor C28, and the first terminal of the twenty-fourth capacitor C29. The cathode port of the low-precision reference voltage source U6 outputs a 3.3V reference voltage. The second terminal of the thirteenth resistor R13, the anode terminal of the low-precision reference voltage source U6, the second terminal of the twenty-third capacitor C28, and the second terminal of the twenty-fourth capacitor C29 are all grounded. The eleventh resistor R11 has a resistance of 1KΩ, the twelfth resistor R12 has a resistance of 1.5KΩ, the thirteenth resistor R13 has a resistance of 4.7KΩ, the twenty-third capacitor C28 has a capacitance of 10μF, and the twenty-fourth capacitor C29 has a capacitance of 100nF. This allows the eleventh resistor R11 to limit current, the twelfth and thirteenth resistors R12 and R13 to divide the voltage, and the twenty-third and twenty-fourth capacitors C28 and C29 to filter the reference voltage, ensuring that the reference power supply unit 83 can stably output a reference voltage. The output of the reference power supply unit 83 is electrically connected to pins 1-20 of the main control module 1 and the common-mode voltage input port of the differential amplifier U16, so that the reference power supply unit 83 can provide a reference voltage to the main control module 1 and the sampling module 5.

[0100] In addition, continue to refer to Figure 2Pins 1-42 and 1-43 of the main control module 1 are specifically used to output level signals to control the on / off state and blinking of the first LED (LED3) and the second LED (LED2), respectively, to indicate the working status of the impedance imaging device. A fourteenth resistor R14 is provided between pins 1-42 and the first LED (LED3), and a fifteenth resistor R15 is provided between pins 1-43 and the second LED (LED2). Both resistors R14 and R15 have a resistance value of 1KΩ, which limits current to prevent damage to the first LED (LED3) and the second LED (LED2) due to excessive current, ensuring circuit safety. Pins 1-31 of the main control module 1 are electrically connected to the intelligent RGB LED (LED4). Pins 1-31 are used to control the intelligent RGB LED (LED4) to achieve precise control of RGB color and brightness, enabling the first LED (LED3) and the second LED (LED2) to display rich color effects.

[0101] It is also understood that multiple decoupling capacitors can be set in the electrical impedance imaging device. For example, the decoupling capacitors can be ceramic capacitors with a capacitance of 100nF. The decoupling capacitors can be set close to the power supply pins of the main control module 1, the excitation signal buffer module 2, the excitation signal amplification module 3, the output control module 4, and the sampling module 5, such as the VCCA and VEEA pins, so as to reduce parasitic inductance, suppress high-frequency electromagnetic interference, and improve the power supply rejection ratio (PSRR) through the decoupling capacitors. This can meet the needs of medical and industrial equipment for electrical impedance distribution measurement, and reduce the circuit manufacturing cost of the electrical impedance imaging device, thereby improving the performance and economy of the electrical impedance imaging device.

[0102] It is also understandable that by setting up an excitation signal buffer module 2 and an excitation signal amplification module 3 in the electrical impedance imaging device to process the excitation signal, the use of filter chips and isolation chips in the traditional single-stage amplification scheme is avoided, simplifying the circuit structure of the electrical impedance imaging device. Therefore, the electrical impedance imaging device can reduce the number of PCB layers required, achieving the performance of a traditional electrical impedance imaging device with only 2 PCB layers, reducing the circuit manufacturing cost of the electrical impedance imaging device, and improving the performance and economy of the electrical impedance imaging device.

[0103] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

[0104] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A power impedance imaging device for measuring the power impedance distribution of a target, characterized in that, include: Electrode array, main control module, excitation signal buffer module, excitation signal amplification module, output control module, and sampling module; The electrode array is used to contact the target under test; the electrode array includes multiple electrodes; The main control module is electrically connected to the excitation signal buffer module, and the main control module is used to provide excitation signals to the excitation signal buffer module; The excitation signal buffer module is also electrically connected to the excitation signal amplification module. The excitation signal buffer module is used to buffer the excitation signal and provide it to the excitation signal amplification module. The excitation signal amplification module is also electrically connected to the output control module. The excitation signal amplification module is used to amplify the excitation signal after it has been buffered by the excitation signal buffer module and provide it to the output control module. The output control module is also electrically connected to each of the electrodes, and the output control module is used to provide the excitation signal amplified by the excitation signal amplification module to each of the electrodes in a time-division manner. The sampling module is electrically connected to each of the electrodes, and the sampling module is used to collect the sampling signals fed back by each of the electrodes; The main control module is also electrically connected to the sampling module. The main control module is also used to acquire the sampling signals of each electrode collected by the sampling module, and to determine the impedance distribution of the target under test based on the sampling signals of each electrode. The excitation signal amplification module includes a third operational amplifier, an instrumentation amplifier, a voltage reference chip, a fourth resistor, a fifth resistor, a positive output terminal, and a negative output terminal. The positive input terminal of the third operational amplifier is electrically connected to the excitation signal buffer module, the inverting input terminal of the third operational amplifier is grounded, and the output terminal of the third operational amplifier is electrically connected to the positive output terminal through the fourth resistor. The inverting input terminal of the instrumentation amplifier is electrically connected to the output terminal of the instrumentation amplifier, and the non-inverting input terminal of the instrumentation amplifier is electrically connected to the positive output terminal. The reference voltage output terminal of the voltage reference chip is electrically connected to the inverting input terminal of the instrumentation amplifier, and the sensing output terminal of the voltage reference chip is electrically connected to the output terminal of the third operational amplifier. The negative output terminal is grounded through the fifth resistor. Both the positive and negative output terminals are electrically connected to the output control module.

2. The electrical impedance imaging device according to claim 1, characterized in that, The excitation signal buffer module includes a first operational amplifier unit, a second operational amplifier unit, and a first capacitor; The main control module is electrically connected to the first operational amplifier unit, the first operational amplifier unit is electrically connected to the second operational amplifier unit through the first capacitor, and the second operational amplifier unit is electrically connected to the excitation signal amplification module.

3. The electrical impedance imaging device according to claim 2, characterized in that, The first operational amplifier unit includes an LC oscillation circuit, a first operational amplifier, a first resistor, and a second resistor; The main control module is electrically connected to the input terminal of the LC oscillation circuit, the output terminal of the LC oscillation circuit is electrically connected to the positive input terminal of the first operational amplifier, the inverting input terminal of the first operational amplifier is grounded through the first resistor, the inverting input terminal of the first operational amplifier is electrically connected to the output terminal of the first operational amplifier through the second resistor, and the output terminal of the first operational amplifier is electrically connected to the first terminal of the first capacitor.

4. The electrical impedance imaging device according to claim 2, characterized in that, The second operational amplifier unit includes a second operational amplifier and a third resistor; The second end of the first capacitor is electrically connected to the positive input terminal of the second operational amplifier. The positive input terminal of the second operational amplifier is grounded through the third resistor. The inverting input terminal and the output terminal of the second operational amplifier are both electrically connected to the excitation signal amplification module.

5. The electrical impedance imaging device according to claim 1, characterized in that, The output control module includes at least one output multiplexer group; the output multiplexer group includes a first multiplexer and a second multiplexer; the first multiplexer includes a first input terminal, multiple first output terminals and a first control terminal; the second multiplexer includes a second input terminal, multiple second output terminals and a second control terminal; The excitation signal amplification module includes a positive output terminal and a negative output terminal; the first input terminal is electrically connected to the positive output terminal; the second input terminal is electrically connected to the negative output terminal; Each of the first output terminals is electrically connected to each of the electrodes, and each of the second output terminals is electrically connected to each of the electrodes. The first control signal output terminal of the main control module is electrically connected to the first control terminal, and the second control signal output terminal of the main control module is electrically connected to the second control terminal. The main control module is specifically used to control the first multiplexer to provide the excitation signal to each of the electrodes in a time-division manner, and at the same time, control the second multiplexer to provide the excitation signal to the electrode adjacent to the electrode that receives the excitation signal provided by the first multiplexer.

6. The electrical impedance imaging device according to claim 1, characterized in that, The sampling module includes at least one sampling multiplexer group and a programmable gain amplifier; The sampling multiplexer group includes a third multiplexer; The third multiplexer includes multiple third input terminals, third output terminals, and third control terminals; each of the third input terminals is electrically connected to a corresponding electrode, the third control terminal is electrically connected to the third control signal output terminal of the main control module, and the third output terminal is electrically connected to the input terminal of the programmable gain amplifier. The main control module is also used to control the third multiplexer to transmit the sampling signals fed back by each electrode to the programmable gain amplifier in a time-division manner; The output of the programmable gain amplifier is electrically connected to the main control module. The programmable gain amplifier is used to amplify the sampling signal transmitted by the third multiplexer and then provide it to the main control module.

7. The electrical impedance imaging device according to claim 6, characterized in that, The programmable gain amplifier includes a second capacitor, a fourth operational amplifier, and a differential amplifier; The output terminal of the third multiplexer is electrically connected to the first terminal of the second capacitor, the second terminal of the second capacitor is electrically connected to the positive input terminal of the fourth operational amplifier, the inverting input terminal of the fourth operational amplifier is grounded, and the output terminal of the fourth operational amplifier is electrically connected to the inverting input terminal of the differential amplifier. The non-inverting input terminal of the differential amplifier is grounded, the non-inverting output terminal of the differential amplifier is electrically connected to the main control module, and the inverting output terminal of the differential amplifier is grounded.

8. The electrical impedance imaging device according to claim 1, characterized in that, Also includes: Host computer; The main control module also includes a communication interface; the communication interface is connected to the host computer. The main control module is also used to provide the sampling signal to the host computer through the communication interface.

9. The electrical impedance imaging device according to claim 1, characterized in that, Also includes: Storage module; The main control module is also electrically connected to the storage module, and the main control module is also used to store the sampled signal in the storage module.

10. The electrical impedance imaging device according to claim 1, characterized in that, Also includes: Power module; The power supply module is used to supply power to the main control module, the excitation signal buffer module, the excitation signal amplification module, the output control module, and the sampling module respectively.

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