Design method, device and equipment of virtual system model based on sysml language and medium

Abstract

The application discloses a design method, device and equipment of a virtual system model based on a SysML language, and a medium, and relates to the field of system model structure design. The method comprises the following steps: defining a function unit group and a simulation unit group; determining a nesting relationship between the function unit group and the simulation unit group; constructing an association relationship between subunit groups of the function unit group; constructing an association relationship between subunit groups of the simulation unit group; constructing an association relationship between the subunit groups of the function unit group and the subunit groups of the simulation unit group; and performing time design on tasks and CPUs.

Description

Technical Field

[0001] This invention relates to the field of system model structure design, and in particular to the design methods, apparatus, devices and media for virtual system models created based on the SysML language. Background Technology

[0002] SysML (System Modeling Language) is a standardized modeling methodology for describing and analyzing complex systems. The SysML language definition comprises two parts: SysML semantics and SysML notation. Semantically, it defines semantics for the system's structural model, behavioral model, requirement model, and parametric model, emphasizing different aspects of the system respectively.

[0003] Existing system design solutions based on SysML only describe the overall process architecture of applying test cases to the system simulation architecture, lacking a description of the construction of a virtual synthesis system model from SysML, and failing to elaborate on how to build a virtual synthesis system based on the SysML meta-model. Therefore, how to construct a simulation system architecture based on SysML is an urgent problem to be solved. Summary of the Invention

[0004] This invention solves the technical problem of how to construct simulation system architecture in the prior art by providing a design method, apparatus, device and medium for virtual system models created based on the SysML language, and achieves the technical effect of efficiently constructing simulation system architecture.

[0005] In a first aspect, the present invention provides a design method for a virtual system model based on the SysML language, including:

[0006] Define functional unit groups and simulation unit groups, each of which contains several sub-unit groups;

[0007] Determine the nesting relationship between functional unit groups and simulation unit groups, where the nesting relationship refers to the nesting relationship between the sub-unit groups of functional unit groups and the sub-unit groups of simulation unit groups;

[0008] Establish the relationships between the sub-unit groups of the functional unit group;

[0009] Establish the relationships between sub-unit groups of the simulation unit group;

[0010] Establish the relationships between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group;

[0011] The timing design is performed for tasks and CPUs, where both tasks and CPUs are sub-units within the simulation unit group.

[0012] Furthermore, the sub-unit groups of the functional unit group include:

[0013] Functional units, FMU, LUA, judgments, variables, and plugins.

[0014] Furthermore, the sub-unit groups of the simulation unit group include:

[0015] Tasks, systems, devices, CPUs, and buses.

[0016] Furthermore, the nesting relationship between functional unit groups and simulation unit groups is determined, including:

[0017] The system may contain several other systems, several devices, or several buses.

[0018] The device may contain several CPUs or several buses.

[0019] CPU nests several tasks;

[0020] A task is nested within a functional unit.

[0021] Furthermore, the relationships between the sub-unit groups of the functional unit group are constructed, including:

[0022] Based on ports, the FMU interacts with other sub-unit groups of the functional unit group via data flow or control flow;

[0023] Based on ports, LUA interacts with other subgroups of functional units via data flow or control flow.

[0024] The decision is made to interact with other subgroups of the functional unit group via control flow.

[0025] Based on ports, variables interact with other subgroups of functional units via data flow or control flow;

[0026] Based on ports, functional units interact with other sub-unit groups of functional unit groups via data flow or control flow.

[0027] Furthermore, the relationships between the sub-unit groups of the simulation unit group are constructed, including:

[0028] The task interacts with the remaining sub-units of the simulation unit group via control flow;

[0029] Based on the channel, the system interacts with the other sub-units of the simulation unit group via data streams;

[0030] Based on the channel, the device interacts with the other sub-units of the simulation unit group via data streams;

[0031] The CPU interacts with the other sub-units of the simulation unit group via control flow;

[0032] Based on bus nodes, the bus interacts with the other sub-unit groups of the simulation unit group via data streams.

[0033] Furthermore, the timing design for tasks and CPUs includes:

[0034] Determine the start time, execution time, end time, cycle time, and jitter time for each task or CPU.

[0035] Secondly, the present invention provides a design apparatus for a virtual system model based on the SysML language, comprising:

[0036] The definition module is used to define functional unit groups and simulation unit groups, each of which contains several sub-unit groups.

[0037] Nested modules are used to determine the nesting relationship between functional unit groups and simulation unit groups, where the nesting relationship refers to the nesting relationship between the sub-unit groups of functional unit groups and the sub-unit groups of simulation unit groups;

[0038] The first association module is used to construct the association relationships between the sub-unit groups of the functional unit group;

[0039] The second association module is used to construct the association relationships between the sub-unit groups of the simulation unit group;

[0040] The third association module is used to construct the association relationship between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group;

[0041] The timing design module is used to design the timing of tasks and CPUs, where tasks and CPUs are sub-units within the simulation unit group.

[0042] Thirdly, the present invention provides an electronic device, comprising:

[0043] processor;

[0044] Memory used to store processor-executable instructions;

[0045] The processor is configured to execute a design method for a virtual system model created using the SysML language, as provided in the first aspect.

[0046] Fourthly, the present invention provides a non-transitory computer-readable storage medium, wherein when the instructions in the non-transitory computer-readable storage medium are executed by a processor of an electronic device, the electronic device is able to execute a design method for implementing a virtual system model based on the SysML language as provided in the first aspect.

[0047] One or more technical solutions provided in this invention have at least the following technical effects or advantages:

[0048] This invention provides a design method for SysML bearer functional unit groups, a design method for SysML bearer simulation unit groups, and a design method for SysML bearer CPUs and tasks in terms of time attributes.

[0049] This method leverages the advantages of SysML in system modeling to provide a structured solution for the design of virtual system models. In the SysML-based design method for functional unit groups, by defining and organizing sub-unit groups and their relationships, the functional architecture of the system can be clearly described, which helps to improve the modularity and maintainability of the design.

[0050] The design method for SysML-based simulation unit groups determines the nesting and correlation between functions and simulation unit groups, enabling complex system behaviors to be accurately simulated through models. This helps to identify potential problems in advance and optimize system performance.

[0051] SysML provides a design methodology for CPU and task time attributes, allowing for detailed planning and verification of the system's time dimension. This ensures efficient task scheduling and resource allocation, thereby improving the system's real-time responsiveness and overall performance. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 A flowchart illustrating the design method for a virtual system model based on the SysML language provided by this invention;

[0054] Figure 2 A schematic diagram illustrating the nesting relationship between subunit groups provided by the present invention;

[0055] Figure 3 This invention provides a schematic diagram illustrating the relationships between sub-unit groups of a functional unit group.

[0056] Figure 4 A schematic diagram illustrating the relationship between sub-unit groups of the simulation unit group provided by this invention;

[0057] Figure 5This is a schematic diagram illustrating the relationship between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group provided by the present invention. Detailed Implementation

[0058] This invention provides a design method for virtual system models created using the SysML language, thus solving the technical problem of how to construct simulation system architecture in the prior art.

[0059] The technical solution of this invention is to solve the above-mentioned technical problems, and the overall idea is as follows:

[0060] The design method for virtual system models created using SysML includes: defining functional unit groups and simulation unit groups, each containing several sub-unit groups; determining the nesting relationship between functional unit groups and simulation unit groups, where nesting refers to the nesting relationship between sub-unit groups of functional unit groups and sub-unit groups of simulation unit groups; constructing the association relationship between sub-unit groups of functional unit groups; constructing the association relationship between sub-unit groups of simulation unit groups; constructing the association relationship between sub-unit groups of functional unit groups and sub-unit groups of simulation unit groups; and performing time design for tasks and CPUs, where tasks and CPUs are both sub-unit groups within simulation unit groups.

[0061] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0062] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0063] In the XML representation of SysML (System Modeling Language), the packagedElement is an important syntactic element used to define various elements in the model, such as classes, packages, and relationships. The entire solution combines the syntactic features of SysML to describe the essential elements required for a virtual integrated system model.

[0064] This allows for the integration and expression of various system elements, such as structure, behavior, and performance, within the MBSE framework, in the form of models, forming a methodology for constructing XML-formatted model files. Computer simulation technology is then used to parse this XML file, simulating the system's operation under different conditions from a design principle perspective, thereby achieving goals such as functional verification, performance evaluation, and optimization design of the system.

[0065] In the solution provided by this invention, a class is defined by packagedElement, the following unit group categories are designed, and then the data transmission and logical nesting relationship between unit groups is established to realize the construction of a virtual integrated simulation system model.

[0066] This invention provides, for example Figure 1 The design method for the virtual system model created using the SysML language, as shown, includes steps S11-S16:

[0067] Step S11: Define functional unit groups and simulation unit groups. Both functional unit groups and simulation unit groups contain several sub-unit groups.

[0068] The functional unit group includes subgroups such as: functional units, FMU, LUA, decision, variables, and plugins.

[0069] FMU (Functional Mock-up Unit): Contains an FMU loader for integrating FMU models based on the FMI standard.

[0070] LUA (Lightweight, efficient, and embeddable scripting language): Supports loading Lua file models and automatically adding ports based on the file.

[0071] Port: A port that carries signal data and is used for exchanging data between the inside and outside of a structure.

[0072] Judgment: Used in conjunction with control flow, this determines whether the control structure is executed. The target structure will only be executed if the conditions are met.

[0073] Variables: Provides system variable data during simulation and supports custom constants.

[0074] Plugins: Custom, extensible, special functional units

[0075] The simulation unit group consists of sub-unit groups, including: tasks, systems, devices, CPUs, and buses.

[0076] System: A nestable simulation architecture that supports the addition of other systems, devices, and buses.

[0077] Devices: Cannot be nested, but internally support the addition of CPUs, tasks, and buses;

[0078] Task: The smallest unit of the simulation model, bound to functional units as execution logic;

[0079] Bus: Used to simulate different types of bus transmission behavior;

[0080] CPU: A task-dedicated computing resource that supports multiple cores and is used to simulate task concurrency and preemption.

[0081] See Table 1 for details:

[0082] Table 1

[0083]

[0084] In addition, a functional unit called "digital generator" is also provided.

[0085] SysML syntax:

[0086] <packagedelement isreentrant="true" name="数字产生器" visibility="public" xmi:id="82028976816037184" xmi:type="uml:Activity">

[0087] < / packagedelement>

[0088] <WinRingSimProfile:SimulationUnitbase_Activity="82028976816037184"xmi:id="82028976816037184_application" / >

[0089] Regarding the code implementation of the above functional unit groups and simulation unit groups:

[0090] Complete SysML packagedElement definition semantics

[0091] <winringsimprofile: SimulationTask base_Class="略" xmi:id="略" / >

[0092] <winringsimprofile: SimulationSystem base_Class="略" xmi:id="略" / >

[0093] <winringsimprofile: SimulationDevice base_Class="略" xmi:id="略" / >

[0094] <winringsimprofile: SimulationCPU base_Class="略" xmi:id="略" / >

[0095] <winringsimprofile: SimulationBus base_Class="略" xmi:id="略" / >

[0096] <winringsimprofile: SimulationUnit base_Activity="略" xmi:id="略" / >

[0097] <winringsimprofile: SimulationFMU base_Activity="略" xmi:id="略" / >

[0098] <winringsimprofile: SimulationLua base_Activity="略" xmi:id="略" / >

[0099] <winringsimprofile: SimulationDecisionNode base_Activity="略" xmi:id="略" / >

[0100] <winringsimprofile: SimulationVariable base_Activity="略" xmi:id="略" / >

[0101] <winringsimprofile: SimulationPlugin base_Activity="略" xmi:id="略" / >

[0102] Step S12: Determine the nesting relationship between the functional unit group and the simulation unit group, where the nesting relationship refers to the nesting relationship between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group.

[0103] like Figure 2As shown, Figure 2 This is a schematic diagram illustrating the nesting relationship between sub-unit groups provided by the present invention. It is understood that, regardless of the nesting method, the following description is sufficient. Figure 2 Taking this as an example, the overall system is the system. The overall system can nest system A, system A can nest multiple devices, and each device can nest a CPU, and each CPU can nest several tasks.

[0104] Determine the nesting relationship between functional unit groups and simulation unit groups, including: a system nests several other systems, or nests several devices, or nests several buses; a device nests several CPUs, or nests several buses; a CPU nests several tasks; a task nests a functional unit.

[0105] Step S13: Construct the association relationship between the sub-unit groups of the functional unit group.

[0106] The following terms will be explained in detail:

[0107] The relationships between sub-unit groups involve data flow and control flow. The nodes where data interacts between sub-unit groups are called interfaces. Interfaces are distinguished by different types on different design elements, including ports, channels, and bus nodes.

[0108] Data stream: The behavior of transferring specified data between ports, supporting byte transmission and signal transmission.

[0109] Control flow: controls the execution order; the structure it points to is executed after the structure that initiated it.

[0110] Port: An interface that carries signal data and is used for exchanging data within or outside the functional unit structure. It can carry specific data transmission formats.

[0111] Channel: The interface through which systems and devices exchange internal and external data, and can carry specific data transmission formats.

[0112] Bus node: The interface between internal and external data on the bus, which can carry specific data transmission formats.

[0113] It is understandable that the above description is applicable in steps S13, S14, and S15.

[0114] like Figure 3 As shown, Figure 3 This is a schematic diagram illustrating the relationship between sub-unit groups of the functional unit group provided by the present invention. It can be understood that... Figure 3 This is merely one form provided by the present invention, and any form that satisfies the following description is acceptable. Figure 3For example, the leftmost functional unit contains two ports, which are connected to the judgment in the form of control flow transmission. After the judgment logic is executed, they are connected to the other two functional units respectively according to the logic in the judgment.

[0115] Establish the relationships between subgroups of functional unit groups, including:

[0116] Based on ports, the FMU interacts with other sub-unit groups of the functional unit group via data flow or control flow;

[0117] Based on ports, LUA interacts with other subgroups of functional units via data flow or control flow.

[0118] The decision is made to interact with other subgroups of the functional unit group via control flow.

[0119] Based on ports, variables interact with other subgroups of functional units via data flow or control flow;

[0120] Based on ports, functional units interact with other sub-unit groups of functional unit groups via data flow or control flow.

[0121] Step S14: Construct the association relationship between the sub-unit groups of the simulation unit group.

[0122] like Figure 4 As shown, Figure 4 The diagram illustrating the relationship between sub-unit groups of the simulation unit group provided by this invention is, as mentioned above, Figure 4 The connection relationship shown is only one possible form of connection. The specific relationship should meet the following requirements.

[0123] Constructing the relationships between sub-unit groups of the simulation unit group includes:

[0124] The task interacts with the remaining sub-units of the simulation unit group via control flow;

[0125] Based on the channel, the system interacts with the other sub-units of the simulation unit group via data streams;

[0126] Based on the channel, the device interacts with the other sub-units of the simulation unit group via data streams;

[0127] The CPU interacts with the other sub-units of the simulation unit group via control flow;

[0128] Based on bus nodes, the bus interacts with the other sub-unit groups of the simulation unit group via data streams.

[0129] Step S15: Establish the association between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group.

[0130] Figure 5 This is a schematic diagram illustrating the relationship between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group provided by the present invention. Specifically, it should meet the following requirements.

[0131] Specifically, it includes:

[0132] Based on ports, the FMU interacts with other sub-unit groups via data flow or control flow;

[0133] Based on ports, LUA interacts with other sub-unit groups via data flow or control flow;

[0134] Determine whether there is interaction with other sub-unit groups via control flow;

[0135] Based on ports, variables interact with other sub-unit groups via data flow or control flow;

[0136] Based on ports, functional units interact with other subunit groups via data flow or control flow;

[0137] The task interacts with the other sub-unit groups via control flow;

[0138] Based on the channel, the system interacts with the other sub-unit groups via data streams;

[0139] Based on the channel, the device interacts with the other sub-unit groups via data streams;

[0140] The CPU interacts with the other subunit groups via control flow;

[0141] Based on bus nodes, the bus interacts with the remaining sub-unit groups via data streams.

[0142] Table 2 can be used as a reference for the relationships between subunit groups.

[0143] Table 2

[0144]

[0145] Step S16: Perform time design for the task and CPU, where both the task and CPU are sub-unit groups in the simulation unit group.

[0146] The timing design for tasks and CPUs includes: determining the start time, execution time, end time, cycle time, and jitter time for each task or CPU.

[0147] By incorporating time-based design into tasks and CPUs, the execution order and cyclical patterns of tasks can be established.

[0148] The task begins execution, generating specific data through associated functional units. This data is transmitted via ports to the next interface, which could be a port of the next functional unit, a channel of the next simulation unit, or a bus node. Through the relationships between these interfaces, the data flows between different units. Finally, the data reaches the target unit of the design.

[0149] The time design includes the task's start time, execution time, end time, and cycle time. To better simulate realistic physical models, the concept of "time jitter" has been added to the time design.

[0150] Time jitter refers to the instability of a signal along the time axis, manifested as a random deviation between the actual arrival time of the signal and the ideal time. In fields such as digital signal processing, communication system simulation, and computer system simulation, time jitter is a critical performance indicator that directly affects the stability, accuracy, and reliability of the system.

[0151] A CPU can contain multiple tasks, and the time attributes of a task can be inherited from the CPU. The range of time jitter can be randomly distributed or normally distributed.

[0152] Table 3 shows the element attributes for CPU and task time design.

[0153] Table 3

[0154]

[0155] In summary, this invention provides a design method for virtual system models created using the SysML language, including: defining functional unit groups and simulation unit groups, each containing several sub-unit groups; determining the nesting relationship between functional unit groups and simulation unit groups, where the nesting relationship refers to the nesting relationship between sub-unit groups of functional unit groups and sub-unit groups of simulation unit groups; constructing the association relationship between sub-unit groups of functional unit groups; constructing the association relationship between sub-unit groups of simulation unit groups; constructing the association relationship between sub-unit groups of functional unit groups and sub-unit groups of simulation unit groups; and performing time design for tasks and CPUs, where tasks and CPUs are both sub-unit groups within simulation unit groups. This invention provides a design method for SysML-based functional unit groups, a design method for SysML-based simulation unit groups, and a design method for SysML-based CPUs and tasks in terms of time attributes. This method leverages the advantages of SysML in system modeling, providing a structured solution for the design of virtual system models. In the SysML-based design method for functional unit groups, defining and organizing sub-unit groups and their interrelationships clearly describes the system's functional architecture, improving modularity and maintainability. For the SysML-based design method for simulation unit groups, defining the nesting and interrelationships between functional and simulation unit groups allows for accurate simulation of complex system behaviors, facilitating early detection of potential problems and optimization of system performance. The SysML-based design method for CPU and task time attributes allows for detailed planning and verification of the system's time dimension, ensuring efficient task scheduling and resource allocation, thereby enhancing the system's real-time responsiveness and overall performance.

[0156] Based on the same inventive concept, the present invention provides a design apparatus for a virtual system model created using the SysML language, comprising:

[0157] The definition module is used to define functional unit groups and simulation unit groups, each of which contains several sub-unit groups.

[0158] Nested modules are used to determine the nesting relationship between functional unit groups and simulation unit groups, where the nesting relationship refers to the nesting relationship between the sub-unit groups of functional unit groups and the sub-unit groups of simulation unit groups;

[0159] The first association module is used to construct the association relationships between the sub-unit groups of the functional unit group;

[0160] The second association module is used to construct the association relationships between the sub-unit groups of the simulation unit group;

[0161] The third association module is used to construct the association relationship between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group;

[0162] The timing design module is used to design the timing of tasks and CPUs, where tasks and CPUs are sub-units within the simulation unit group.

[0163] Based on the same inventive concept, an electronic device is also provided, comprising:

[0164] processor;

[0165] Memory used to store processor-executable instructions;

[0166] The processor is configured to execute a design method for a virtual system model created using the SysML language, as described above.

[0167] Based on the same inventive concept, this invention also provides a non-transitory computer-readable storage medium that, when the instructions in the storage medium are executed by the processor of an electronic device, enables the electronic device to execute a design method that implements the virtual system model created based on the SysML language as described above.

[0168] Since the electronic device described in this embodiment is an electronic device used to implement the information processing method in the embodiments of the present invention, those skilled in the art can understand the specific implementation methods and various variations of the electronic device in this embodiment based on the information processing method described in the embodiments of the present invention. Therefore, how the electronic device implements the method in the embodiments of the present invention will not be described in detail here. Any electronic device used by those skilled in the art to implement the information processing method in the embodiments of the present invention falls within the scope of protection of the present invention.

[0169] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0170] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0171] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0172] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0173] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0174] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A design method for virtual system models based on the SysML language, characterized in that, include; Define functional unit groups and simulation unit groups, each of which contains several sub-unit groups; Determine the nesting relationship between the functional unit group and the simulation unit group, wherein the nesting relationship refers to the nesting relationship between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group; Establish the relationships between the sub-unit groups of the functional unit group; Construct the relationships between the sub-unit groups of the simulation unit group; Establish the association relationship between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group; The timing design is performed for tasks and CPUs, where both tasks and CPUs are sub-unit groups within the simulation unit group; The sub-unit groups of the functional unit group include: Functional units, FMU, LUA, conditional statements, variables, and plugins; The simulation unit group includes the following sub-unit groups: Tasks, systems, devices, CPUs, and buses; Determining the nesting relationship between the functional unit group and the simulation unit group includes: The system may contain several other systems, several devices, or several buses. The device may contain several CPUs or several buses. CPU nests several tasks; A task is nested within a functional unit; The process of establishing the relationships between the sub-unit groups of the functional unit group includes: Based on the port, the FMU interacts with other sub-unit groups of the functional unit group via data flow or control flow; Based on the port, the LUA interacts with other sub-unit groups of the functional unit group via data flow or control flow; The judgment interacts with other sub-unit groups of the functional unit group via control flow; Based on the port, the variable interacts with other sub-unit groups of the functional unit group via data flow or control flow; Based on the port, the functional unit interacts with other sub-unit groups of the functional unit group via data flow or control flow; The process of establishing the relationships between the sub-unit groups of the simulation unit group includes: The task interacts with the remaining sub-units of the simulation unit group via control flow; Based on the channel, the system interacts with the other sub-units of the simulation unit group via data streams; Based on the channel, the device interacts with the other sub-units of the simulation unit group via data streams; The CPU interacts with the other sub-units of the simulation unit group via control flow. Based on the bus node, the bus interacts with the other sub-unit groups of the simulation unit group via data streams.

2. The design method for a virtual system model based on SysML language as described in claim 1, characterized in that, Time design for tasks and CPU includes: Determine the start time, execution time, end time, cycle time, and jitter time for each task or CPU.

3. A design device for a virtual system model created using the SysML language, characterized in that, The design method for a virtual system model created using SysML language as described in any one of claims 1-2 includes: The definition module is used to define functional unit groups and simulation unit groups, each of which contains several sub-unit groups. A nested module is used to determine the nesting relationship between the functional unit group and the simulation unit group, wherein the nesting relationship refers to the nesting relationship between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group. The first association module is used to construct the association relationship between the sub-unit groups of the functional unit group; The second association module is used to construct the association relationship between the sub-unit groups of the simulation unit group; The third association module is used to construct the association relationship between the sub-unit groups of the functional unit group and the sub-unit groups of the simulation unit group; The timing design module is used to design the timing of tasks and CPUs, where both tasks and CPUs are sub-units within the simulation unit group.

4. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute a design method for a virtual system model created using the SysML language as described in any one of claims 1 to 2.

5. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the non-transitory computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to execute a design method that implements a virtual system model created based on the SysML language as described in any one of claims 1 to 2.

Images