RFSOC-based distributed cooperative observation and data fusion method and system for FAST core array

Abstract

This invention discloses a distributed collaborative observation and data fusion method and system for the FAST core array based on RFSOC, comprising: S1 System initialization: The master node RFSOC generates a global clock, and achieves phase synchronization of multiple boards through SYSREF differential signals, completing a three-level clock tree calibration; S2 Signal acquisition and preprocessing: 3-8GHz radio frequency signals are directly sampled by an ADC and digitally down-converted to baseband signals; S3 Intelligent resource scheduling: Signal types are identified based on an echo state neural network (ESN), and FPGA logic resources are dynamically allocated through an improved ant colony algorithm; S4 Heterogeneous computing acceleration: A 128-channel digital beamforming pipeline is executed on the FPGA; S5 Cross-domain data fusion; S6 Collaborative observation planning; S7 Data output. This invention is applicable to scenarios involving multi-beamforming, cross-regional joint observation, and real-time processing of massive amounts of data, providing key technical support for solving cutting-edge scientific problems such as the origin of fast radio bursts and monitoring black hole activity.

Description

Technical Field

[0001] This invention relates to the field of radio astronomy observation technology, specifically to a method and system for distributed collaborative observation and data fusion of the FAST core array based on RFSOC. Background Technology

[0002] In the field of radio astronomy, the FAST core array digital terminal system, as the core equipment for realizing high-precision radio signal acquisition, processing, and collaborative observation, directly determines the ability to capture cosmic transient phenomena (such as fast radio bursts and pulsar single pulses). However, the traditional architecture, represented by the currently operational ROACH2 platform, faces multiple technical bottlenecks: low distributed collaboration efficiency (microsecond-level synchronization accuracy results in signal superposition efficiency of less than 70% for long-term phase observations), rigid resource allocation (fixed functional unit design results in FPGA resource utilization of less than 40% for a long time), fragmented heterogeneous computing (120ns delay in data interaction between the ADC analog front-end and the FPGA / ARM processing unit), and poor cross-system compatibility (only supports independent observation by a single telescope and cannot be adapted to the SDPv3 protocol of the SKA intermediate frequency array and the Mark 5B format of the VLBI global network). These problems are particularly prominent in real-time tracking scenarios of fast radio bursts (FRBs). Traditional architectures have a response delay of more than 1.2 seconds to burst signals, resulting in only one effective sampling within the millisecond period of an FRB, which severely restricts the analysis of the fine temporal structure of the signal. In multi-band transient source monitoring, fixed-band processing units cannot dynamically allocate resources, resulting in fewer than 32 channels for observations in high-frequency bands above 2 GHz, with a missed detection probability of more than 25%.

[0003] The core problem lies in the fact that traditional designs fail to fully utilize the mixed-signal processing advantages of FPGA chips. The integrated 12-bit 1.5GSPS ADC / DAC, 28nm FPGA logic units (including 500k logic units), and Cortex-A53 quad-core ARM processor could theoretically construct an integrated architecture of "analog front-end - digital processing - intelligent control," but current solutions use it only as an independent functional module, failing to achieve nanosecond-level synchronous control and dynamic collaboration of heterogeneous resources. For example, the ROACH2 platform uses external GPS timing, with a synchronization error of ±500ns, while the RFSOC's built-in phase-locked loop (PLL) combined with an onboard crystal oscillator (frequency stability ±0.01ppm) could theoretically improve synchronization accuracy to ±100ps. Furthermore, the fixed pipeline design of traditional architectures cannot adapt to the dynamic task switching requirements of "single-pulse search - beamforming - spectrum analysis" in radio observation, resulting in observation mode switching times exceeding 30 seconds. In contrast, RFSOC-based reconfiguration technology can complete hardware logic reconfiguration within 2ms. Summary of the Invention

[0004] To address the problems existing in the prior art, the present invention aims to provide a distributed collaborative observation and data fusion method for the FAST core array based on RFSOC. This method achieves nanosecond-level synchronous control, intelligent resource scheduling, heterogeneous computing acceleration, cross-domain data fusion, collaborative observation planning, and flexible interface adaptation through seven core functional modules. It is suitable for scenarios involving multi-beamforming, cross-regional joint observation, and real-time processing of massive amounts of data. Another objective of the present invention is to provide a distributed collaborative observation and data fusion system for the FAST core array based on RFSOC that implements the above method.

[0005] To achieve the above objectives, this invention provides a distributed collaborative observation and data fusion method for the FAST core array based on RFSOC, comprising the following steps:

[0006] S1. System Initialization: The master node RFSOC generates a global clock, and uses the SYSREF differential signal to achieve phase synchronization of multiple boards and complete the three-level clock tree calibration;

[0007] S2. Signal Acquisition and Preprocessing: The 3-8GHz radio frequency signal is directly sampled by an ADC and then digitally down-converted to a baseband signal;

[0008] S3. Intelligent Resource Scheduling: Based on the Echo State Neural Network (ESN) to identify signal types, FPGA logic resources are dynamically allocated through an improved ant colony algorithm;

[0009] S4. Heterogeneous computing acceleration: Execute a 128-channel digital beamforming pipeline on an FPGA;

[0010] S5. Cross-domain data fusion: Time delay compensation, gain equalization, and time-frequency domain layered fusion of data from multiple boards;

[0011] S6. Collaborative observation planning: Allocating multi-telescope observation resources based on graph neural network GAT;

[0012] S7. Data Output: The data is converted to SKA SDPv3, VLBI Mark5B, or a custom protocol format via the flexible interface module for output.

[0013] Furthermore, the phase synchronization includes: a dynamic phase calibration algorithm that monitors crystal oscillator frequency drift in real time and compensates for phase accuracy up to λ / 16@2GHz;

[0014] The event trigger signal is generated by the ARM core and synchronized to all processing nodes via the AXI bus to complete the three-level clock tree calibration of global clock → regional clock → logic unit clock, with a synchronization error of <500ps.

[0015] Furthermore, the intelligent resource scheduling includes:

[0016] The ESN neural network contains a sparse random connection pool of 1000 neurons, outputs a resource allocation weight matrix, and has the following objective function:

[0017] ;

[0018] in, To calculate the delay, For resource utilization rate, For power consumption; α, γ and γ are the corresponding weighting coefficients, and their values ​​are dynamically and adaptively adjusted according to the needs of the observation task.

[0019] The incremental learning mechanism updates the ESN weights every 200 new samples.

[0020] Furthermore, the heterogeneous computing acceleration includes:

[0021] The ARM core dynamically adjusts the FPGA frequency through DVFS technology and monitors the FPGA temperature, logic cell utilization, and DDR4 bandwidth in real time.

[0022] Beamforming employs a double-precision floating-point arithmetic unit, with a phase error ≤λ / 32@2GHz.

[0023] Furthermore, the cross-domain data fusion includes:

[0024] Cross-band spectrum splicing employs multi-resolution wavelet transform;

[0025] Radio frequency interference suppression employs a blind source separation algorithm, achieving an interference suppression ratio of 40dB.

[0026] Furthermore, the collaborative observation plan includes:

[0027] Construct a multi-layered heterogeneous resource graph G=(V,E), where node attributes include device parameters, status parameters, and observation target parameters;

[0028] The GAT model employs an 8-head attention mechanism, outputting a task assignment matrix A∈R. N×M N is the number of nodes, M is the number of tasks, and the constraints of single-node task count ≤ 4, frequency band isolation, and transmission delay < 50μs are satisfied.

[0029] Furthermore, in S6, multi-telescope observation resources are allocated based on graph neural networks (GAT), and in case of an emergency, the task is replanned within 100ms using the PPO reinforcement learning algorithm;

[0030] Emergency response includes:

[0031] When an FRB signal with an SNR > 7dB is detected, 16 high-sensitivity channels are prioritized for scheduling, with a signal acquisition delay of < 200ms.

[0032] The radio and optical telescopes are triggered synchronously in the time domain, with an alignment error between the exposure time and the integration time of less than 10 ms.

[0033] Furthermore, the data output includes:

[0034] Adding a CRC-32 check module to the end of the FPGA pipeline improves the accuracy of bit error rate monitoring. Data reliability > 99.999%;

[0035] Supports clock synchronization and data stream interaction for SKA intermediate frequency array and VLA telescope.

[0036] Furthermore, the system initialization phase also includes:

[0037] Load the lightweight GAT model (the original GAT model has about 1.5 million parameters, pruned to 9.8MB (compressed 15 times)) and the ESN model onto the FPGA;

[0038] The federated learning architecture aggregates locally updated model parameters from each node, including the ESN's pooled connection weights and output layer weights, as well as the GAT's attention weights and graph convolutional layer weights. These parameters optimize signal recognition and resource allocation efficiency through a distributed update mechanism, while meeting the technical requirements of "nanosecond-level synchronization" and "dynamic collaboration of heterogeneous resources."

[0039] The FAST core array distributed collaborative observation and data fusion system based on RFSOC includes the following modules:

[0040] Nanosecond-level synchronization control module: Integrated into the clock management unit of RFSOC, it generates a 100MHz±0.1ppm global clock and achieves multi-board synchronization through SYSREF differential signals and a three-level clock buffer architecture;

[0041] Intelligent resource scheduling module: Deployed on the ARM core, the ESN neural network and the improved ant colony algorithm construct a 3×5 feature-resource correlation matrix to dynamically allocate FPGA logic resources.

[0042] Heterogeneous computing acceleration module: A 128-channel digital beamforming pipeline on an FPGA, which interacts with the ARM core through a ping-pong cache architecture;

[0043] Cross-domain data fusion module: Enables spatiotemporal calibration and multi-level fusion of FAST and external telescope data;

[0044] Collaborative observation and planning module: Based on the GAT model task allocation engine and PPO reinforcement learning emergency response engine, it supports real-time replanning for emergency events;

[0045] Flexible interface adapter module: including 16 front-end 3-8GHz RF inputs, dual 10 Gigabit SFP+ interfaces and PCIe 4.0 interface at the rear;

[0046] External interface interaction module: supports PTP clock synchronization, SDP protocol data transmission and standard API interface.

[0047] The beneficial effects of this invention are as follows:

[0048] This invention, through a seven-modular architecture design (high-precision synchronization module, dynamic resource scheduling module, heterogeneous collaborative computing module, etc.), achieves for the first time nanosecond-level distributed synchronization control (synchronization error <200ps), dynamic reconfiguration of heterogeneous resources (function switching delay <5ms), and flexible adaptation to multiple protocols (supporting 6 international standard protocols such as SKA and VLBI). It improves the signal superposition efficiency of long-term phase observation to over 92%, increases resource utilization to 75%, and supports real-time collaborative observation between FAST, SKA intermediate frequency array, and VLBI global network, providing key technical support for solving cutting-edge scientific problems such as the origin of fast radio bursts and monitoring of black hole activity. Attached Figure Description

[0049] Figure 1 This is a diagram of the overall system architecture.

[0050] Figure 2 Timing diagram for nanosecond-level synchronization control module;

[0051] Figure 3 Hardware architecture diagram of the heterogeneous computing acceleration module;

[0052] Figure 4 This is a comparison of the performance of the present invention with that of traditional solutions based on actual measurements;

[0053] Figure 5 This is a flowchart of the present invention. Detailed Implementation

[0054] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0056] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0057] The following combination Figures 1-5 Specific embodiments of the present invention will be described in detail below. It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the present invention.

[0058] This invention relates to a distributed collaborative observation and data fusion method and system for the FAST core array based on RFSOC. Specifically, it is a distributed collaborative observation system and method for the 500-meter Aperture Spherical Radio Telescope (FAST) core array based on Radio Frequency System-on-Chip (RFSOC). Through seven core functional modules, it achieves nanosecond-level synchronous control, intelligent resource scheduling, heterogeneous computing acceleration, cross-domain data fusion, collaborative observation planning, and flexible interface adaptation. It is suitable for scenarios involving multi-beam synthesis, cross-regional joint observation, and real-time processing of massive amounts of data.

[0059] A distributed collaborative observation and data fusion method for the FAST core array based on RFSOC, such as Figure 5 As shown, it includes the following steps:

[0060] S1. System Initialization: The master node RFSOC generates a global clock, and uses the SYSREF differential signal to achieve phase synchronization of multiple boards and complete the three-level clock tree calibration;

[0061] S2. Signal Acquisition and Preprocessing: The 3-8GHz radio frequency signal is directly sampled by an ADC and then digitally down-converted to a baseband signal;

[0062] S3. Intelligent Resource Scheduling: Based on the Echo State Neural Network (ESN) to identify signal types, FPGA logic resources are dynamically allocated through an improved ant colony algorithm;

[0063] S4. Heterogeneous computing acceleration: Execute a 128-channel digital beamforming pipeline on an FPGA;

[0064] S5. Cross-domain data fusion: Time delay compensation, gain equalization, and time-frequency domain layered fusion of data from multiple boards;

[0065] S6. Collaborative observation planning: Allocating multi-telescope observation resources based on graph neural network GAT;

[0066] S7. Data Output: The data is converted to SKA SDPv3, VLBI Mark5B, or a custom protocol format via the flexible interface module for output.

[0067] The present invention specifically adopts the following modular architecture design and processing flow:

[0068] I. Core functional module architecture design, such as Figure 1 As shown:

[0069] Module 1: Nanosecond-level synchronization control module, such as Figure 2 As shown, a high-precision synchronization benchmark is constructed for the entire system to support multi-node coherent synthesis and cross-telescope time slot alignment.

[0070] A hardware-level synchronization reference is adopted: First, a 100MHz ± 0.1ppm global reference clock is generated using the RFSOC's internal clock management unit (CMT). Multi-board phase synchronization is achieved through a SYSREF differential signal, with a synchronization error of <500ps (differential signal suppresses common-mode noise, transmission delay deviation <200ps). A three-level clock buffer architecture (global clock → regional clock → logic unit clock) is used in conjunction with a dynamic phase calibration algorithm (crystal frequency drift monitoring period of 10ms, phase compensation accuracy λ / 16@2GHz). Its crystal drift compensation is based on an adaptive Kalman filter framework, combined with the FPGA hardware CMT unit design. The specific formula is as follows:

[0071] Global clock drift compensation:

[0072] ;

[0073] in: (k) represents the estimated global clock frequency in the k-th iteration. (k) is the current crystal oscillator frequency measurement value (obtained through PLL feedback), and α is the adaptive gain coefficient (dynamically adjusted according to the 10ms monitoring period).

[0074] Regional transmission delay compensation:

[0075] ;

[0076] in, The SYSREF differential signal transmission delay bias is given by c, where c is the speed of light. The regional delay compensation weights (calculated based on λ / 16@2GHz phase accuracy) ), The maximum permissible transmission delay deviation of the SYSREF differential signal (set to ≤200ps) is used to ensure that the regional delay compensation weight β satisfies the phase accuracy constraint of λ / 16 (when the actual delay deviation...). ≤ When the phase compensation error is ≤λ / 16.

[0077] Logic unit phase error correction:

[0078] ;

[0079] in, (k) represents the actual phase error of the logic cell (measured by a phase detector), and γ represents the correction coefficient of the logic cell (capacitor charge and discharge time of TSMC 16nm process). This represents the phase error of the logic unit after correction in the k-th iteration, and its value is derived from the previous error. The current correction amount (based on the deviation between the target accuracy λ / 16 and the measured error) is dynamically updated, eventually bringing the logic unit phase error to within λ / 16.

[0080] The overall formula for three-level calibration, and the phase error propagation relationship between the global, regional, and logic unit levels, are as follows:

[0081] ;

[0082] in, (k) represents the total phase error of the system at the kth iteration, reflecting the comprehensive phase deviation of the entire clock tree after three-level calibration; (k) represents the phase error of the global clock at the kth iteration, which is caused by factors such as crystal frequency drift and temperature drift, and is dynamically corrected by the global clock drift compensation formula; (k) represents the phase error of the regional transmission at the k-th iteration, which is derived from the delay deviation of the SYSREF signal in the regional transmission. This represents the corrected phase error of the logic unit. α is updated iteratively. The γ coefficient enables dynamic calibration.

[0083] Event triggering and time slot alignment: The ARM core generates nanosecond-level trigger signals (time stamp resolution of 1ns, including task ID, integration time and other metadata), which are synchronized to all processing nodes via the AXI bus; it supports observation time slot alignment accuracy of <10ns for telescopes such as FAST and SKA, and meets the phase stability requirements of coherent integration time >1 hour.

[0084] Innovative advantages: Eliminates dependence on external synchronization modules, improves phase synchronization accuracy by two orders of magnitude compared to traditional solutions, and supports signal superposition for long-term phase observation.

[0085] Module 2: Intelligent Resource Scheduling Module. This module dynamically allocates computing resources based on signal characteristics, enabling real-time switching between multiple observation modes. An Echo State Neural Network (ESN) is deployed on the ARM core to achieve signal feature extraction and dynamic allocation of computing resources. The 1GSps baseband signal is converted to a time-spectrum matrix via STFT and then input into a sparse random connection pool containing 1000 neurons (sparseness 0.1, spectral radius 0.95). The weight matrix is ​​trained using linear regression, with the objective function being:

[0086] ;

[0087] in, To calculate the delay, For resource utilization rate, For power consumption, α, β, and γ are the corresponding weight coefficients, satisfying α+β+γ=1. The weight coefficients are dynamically adaptive, achieving an accuracy of ≥98.2% for identifying three types of signals: pulsars, continuous spectra, and spectral lines. An incremental learning mechanism is introduced (a weight update is triggered every 200 new samples) to support online adaptive adjustment of the model.

[0088] Multi-dimensional resource scheduling model: The improved ant colony algorithm is combined with the dynamic feature vector output by ESN to construct a 3×5 feature-resource correlation matrix, optimize the pheromone update strategy, realize differentiated resource allocation for different signal types, and realize dynamic allocation of FPGA logic resources (FFT core, multiplier, BRAM) (e.g., 16k-point FFT core + 8-bit fixed-point arithmetic unit for pulsar signals).

[0089] Dynamic channel switching mechanism: Real-time switching of 8 observation modes on a single board is achieved through the internal AXI-Stream interface of RFSOC. Dynamic FIFO buffer (depth 1024) is configured to avoid data congestion and data routing latency is <1μs.

[0090] Traditional ant colony optimization (ACO) algorithms are suitable for static path optimization, but they suffer from the following shortcomings in FPGA dynamic resource scheduling: they cannot adapt to real-time changes in signal characteristics (such as the burst characteristics of FRBs), the fixed pheromone evaporation coefficient is difficult to balance convergence speed and global optimization, and they lack a direct mapping to hardware resource characteristics (such as logic units and BRAM). The innovative design of the improved ACO algorithm is as follows:

[0091] Feature-Resource Correlation Matrix: A 3×5 dimensional matrix (3 types of signal features × 5 types of resource types) is constructed to replace the traditional path graph. This is achieved through an improved transition probability formula. The traditional transition probability calculation formula is as follows:

[0092] ;

[0093] The improved transition probability formula, combining signal characteristics and hardware state, is as follows:

[0094] ;

[0095] in, The fit of signal type s to resource j in the feature-resource matrix (e.g., the fit of pulsar to 16k FFT kernel is 0.9). Hardware load impact factor ( For coefficients, (where Z is the current resource utilization rate); Z is the normalization factor.

[0096] Dynamic pheromone update strategy: Adaptively adjusts the evaporation coefficient based on ESN signal recognition results and hardware status; Multi-objective joint optimization: Integrates computational latency, resource utilization, and power consumption. The adaptive pheromone update strategy calculation formula is as follows:

[0097] ;

[0098] in, for In the next iteration, the pheromone concentration from resource node i to resource node j (i and j are resource type indices, such as i = FFT kernel, j = multiplier). The pheromone increment from resource node i to j (the newly added pheromone concentration in this iteration). The pheromone evaporation coefficient is dynamically adjusted over time (controlling the rate of pheromone decay; a higher value indicates faster decay). It adjusts dynamically with temperature. The current FPGA temperature, Volatility coefficient, benchmark value =0.1, The temperature influence coefficient has a reference value of [value missing]. =0.05; pheromone increment Where Q is a constant, Let be the path length (resource allocation cost) of the k-th ant. .

[0099] Innovation advantages: resource utilization is improved by 60%, power consumption in typical scenarios is reduced by 40%, and hardware resources can be dynamically reconfigured to support parallel observation of multiple targets.

[0100] Module 3: Heterogeneous computing acceleration module, such as Figure 3 As shown, a collaborative computing architecture combining FPGA hardware acceleration and ARM intelligent scheduling is constructed to improve signal processing efficiency.

[0101] FPGA hardware-accelerated pipeline: Implements a 128-channel digital beamforming (DBF) pipeline with a processing rate of 2GSps, supporting real-time computation with 16-bit precision in the complex domain (≥32 parallel multiplication and accumulation units); the pipeline includes an automatic gain control (AGC) module with a dynamic range of 100dB, supporting direct sampling of 3-8GHz wideband signals (5Gsps@14bit ADC).

[0102] ARM intelligent scheduling and power consumption optimization: Real-time acquisition of FPGA temperature (accuracy ±1℃), logic cell occupancy rate (resolution 1%), and DDR4 bandwidth (sampling interval 5ms), and dynamic adjustment of FPGA frequency (100-250MHz, adjustment step size 10MHz) through DVFS technology; power consumption is reduced to 50W under low load (traditional solution ≥150W), and maintains efficient operation of 150W under full load.

[0103] Hardware and software collaborative interaction: Shared memory communication is achieved through the AXI-HP interface, supporting a data throughput of 8GB / s. The interaction latency between preprocessed data (such as beamforming baseband signals) and post-processing algorithms (general CLEAN imaging, pulsar period search algorithm, etc.) is <200ns.

[0104] Innovation advantages: End-to-end processing latency is reduced from 50μs to 15μs, and the utilization rate of heterogeneous computing resources is increased to 85%, breaking through the data interaction bottleneck of traditional software and hardware separation architecture.

[0105] FPGA pipeline optimization: A double-precision floating-point arithmetic unit (supporting the IEEE 754-2019 standard) is used to realize dynamic updates of beamforming weights. Compared with traditional fixed-point arithmetic, the phase error is reduced to λ / 32@2GHz, and the sidelobe suppression ratio of the synthesized beam is improved by 10dB.

[0106] Heterogeneous computing collaboration mechanism: A ping-pong cache architecture (dual-port BRAM depth 64k) is designed to realize non-blocking data interaction between the FPGA pipeline and the ARM processor. Compared with the traditional FIFO solution, the throughput is increased to 16GB / s and the interaction latency is stabilized within 100ns.

[0107] Module 4: Cross-domain data fusion module, realizing spatiotemporal calibration and multi-level fusion of FAST and external telescope data to improve joint observation accuracy. It adopts a multi-source data spatiotemporal calibration design. For delay compensation, it employs an FFT-based cross-correlation algorithm (computation period <1μs), achieving a compensation accuracy of 1 / 8 of the sampling period (corresponding to a delay of <0.2ns@5Gsps). For gain equalization, it designs an adaptive filter with a dynamic range of 120dB (coefficient update frequency 10kHz) to eliminate inter-channel gain differences (gain deviation <0.1dB after calibration). Regarding the hierarchical fusion strategy, the temporal layer implements sliding window weighted fusion (window length dynamically adjustable from 100ns to 1μs, Hanning window reduces spectral leakage), and the frequency domain layer implements Wiener filter spectral enhancement (noise suppression ratio improved by 25dB, filter coefficients updated in real-time noise estimation). This design supports data fusion from FAST and SKA and other telescopes of different systems, achieving seamless integration of cross-frequency band (1GHz-8GHz) and cross-regional observation data.

[0108] Cross-band fusion extension: Supports data fusion of FAST (1-3GHz) and SKA mid-frequency array (3-8GHz), and achieves cross-band spectrum stitching through multi-resolution wavelet transform (5 decomposition layers). The frequency coverage of joint imaging is extended to 1GHz-8GHz, and the resolution is improved to 0.1 arcseconds (equivalent to a 10km baseline interferometer).

[0109] Real-time interference suppression: The blind source separation algorithm (JADE algorithm) is introduced to separate RFI (radio frequency interference) at the time domain level, with an interference suppression ratio of 40dB, which significantly improves the detection capability of weak signals (such as pulsar single pulses).

[0110] Module 5: Collaborative Observation Planning Module. Based on a graph neural network, this module achieves global optimization allocation of multi-telescope resources and supports real-time replanning for emergency events. It models the observation resource graph, constructing a multi-layered heterogeneous resource graph G=(V,E), where nodes V include FAST feeds (19), SKA antennas (133), VLBI stations, etc. (32-dimensional attributes: equipment parameters / status parameters / observation target parameters). A task allocation optimization engine is implemented, constructing a graph attention network (GAT) with an 8-head attention mechanism, an embedding encoding dimension of 256, and using the LeakyReLU activation function to capture node collaborative relationships (such as frequency band complementarity). The output task allocation matrix A∈R is then completed. N×MN represents the number of nodes, and M represents the number of tasks, satisfying constraints such as ≤4 tasks per node, frequency band isolation, and transmission delay <50μs (feasibility verified using integer linear programming). The above design implements a real-time replanning mechanism. When an emergency event is detected (such as an FRB, trigger threshold SNR>7dB), the PPO reinforcement learning algorithm is activated (50-dimensional state space, task adjustment operations in action space), completing resource reallocation and dynamic insertion of priority tasks within 100ms.

[0111] Emergency response performance test: In the FRB simulation test, the system's capture delay for sudden signals is 180ms, which is 6.6 times better than the ROACH2 platform (1.2s delay), ensuring that at least 3 effective samples are completed within the signal period.

[0112] Innovative advantages: The efficiency of multi-telescope joint observation is improved by 50%, the resource conflict rate is reduced from 15% to 2%, and the time-domain-frequency domain collaborative observation of radio / optical telescopes (such as LAMOST and JWST) is realized for the first time.

[0113] Module 6: Flexible Interface Adaptor Module. This module enables modular hardware interface design and multi-protocol adaptive operation, supporting system expansion and cross-platform compatibility. It adopts a modular hardware interface design, with a front-end of 16 channels of 3-8GHz RF input (SMA type interface, integrated anti-aliasing filter, roll-off factor 0.22), single-channel 5Gsps@14bit ADC sampling, and a back-end of dual 10G SFP+ interfaces (supporting UDP / IP and SDP protocols, link aggregation bandwidth of 20Gbps) and a 12Gbps PCIe 4.0 interface, supporting 256-node cascade expansion (clock skew <500ps).

[0114] Protocol Adaptive Engine: The ARM core runs a multi-protocol conversion middleware (format parsing / reconstruction / verification module), supporting real-time conversion between FAST custom format and SKA standard format (latency <5μs); it is compatible with the data interaction protocols of devices such as China VLBI Network and ALMA, and supports plug-and-play modular deployment.

[0115] Innovative advantages: System scalability is improved by 3 times; hardware compatibility covers 90% of mainstream radio equipment; and protocol conversion latency is reduced by 70% compared to traditional solutions. For example... Figure 4 As shown.

[0116] Module 7: External Interface Interaction Module, which enables standardized interaction between the system and external observation equipment and back-end processing platforms, and builds an open observation network.

[0117] Front-end signal input: Directly connected to the feed network of the 19-unit core array of FAST, supporting full-band signal input of 3-8GHz, integrating feed noise suppression preprocessing module (noise figure <2dB); compatible with feed polarization signal processing (left-hand / right-hand independent channels, polarization degree measurement accuracy ±1%).

[0118] Cross-telescope collaboration interface: Supports clock synchronization (PTP protocol, synchronization accuracy <10ns) and data stream interaction (SDP protocol, transmission rate 10Gbps) with international telescopes such as SKA intermediate frequency array (133 elements) and VLA; provides standard API interface for third-party devices to call, and supports remote configuration of observation parameters (latency <10ms).

[0119] Backend data output: The 10 Gigabit Ethernet port outputs the processed baseband signal (supports multicast mode, single node bandwidth 4Gbps); the PCIe interface connects to the backend related machines (such as the FAST pulsar search engine), with a data throughput of 12Gbps, meeting the real-time related processing requirements (integration period <1ms).

[0120] Innovation advantages: We have built a standardized interface system to support seamless access for equipment from multiple brands, and promoted the openness and internationalization of radio astronomy observation networks.

[0121] II. Processing Flow

[0122] 1. System initialization phase: Synchronous network construction, the master node RFSOC generates a global clock, the slave nodes lock the phase through SYSREF, and complete the three-level clock tree calibration (<100ms); Resource graph initialization, collect the device parameters (bandwidth, accuracy) and status (load rate, calibration status) of each node, and construct the initial observation resource graph G0; Model loading, the FPGA loads the GAT task allocation model (9.8MB) and the ESN signal recognition model (parameter scale 3M), and the ARM core starts the resource monitoring service.

[0123] 2. Routine observation and processing procedures:

[0124] Signal acquisition and preprocessing: The front-end ADC directly samples the 3-8GHz signal (5Gsps), digitally down-converts it to baseband (I / Q channels, 1GSps), inputs it into the FPGA to execute the DBF pipeline, and the FPGA calculates the 128-channel weighting coefficients in real time, outputting a synthesized high signal-to-noise ratio signal (signal-to-noise improvement ratio >15dB).

[0125] Intelligent scheduling and data fusion: The ARM core identifies the signal type and triggers the DDRP protocol to allocate resources (such as allocating a 4k-point FFT core + 4-bit quantization unit for neutral hydrogen signals). The fusion module performs time delay compensation, gain equalization and three-layer fusion on data from multiple boards and outputs feature data (such as spectral profiles and phase difference matrices).

[0126] Data output and storage are converted to standard format via the flexible interface module and transmitted to back-end related machines (latency <5μs) or storage systems (supports RAID5, write speed 2GB / s) via 10 Gigabit Ethernet.

[0127] Data integrity verification is achieved by adding a CRC-32 check module at the end of the FPGA pipeline to perform real-time verification of the 128-channel beamforming data, achieving a high bit error rate monitoring accuracy. This ensures that the reliability of data transmitted to the backend is >99.999%.

[0128] 3. Collaborative observation planning process:

[0129] Task reception and allocation: The master node receives the observation target parameters (right ascension, declination, bandwidth), and the GAT model generates the task allocation matrix A to ensure that the load of a single node is ≤3 and that there is no frequency band overlap; configuration instructions (including FFT kernel parameters, beam weights, and data routing paths) are issued to each RFSOC node.

[0130] In emergency response, when an FRB signal is detected, the PPO algorithm prioritizes scheduling 16 high-sensitivity channels (shutting down low-priority tasks), with a replanning time of 95ms and a signal capture delay of <200ms; it also updates the resource graph G in real time and records emergency task processing logs (timestamp accuracy 1ns).

[0131] The radio-optical joint observation is connected to the real-time data stream of the LAMOST optical telescope. The time-domain synchronous triggering is achieved through the collaborative observation planning module (the alignment error between optical exposure time and radio integration time is <10ms), and it supports joint analysis of multi-band energy spectra of transient sources.

[0132] This invention achieves its technical functions based on the following hardware platform and software system:

[0133] I. Hardware Platform Implementation

[0134] 1. Core board design: It adopts Xilinx Zynq UltraScale+RFSoC 4x2 device, integrating 4-channel 14-bit ADC (5Gsps), 2-channel 16-bit DAC (6.5Gsps), 3.4M system gate FPGA logic and quad-core Cortex-A53ARM (1.5GHz); the board size is 160mm×100mm, the power supply design supports wide voltage input (9-15V), and the operating temperature range is -40℃~+85℃.

[0135] 2. System cascading solution: Synchronization of 100+ boards is achieved through SYSREF differential signal (maximum transmission distance 10m, signal attenuation <3dB); 10 Gigabit Ethernet ports are configured with TSN protocol (Time Sensitive Network), transmission delay jitter <10ns, and support real-time data aggregation from multiple boards.

[0136] 3. Actual test of synchronization performance: In the test of cascading 100 boards, the maximum synchronization error was 480ps and the root mean square error was 210ps, which meets the stringent requirements of SKA for the synchronization accuracy of distributed arrays (<500ps).

[0137] 4. Power consumption optimization verification: In pulsar search mode, the power consumption of a single board is as low as 45W (the traditional ROACH2 platform requires 180W), and the temperature rise caused by heat accumulation during 8 hours of continuous observation is only 6℃, without the need for an additional liquid cooling system.

[0138] II. Software System Implementation

[0139] 1. Synchronization control software: Master node synchronization engine: CMT unit configuration, SYSREF signal generation, dynamic phase calibration algorithm (implemented in C language, running on ARM core 0); Slave node synchronization agent: PLL locking algorithm, phase error compensation (implemented in Verilog, running on FPGA logic).

[0140] 2. Resource scheduling software: CNN signal recognition model: based on the TensorFlow Lite framework, quantized to 8-bit fixed-point arithmetic, inference latency <1ms; improved ant colony algorithm: modeled and optimized in MATLAB and then ported to the ARM core, with a resource allocation cycle of 5ms.

[0141] 3. Collaborative observation planning software: GAT model lightweighting: the model size after pruning is 9.8MB, FPGA hardware accelerated inference (convolutional layer calculation speed is improved by 20 times); PPO reinforcement learning engine: experience replay buffer capacity of 100,000, training update cycle of 100ms, running on ARM cores 1-3 (multi-core parallelism).

[0142] 4. Distributed training support: The collaborative observation planning module supports a federated learning architecture, where each node can update GAT model parameters locally and aggregate the global model through encrypted communication, protecting the privacy of observation data while improving the model's generalization ability.

[0143] Technical advantages of this invention:

[0144] High-precision synchronization across the entire link: Nanosecond-level phase synchronization technology supports long-term phase observation, with a phase coherence synthesis efficiency of over 95%;

[0145] Intelligent dynamic resource management: Based on deep learning signal recognition and ant colony algorithm scheduling, resource utilization is improved by 60% and power consumption is reduced by 40%;

[0146] Deep collaboration in heterogeneous computing: The combination of FPGA hardware acceleration and ARM intelligent scheduling reduces end-to-end processing latency to 15μs, breaking through the performance bottleneck of traditional architecture.

[0147] Cross-domain collaborative observation capability: Graph neural network-driven multi-telescope resource allocation improves joint observation efficiency by 50% and supports real-time collaboration of radio / optical telescopes;

[0148] Flexible expansion and compatibility: The modular interface design supports cascading of 256 nodes, and the multi-protocol adaptive engine covers 90% of mainstream devices, building an open observation network.

[0149] Enhanced scientific discovery capabilities:

[0150] Nanosecond-level synchronization and cross-domain fusion technology have improved FAST's positioning accuracy for FRBs from 10 square degrees to 0.1 square degrees, helping to achieve major scientific breakthroughs such as the "origin of fast radio bursts".

[0151] With international cooperation and compatibility, the flexible interface adapter module supports the SKA standard protocol (SDPv3), VLBI related machine protocol (Mark 5B), and the custom format of the China VLBI Network. It has passed the interoperability test (IOP) of the SKA organization, becoming the first case of non-SKA native equipment being connected to its global testbed.

[0152] This invention solves the key technical challenges of the digital terminal of the FAST core array through the innovative design of seven modules, and provides a reusable technical paradigm for the next generation of radio astronomy observation equipment.

[0153] Any process or method described in the flowcharts of this invention or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, which can be implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device. The computer-readable medium can be any medium containing a program for storage, communication, propagation, or transmission for use by the execution system, apparatus, or device, including read-only memory, magnetic disks, or optical disks.

[0154] In the description of this specification, references to terms such as "embodiment," "example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, those skilled in the art can combine or combine the different embodiments or examples described in this specification and the features therein without causing contradiction.

[0155] While embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and alterations to the above embodiments within the scope of the present invention.

Claims

1. A distributed collaborative observation and data fusion method for the FAST core array based on RFSOC, characterized in that, Includes the following steps: S1. System Initialization: The master node RFSOC generates a global clock, and uses the SYSREF differential signal to achieve phase synchronization of multiple boards and complete the three-level clock tree calibration; S2. Signal Acquisition and Preprocessing: The 3-8GHz radio frequency signal is directly sampled by an ADC and then digitally down-converted to a baseband signal; S3. Intelligent Resource Scheduling: Based on the Echo State Neural Network (ESN) to identify signal types, FPGA logic resources are dynamically allocated through an improved ant colony algorithm; S4. Heterogeneous computing acceleration: Execute a 128-channel digital beamforming pipeline on an FPGA; S5. Cross-domain data fusion: Time delay compensation, gain equalization, and time-frequency domain layered fusion of data from multiple boards; S6. Collaborative observation planning: Allocating multi-telescope observation resources based on graph neural network GAT; S7. Data Output: The data is converted to SKA SDPv3, VLBI Mark5B, or a custom protocol format via the flexible interface module for output.

2. The FAST core array distributed collaborative observation and data fusion method based on RFSOC as described in claim 1, characterized in that, The phase synchronization includes: The dynamic phase calibration algorithm monitors crystal oscillator frequency drift in real time and compensates for phase accuracy up to λ / 16@2GHz. The event trigger signal is generated by the ARM core and synchronized to all processing nodes via the AXI bus to complete the three-level clock tree calibration of global clock → regional clock → logic unit clock, with a synchronization error of <500ps.

3. The distributed collaborative observation and data fusion method for the FAST core array based on RFSOC as described in claim 1, characterized in that, Intelligent resource scheduling includes: The ESN neural network contains a sparse random connection pool of 1000 neurons, outputs a resource allocation weight matrix, and has the following objective function: ； in, To calculate the delay, For resource utilization rate, For power consumption, α, β, and γ are the corresponding weighting coefficients, satisfying α+β+γ=1, and the weighting coefficients are dynamically adaptive; The incremental learning mechanism updates the ESN weights every 200 new samples.

4. The distributed collaborative observation and data fusion method for the FAST core array based on RFSOC as described in claim 1, characterized in that, Heterogeneous computing acceleration includes: The ARM core dynamically adjusts the FPGA frequency through DVFS technology and monitors the FPGA temperature, logic cell utilization, and DDR4 bandwidth in real time. Beamforming employs a double-precision floating-point arithmetic unit, with a phase error ≤λ / 32@2GHz.

5. The FAST core array distributed collaborative observation and data fusion method based on RFSOC as described in claim 1, characterized in that, Cross-domain data fusion includes: Cross-band spectrum splicing employs multi-resolution wavelet transform; Radio frequency interference suppression employs a blind source separation algorithm, achieving an interference suppression ratio of 40dB.

6. The FAST core array distributed collaborative observation and data fusion method based on RFSOC as described in claim 1, characterized in that, The collaborative observation plan includes: Construct a multi-layered heterogeneous resource graph G=(V,E), where node attributes include device parameters, status parameters, and observation target parameters; The GAT model employs an 8-head attention mechanism, outputting a task assignment matrix A∈R. N×M N is the number of nodes, M is the number of tasks, and the constraints of single-node task count ≤ 4, frequency band isolation, and transmission delay < 50μs are satisfied.

7. The FAST core array distributed collaborative observation and data fusion method based on RFSOC as described in claim 1, characterized in that, In S6, multi-telescope observation resources are allocated based on graph neural network GAT, and in case of emergency, the task is replanned within 100ms using PPO reinforcement learning algorithm. Emergency response includes: When an FRB signal with a trigger threshold SNR > 7dB is detected, 16 high-sensitivity channels are prioritized for scheduling, with a signal acquisition delay of < 200ms. The radio and optical telescopes are triggered synchronously in the time domain, with an alignment error between the exposure time and the integration time of less than 10 ms.

8. The distributed collaborative observation and data fusion method for the FAST core array based on RFSOC as described in claim 1, characterized in that, Data output includes: Adding a CRC-32 check module to the end of the FPGA pipeline improves the accuracy of bit error rate monitoring. Data reliability > 99.999%; Supports clock synchronization and data stream interaction for SKA intermediate frequency array and VLA telescope.

9. The FAST core array distributed collaborative observation and data fusion method based on RFSOC according to any one of claims 1-8, characterized in that, The system initialization phase also includes: Load lightweight GAT and ESN models onto the FPGA; The model parameters updated locally by each node are aggregated through a federated learning architecture.

10. A distributed collaborative observation and data fusion system for the FAST core array based on RFSOC, characterized in that, This system is used to implement the distributed collaborative observation and data fusion method of FAST core array based on RFSOC as described in any one of claims 1-8. The system includes the following modules: Nanosecond-level synchronization control module: Integrated into the clock management unit of RFSOC, it generates a 100MHz±0.1ppm global clock and achieves multi-board synchronization through SYSREF differential signals and a three-level clock buffer architecture; Intelligent resource scheduling module: Deployed on the ARM core, the ESN neural network and improved ant colony algorithm construct a 3×5 feature-resource correlation matrix to dynamically allocate FPGA logic resources; Heterogeneous computing acceleration module: A 128-channel digital beamforming pipeline on an FPGA, which interacts with the ARM core through a ping-pong cache architecture; Cross-domain data fusion module: Enables spatiotemporal calibration and multi-level fusion of FAST and external telescope data; Collaborative observation and planning module: Based on the GAT model task allocation engine and PPO reinforcement learning emergency response engine, it supports real-time replanning for emergency events; Flexible interface adapter module: including 16 front-end 3-8GHz RF inputs, dual 10 Gigabit SFP+ interfaces and PCIe 4.0 interface at the rear; External interface interaction module: supports PTP clock synchronization, SDP protocol data transmission and standard API interface.

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