Multidimensional Test Case Generation Method and Device

Abstract

This application discloses a multi-dimensional test case generation method and apparatus, relating to the field of test case generation technology. It includes: addressing the verification needs of complex electronic systems by constructing a unified cause-effect graph model through multi-source inputs such as circuit schematics, design constraint documents, and simulation data, and automatically generating multi-dimensional test cases. This solves the technical problems in related technologies, such as strong model type dependency, lack of natural language constraint parsing operations, isolated existence of data such as schematics, design specifications, and signal integrity simulations generated during the design phase, and neglect of out-of-limit scenarios, resulting in limited scenario coverage. The method achieves the technical effect of constructing a unified cause-effect graph model by integrating multi-source design data, realizing the complete expression of design intent and the explicitness of implicit knowledge, thereby significantly improving the coverage of test scenarios and the utilization efficiency of test resources.

Description

Technical Field

[0001] This application relates to the field of test case generation technology, and in particular to a method and apparatus for generating multidimensional test cases. Background Technology

[0002] Currently, Electronic Design Automation (EDA) and hardware verification technologies lack natural language constraint processing, making it difficult to integrate physical laws. Furthermore, boundary testing has significant limitations, greatly impacting the efficiency and reliability of test case generation.

[0003] To address the aforementioned issues, the relevant technologies first simplify and transform the original system model (such as the Simulink design model) by extracting core functional subgraphs relevant to the test requirements to generate an intermediate representation model. Second, a mapping relationship is established between the test objectives and the model's computational path, and path tracing technology is used to ensure that test cases accurately cover key functional interfaces and core behavioral logic. Finally, based on path constraints and test objectives, a test case table is automatically constructed, systematically generating a complete test plan that includes combinations of input variables, expected outputs, and coverage criteria.

[0004] However, the related technologies are highly dependent on model types and lack natural language constraint parsing operations. Furthermore, the schematic diagrams, design specifications, signal integrity simulations, and other data generated during the design phase exist in isolation. In addition, the related technologies only verify the design requirements range and ignore out-of-limit scenarios, resulting in a high degree of limitation in scenario coverage, which urgently needs to be addressed. Summary of the Invention

[0005] This application provides a multi-dimensional test case generation method and apparatus to at least solve the technical problems in related technologies, such as strong model type dependence, lack of natural language constraint parsing operations, isolated existence of schematic diagrams, design specifications, signal integrity simulations and other data generated in the design stage, and neglect of out-of-limit scenarios, resulting in a high degree of limitation in scenario coverage.

[0006] This application provides a method for generating multi-dimensional test cases, comprising the following steps: acquiring original multi-source data corresponding to a target electronic system and converting the original multi-source data into corresponding standardized data, wherein the standardized data includes at least one of a topology graph, constraint rules, causal relationships, a boundary condition dictionary, and a fault path list; constructing a topology skeleton corresponding to the target electronic system based on the topology graph, converting the constraint rules into virtual constraint nodes, constructing causal edges and node attributes corresponding to the topology skeleton according to the causal relationships and the boundary condition dictionary, and calculating the edge weights corresponding to the causal edges, so as to establish a unified causal graph model corresponding to the target electronic system based on the topology skeleton, the virtual constraint nodes, the causal edges, the node attributes, and the edge weights; performing multi-dimensional testing using the unified causal graph model to generate multiple test case sets, determining resource consumption data and at least one ranking index corresponding to the multiple test case sets, ranking the multiple test case sets according to the at least one ranking index, and grouping the ranked multiple test case sets using the resource consumption data to generate the final test sequence of the target electronic system.

[0007] This application also provides a multi-dimensional test case generation device, comprising: a data standardization module, used to acquire original multi-source data corresponding to a target electronic system and convert the original multi-source data into corresponding standardized data, wherein the standardized data includes at least one of a topology graph, constraint rules, causal relationships, a boundary condition dictionary, and a fault path list; a causal graph construction module, used to construct a topology skeleton corresponding to the target electronic system based on the topology graph, convert the constraint rules into virtual constraint nodes, construct causal edges and node attributes corresponding to the topology skeleton according to the causal relationships and the boundary condition dictionary, and calculate the edge weights corresponding to the causal edges, so as to establish a unified causal graph model corresponding to the target electronic system based on the topology skeleton, the virtual constraint nodes, the causal edges, the node attributes, and the edge weights; and a test sequence generation module, used to perform multi-dimensional testing using the unified causal graph model to generate multiple test case sets, and determine resource consumption data and at least one ranking index corresponding to the multiple test case sets, so as to rank the multiple test case sets according to the at least one ranking index, and use the resource consumption data to group the ranked multiple test case sets into test cases, so as to generate the final test sequence of the target electronic system.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described multidimensional test case generation methods when executing the computer program.

[0009] This application also provides a non-volatile computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described multidimensional test case generation methods.

[0010] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described multidimensional test case generation methods.

[0011] This application enables the acquisition of raw multi-source data corresponding to a target electronic system, which is then converted into standardized data. The standardized data includes at least one of the following: a topology graph, constraint rules, causal relationships, a boundary condition dictionary, and a fault path list. A topological skeleton corresponding to the target electronic system is constructed based on the topology graph, and constraint rules are converted into virtual constraint nodes. Causal edges and node attributes corresponding to the topological skeleton are constructed based on the causal relationships and boundary condition dictionary, and edge weights are calculated. A unified causal graph model corresponding to the target electronic system is then established based on the topology skeleton, virtual constraint nodes, causal edges, node attributes, and edge weights. Multi-dimensional testing is performed using the unified causal graph model to generate multiple test case sets, and the corresponding test case sets are determined. This method utilizes resource consumption data and at least one ranking metric to rank multiple test case sets according to the ranking metric. Furthermore, it uses resource consumption data to group the ranked test case sets into test case groups to generate the final test sequence for the target electronic system. Therefore, it addresses the technical problems in related technologies, such as strong model type dependency, lack of natural language constraint parsing operations, isolated existence of schematic diagrams, design specifications, signal integrity simulations, etc., generated during the design phase, and neglect of over-limit scenarios, resulting in limited scenario coverage. By integrating multi-source design data, a unified causal graph model is constructed, achieving a complete expression of design intent and the explicit manifestation of tacit knowledge, thereby significantly improving the coverage of test scenarios and the utilization efficiency of test resources. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of a multidimensional test case generation method provided according to an embodiment of this application;

[0014] Figure 2 A schematic diagram of the structure of a topology parser is provided for one embodiment of this application;

[0015] Figure 3 A schematic diagram of a constraint extractor provided for one embodiment of this application;

[0016] Figure 4 A schematic diagram of a feature analyzer provided for one embodiment of this application;

[0017] Figure 5 A schematic diagram of the execution logic for data source alignment is provided for one embodiment of this application;

[0018] Figure 6 A schematic diagram illustrating the construction process of a unified cause-effect graph model provided in one embodiment of this application;

[0019] Figure 7 A schematic diagram illustrating the execution flow of a counterfactual test provided for one embodiment of this application;

[0020] Figure 8 A schematic diagram of the logical architecture of a multidimensional test case generation method provided in one embodiment of this application;

[0021] Figure 9 A schematic diagram of the logical architecture of a data preprocessing engine provided for one embodiment of this application;

[0022] Figure 10 A schematic diagram of a logical architecture for multidimensional data mounting is provided for one embodiment of this application;

[0023] Figure 11 A schematic diagram illustrating the execution logic of a multidimensional test generation algorithm provided for one embodiment of this application;

[0024] Figure 12 A schematic diagram illustrating the causal relationship of charge and discharge control of a lithium battery BBU (Battery Backup Unit) provided for one embodiment of this application;

[0025] Figure 13 A schematic diagram illustrating the causal relationship in a fan array coordinated speed regulation verification process is provided as an embodiment of this application;

[0026] Figure 14 A schematic diagram illustrating the causal relationship during a high-temperature environment fan speed regulation verification process, provided as an embodiment of this application;

[0027] Figure 15 This is an example diagram of a multidimensional test case generation device according to an embodiment of this application.

[0028] Among them, there are 10-multidimensional test case generation device, 100-data standardization module, 200-cause graph construction module, and 300-test sequence generation module. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0030] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0031] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] The specific application environment architecture or specific hardware architecture on which the execution of the multidimensional test case generation method depends is described here.

[0033] The embodiments of this application provide a method for generating multidimensional test cases.

[0034] like Figure 1 The diagram shows a flowchart of a multi-dimensional test case generation method according to an embodiment of this application. The multi-dimensional test case generation method includes the following steps:

[0035] In step S101, the original multi-source data corresponding to the target electronic system is obtained, and the original multi-source data is converted into corresponding standardized data. The standardized data includes at least one of the following: topology diagram, constraint rules, causal relationships, boundary condition dictionary, and fault path list.

[0036] Those skilled in the art should understand that the following problems currently exist in the field of electronic design automation and hardware verification:

[0037] 1. Data silo problem: Schematics, design specifications, signal integrity simulations and other data generated during the design phase exist in isolation and lack unified modeling, which leads to test case generation relying on local data sources and insufficient coverage.

[0038] 2. Lack of natural language constraint processing: Text constraints in design documents (such as "temperature range -40℃~85℃") need to be manually coded into machine rules, which is costly to maintain and prone to errors.

[0039] 3. Difficulty in integrating physical laws: Traditional methods cannot automatically convert physical laws (such as thermal derating effect and Ohm's law) into test constraints, resulting in a lack of verification for multi-physics coupling scenarios (such as voltage tolerance reduction at high temperatures).

[0040] 4. Limitations of boundary testing: Traditional methods only verify the design requirement range (such as voltage 18-36V), and lack the ability to perform tests in over-limit scenarios (such as sudden change to 40V) and counterfactual scenarios.

[0041] To address the aforementioned issues, embodiments of this application can construct a unified cause-effect graph model based on the verification requirements of complex electronic systems (such as server power modules, high-speed interface circuits, etc.) by analyzing multiple input sources such as circuit schematics, design constraint documents, and simulation data, and automatically generate multi-dimensional test cases.

[0042] Therefore, the embodiments of this application can first obtain the original multi-source data corresponding to the electronic system, which covers five dimensions: circuit topology, design intent, physical characteristics, failure cases, and device limits. Secondly, the embodiments of this application can perform data preprocessing operations on the original multi-source data through a topology parser, constraint extractor, feature analyzer, boundary extractor, and fault extractor to obtain unified structured data such as the corresponding topology graph, constraint rules, causal relationships, boundary condition dictionary, or fault path list. The unified structured data is then named and standardized to obtain the corresponding standardized data.

[0043] Therefore, the embodiments of this application obtain standardized data by acquiring the original multi-source data corresponding to the electronic system and performing data preprocessing and naming standardization operations on it, thereby providing reliable data guidance and basis for the subsequent generation of multi-dimensional test cases.

[0044] Optionally, in one embodiment of this application, obtaining the original multi-source data corresponding to the target electronic system and converting the original multi-source data into corresponding standardized data includes: obtaining the original multi-source data corresponding to the target electronic system, performing data preprocessing operations on the original multi-source data to obtain corresponding preprocessed data, and performing data fusion operations on the preprocessed data to generate unified structured data, wherein the unified structured data includes topology graphs, constraint rules, causal relationships, boundary condition dictionaries, or fault path lists; and performing data alignment on the unified structured data to convert the original multi-source data into a unified namespace to generate corresponding standardized data.

[0045] It should be noted that the original multi-source data of the electronic system obtained in this application embodiment covers various heterogeneous data such as circuit schematics, design documents, simulation reports, and fault records. In the preprocessing of the above-mentioned original data, this application embodiment can use a format conversion tool to convert unstructured data (such as natural language design specifications) into structured tables, and extract and complete fields for semi-structured data (such as simulation logs in XML (eXtensible Markup Language) format); secondly, through data cleaning to remove duplicate records and correct outliers (such as parameters that exceed the physical reasonable range), unified structured data is obtained, which includes topology diagrams (component connection relationships), constraint rules (such as voltage and current limits), causal relationships (such as signal transmission logic), boundary condition dictionaries (such as environmental parameter ranges), and fault path lists (such as historical failure links).

[0046] Subsequently, embodiments of this application can use a fuzzy matching algorithm based on a preset domain vocabulary to resolve naming differences between data from different sources, and establish a cross-data source mapping table to achieve a unique identifier association between the same component in the topology diagram and fault records; parameter contradictions are handled through a conflict resolution mechanism, and finally all data are converted to a unified namespace to generate standardized data with consistent format and unified semantics.

[0047] Therefore, this application embodiment transforms heterogeneous multi-source data into standardized data through preprocessing and data alignment, thereby eliminating naming and format differences, ensuring data consistency, and providing a high-quality data foundation for the subsequent construction of causal graph models.

[0048] Optionally, in one embodiment of this application, the original multi-source data corresponding to the target electronic system is obtained, and data preprocessing is performed on the original multi-source data to obtain corresponding preprocessed data. Data fusion is then performed on the preprocessed data to generate unified structured data. This includes: obtaining the original multi-source data corresponding to the target electronic system, wherein the original multi-source data includes circuit schematics, design documents, simulation data, historical fault databases, and component manuals; parsing the netlist data in the electronic design exchange format of the circuit schematic to extract corresponding component identifiers, and performing signal flow analysis on the circuit schematic based on the component identifiers to calculate the path weights of the circuit schematic, and marking the corresponding critical paths according to the path weights to generate a topology graph through the critical paths; performing text preprocessing on the design documents, and performing regular expression matching on the preprocessed design documents based on a preset rule template library to obtain corresponding matching results, and converting the matching results into constraint rules.

[0049] It should be noted that the embodiments of this application can first obtain raw data from five dimensions in the input layer: circuit schematic diagram (EDIF (Electronic Design Interchange Format) / Schematic format), design document (PDF (Portable Document Format) / DOC / Natural Language), simulation data (SPICE (Simulation Program with Integrated Circuit Emphasis) / CSV (Comma-Separated Values) / Text Report), historical fault database (SQL (Structured Query Language)) / XML database), and device manual (PDF / Datasheet).

[0050] Secondly, such as Figure 2 As shown, embodiments of this application can use a topology parser to parse the netlist data in the electronic design exchange format of the circuit schematic, thereby converting the circuit schematic into a computer-processable topology network. The specific process is as follows:

[0051] 1. Netlist parsing:

[0052] By parsing circuit schematics in formats such as EDIF / Schematic, the components and their connections in the circuit are extracted. Each component is converted into a node in the topology graph, containing metadata such as component type (resistor / capacitor / MOSFET, etc.) and device parameters (resistance value / capacitance value / model). The connection relationship is converted into directed edges between nodes, recording the network name (such as VCC (Voltage To Current Converter, circuit voltage), GND (Ground, ground terminal, etc.).

[0053] In one possible approach, embodiments of this application can use a recursive descent parser to decompose the netlist hierarchy and identify key syntax elements, such as identifying R1 N001 N002 10K as resistor nodes and NET N001U1.PIN5 as connection edges; subsequently, embodiments of this application can expand the sub-circuits corresponding to the circuit schematic into a planar network.

[0054] 2. Critical path marker:

[0055] Based on a user-defined list of critical paths (such as power input and clock source), the system automatically marks the component nodes on these paths. For example, in the power module, the path from "input filtering" to "PWM controller" to "MOSFET driver" will be marked as a critical path and given a higher weight value (1.0). This ensures that critical functional paths are covered first when subsequent tests are generated.

[0056] In embodiments of this application, signal flow analysis can be performed based on forward propagation and backward tracking strategies to calculate path weights, as shown in the following formula:

[0057]

[0058] In the embodiments of this application, the power supply element coefficient can be set to 1.0, the clock element coefficient can be set to 0.8, and the logic element coefficient can be set to 0.5.

[0059] Subsequently, the embodiments of this application also require user-defined overriding to support user-annotated critical paths, and automatically merge the analysis results with user annotations through hybrid mode.

[0060] 3. Topology graph generation:

[0061] The embodiments of this application can determine the node attributes corresponding to each component based on the component type, electrical parameters, and critical path markers, so as to convert each component into a corresponding node, and determine the edge attributes between each component based on the connection type (power / signal / ground), network name, and signal direction, so as to convert the connection relationship between nodes into the corresponding edge, thereby generating the corresponding topology graph.

[0062] Therefore, the topology graph constructed in this application embodiment can completely preserve the physical connection relationship of the circuit, providing skeletal support for subsequent constraint injection and feature association.

[0063] After that, as Figure 3 As shown, embodiments of this application also require processing the design document using a constraint extractor to convert the design specifications described in natural language into structured machine rules, thereby obtaining the corresponding constraint rules, as detailed below:

[0064] 1. Text preprocessing:

[0065] The original text is extracted using a PDF / DOC parsing engine, and then segmented, terminology is standardized (e.g., "voltage" is described as "Voltage"), and units are unified ("volt" is described as "V"). Key paragraphs are identified, such as those containing keywords like "constraint," "range," and "limit."

[0066] 2. Rule template matching:

[0067] (1) Regular expression matching based on a predefined rule template library:

[0068] 1) Voltage range: r'(\w+)V to (\d+)V', to capture target components and limits;

[0069] 2) Frequency tolerance: The frequency r'(\w+) must be maintained at (\d+)kHz±(\d+)%' to capture the nominal value and deviation;

[0070] 3) Temperature range: r'Operating temperature: (-?\d+)℃ to (-?\d+)℃', to capture temperature boundaries.

[0071] Therefore, the embodiments of this application can support user-defined template extensions and can adapt to different design specification formats.

[0072] 3. Constraint rule generation:

[0073] The matching results are converted into structured JSON (JavaScript Object Notation) rules (i.e., constraint rules), as described below:

[0074] {

[0075] "type": "VOLTAGE_RANGE",

[0076] "target": "input level",

[0077] "min": 18,

[0078] "max": 36,

[0079] "unit": "V"

[0080] }

[0081] It should be noted that, in the embodiments of this application, each of the above constraint rules includes a target element, constraint type, numerical boundary, and unit of measurement, thereby providing design intent input for subsequent causal graph construction.

[0082] Subsequently, embodiments of this application may use a semantic similarity algorithm based on cosine similarity and word embedding strategy to perform fuzzy matching processing, and sort the priorities according to preset priorities, such as the priority of the principle diagram annotation is higher than the priority of the design document, and the priority of the design document is higher than the priority of the simulation report, in order to resolve conflicts.

[0083] Therefore, the embodiments of this application achieve intelligent parsing and rule extraction of electronic design data through multi-source data fusion and structured transformation, significantly improving design verification efficiency. In addition, the embodiments of this application accurately restore circuit connection relationships through topology parser and convert natural language specifications into executable rules using constraint extractor, combined with priority mechanism to ensure the reliability of conflict resolution, providing a complete and accurate input foundation for subsequent automated testing.

[0084] Optionally, in one embodiment of this application, the original multi-source data corresponding to the target electronic system is obtained, and data preprocessing is performed on the original multi-source data to obtain corresponding preprocessed data. Data fusion is then performed on the preprocessed data to generate unified structured data. The method further includes: cleaning the simulation data to obtain corresponding standard data, calculating the correlation coefficient matrix corresponding to the standard data, and performing thermal effect modeling based on the standard data to construct a corresponding temperature-parameter response model; calculating the corresponding time margin based on the standard data to determine the corresponding time-series relationship through the time margin, and mapping the correlation coefficient matrix, temperature-parameter response model, and time-series relationship to a causal relationship; extracting causal chains from the historical fault database to obtain a fault path list, and extracting boundaries from the device manual to obtain a boundary condition dictionary.

[0085] In actual implementation, such as Figure 4 As shown, embodiments of this application also require the use of a feature analyzer to mine implicit causal relationships from simulation data in order to extract the corresponding physical characteristics and obtain the corresponding causal relationships, as described below:

[0086] 1. Data cleaning:

[0087] Preprocessing operations such as filling missing values, smoothing noisy data, and normalization are performed on the simulation data in SPICE / CSV format to ensure that the data quality meets the analysis requirements.

[0088] 2. Feature Extraction: Corresponding algorithms are used for feature extraction based on different simulation types of data.

[0089] (1) Parameter sensitivity: The correlation coefficient matrix is ​​calculated using the following formula to identify strongly correlated parameters:

[0090]

[0091] in, X represents an input variable or parameter. In the embodiments of this application, X represents a causal factor or independent variable (i.e., the amount of change of the input variable) extracted from the simulation data, such as ambient temperature, input voltage, signal frequency, etc. Y represents another input variable or parameter. In the embodiments of this application, Y can represent the result factor or dependent variable (i.e., the change in output response) affected by X, such as the on-resistance of the MOSFET, the delay of the output signal, the efficiency of the power module, etc. It represents the covariance of variables X and Y, which measures the trend of change in the two variables; The standard deviation of variable X represents the degree of dispersion of X. The standard deviation of variable Y represents the degree of dispersion of Y; The Pearson correlation coefficient represents the degree of linear correlation between variables X and Y, and its value ranges from [-1, 1]. When = 1, it indicates a perfectly positive correlation. =-1 indicates a completely negative correlation. When =0, it indicates that there is no linear dependence.

[0092] (2) Thermal coupling effect: Establish a temperature-parameter response model, such as the MOSFET on-resistance temperature rise model, the mathematical expression of which is shown below:

[0093] in, This represents the on-resistance of the MOSFET at temperature T. This indicates the change in temperature, specifically T-25°C, with the unit being °C. This indicates the on-resistance at 25°C (i.e., the reference value). This represents the temperature coefficient, which indicates the rate at which the resistance changes with temperature. This parameter value can be obtained from the device datasheet.

[0094] (3) Timing relationship: Analyze the signal establishment time and holding time to calculate the corresponding timing margin, thereby obtaining the corresponding characteristic relationship.

[0095] 3. Causal mapping:

[0096] (1) Map the feature relationships to edges in the causal graph:

[0097] 1) Source node: Influencing factors (such as temperature);

[0098] 2) Target node: Affected components (such as MOSFETs);

[0099] 3) Edge attributes: relation type (thermal_impact), sensitivity coefficient, confidence level.

[0100] (2) Calculate the corresponding sensitivity coefficient using the following sensitivity coefficient calculation formula:

[0101] Where X represents the change in the input variable and Y represents the change in the output response.

[0102] It should be noted that the causal mapping rules in the embodiments of this application are shown in Table 1:

[0103] Table 1

[0104]

[0105] 4. Model Building:

[0106] Furthermore, embodiments of this application can generate mathematical expressions for causal relationships, such as the heat effect equation, and inject this equation as domain knowledge into the causal graph:

[0107] Rds_on = 0.02*(1+0.0038*(T-25))

[0108] in, This indicates the on-resistance of the MOSFET at the current temperature T; T represents the current temperature in °C.

[0109] In addition, embodiments of this application also require processing of the device datasheet and historical fault database through a boundary extractor and a fault extractor to output a boundary condition dictionary (such as {"MOSFET": {"V_max": 40V}}) and a fault path list.

[0110] Therefore, the embodiments of this application achieve in-depth mining and modeling of electronic system characteristics through multi-source data fusion and causal analysis. In addition, the embodiments of this application extract physical characteristics and causal relationships from simulation data through a feature analyzer, and combine them with boundary and fault information to construct a high-confidence causal graph, thereby providing accurate domain knowledge support for design verification and fault prediction, and significantly improving system reliability and analysis efficiency.

[0111] Optionally, in one embodiment of this application, data alignment is performed on the unified structured data to convert the original multi-source data to a unified namespace and generate corresponding standardized data. This includes: standardizing the original name of each type of data in the original multi-source data to obtain the corresponding standard name, and constructing a mapping table between the original name and the standard name; determining whether there is a name conflict among all standard names based on the mapping table, wherein, if there is a name conflict among all standard names, different weights are set for the data with name conflicts based on a preset confidence voting strategy to obtain standardized data.

[0112] In actual implementation, such as Figure 5As shown, this application standardizes the names of circuit topology nodes, design constraint targets, simulation feature elements, and the main body of the device manual, converting them to a unified namespace for unified naming. The specific process is as follows:

[0113] 1. Naming standardization:

[0114] The embodiments of this application may employ a fuzzy matching algorithm based on Levenshtein distance (i.e., Levenshtein distance or edit distance) to resolve naming differences between different data sources. For example, "Q1" in the schematic diagram is "main MOSFET" in the design document and "IRF3205" in the manual.

[0115] 2. Establish a mapping dictionary:

[0116] Generate a mapping table of <original name, standard name>.

[0117] 3. Conflict resolution mechanism:

[0118] When multiple standard names conflict, a confidence-based voting strategy is used to assign different weights to the data with conflicting names (e.g., design document weight 0.7, schematic diagram weight 0.9).

[0119] Therefore, the embodiments of this application effectively solve the naming differences and conflicts between different data sources by standardizing naming, establishing a mapping dictionary and conflict resolution mechanism, realize data alignment, generate standardized data, and provide a unified and reliable data foundation for subsequent system modeling.

[0120] Optionally, in one embodiment of this application, the original names of each type of data in the original multi-source data are standardized to obtain corresponding standard names. This includes: extracting component naming features from the original multi-source data and constructing corresponding structured feature vectors based on the component naming features; associating symbol identifiers and functional descriptions in the original multi-source data through a preset domain knowledge graph to construct corresponding semantic mapping rules; and adaptively adjusting the editing operation weights corresponding to various editing operations based on the structured feature vectors and semantic mapping rules, and selecting target editing operation weights that meet preset editing requirements for various editing operations, so as to determine the corresponding standard names based on the target editing operation weights.

[0121] It should be noted that the process of standardizing the original names of the original multi-source data using the fuzzy matching algorithm in the embodiments of this application is as follows:

[0122] 1. Extract component naming features from raw multi-source data (such as schematics, design documents, component manuals), including naming prefixes (such as "R" representing resistor), serial numbers (such as "123"), and functional suffixes (such as "_power"). Construct structured feature vectors through part-of-speech tagging and feature encoding to accurately represent the naming logic.

[0123] 2. Based on the pre-set domain knowledge graph (covering the relationships of component type, functional attributes, model parameters, etc.), semantically associate the symbol identifiers (such as "Q1") in the original data with the functional descriptions (such as "high voltage switching tube") to generate semantic mapping rules containing synonyms and hyponyms, for example, mapping "MOS tube" and "field effect tube" to the same functional category.

[0124] 3. Based on the similarity of structured feature vectors and the matching degree of semantic mapping rules, the weights of insertion, deletion and replacement operations in the edit distance algorithm are adaptively adjusted. That is, the editing operation of functional feature words (such as "power") is given higher weight, and the editing operation of serial number characters (such as "123") is given lower weight. The matching result corresponding to the maximum editing operation weight is selected as the standard name to ensure that the naming standardization takes into account both structural consistency and semantic accuracy.

[0125] Therefore, the embodiments of this application optimize fuzzy matching through structured features and semantic association, thereby achieving accurate standardization of multi-source data naming, effectively eliminating naming differences, and improving data consistency and the reliability of subsequent processing.

[0126] In step S102, a topological skeleton corresponding to the target electronic system is constructed based on the topological graph, and the constraint rules are converted into virtual constraint nodes. Causal edges and node attributes corresponding to the topological skeleton are constructed according to the causal relationship and boundary condition dictionary, and the edge weights corresponding to the causal edges are calculated, so as to establish a unified causal graph model corresponding to the target electronic system based on the topological skeleton, virtual constraint nodes, causal edges, node attributes and edge weights.

[0127] Furthermore, embodiments of this application also require integrating multiple structured data and completing data alignment to generate standardized data; constructing the topological skeleton of the electronic system based on the topological graph therein, transforming constraint rules into virtual constraint nodes; and then adding causal edges and node attributes to the topological skeleton according to the causal relationships and boundary condition dictionary in the data, calculating the weights of the causal edges, and finally constructing a unified causal graph model of the electronic system.

[0128] It is understood that the embodiments of this application solve the problem of data fragmentation in related technologies by constructing a unified causal graph model by integrating multi-source design data (schematics, constraint documents, simulation reports, historical fault databases, and device manuals), realize the complete expression of design intent and the explicitness of implicit knowledge (such as physical effects and historical fault modes), thereby significantly improving the coverage of test scenarios such as multi-physics coupling and exceeding limits.

[0129] Therefore, the embodiments of this application generate a weighted causal graph (which is mainly composed of nodes, edges and corresponding node attributes) based on the preprocessed structured data through data integration and structured modeling. This achieves a unified representation of the electronic system topology, constraints and causal relationships, improves the integrity and relevance of the model, and provides a reliable foundation for subsequent analysis.

[0130] Optionally, in one embodiment of this application, constructing the topological skeleton corresponding to the target electronic system based on the topological graph includes: analyzing the electronic components in the netlist data of the circuit schematic to obtain the corresponding analytical data, and determining the entity nodes corresponding to the electronic components based on the analytical data; extracting the electrical connection relationships in the netlist data and converting the electrical connection relationships into corresponding causal edges; constructing an initial directed graph based on the causal edges and the entity nodes corresponding to the electronic components, and determining the topological skeleton through the initial directed graph.

[0131] Specifically, in the embodiments of this application, when parsing circuit schematic netlist data, electronic components such as resistors, capacitors, and ICs are first identified, their model numbers, parameters, and other information are extracted, and each component is mapped as a unique entity node to ensure that the node attributes are consistent with the physical characteristics of the component; at the same time, the electrical connection relationships (such as pin connections and signal transmission paths) in the netlist are extracted and converted into directed causal edges (e.g., "output pin of component A - drive signal - input pin of component B") according to the current flow direction and signal driving logic.

[0132] Secondly, the embodiments of this application can use netlist-graph structure automatic mapping technology when constructing an initial directed graph based on entity nodes and causal edges. By matching pin numbers and associating signal names, the connection relationship is ensured to be complete. For complex modules (such as integrated circuits), sub-nodes are split according to internal functional units, and the hierarchical connection between modules is preserved. Finally, a complete topological skeleton that reflects the circuit signal flow and connection relationship is formed, ensuring the structural integrity of the circuit topology.

[0133] Therefore, the embodiments of this application construct a complete topological skeleton through precise mapping of components-nodes and connection relationships-causal edges, clearly presenting the circuit structure and signal flow, and providing a reliable foundation for subsequent circuit analysis.

[0134] Optionally, in one embodiment of this application, constraint rules are converted into virtual constraint nodes, and causal edges and node attributes corresponding to the topological skeleton are constructed according to the causal relationship and boundary condition dictionary. The edge weights corresponding to the causal edges are calculated to establish a unified causal graph model corresponding to the target electronic system based on the topological skeleton, virtual constraint nodes, causal edges, node attributes, and edge weights. This includes: extracting the failure count and total usage count of the target component from a preset enterprise fault database, and calculating the corresponding risk coefficient based on the failure count, total usage count, and preset failure severity level; determining the number of Monte Carlo simulations corresponding to the target electronic system, and determining the corresponding confidence level through the number of Monte Carlo simulations, and calculating the edge weights based on the risk coefficient and confidence level.

[0135] It should be noted that, as Figure 6 The specific process by which embodiments of this application establish a causal graph (i.e., a unified causal graph model) through operations such as multi-source data input, constraint node embedding, physical rule injection, dynamic weight assignment, and causal graph output is described below:

[0136] 1. Multi-source data input:

[0137] Input is the standardized data after data preprocessing and data alignment of the original multi-source data.

[0138] 2. Constraint Node Embedding (Design Intent Integration):

[0139] (1) Input data: Natural language constraints in the design document;

[0140] (2) Processing procedure:

[0141] 1) Identify key parameter boundaries (such as "voltage not greater than 36V") through NLP (Nature Language Processing).

[0142] 2) Create virtual constraint nodes (CONST_ type);

[0143] 3) Establish constraint relationships between virtual constraint nodes: constraint node - constraint relationship - target element, for example, CONST_Voltage - "constrains" - MOSFET_Gate.

[0144] 3. Physical rule injection (domain knowledge enhancement):

[0145] (1) Input data: physical law library and simulation data;

[0146] (2) Processing procedure:

[0147] 1) Load predefined physical rules (Ohm's law, heat derating curve, etc.);

[0148] 2) Instantiate the physical rules as super nodes;

[0149] 3) Establish dominance relationships: Physical rules - "governs" - related component groups;

[0150] 4) Supernodes have global influence and can propagate effects across levels. The scope of a supernode's dominance is determined by the domain of physical laws. In the embodiments of this application, circuit-level laws (such as Kirchhoff's laws) dominate the entire graph; component-level laws (such as the MOSFET temperature rise model) dominate the associated component group.

[0151] 4. Dynamic weight assignment (quantifying the strength of causal relationships):

[0152] The embodiments of this application first determine the number of Monte Carlo simulations for the electronic system, and then determine the corresponding simulation data confidence level based on the number of Monte Carlo simulations. Furthermore, historical fault statistics are obtained based on the component failure probability to determine the corresponding risk coefficient. Secondly, the embodiments of this application can calculate the corresponding edge weights based on the risk coefficient and the simulation data confidence level, combined with the following calculation:

[0153] W edge = k 1• + k 2•

[0154] in, Indicates the simulation confidence level; The value represents the risk coefficient; as shown in the above formula, the higher the edge weight, the more significant the corresponding causal relationship.

[0155] It should be noted that the expression for calculating the simulation confidence level in the embodiments of this application is as follows: in, Number of Monte Carlo simulations.

[0156] The expression for calculating the risk coefficient is:

[0157]

[0158] in, This indicates the number of times the target component has failed in the historical fault database (i.e., the fault statistics under specific conditions), which can generally be obtained from the enterprise fault database or SQL record data (such as the number of MOSFET failures under overvoltage scenarios); This indicates the total number of times the target component has been used (including normal and failure conditions), which can generally be obtained from production batch record data or device datasheets (total number of uses for a certain type of MOSFET). The severity level of the failure is indicated by the classification and quantification of the consequences of the failure. According to industry standards (such as JEDEC JESD94), the severity levels can be divided into: catastrophic = 1.0, severe = 0.7, and moderate = 0.4.

[0159] 5. Cause-effect graph output:

[0160] Output a unified causal graph model consisting of nodes, edges, and attributes.

[0161] It is understood that the embodiments of this application achieve automated embedding of domain knowledge by introducing supernodes representing physical laws and establishing their dominance relationship with related component groups, thereby enabling the generated test cases to more accurately reflect the behavior of the actual physical system.

[0162] Therefore, the embodiments of this application construct comprehensive and accurate constraint and causal relationships by embedding constraint nodes to integrate design intent, injecting physical rules to enhance domain knowledge, and assigning dynamic weights to quantify causal strength, thereby improving the reliability and analysis depth of the electronic system model.

[0163] In step S103, multi-dimensional testing is performed using a unified cause-effect graph model to generate multiple test case sets. Resource consumption data and at least one ranking index corresponding to the multiple test case sets are determined to rank the multiple test case sets according to at least one ranking index. The resource consumption data is then used to group the ranked multiple test case sets into test cases to generate the final test sequence of the target electronic system.

[0164] Subsequently, embodiments of this application can utilize a unified cause-effect graph model to perform multi-dimensional testing, generate multiple test case sets, and perform sorting optimization and resource grouping operations on the multiple test case sets to obtain an optimized executable test sequence, i.e., the final test sequence.

[0165] Therefore, the embodiments of this application improve the utilization efficiency of test resources and the targeting of test execution by prioritizing the coverage of critical paths and high-risk components through a test sequence generation strategy based on weight optimization.

[0166] Optionally, in one embodiment of this application, multi-dimensional testing is performed using a unified cause-effect graph model to generate multiple test case sets, including: identifying key signal paths in the unified cause-effect graph model, generating input-output verification data under standard operating conditions based on the key signal paths, performing design verification testing through the input-output verification data, and outputting a design verification test case set that meets preset verification function requirements; extracting the limit values ​​of virtual constraint nodes in the unified cause-effect graph model, and performing boundary testing operations based on the limit values ​​to obtain a boundary test case set; and injecting defect information into the unified cause-effect graph model through a historical fault database to perform fault injection testing on the unified cause-effect graph model, thereby generating a fault injection test case set.

[0167] It should be noted that the embodiments of this application can utilize a unified cause-effect graph model for multi-dimensional testing to generate corresponding test case sets, as described below:

[0168] 1. Design verification testing:

[0169] (1) Generation principle: Generate corresponding test cases along the main path of the cause-effect graph;

[0170] (2) Test steps:

[0171] Step 1: Identify high-weight critical paths (such as clock-logic-output);

[0172] Step 2: Generate standard input combinations and expected outputs to obtain a set of design verification test cases that meet the preset verification function requirements (i.e., a set of design verification test cases that outputs the correct verification function).

[0173] 2. Boundary testing:

[0174] (1) Generation principle: Exploring parameter boundary combinations;

[0175] (2) Test steps:

[0176] Step 1: Extract the limit values ​​of the constraint nodes (e.g., Vmin=18V, Vmax=36V).

[0177] Step 2: Combine Cartesian product parameters (such as voltage, temperature, and frequency combination parameters: 36V@85℃, maximum clock frequency) to obtain the boundary test case set.

[0178] 3. Fault injection test:

[0179] (1) Generation principle: Simulating component failure;

[0180] (2) Test steps:

[0181] Step 1: Map the fault library to the causal node (e.g., open resistor);

[0182] Step 2: Activate the vulnerable path to generate abnormal scenarios in order to generate a set of fault injection test cases.

[0183] Therefore, the embodiments of this application generate multi-dimensional test case sets for design verification, boundary conditions, and fault injection based on a unified cause-effect graph model, thereby covering critical paths, parameter boundaries, and failure scenarios, comprehensively verifying system performance, and improving the completeness and effectiveness of testing.

[0184] Optionally, in one embodiment of this application, key signal paths in a unified causal graph model are identified, and input / output verification data under standard operating conditions is generated based on the key signal paths. Design verification testing is then performed using this input / output verification data to output a set of design verification test cases that meet preset verification function requirements. This includes: constructing a digital twin dynamic mapping model based on the main path of the unified causal graph model, and synchronizing the physical parameters and virtual simulation parameters of the key signal paths in real time through the digital twin dynamic mapping model. The physical parameters include signal transmission delay and logic unit temperature drift coefficient, while the virtual simulation parameters include path node state variables and a signal attenuation model. The digital twin dynamic mapping model is trained based on a preset reinforcement learning algorithm, using the input / output verification results under standard operating conditions as the reward function to generate an adaptive test sequence generation strategy for key signal path parameter drift. Multi-dimensional perturbation factors are injected into the identified key signal paths according to the test sequence generation strategy to generate extended test sequences containing perturbation response verification. The extended test sequences are then subjected to virtual-real comparison analysis through the digital twin dynamic mapping model to output a set of design verification test cases that meet preset verification function requirements.

[0185] In the specific implementation process, when designing verification tests, the embodiments of this application can first combine the main path and high-weight critical path (such as clock-logic-output path) of the unified cause-effect graph model to accurately identify the core signal transmission link; based on this, a digital twin dynamic mapping model is constructed to synchronize the physical parameters (signal transmission delay, logic unit temperature drift coefficient, etc.) of the critical path with the virtual simulation parameters (path node state variables, signal attenuation model, etc.) in real time, so as to realize the linkage of virtual and real parameters.

[0186] Secondly, embodiments of this application can use a preset reinforcement learning algorithm to train the model, using the matching degree of input and output verification results under standard working conditions as the reward function, to generate a test sequence generation strategy that can adapt to critical path parameter drift (such as signal delay caused by temperature drift); subsequently, embodiments of this application can inject multi-dimensional perturbation factors (such as voltage fluctuations and frequency deviations) along the identified critical path to generate an extended test sequence that includes perturbation response verification, covering parameter drift scenarios.

[0187] Finally, the embodiments of this application can use a digital twin model to perform a virtual-real comparison analysis on the extended test sequences (cross-verification of physical measured data and virtual simulation results) to filter out sequences with correct functional verification and form a set of design verification test cases.

[0188] Therefore, the embodiments of this application, by integrating digital twins and reinforcement learning, accurately cover critical paths and parameter drift scenarios, improve test adaptability and verification depth, and ensure the comprehensiveness and accuracy of design verification.

[0189] Optionally, in one embodiment of this application, the limit values ​​of virtual constraint nodes in the unified causal graph model are extracted, and boundary testing is performed based on the limit values ​​to obtain a boundary test case set. This includes: semantically labeling the limit values ​​of virtual constraint nodes based on a pre-built parameter association knowledge graph to obtain multiple parameters with semantic information, and obtaining the implicit constraint relationships between the multiple parameters through a preset graph neural network; generating boundary combination samples based on the parameter association knowledge graph and the implicit constraint relationships, and using an adaptive particle swarm optimization algorithm, and extending and verifying the boundary combination samples through a preset Monte Carlo simulation strategy to obtain a boundary test case set.

[0190] It should be noted that, during boundary testing, the embodiments of this application can first extract limit values ​​from the virtual constraint nodes of the unified causal graph model, and then semantically annotate these limit values ​​in conjunction with the parameter association knowledge graph to clarify the physical meaning of the parameters (such as the upper limit of voltage and the critical value of temperature); secondly, the implicit constraint relationship between parameters (such as the coupling effect of voltage and temperature) is mined through graph neural networks.

[0191] Subsequently, embodiments of this application can generate boundary combination samples based on knowledge graphs and implicit constraint relationships, using an adaptive particle swarm optimization algorithm to replace traditional Cartesian product combinations and reduce redundant samples; at the same time, a Monte Carlo simulation strategy is introduced to randomly perturb and expand the samples (such as fluctuating within ±5% of the limit value) to verify the impact of small parameter changes on the system, ultimately forming a boundary test case set covering explicit and implicit constraint relationships.

[0192] Therefore, the embodiments of this application optimize parameter combinations through semantic annotation and implicit relationship mining, and improve boundary scene coverage by combining simulation expansion, thereby enhancing the accuracy and efficiency of testing and fully verifying the adaptability of the system boundary.

[0193] Optionally, in one embodiment of this application, defect information is injected into the unified cause-effect graph model through a historical fault database to perform fault injection testing on the unified cause-effect graph model and generate a fault injection test case set. This includes: extracting at least one typical fault mode that meets the fault occurrence frequency based on the historical fault database, and establishing a multi-dimensional fault model database based on the at least one typical fault mode; determining at least one vulnerable node in the unified cause-effect graph model that meets preset vulnerability requirements, and establishing a dynamic mapping relationship between the multi-dimensional fault model database and the at least one vulnerable node, and constructing a fault path set based on the dynamic mapping relationship; determining the test requirements corresponding to the target server, and selecting multiple target nodes from the fault path set according to the test requirements, and determining the target fault modes corresponding to the multiple target nodes in the multi-dimensional fault model database; and injecting the target fault modes into the unified cause-effect graph model to generate a fault injection test case set.

[0194] Specifically, during fault injection testing, this embodiment first extracts high-frequency typical fault modes (such as resistor open circuit and capacitor short circuit) from the historical fault database to construct a multi-dimensional fault model library covering electrical failures and logical errors. Secondly, this embodiment can combine a unified cause-effect graph model to identify vulnerable nodes (such as high-power components and signal bottleneck nodes) through node load rate and connection edge weight, and establish a dynamic mapping between fault models and vulnerable nodes (such as mapping "overvoltage breakdown" to power transistor nodes).

[0195] Furthermore, in this application embodiment, based on server testing requirements (such as reliability verification and fault tolerance testing), key target nodes can be selected from the fault path set and matched with corresponding target fault modes (such as injecting a "voltage drop" fault into the power module). Subsequently, after the fault mode is injected into the model, the embodiment of this application can track the propagation path of the fault in the cause-effect graph (such as the chain effect from the power node to the logic unit), activate the vulnerable path to generate abnormal scenarios, and finally form a fault injection test case set covering typical faults and critical paths.

[0196] Therefore, the embodiments of this application, through typical fault modeling and precise mapping of vulnerable nodes, and combined with the requirement to screen target faults, fully activate abnormal scenarios, thereby improving the pertinence and coverage of fault testing and ensuring the effectiveness of system reliability verification.

[0197] Optionally, in one embodiment of this application, multi-dimensional testing using a unified cause-effect graph model to generate multiple test case sets further includes: determining the target constraint node in the unified cause-effect graph model and extracting all thermally relevant incoming edges of the target constraint node; determining the edge weight and direct sensitivity of all thermally relevant incoming edges, and calculating the thermal sensitivity of all thermally relevant incoming edges based on the edge weight and direct sensitivity; fitting historical fault data in a historical fault database to obtain the corresponding sensitivity attenuation coefficient, and calculating the safety margin of all thermally relevant incoming edges based on a preset maximum material tolerance coefficient and basic safety offset, combined with the sensitivity attenuation coefficient and thermal sensitivity; calculating the breakthrough value corresponding to all thermally relevant incoming edges based on the safety margin, and constructing a counterfactual test case set based on the breakthrough value.

[0198] It should be noted that, as Figure 7 As shown, this application embodiment can construct a counterfactual test case set based on the exploratory testing principle of breaking design constraints by performing steps such as locating constraint nodes, calculating safety margins, deriving breakthrough values, and constructing test scenarios. The mathematical expression of the safety margin calculation model is shown below:

[0199] in, This represents thermal sensitivity (which can be calculated using a cause-effect graph). k This represents the attenuation coefficient, and its default value can be set to 0.5. α and β All of these are material calibration parameters obtained by fitting historical fault data. α The maximum tolerance coefficient of the material. β Based on the safety offset.

[0200] In the embodiments of this application, thermal sensitivity The calculation process is as follows:

[0201] 1. Extract all thermally relevant incoming edges from the cause-effect graph of the target constraint node, and calculate the weighted sensitivity, as shown in the following formula:

[0202]

[0203] in, Indicates the edge weight (0.0~1.0); This represents the direct sensitivity determined through simulation calculations.

[0204] For example, a MOSFET node has 3 incoming edges:

[0205] 1) Ambient temperature - junction temperature: =0.8, S =0.5;

[0206] 2) Power consumption - junction temperature: =0.9, S =0.7;

[0207] Therefore, the thermal sensitivity of the MOSFET node is as follows: .

[0208] Furthermore, embodiments of this application can also determine the sensitivity attenuation coefficient by fitting historical fault data using the least squares method. k The specific process is as follows:

[0209] 1. Collect fault data: S (Thermal sensitivity) and critical margin ;

[0210] 2. Optimization k Minimize the error: ,in, This represents the margin value calculated based on the aforementioned safety margin calculation model.

[0211] In the embodiments of this application, material calibration parameters α , β and sensitivity attenuation coefficient k The physical meaning and determination method of are shown in Table 2:

[0212] Table 2

[0213]

[0214] Furthermore, in this embodiment, the corresponding edge weights can also be calculated using the confidence level, risk coefficient, and corresponding weight coefficients. The calculation expression for the edge weights is as follows:

[0215]

[0216] in, and These are the weighting coefficients, and their default configuration is... =0.7, =0.3.

[0217] Furthermore, the optimization results based on 200 sets of historical validation cases... When the confidence level is >0.8, excessively high confidence leads to a 15% increase in the boundary test omission rate; when When the risk weight is greater than 0.5, an excessively high risk weight leads to a 22% increase in the false positive rate of the counterfactual test.

[0218] Therefore, in the embodiments of this application, (default The embodiments of this application can be used for... and The coefficient can be dynamically configured, and can be increased in high-risk applications. .

[0219] After obtaining the safety margin, embodiments of this application can calculate the corresponding breakthrough value (i.e., test value) based on the safety margin to quantitatively assess the near-failure but undocumented critical point. The calculation expression for the test value is shown in the following formula:

[0220] Test value = constraint value × (1 + margin)

[0221] It is understandable that the essential difference between counterfactual testing and boundary testing is that boundary testing verifies the combination within the design constraint boundaries, while counterfactual testing actively and computationally breaks through the constraint boundaries (based on the margin model) to explore the consequences of violating the constraints and the location of the critical point.

[0222] Therefore, the embodiments of this application automatically generate counterfactual test cases based on the cause-effect graph model and the safety margin calculation model, thereby enabling boundary exploration to break through design constraints, proactively discover potential failure thresholds, and improve the ability to detect potential defects.

[0223] Optionally, in one embodiment of this application, determining resource consumption data and at least one ranking index corresponding to multiple test case sets, sorting the multiple test case sets according to the at least one ranking index, and grouping test cases into the sorted multiple test case sets using the resource consumption data to generate the final test sequence of the target electronic system, includes: determining the edge weight and component failure rate of each test case set in the multiple test case sets, and sorting the multiple test case sets according to the edge weight and component failure rate respectively to generate the corresponding executable test sequence; determining the resource consumption data of each test case set, and grouping the executable test sequence into resource groups according to the resource consumption data to obtain the final test sequence.

[0224] Specifically, when optimizing the test sequence, this application embodiment can first extract the edge weights (reflecting the criticality of the path) and the failure rates of the involved components (reflecting the failure risk) of multiple test case sets, and calculate the comprehensive priority (critical path weight accounts for 60%, failure rate accounts for 40%) using a weighted summation method, and generate an executable test sequence in descending order of priority to ensure that test cases corresponding to high-weight paths and high-risk components are executed first.

[0225] Secondly, the embodiments of this application can analyze the resource consumption data of each type of use case (such as power load, test interface occupation, execution time), identify parallel use cases (such as tests of shared power modules and non-conflicting interfaces) through resource dependency graphs, and perform clustering and grouping; then, the embodiments of this application can sort resource conflicting use cases (such as exclusive core test instruments) according to the execution time ladder, and finally form a final test sequence that takes into account both priority and resource efficiency.

[0226] Therefore, the embodiments of this application improve testing efficiency and the timeliness of problem discovery by comprehensively prioritizing the coverage of critical and high-risk scenarios and by achieving parallel execution through resource grouping, thereby optimizing resource utilization.

[0227] Furthermore, in one embodiment of this application, resource consumption data for each type of test case set is determined, and executable test sequences are grouped according to resource consumption data to obtain the final test sequence. This includes: collecting resource consumption data and historical execution parameters for various types of test cases to construct a dynamic resource dependency graph; identifying parallel executable test cases based on the dynamic resource dependency graph and a shared resource load threshold, grouping them using an adaptive clustering algorithm to form dynamic parallel test groups; for test cases with resource conflicts, sorting them by execution duration stepwise, and then introducing a priority weight coefficient for secondary sorting; monitoring resource occupancy status in real time, dynamically adjusting the test sequence, and optimizing the execution order using a machine learning prediction model to generate the final test sequence.

[0228] Specifically, the process of generating test sequences based on priority and resource efficiency in this application embodiment is as follows:

[0229] 1. Dynamic resource data acquisition and map construction:

[0230] In addition to collecting hardware and software resource consumption data, parameters such as historical execution success rate and resource fluctuation coefficient are added. A dynamic graph is constructed through time-series correlation analysis to update resource dependencies in real time.

[0231] 2. Adaptive clustering grouping:

[0232] After identifying dependency-free use cases based on dynamic graphs, and combining load thresholds of resources such as shared power supplies (e.g., power supply at 80% maximum power), a density clustering algorithm is used to automatically adjust the clustering granularity. When the load of shared resources exceeds the threshold, some use cases are split into new groups.

[0233] 3. Weighted conflict sorting:

[0234] For resource conflict test cases, first sort them by duration, then introduce priority weight coefficients (1-10), and sort them again by the formula "adjustment value = duration × (1 / weight)" to ensure that high priority test cases are executed first within the same duration range.

[0235] 4. Intelligent dynamic optimization:

[0236] By monitoring resource utilization in real time, when the idle rate of a certain resource exceeds 30%, the parallel group is split. The execution time deviation of test cases is predicted using an LSTM (Long Short-Term Memory) model, and the sorting sequence is dynamically corrected.

[0237] Therefore, the embodiments of this application, by introducing dynamic adjustment and intelligent prediction, further improve resource utilization, shorten the testing cycle, and achieve a precise balance between priority and efficiency through adaptive clustering and weighted sorting.

[0238] The execution logic of the multidimensional test case generation method of this application will be described below with reference to the accompanying drawings.

[0239] Figure 8 This is a schematic diagram of the logical architecture of the multi-dimensional test case generation method for this application. (See diagram below.) Figure 8 As shown, this application first obtains circuit schematics, design documents, simulation data, historical fault databases, and device manuals at the input layer. Then, it preprocesses the circuit schematics, design documents, simulation data, historical fault databases, and device manuals through a data preprocessing engine to obtain corresponding unified structured data. Based on the unified structured data, a unified cause-effect graph model is constructed. Based on this unified cause-effect graph model, a four-dimensional test generation operation is performed, including design verification testing, boundary testing, fault injection testing, and counterfactual testing, to construct a test case library based on the obtained test cases.

[0240] Figure 9 This is a schematic diagram of the logical architecture of the data preprocessing engine. (Example:) Figure 9 As shown, in this embodiment, a topology parser can parse the circuit schematic to obtain the corresponding topology diagram; a constraint extractor can extract constraints from the design document to obtain the corresponding constraint rules; a feature analyzer can perform feature analysis on the simulation data to obtain the corresponding causal features; a fault extractor can extract causal chains from the historical fault database to obtain the corresponding fault causal chains; and a boundary extractor can perform boundary extraction operations on the device manual to obtain the corresponding operational limits. Furthermore, this application can perform multi-source data fusion on the topology diagram, constraint rules, causal features, fault causal chains, and operational limits to obtain the corresponding unified data structure.

[0241] The input and output data types and processing methods in the multi-source data processing process are shown in Table 3:

[0242] Table 3

[0243]

[0244] It is understandable that unified structured data is the final product of multi-source data fusion. Its essence is to construct a cross-domain knowledge graph, and the design of this data follows the principles below:

[0245] 1. Topology skeleton principle: Use the circuit topology diagram as the basic framework, and use other data as attribute annotations;

[0246] 2. Causal correlation principle: Establish a causal relationship chain between design constraints, physical characteristics, and failure modes;

[0247] 3. Dynamic evolution principle: Supports incremental updates based on subsequent test feedback.

[0248] After obtaining the unified structured data, embodiments of this application can perform data source alignment on the unified structured data to unify the namespace and obtain corresponding standardized data; furthermore, as Figure 10 As shown in the embodiments of this application, multi-dimensional data mounting operations can be performed on standardized data to mount design constraints, simulation features, boundary conditions, and failure modes from the standardized data to the corresponding topology nodes. The specific process is as follows:

[0249] 1. Constraint Mounting:

[0250] (1) Locate the nodes of the constraint target in the topology graph;

[0251] (2) Create a "Design Constraints" property group to store constraint types and numerical ranges;

[0252] (3) Establish the "constraint relationship" edges from the constraint node to the target element.

[0253] 2. Feature fusion:

[0254] (1) Convert simulation features into causal edges: for example, temperature node - thermal effect - MOSFET node;

[0255] (2) Quantitative attributes: sensitivity coefficient (0.0~1.0), confidence level (0.0~1.0).

[0256] 3. Boundary injection:

[0257] (1) Extract the operating limits from the device datasheet;

[0258] (2) Create a "Boundary Conditions" property group that includes electrical / thermal / mechanical limits.

[0259] 4. Failure path integration:

[0260] (1) Convert the causal chain of historical faults from overvoltage to insulation failure to short circuit into a path sequence;

[0261] (2) Add a "failure risk" label to the corresponding node.

[0262] Therefore, the embodiments of this application construct a cause-effect graph model through the above process, and perform multi-dimensional testing and test sequence optimization on the cause-effect graph model based on a multi-dimensional test generation algorithm to establish a corresponding test case library.

[0263] The execution logic of the multidimensional test generation algorithm is as follows: Figure 11 As shown, by Figure 11 As can be seen, the embodiments of this application can perform design verification testing, boundary testing, fault injection testing and counterfactual testing by traversing the cause-effect graph, and optimize the test sequence to build a test case library.

[0264] The execution process of the multidimensional test case generation method of this application will be described below through specific embodiments and in conjunction with the accompanying drawings.

[0265] Specific Implementation Example 1: BBU Charge / Discharge Strategy Verification:

[0266] Test subject: Lithium battery BBU charge and discharge control.

[0267] 1. Data fusion process:

[0268] (1) Topology parser:

[0269] 1) Input the BBU schematic diagram (EDIF format);

[0270] 2) Parse the netlist (recursive descent method);

[0271] 3) Extract the critical path (e.g., "charging IC-MOSFET-cell") and generate the topology skeleton. Nodes include physical components (MOSFET, voltage sensor) and edges record the connection relationships (drive signals, power networks).

[0272] (2) Constraint Extractor:

[0273] 1) Input the design document (PDF);

[0274] 2) Matching rule template (e.g., "Charging voltage range: 18V-36V");

[0275] 3) Generate structured rules:

[0276] { "type": "VOLTAGE_RANGE", "target": "Charging IC", "min": 18, "max": 36,"unit": "V"}.

[0277] (3) Feature analyzer:

[0278] 1) Input cell aging simulation data (CSV);

[0279] 2) Extract the capacity decay model (capacity after 500 cycles = initial value × 0.8);

[0280] 3) Generation sensitivity coefficient: The effect of temperature on internal resistance ( S =0.7).

[0281] (4) Boundary extraction:

[0282] 1) Input device manual;

[0283] 2) Extract the cell's operating limits (pulse discharge rate not greater than 20C).

[0284] 2. Causal modeling:

[0285] Figure 12 A schematic diagram illustrating the causal relationship of charge and discharge control in a lithium battery BBU. (Example) Figure 12 As mentioned above, during the charging process, when the temperature drops, the internal resistance increases, leading to a decrease in charging efficiency; during the discharging process, when the load suddenly increases, the depth of discharge becomes abnormal, resulting in cell damage.

[0286] It should be noted that the key nodes, important edges, weights, and weight calculation process in the causal modeling process are as follows:

[0287] (1) Key nodes:

[0288] 1) Physical nodes: MOSFET_Q1, Cell_Cell1 (including parameters: internal resistance = 5mΩ);

[0289] 2) Constraint node: CONST_Voltage (min=18V, max=36V);

[0290] 3) Supernode: Thermal_Derating (the law of thermal derating governs the change in cell internal resistance).

[0291] (2) Important edges and their weights:

[0292] 1) Causal edge: ambient temperature - [thermal_impact, W=0.8] - cell internal resistance (weights based on simulation confidence);

[0293] 2) Constraint edge: CONST_Voltage-[constrains, W=1.0]-MOSFET_Gate;

[0294] 3) Physically dominating edge: Thermal_Derating -[governs]-cell cluster (global propagation effect).

[0295] (3) Weight calculation:

[0296] .

[0297] 3. Test generation:

[0298] (1) Design verification test: Generate standard scenario test cases (25℃ environment, 20A constant current charging);

[0299] (2) Boundary test: combined limit parameters (-10℃ environment + 20C pulse discharge);

[0300] (3) Fault injection: Simulate BMS (Battery Management System) voltage detection ±5% deviation;

[0301] (4) Counterfactual test generation:

[0302] 1) Target constraint: Sudden load increase shall not exceed 100% of rated value;

[0303] 2) Margin calculation:

[0304] Sensitivity (Temperature - Internal Resistance) + 0.9 × 0.7 (Load - Damage) = 1.03;

[0305] Margin = ≈ 0.21 (α=0.15 for silicon-based materials, k=2.0 for fitting parameters);

[0306] 3) Breakthrough value: Test load = 100% × (1 + 0.21) = 121%;

[0307] 4) Significance of the test: To verify the failure mechanism (such as voltage drop) of 80% of aged cells at the overload critical point and to reveal undocumented safety boundaries;

[0308] 5) Priority rule: Select constraint nodes in descending order of risk coefficient. .

[0309] 4. Verification indicators:

[0310] (1) Charging efficiency not less than 92% (referencing design specifications): by covering the causal path of "charging IC-cell";

[0311] (2) Over-discharge protection response is no more than 10ms: "Voltage detection-shutdown logic" path (weight 0.95) in the cause-effect diagram to verify signal transmission delay.

[0312] Specific Implementation Example 2: Verification of Coordinated Speed ​​Regulation of Fan Array:

[0313] Test subject: Multi-fan speed coordination controlled by PID (Proportional Integration Differentiation) controller.

[0314] 1. Data fusion:

[0315] (1) Topology parser:

[0316] 1) Input the fan drive schematic diagram;

[0317] 2) Extract the PWM (Pulse Width Modulation Controller) and temperature sensor nodes.

[0318] (2) Constraint Extractor:

[0319] 1) Analyze the design document;

[0320] 2) Capture the text constraint “speed fluctuation ≤ 3%”.

[0321] (3) Feature analyzer:

[0322] 1) Input CFD (Computational Fluid Dynamics) airflow simulation;

[0323] 2) Generation dead zone distribution and resonant frequency characteristics (800-1200Hz).

[0324] 2. Causal modeling:

[0325] Figure 13 This is a schematic diagram illustrating the causal relationship during the verification process of coordinated speed regulation of the fan array. (Example:) Figure 13 As shown, the causal relationship in the fan array coordinated speed regulation verification process is as follows: First, when a single fan fails, the vibration intensifies, leading to airflow imbalance, resulting in false temperature alarms, which in turn causes PID overcompensation, and finally leads to bearing wear.

[0326] The key edges and supernodes involved in this causal modeling are as follows:

[0327] (1) Critical edge: Single fan failure - -Bearing wear (weighted based on failure statistics);

[0328] (2) Supernode: (Control controller temperature drift effect).

[0329] 3. Counterfactual test:

[0330] (1) Constraint: The temperature sensor error shall not exceed 1℃;

[0331] (2) Margin calculation: S = 0.85 (temperature drift sensitivity), margin = 0.18, therefore the breakthrough value = 1℃ × 1.18 ≈ 1.2℃;

[0332] (3) Test scenario: simulate sensor failure and main control communication delay to verify the anti-interference capability of PID.

[0333] 4. Verification indicators:

[0334] (1) Temperature control accuracy ±0.8℃: achieved through sensor deviation testing;

[0335] (2) Rotational speed fluctuation is no more than 3% (referencing JEDEC JESD94 standard): Cause-effect diagram covers the vibration transmission path to ensure this.

[0336] Example 3: Verification of fan speed regulation in high-temperature environments:

[0337] Test subject: Temperature-speed curve adaptive adjustment circuit.

[0338] 1. Data fusion:

[0339] (1) Import the thermal expansion coefficient of the material (fan clearance change), integrate the lubrication characteristics of high temperature bearings, and combine the PID parameter temperature drift model;

[0340] (2) Feature Analyzer: Input the high-temperature lubrication data of the bearing and construct a thermal expansion model (the clearance change rate is 0.05 μm / ℃).

[0341] (3) Boundary extraction: The upper limit of bearing temperature in the device manual is 120℃.

[0342] 2. Causal modeling:

[0343] Figure 14 This is a schematic diagram illustrating the causal relationship during the verification process of fan speed regulation in a high-temperature environment. (Example:) Figure 14 As shown, the causal relationship in the high-temperature environment fan speed regulation verification process is as follows: when the ambient temperature rises, the bearing resistance increases, and at the same time, the controller temperature drifts, causing PID misalignment; due to the increased bearing resistance and PID misalignment, the speed decreases, ultimately leading to insufficient cooling.

[0344] 3. Test generation:

[0345] (1) Boundary test: Full load operation in a 65℃ environment;

[0346] (2) Counterfactual test:

[0347] 1) Target constraint: Bearing temperature not exceeding 120℃ (upper limit in the device manual);

[0348] 2) Margin calculation: S=0.85, margin calculated by formula ≈0.15;

[0349] 3) Derivation of the breakthrough value: Test temperature = constraint value × (1 + margin) = 120℃ × (1 + 0.15) = 138℃;

[0350] 4) Constraint value: The temperature is 120℃, the margin can be calculated as 0.15, and then the breakthrough value is 138℃, which finally verifies the critical point of bearing material failure.

[0351] (3) Fault injection: Inject ±20% deviation into the speed feedback line.

[0352] 4. Verification indicators:

[0353] (1) The high temperature speed maintenance rate is not less than 98%, which is facilitated by the boundary test coverage of the path from "temperature drift model" to "PID output" in the cause-effect diagram.

[0354] (2) Control accuracy: ±50RPM at 65℃.

[0355] In summary, this application embodiment constructs a topological skeleton containing component nodes and their connecting edges by parsing the circuit schematic netlist; it parses the natural language description in the design constraint document, extracts design constraint rules through rule template matching and converts them into structured machine-executable rules, creates virtual constraint nodes and associates them with target component nodes; it analyzes simulation report data, extracts causal feature relationships between parameters (such as sensitivity, thermal coupling, and timing), and maps these feature relationships to causal edges and attributes between source nodes and target nodes in the topological skeleton; it extracts operational limit parameters from the device manual and attaches them as boundary condition attributes to the corresponding component nodes; and it aligns component identifiers from different data sources based on preset naming standardization rules to construct a unified causal graph model containing the topological skeleton, virtual constraint nodes, causal edges and attributes, and boundary condition attributes.

[0356] It is understood that the core of causal-driven testing in this application lies in constructing an explicit causal graph model that integrates physical connections, design intent, physical laws, and failure knowledge. This model serves as the sole or primary basis and engine for driving the automatic generation, optimization, and interpretation of subsequent multi-dimensional test cases. This technique differs from traditional testing methods based on coverage criteria (such as code coverage or functional coverage) or random input generation, as well as from simple analysis that relies solely on a single data source (such as pure netlists or pure simulation data). This allows for a deeper understanding of the intrinsic mechanisms of system behavior, thereby generating a more comprehensive (covering both explicit and implicit relationships), more efficient (focusing on key causal chains), and more insightful (especially counterfactual testing) verification scheme.

[0357] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0358] Embodiments of this application also provide a multidimensional test case generation apparatus.

[0359] like Figure 15 As shown, the multidimensional test case generation device 10 includes: a data standardization module 100, a cause-effect graph construction module 200, and a test sequence generation module 300.

[0360] The data standardization module 100 is used to acquire the original multi-source data corresponding to the target electronic system and convert the original multi-source data into the corresponding standardized data. The standardized data includes at least one of the following: topology diagram, constraint rules, causal relationships, boundary condition dictionary, and fault path list.

[0361] The causal graph construction module 200 is used to construct the topological skeleton corresponding to the target electronic system based on the topological graph, convert the constraint rules into virtual constraint nodes, construct the causal edges and node attributes corresponding to the topological skeleton according to the causal relationship and boundary condition dictionary, and calculate the edge weights corresponding to the causal edges, so as to establish a unified causal graph model corresponding to the target electronic system based on the topological skeleton, virtual constraint nodes, causal edges, node attributes and edge weights.

[0362] The test sequence generation module 300 is used to perform multi-dimensional testing using a unified cause-effect graph model to generate multiple test case sets, determine the resource consumption data and at least one ranking index corresponding to the multiple test case sets, sort the multiple test case sets according to the at least one ranking index, and group the sorted multiple test case sets using the resource consumption data to generate the final test sequence of the target electronic system.

[0363] Optionally, in one embodiment of this application, the data standardization module 100 includes a preprocessing unit and a data alignment unit.

[0364] The preprocessing unit is used to acquire the original multi-source data corresponding to the target electronic system, perform data preprocessing operations on the original multi-source data to obtain the corresponding preprocessed data, and perform data fusion operations on the preprocessed data to generate unified structured data.

[0365] The data alignment unit is used to align unified structured data, transforming raw multi-source data into a unified namespace and generating corresponding standardized data.

[0366] Optionally, in one embodiment of this application, the preprocessing unit includes: an acquisition subunit, a parsing subunit, and a matching subunit.

[0367] The acquisition subunit is used to acquire the original multi-source data corresponding to the target electronic system. The original multi-source data includes circuit schematics, design documents, simulation data, historical fault databases, and component manuals.

[0368] The parsing sub-unit is used to parse the netlist data in the electronic design exchange format of the circuit schematic to extract the corresponding component identifiers. Based on the component identifiers, signal flow analysis is performed on the circuit schematic to calculate the path weights of the circuit schematic. The corresponding critical paths are marked according to the path weights to generate a topology graph through the critical paths.

[0369] The matching subunit is used to preprocess the design document text and perform regular expression matching on the preprocessed design document based on a preset rule template library to obtain the corresponding matching results, and then convert the matching results into constraint rules.

[0370] Optionally, in one embodiment of this application, the preprocessing unit further includes: a data cleaning subunit, a mapping subunit, and an extraction subunit.

[0371] The data cleaning subunit is used to clean the simulation data to obtain the corresponding standard data, calculate the correlation coefficient matrix corresponding to the standard data, and perform thermal effect modeling based on the standard data to construct the corresponding temperature-parameter response model.

[0372] The mapping subunit is used to calculate the corresponding time margin based on standard data, so as to determine the corresponding time relationship through the time margin, and map the correlation coefficient matrix, temperature-parameter response model and time relationship into causal relationship.

[0373] The extraction sub-unit is used to perform causal chain extraction operations on the historical fault database to obtain a fault path list, and to perform boundary extraction operations on the device manual to obtain a boundary condition dictionary.

[0374] Optionally, in one embodiment of this application, the data alignment unit includes: a construction subunit and a judgment subunit.

[0375] The sub-unit is used to standardize the original name of each data in the original multi-source data to obtain the corresponding standard name, and to build a mapping table between the original name and the standard name.

[0376] The judgment sub-unit is used to determine whether there is a name conflict among all standard names based on the mapping relationship table. If there is a name conflict among all standard names, different weights are set for the data with name conflicts based on a preset confidence voting strategy to obtain standardized data.

[0377] Optionally, in one embodiment of this application, the cause-effect graph construction module 200 includes: a node determination unit, a transformation unit, and a skeleton determination unit.

[0378] The node determination unit is used to parse the electronic components in the netlist data of the circuit schematic to obtain the corresponding parsed data, and to determine the entity nodes corresponding to the electronic components based on the parsed data.

[0379] The transformation unit is used to extract electrical connections from the netlist data and convert the electrical connections into corresponding causal edges.

[0380] The skeleton determination unit is used to construct an initial directed graph based on causal edges and the entity nodes corresponding to electronic components, and to determine the topological skeleton through the initial directed graph.

[0381] Optionally, in one embodiment of this application, the causal graph construction module 200 further includes: a first computing unit and a second computing unit.

[0382] The first calculation unit is used to extract the number of failures and the total number of uses of the target component from the preset enterprise fault database, and calculate the corresponding risk coefficient based on the number of failures, the total number of uses and the preset failure severity level.

[0383] The second calculation unit is used to determine the number of Monte Carlo simulations corresponding to the target electronic system, and to determine the corresponding confidence level based on the number of Monte Carlo simulations, so as to calculate the edge weights based on the risk coefficient and the confidence level.

[0384] Optionally, in one embodiment of this application, the test sequence generation module 300 includes: an identification unit, a boundary test unit, and a fault injection test unit.

[0385] The identification unit is used to identify key signal paths in the unified cause-effect graph model and generate input-output verification data under standard operating conditions based on the key signal paths. The input-output verification data is used to perform design verification testing and output a set of design verification test cases that meet the preset verification function requirements.

[0386] The boundary test unit is used to extract the limit values ​​of virtual constraint nodes in the unified cause-effect graph model, and perform boundary test operations based on the limit values ​​to obtain a boundary test case set.

[0387] The fault injection test unit is used to inject defect information into the unified cause-effect graph model through the historical fault database, so as to perform fault injection testing on the unified cause-effect graph model and generate a fault injection test case set.

[0388] Optionally, in one embodiment of this application, the identification unit includes: a modeling subunit, a training subunit, an injection subunit, and an alignment analysis subunit.

[0389] The modeling subunit is used to construct a digital twin dynamic mapping model based on the main path of the unified causal graph model. It also uses the digital twin dynamic mapping model to synchronize the physical parameters and virtual simulation parameters of the key signal path in real time. The physical parameters include signal transmission delay and logic unit temperature drift coefficient, while the virtual simulation parameters include path node state variables and signal attenuation model.

[0390] The training subunit is used to train the digital twin dynamic mapping model based on a preset reinforcement learning algorithm, using the input-output verification results under standard working conditions as the reward function, and to generate a test sequence generation strategy that adapts to the drift of key signal path parameters.

[0391] The injection subunit is used to inject multi-dimensional perturbation factors into the identified key signal paths according to the test sequence generation strategy, so as to generate an extended test sequence containing perturbation response verification.

[0392] The comparison analysis subunit is used to perform virtual-real comparison analysis on the extended test sequence through the digital twin dynamic mapping model, so as to output a set of design verification test cases that meet the preset verification function requirements.

[0393] Optionally, in one embodiment of this application, the boundary testing unit includes: a semantic annotation subunit and an extended verification subunit.

[0394] The semantic annotation subunit is used to semantically annotate the limit values ​​of virtual constraint nodes based on a pre-built parameter association knowledge graph, so as to obtain multiple parameters with semantic information, and obtain the implicit constraint relationship between multiple parameters through a pre-set graph neural network.

[0395] The extended verification subunit is used to generate boundary combination samples based on parameter association knowledge graphs and implicit constraint relationships, and to perform extended verification on the boundary combination samples to obtain a boundary test case set.

[0396] Optionally, in one embodiment of this application, the test sequence generation module 300 further includes: an incoming edge extraction unit, a third calculation unit, a fitting unit, and a breakthrough value calculation unit.

[0397] The incoming edge extraction unit is used to determine the target constraint node in the unified causal graph model and extract all thermally relevant incoming edges of the target constraint node.

[0398] The third calculation unit is used to determine the edge weights and direct sensitivities of all thermally related incoming edges, and to calculate the thermal sensitivities of all thermally related incoming edges based on the edge weights and direct sensitivities.

[0399] The fitting unit is used to fit historical fault data in the historical fault database to obtain the corresponding sensitivity attenuation coefficient. Based on the preset maximum tolerance coefficient of the material and the basic safety offset, and combined with the sensitivity attenuation coefficient and thermal sensitivity, the safety margin of all thermally related incoming edges is calculated.

[0400] The breakthrough value calculation unit is used to calculate the breakthrough value corresponding to all thermally relevant incoming edges based on the safety margin, so as to construct a counterfactual test case set based on the breakthrough value.

[0401] Optionally, in one embodiment of this application, the test sequence generation module 300 further includes a sorting unit and a grouping unit.

[0402] The sorting unit is used to determine the edge weight and component failure rate of each test case set in the multi-type test case set, and sort the multi-type test case sets according to the edge weight and component failure rate to generate the corresponding executable test sequence.

[0403] The grouping unit is used to determine the resource consumption data for each type of test case set, and to group the executable test sequences according to the resource consumption data to obtain the final test sequence.

[0404] For a description of the features in the embodiment corresponding to the multidimensional test case generation device, please refer to the relevant description of the embodiment corresponding to the multidimensional test case generation method, which will not be repeated here.

[0405] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above embodiments of the multidimensional test case generation method.

[0406] Embodiments of this application also provide a non-volatile computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the multidimensional test case generation method at runtime.

[0407] In one exemplary embodiment, the aforementioned non-volatile computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0408] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the multidimensional test case generation method.

[0409] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the multidimensional test case generation method.

[0410] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0411] The foregoing has provided a detailed description of the multidimensional test case generation method, apparatus, device, and medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for generating multidimensional test cases, characterized in that, Includes the following steps: Obtain the original multi-source data corresponding to the target electronic system, and convert the original multi-source data into corresponding standardized data, wherein the standardized data includes at least one of the following: topology graph, constraint rules, causal relationships, boundary condition dictionary, and fault path list; Based on the topology graph, a topological skeleton corresponding to the target electronic system is constructed, and the constraint rules are converted into virtual constraint nodes. Causal edges and node attributes corresponding to the topological skeleton are constructed according to the causal relationship and the boundary condition dictionary, and the edge weights corresponding to the causal edges are calculated. A unified causal graph model corresponding to the target electronic system is established based on the topological skeleton, the virtual constraint nodes, the causal edges, the node attributes, and the edge weights. Multi-dimensional testing is performed using the unified cause-effect graph model to generate multiple test case sets. Resource consumption data and at least one ranking index corresponding to the multiple test case sets are determined to rank the multiple test case sets according to the at least one ranking index. Test case groups are then performed on the ranked multiple test case sets using the resource consumption data to generate the final test sequence of the target electronic system. The step of constructing the topological skeleton corresponding to the target electronic system based on the topological graph includes: The electronic components in the netlist data of the circuit schematic are analyzed to obtain the corresponding analytical data, and the entity nodes corresponding to the electronic components are determined based on the analytical data. Extract the electrical connections from the netlist data and convert the electrical connections into corresponding causal edges; Based on the causal edges and the entity nodes corresponding to the electronic components, an initial directed graph is constructed, and the topological skeleton is determined through the initial directed graph; The step of converting the constraint rules into virtual constraint nodes, constructing causal edges and node attributes corresponding to the topological skeleton based on the causal relationships and the boundary condition dictionary, and calculating the edge weights corresponding to the causal edges, to establish a unified causal graph model corresponding to the target electronic system based on the topological skeleton, the virtual constraint nodes, the causal edges, the node attributes, and the edge weights, includes: Extract the number of failures of the target component and the total number of uses of the target component from the preset enterprise fault database, and calculate the corresponding risk coefficient based on the number of failures, the total number of uses and the preset failure severity level; The number of Monte Carlo simulations corresponding to the target electronic system is determined, and the corresponding confidence level is determined by the number of Monte Carlo simulations. The edge weights are then calculated based on the risk coefficient and the confidence level.

2. The multidimensional test case generation method according to claim 1, characterized in that, The process of acquiring the raw multi-source data corresponding to the target electronic system and converting the raw multi-source data into corresponding standardized data includes: The original multi-source data corresponding to the target electronic system is acquired, and the original multi-source data is preprocessed to obtain the corresponding preprocessed data. The preprocessed data is then fused to generate unified structured data. Data alignment is performed on the unified structured data to transform the original multi-source data into a unified namespace and generate corresponding standardized data.

3. The multidimensional test case generation method according to claim 2, characterized in that, The process of acquiring the original multi-source data corresponding to the target electronic system, performing data preprocessing on the original multi-source data to obtain corresponding preprocessed data, and performing data fusion on the preprocessed data to generate unified structured data includes: Obtain the original multi-source data corresponding to the target electronic system, wherein the original multi-source data includes circuit schematics, design documents, simulation data, historical fault databases, and component manuals; The netlist data in the electronic design exchange format of the circuit schematic is parsed to extract the corresponding component identifiers. Based on the component identifiers, signal flow analysis is performed on the circuit schematic to calculate the path weights of the circuit schematic. The corresponding critical paths are marked according to the path weights to generate the topology graph through the critical paths. The design document is preprocessed with text, and based on a preset rule template library, a regular expression matching operation is performed on the preprocessed design document to obtain the corresponding matching results, and the matching results are converted into the constraint rules.

4. The multidimensional test case generation method according to claim 3, characterized in that, The step of acquiring the original multi-source data corresponding to the target electronic system, performing data preprocessing operations on the original multi-source data to obtain corresponding preprocessed data, and performing data fusion operations on the preprocessed data to generate unified structured data further includes: The simulation data is cleaned to obtain corresponding standard data, and the correlation coefficient matrix corresponding to the standard data is calculated. Thermal effect modeling is performed based on the standard data to construct the corresponding temperature-parameter response model. The corresponding time margin is calculated based on the standard data, and the corresponding time relationship is determined through the time margin. The correlation coefficient matrix, the temperature-parameter response model and the time relationship are then mapped to the causal relationship. A causal chain extraction operation is performed on the historical fault database to obtain the fault path list, and a boundary extraction operation is performed on the device manual to obtain the boundary condition dictionary.

5. The multidimensional test case generation method according to claim 2, characterized in that, The step of aligning the unified structured data to transform the original multi-source data into a unified namespace and generate corresponding standardized data includes: The original names of each data in the original multi-source data are standardized to obtain corresponding standard names, and a mapping table between the original names and the standard names is constructed. The mapping table is used to determine whether there are name conflicts among all standard names. If there are name conflicts among all standard names, a preset confidence voting strategy is used to assign different weights to the data with name conflicts in order to obtain the standardized data.

6. The multidimensional test case generation method according to claim 1, characterized in that, The method of using the unified cause-effect graph model for multi-dimensional testing to generate multiple test case sets includes: Identify the key signal paths in the unified cause-effect graph model, and generate input-output verification data under standard operating conditions based on the key signal paths, so as to perform design verification testing through the input-output verification data, and output a set of design verification test cases that meet the preset verification function requirements; Extract the limit values ​​of the virtual constraint nodes in the unified cause-effect graph model, and perform boundary testing operations based on the limit values ​​to obtain a boundary test case set; Defect information is injected into the unified cause-effect graph model by injecting it into the historical fault database to perform fault injection testing on the unified cause-effect graph model and generate a fault injection test case set.

7. The multidimensional test case generation method according to claim 6, characterized in that, The process of identifying key signal paths in the unified cause-effect graph model and generating input-output verification data under standard operating conditions based on these key signal paths, followed by design verification testing using this data, and outputting a set of design verification test cases that meet preset verification function requirements, includes: Based on the main path of the unified cause-effect graph model, a digital twin dynamic mapping model is constructed, and the physical parameters and virtual simulation parameters of the key signal path are synchronized in real time through the digital twin dynamic mapping model. The physical parameters include signal transmission delay and logic unit temperature drift coefficient, and the virtual simulation parameters include path node state variables and signal attenuation model. Based on a preset reinforcement learning algorithm, the digital twin dynamic mapping model is trained, and the input-output verification results under the standard working conditions are used as the reward function to generate an adaptive test sequence generation strategy for key signal path parameter drift. According to the test sequence generation strategy, multi-dimensional perturbation factors are injected into the identified key signal paths to generate extended test sequences that include perturbation response verification. The extended test sequence is analyzed by comparing the virtual and real data using the digital twin dynamic mapping model to output a set of design verification test cases that meet the preset verification function requirements.

8. The multidimensional test case generation method according to claim 6, characterized in that, The step of extracting the limit values ​​of the virtual constraint nodes in the unified cause-effect graph model and performing boundary testing operations based on the limit values ​​to obtain a boundary test case set includes: Based on a pre-built parameter association knowledge graph, the limit values ​​of the virtual constraint nodes are semantically labeled to obtain multiple parameters with semantic information, and the implicit constraint relationships between the multiple parameters are obtained through a pre-set graph neural network. Based on the parameter association knowledge graph and the implicit constraint relationship, an adaptive particle swarm optimization algorithm is used to generate boundary combination samples, and the boundary combination samples are expanded and verified to obtain the boundary test case set.

9. The multidimensional test case generation method according to claim 6, characterized in that, The method of using the unified cause-effect graph model for multi-dimensional testing to generate multiple test case sets also includes: Identify the target constraint node in the unified cause-effect graph model and extract all hot-related incoming edges of the target constraint node; Determine the edge weights and direct sensitivity of all thermally related incoming edges, and calculate the thermal sensitivity of all thermally related incoming edges based on the edge weights and direct sensitivity; Fit historical fault data in the historical fault database to obtain the corresponding sensitivity attenuation coefficient, and calculate the safety margin of all thermally related incoming edges based on the preset maximum material tolerance coefficient and basic safety offset, and in combination with the sensitivity attenuation coefficient and the thermal sensitivity. Based on the safety margin, the breach value corresponding to all thermally relevant incoming edges is calculated, and a counterfactual test case set is constructed based on the breach value.

10. The multidimensional test case generation method according to claim 1, characterized in that, The step of determining resource consumption data and at least one ranking index corresponding to multiple test case sets, ranking the multiple test case sets according to the at least one ranking index, and grouping test cases into test cases using the resource consumption data to generate the final test sequence of the target electronic system includes: The edge weights and component failure rates of each test case set in the multi-type test case set are determined, and the multi-type test case sets are sorted according to the edge weights and component failure rates respectively to generate corresponding executable test sequences. The resource consumption data for each type of test case set is determined, and the executable test sequence is grouped by resource based on the resource consumption data to obtain the final test sequence.

11. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the multidimensional test case generation method as described in any one of claims 1 to 10 when executing the computer program.

12. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the multidimensional test case generation method as described in any one of claims 1 to 10.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the multidimensional test case generation method as described in any one of claims 1 to 10.

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