Adapter board

Abstract

This application discloses an adapter board, relating to the field of computer technology. The adapter board includes: a first connector for connecting to two device-side connectors of a storage device, the device-side connectors being used to transmit dual-channel communication signals; a second connector for connecting to a hard drive-side connector of a solid-state drive (SSD), the hard drive-side connector being used to transmit four-channel communication signals; and a conversion module including a circuit system, an endpoint subsystem, and a root complex subsystem, the endpoint subsystem being connected to the first connector, and the root complex subsystem being connected to the second connector; wherein, the conversion module is used to convert the two dual-channel communication signals input from the two device-side connectors to the first connector into one four-channel communication signal, and transmit the four-channel communication signal to the hard drive-side connector via the second connector. A single-port SSD can be adaptively used in a storage device using this adapter board.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly to an adapter board. Background Technology

[0002] Compared to hard disk drives (HDDs), solid-state drives (SSDs) offer significant advantages in read / write speeds, power consumption, capacity, noise, and reliability. With continuous advancements in the manufacturing processes and layering of storage media, capacity density has increased, leading to larger individual SSD capacities and lower prices. This has resulted in the widespread adoption of SSDs in servers and storage devices. Among these, PCIe SSDs, based on the Peripheral Component Interconnect Express (PCIe) standard, offer significant advantages in bandwidth and latency, and their market share is steadily rising.

[0003] Typically, PCIe SSDs operate in single-port mode, with four lanes in the SSD PCIe link connecting to a central processing unit (CPU). However, single-port SSDs cannot be used properly in storage devices.

[0004] How to properly use a single-port SSD on a storage device is one of the technical problems that urgently need to be solved in this field. Summary of the Invention

[0005] This application provides an adapter board to at least solve the problem in the related art that single-port mode solid-state drives cannot be used normally on storage devices.

[0006] This application provides an adapter board, including:

[0007] The first connector connects to two device-end connectors of the storage device, the device-end connectors being used to transmit dual-channel communication signals;

[0008] The second connector connects to the hard drive end connector of the solid-state drive, which is used to transmit four-channel communication signals.

[0009] The conversion module includes a circuit system, an endpoint subsystem, and a root complex subsystem, wherein the endpoint subsystem is connected to the first connector, and the root complex subsystem is connected to the second connector.

[0010] The conversion module is used to convert the two dual-channel communication signals input from the two device-end connectors to the first connector into a single four-channel communication signal, and then transmit the single four-channel communication signal to the hard disk connector through the second connector.

[0011] This application includes a first connector, a second connector, and a conversion module. By utilizing the circuit system, endpoint subsystem, and root complex subsystem of the conversion module, two dual-channel communication signals from the storage device are converted into one four-channel communication signal and transmitted to the solid-state drive. The single-port mode solid-state drive can be used adaptively in the storage device through this adapter board. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A schematic diagram illustrating the connection between the adapter board and the solid-state drive and storage device provided in an embodiment of this application;

[0014] Figure 2 This is one of the structural schematic diagrams of the adapter board provided in the embodiments of this application;

[0015] Figure 3 This is the second schematic diagram of the structure of the adapter plate provided in the embodiments of this application;

[0016] Figure 4 This is the third schematic diagram of the adapter board provided in the embodiments of this application.

[0017] Figure label:

[0018] First connector 100, first main power supply pin 110, first auxiliary power supply pin 120, first communication pin 130, first clock pin 140, first reset pin 150, first serial communication interface 160, first general purpose input / output interface 170, first interface detection pin 180, first presence detection pin 190.

[0019] Second connector 200, second main power supply pin 210, second auxiliary power supply pin 220, fourth communication pin 230, fourth clock pin 240, fourth reset pin 250, second serial communication interface 260, second general purpose input / output interface 270, second interface detection pin 280, second presence detection pin 290.

[0020] The system includes a conversion module 300, a power supply module 310, a first step-down circuit 311, a second step-down circuit 312, a third step-down circuit 313, a power redundancy switch 320, an external storage device 330, a firmware storage unit 340, and a debugging device 350.

[0021] Power interface 301, external reset pin 302, third serial communication interface 303, third general purpose input / output interface 304, debug interface 305, firmware interface 306, clock bus interface 307, external clock input pin 308.

[0022] Endpoint subsystem 360, second communication pin 361, second clock pin 362, second reset pin 363.

[0023] Root complex subsystem 370, third communication pin 371, third clock pin 372, third reset pin 373, fourth general purpose input / output interface 374.

[0024] Clock generator 380, first status indication interface 391, first status indicator light 392, second status indication interface 393, second status indicator light 394.

[0025] Storage device 400, device-side connector 410, device-side central processing unit 420

[0026] Solid-state drive 500, hard drive connector 510. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0028] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0029] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Solid State Disks (SSDs) based on the Peripheral Component Interconnectexpress (PCIe) standard typically operate in single-port mode. The PCIe link of an SSD connects four lanes to a central processing unit, and it can be used in server products.

[0031] The storage device has two device-side CPUs. The four lanes in the PCIe link are split into two paths: two lanes connect to one device-side CPU, and the other two lanes connect to the other device-side CPU. Therefore, a single-port SSD cannot be used properly in the storage device.

[0032] How to properly use a single-port SSD on a storage device is one of the technical problems that urgently need to be solved in this field.

[0033] This application provides an adapter board that connects between a storage device 400 and a solid-state drive 500, enabling the storage device 400 to use the solid-state drive 500 in single-port mode.

[0034] like Figure 1 As shown, the adapter board includes: a first connector 100, a second connector 200, and a conversion module 300.

[0035] The first connector 100 is connected to two device-end connectors 410 of the storage device 400, and the device-end connectors 410 are used to transmit dual-channel communication signals.

[0036] The communication signal transmitted by the storage device 400 is divided into two paths: one device-side connector 410 transmits one dual-channel communication signal, and the other device-side connector 410 transmits another dual-channel communication signal.

[0037] For example, storage device 400 has two device-side central processing units 420. The four lanes in the PCIe link are divided into two paths. The communication signals of two lanes are transmitted through one device-side connector 410, and the communication signals of the other two lanes are transmitted through another device-side connector 410. That is, storage device 400 transmits two PCIe×2 signals through the two device-side connectors 410 respectively, and one device-side connector 410 transmits one PCIe×2 signal.

[0038] The first connector 100 is connected to two device-side connectors 410 of the storage device 400. The device-side connectors 410 can be female connectors of the U.2 interface standard, and the first connector 100 can be male connectors of the U.2 interface standard. Two PCIe×2 signals are transmitted between the first connector 100 and the two device-side connectors 410.

[0039] The second connector 200 is connected to the hard drive end connector 510 of the solid-state drive 500, which is used to transmit four-channel communication signals.

[0040] For example, the solid-state drive 500 supports single-port mode, and the hard drive connector 510 transmits four channels of communication signals, that is, the hard drive connector 510 transmits one PCIe×4 signal.

[0041] The second connector 200 is connected to the hard drive end connector 510 of the solid-state drive 500. The second connector 200 can be a female connector with a U.2 interface standard, and the hard drive end connector 510 can be a male connector with a U.2 interface standard. One PCIe×4 signal is transmitted between the second connector 200 and the hard drive end connector 510.

[0042] The conversion module 300 includes a circuit system, an endpoint subsystem 360, and a root composite subsystem 370. The endpoint subsystem 360 is connected to the first connector 100, and the root composite subsystem 370 is connected to the second connector 200.

[0043] It is understandable that the circuit system refers to the most basic hardware and software configuration that enables the conversion module 300 to start and run normally, that is, the minimum system that constitutes the conversion module 300.

[0044] In this embodiment, the conversion module 300 is used to convert the two dual-channel communication signals input from the two device-end connectors 410 to the first connector 100 into a single four-channel communication signal, and transmit the single four-channel communication signal to the hard disk-end connector 510 through the second connector 200.

[0045] For example, the conversion module 300 is used to convert two PCIe×2 signals from the storage device 400 into one PCIe×4 signal, and transmit the PCIe×4 signal to the solid-state drive 500, so that the storage device 400 can use the solid-state drive 500 in single-port mode normally.

[0046] It should be noted that the endpoint subsystem 360 is connected to the first connector 100 and is used to receive and process the two dual-channel communication signals transmitted by the first connector 100. The root complex subsystem 370 is connected to the second connector 200 and is used to generate a four-channel communication signal based on the two dual-channel communication signals and transmit the four-channel communication signal to the second connector 200.

[0047] The following is a specific example.

[0048] The SSD 500 has one external PCIe interface that supports single-port mode. The external PCIe interface supports 4 lanes, corresponding to 4 sets of PCIe transmit signals (TX) and receive signals (RX), 1 set of reset signals (RSTn), and 1 set of reference clock signals (REFCLK). The SSD 500 adopts the PCIe 3.0 interface standard, and is referred to as PCIe 3.0 × 4 single-port SSD.

[0049] It should be noted that the PCIe 3.0 interface standard is only an example, and the adapter board in this application embodiment is also applicable to the PCIe 4.0 interface standard, PCIe 5.0 interface standard, PCIe 6.0 interface standard, etc.

[0050] In server product systems, the solid-state drive 500 can be used directly. In storage product systems, the solid-state drive 500 and storage device 400 are connected via an adapter board.

[0051] The adapter board includes a first connector 100, a second connector 200, and a conversion module 300. Utilizing the circuit system, endpoint subsystem 360, and root complex subsystem 370 of the conversion module 300, two PCIe×2 signals from the storage device 400 are converted into one PCIe×4 signal, enabling the application of a PCIe 3.0×4 single-port SSD on the storage device 400. The device-side central processing unit 420 of the storage device 400 can perform read and write operations on the single-port solid-state drive 500 through the adapter board, compensating for the functional deficiencies of single-port SSDs and helping to improve the overall competitiveness of single-port SSDs.

[0052] The adapter board provided according to the embodiments of this application includes a first connector 100, a second connector 200, and a conversion module 300. The conversion module 300 uses its circuit system, endpoint subsystem 360, and root complex subsystem 370 to convert two dual-channel communication signals from the storage device 400 into one four-channel communication signal and transmit it to the solid-state drive 500. The single-port mode solid-state drive 500 can be adaptively used in the storage device 400 through this adapter board.

[0053] In some embodiments, the circuit system includes a power supply module 310, a clock input circuit, a reset circuit, a debug interface 305, and a firmware storage unit 340.

[0054] The debugging interface 305 is used for developing and testing the adapter board. The debugging interface 305 can be connected to the debugging device 350 to provide debugging functions for the adapter board.

[0055] In actual implementation, the debugging interface 305 can be a hardware interface such as the Joint Test Action Group (JTAG) interface or the Universal Asynchronous Receiver-Transmitter (UART) interface, which can be connected to an external debugging device 350 to provide online debugging and serial port debugging functions for the adapter board.

[0056] The clock input circuit is used to receive and process clock signals.

[0057] In actual implementation, an external 25 MHz crystal or crystal oscillator can be connected to the clock input circuit, that is, connected to the crystal oscillator input or external clock input pin 308 of the conversion module 300, to provide the working system clock of the adapter board and the clock of the external hardware unit.

[0058] In this embodiment, such as Figure 2 As shown, the conversion module 300 is provided with a firmware interface 306, which is connected to an external firmware storage unit 340.

[0059] In actual implementation, firmware interface 306 can be a synchronous serial communication interface (SPI), and firmware storage unit 340 can be a flash memory (NOR Flash). The capacity of firmware storage unit 340 depends on the requirements, such as 32 megabits (Mb), 64Mb, 128Mb, etc.

[0060] In this embodiment, the firmware storage unit 340 is used to store system firmware, which is used to configure the port operating modes of the endpoint subsystem 360 and the root complex subsystem 370.

[0061] For example, endpoint subsystem 360 supports one PCIe 3.0 x8 port operating mode and two PCIe 3.0 x4 port operating modes. Endpoint subsystem 360 needs to convert two PCIe 3.0 x2 signals from storage device 400 into one PCIe 3.0 x4 signal. Endpoint subsystem 360 is configured to operate in two PCIe 3.0 x4 port operating modes. The port operating mode operated by endpoint subsystem 360 is implemented by the firmware of firmware storage unit 340.

[0062] For example, the root complex subsystem 370 supports a two-port PCIe 3.0 x4 mode, a port mode with one PCIe 3.0 x4 port plus two PCIe 3.0 x2 ports, a port mode with two PCIe 3.0 x2 ports plus one PCIe 3.0 x4 port, and a port mode with four PCIe 3.0 x2 ports.

[0063] In this embodiment, the root complex subsystem 370 is connected to the hard disk connector 510 via the second connector 200, requiring the transmission of one PCIe 3.0×4 signal. The root complex subsystem 370 can be configured to operate in a port mode with two PCIe 3.0×4 ports or in a port mode with one PCIe 3.0×4 port plus two PCIe 3.0×2 ports. The root complex subsystem 370 can also be configured to operate in a port mode with two PCIe 3.0×2 ports plus one PCIe 3.0×4 port. The port operating mode operated by the root complex subsystem 370 is implemented by the firmware of the firmware storage unit 340.

[0064] Understandably, in the circuit system of the conversion module 300, the power supply module 310 is the module in the adapter board that implements the power supply function, and the reset circuit is the circuit that generates and manages the reset signal, which is used to initialize the adapter board.

[0065] In some embodiments, the power module 310 includes a first step-down circuit 311, a second step-down circuit 312, and a third step-down circuit 313.

[0066] like Figure 3 As shown, the input terminal of the first step-down circuit 311 is connected to the first main power supply pin 110 of the first connector 100, the output terminal of the first step-down circuit 311 is connected to the input terminal of the second step-down circuit 312, and the input terminal of the third step-down circuit 313 is connected to the first main power supply pin 110.

[0067] In this embodiment, the first step-down circuit 311 is used to convert the first power supply voltage provided by the first main power supply pin 110 into a second power supply voltage and output the second power supply voltage to the second step-down circuit 312. The second step-down circuit 312 is used to convert the second power supply voltage into a third power supply voltage to power the conversion module 300. The third step-down circuit 313 is used to convert the first power supply voltage into a fourth power supply voltage to power the conversion module 300. The fourth power supply voltage is less than the third power supply voltage.

[0068] It is understood that the first step-down circuit 311, the second step-down circuit 312, and the third step-down circuit 313 can be DC / DC step-down circuits.

[0069] Taking the first main power supply pin 110 as an example, which provides a power supply voltage of 12 volts (V).

[0070] The first main power supply pin 110 provides a first power supply voltage of 12V, and the first step-down circuit 311 converts the first power supply voltage of 12V provided by the first main power supply pin 110 into a second power supply voltage of 3.3V.

[0071] The second power supply voltage of 3.3V is used as the input of the second step-down circuit 312. The output of the second step-down circuit 312 is connected to the power interface 301 of the conversion module 300. The second step-down circuit 312 converts the second power supply voltage of 3.3V into the third power supply voltage of 1.8V to power the conversion module 300.

[0072] The first main power supply pin 110 provides a first power supply voltage of 12V and also serves as the input of the third step-down circuit 313. The output of the third step-down circuit 313 is connected to the power interface 301 of the conversion module 300. The third step-down circuit 313 converts the first power supply voltage of 12V into a fourth power supply voltage of 0.9V to power the conversion module 300.

[0073] In some embodiments, the first step-down circuit 311 is further configured to output a power status signal to the second step-down circuit 312 to generate an enable signal for the second step-down circuit 312; the second step-down circuit 312 is further configured to output a power status signal to the third step-down circuit 313 to generate an enable signal for the third step-down circuit 313.

[0074] The Power Status signal (Power Good, PG) is used to indicate whether the power supply is stable, while the enable signal is used to start and stop the buck circuit.

[0075] In this embodiment, while the first step-down circuit 311 outputs the second power supply voltage to the second step-down circuit 312, it also outputs the power status signal corresponding to the first step-down circuit 311 to generate an enable signal for the second step-down circuit 312, thereby controlling the second step-down circuit 312 to start voltage conversion.

[0076] While the second step-down circuit 312 performs voltage conversion, it outputs the power status signal corresponding to the second step-down circuit 312, generates the enable signal of the third step-down circuit 313, and controls the third step-down circuit 313 to start voltage conversion.

[0077] In some embodiments, the third buck circuit 313 is also used to output a power status signal to generate an external reset signal for the conversion module 300.

[0078] In this embodiment, the third step-down circuit 313 is part of the reset circuit. The third step-down circuit 313 is connected to the external reset pin 302. The third step-down circuit 313 outputs its corresponding power status signal as the external reset signal of the conversion module 300.

[0079] It should be noted that the power status signal output by the first step-down circuit 311 enables the second step-down circuit 312, the power status signal output by the second step-down circuit 312 enables the third step-down circuit 313, and the power status signal output by the third step-down circuit 313 provides an external reset signal. This allows for the timing circuit control of the third power supply voltage being powered on first, followed by the fourth power supply voltage, and the external reset signal being pulled high after the power supply is stable.

[0080] It is understood that the first connector 100 includes a first main power supply pin 110 and a first auxiliary power supply pin 120, and the second connector 200 includes a second main power supply pin 210 and a second auxiliary power supply pin 220. The main power supply pin provides the main operating voltage, and the auxiliary power supply pin can power non-core functions or low-power modules.

[0081] In some embodiments, the first auxiliary power pin 120 of the first connector 100 and the output terminal of the first step-down circuit 311 are connected to the external storage device 330 through a power redundancy switch 320. The power redundancy switch 320 is used to convert the auxiliary power voltage and the second power voltage provided by the first auxiliary power pin 120 into an external power voltage to power the external storage device 330. The external storage device 330 is used to store product data.

[0082] In this embodiment, the power redundancy switch 320 can be a power switching circuit including a metal-oxide-semiconductor field-effect transistor (MOSFET) or a diode, the external storage device 330 can be an electrically erasable programmable read-only memory (EEPROM), and the product data is the vital product data (VPD).

[0083] Taking the first main power supply pin 110 as an example, which provides a power supply voltage of 12 volts (V).

[0084] The first main power supply pin 110 provides a first power supply voltage of 12V, and the first step-down circuit 311 converts the first power supply voltage of 12V provided by the first main power supply pin 110 into a second power supply voltage of 3.3V.

[0085] The power redundancy switch 320 converts the auxiliary power voltage provided by the first auxiliary power pin 120 and the second power voltage 3.3V into an external power voltage of 3.3V to power the external storage device 330. When the first main power pin 110 fails to supply power normally, the Baseboard Manager Controller (BMC) of the storage device 400 can obtain the VPD information of the adapter board through the external storage device 330.

[0086] In some embodiments, the first main power pin 110 of the first connector 100 is connected to the second main power pin 210 of the second connector 200; the first auxiliary power pin 120 of the first connector 100 is connected to the second auxiliary power pin 220 of the second connector 200.

[0087] In this embodiment, the first main power pin 110 of the first connector 100 is connected to the second main power pin 210 of the second connector 200, and the first auxiliary power pin 120 of the first connector 100 is connected to the second auxiliary power pin 220 of the second connector 200, so that the storage device 400 supplies power to the solid-state drive 500.

[0088] The endpoint subsystem 360 and the root complex subsystem 370 will be described in detail below.

[0089] In some embodiments, the endpoint subsystem 360 is provided with at least four second communication pins 361.

[0090] When the endpoint subsystem 360 is operating in four-channel mode, the four first communication pins 130 of the first connector 100 are connected one-to-one with the four second communication pins 361 of the endpoint subsystem 360 to transmit two dual-channel communication signals.

[0091] For example, such as Figure 4 As shown, the endpoint subsystem 360 has eight second communication pins 361. One second communication pin 361 can transmit one channel of communication signal. The endpoint subsystem 360 supports one PCIe 3.0 × 8 port working mode and two PCIe 3.0 × 4 port working modes.

[0092] When the endpoint subsystem 360 is operating in a four-channel working mode, that is, when the endpoint subsystem 360 is operating in a two-way PCIe 3.0×4 port working mode, the four first communication pins 130 of the first connector 100 are connected one-to-one with the four second communication pins 361 of the endpoint subsystem 360 to establish a communication link between the endpoint subsystem 360 and the storage device 400, and complete the transmission of two-way PCIe×2 signals.

[0093] In some embodiments, the two first clock pins 140 of the first connector 100 are connected one-to-one with the two second clock pins 362 of the endpoint subsystem 360 to transmit two clock signals.

[0094] In this embodiment, the first clock pin 140 of the first connector 100 is connected to the second clock pin 362 of the endpoint subsystem 360, so that the storage device 400 provides two clock signals (such as a 100MHz clock signal) to the endpoint subsystem 360.

[0095] In some embodiments, the two first reset pins 150 of the first connector 100 are connected one-to-one with the two second reset pins 363 of the endpoint subsystem 360 to transmit two reset signals.

[0096] In this embodiment, the first reset pin 150 of the first connector 100 is connected to the second reset pin 363 of the endpoint subsystem 360, so that the storage device 400 provides two reset signals to the endpoint subsystem 360.

[0097] Understandably, with the combined effect of two clock signals, two reset signals, and two dual-channel communication signals, stable link communication between the storage device 400 and the endpoint subsystem 360 can be achieved.

[0098] It should be noted that the endpoint subsystem 360 has eight second communication pins 361. In the four-channel operating mode, only four second communication pins 361 are used, and the read / write signals of the remaining four second communication pins 361 that are not connected to the first connector 100 are left floating.

[0099] In some embodiments, the conversion module 300 is further provided with two first status indication interfaces 391, which are used to connect to first status indicator lights 392. The two first status indicator lights 392 are used to indicate the transmission status of the two dual-channel communication signals respectively.

[0100] like Figure 4 As shown, the first status indicator interface 391 is connected to the first status indicator 392. The first status indicator 392 lights up with different colors to indicate different signal transmission statuses. Green indicates that the signal transmission is valid, and amber indicates that the signal transmission is faulty. The storage device 400 and the endpoint subsystem 360 transmit two PCIe×2 signals. One first status indicator 392 indicates the transmission status of one PCIe×2 signal, and the other first status indicator 392 indicates the transmission status of the other PCIe×2 signal.

[0101] In actual implementation, the driving logic of the first status indicator 392 can be stored in the firmware storage unit 340.

[0102] In some embodiments, the root complex subsystem 370 is provided with at least four third communication pins 371.

[0103] When the root complex subsystem 370 is operating in four-channel mode, the four third communication pins 371 of the root complex subsystem 370 are connected one-to-one with the four fourth communication pins 230 of the second connector 200 to transmit one four-channel communication signal.

[0104] For example, such as Figure 4 As shown, the root complex subsystem 370 has eight third communication pins 371. Each third communication pin 371 can transmit communication signals for one channel. The root complex subsystem 370 supports two PCIe 3.0 × 4 port operating modes, one PCIe 3.0 × 4 plus two PCIe 3.0 × 2 port operating modes, two PCIe 3.0 × 2 plus one PCIe 3.0 × 4 port operating modes, and four PCIe 3.0 × 2 port operating modes.

[0105] When the root complex subsystem 370 operates in a four-channel working mode, that is, when the endpoint subsystem 360 operates in a two-port PCIe 3.0×4 port working mode, a one-port PCIe 3.0×4 port working mode plus two-port PCIe 3.0×2 port working mode, or a two-port PCIe 3.0×2 port working mode plus one-port PCIe 3.0×4 port working mode, the four third communication pins 371 of the root complex subsystem 370 are connected one-to-one with the four fourth communication pins 230 of the second connector 200 to establish a communication link between the root complex subsystem 370 and the solid-state drive 500, and complete the transmission of one PCIe×4 signal.

[0106] In some embodiments, the adapter board further includes a clock generator 380, which is connected to a third clock pin 372 of the root complex subsystem 370 and a fourth clock pin 240 of the second connector 200. The clock generator 380 is used to generate two clock signals and transmit the two clock signals to the root complex subsystem 370 and the second connector 200, respectively.

[0107] In this embodiment, clock generator 380 provides a common clock signal to solid-state drive 500 connected to second connector 200 and root complex subsystem 370.

[0108] In actual implementation, clock generator 380 can be a 100MHz dual-channel clock output generator. A 25MHz crystal outputs a 25MHz reference clock to clock generator 380. The first clock output of clock generator 380 is sent to root complex subsystem 370, and the second clock output is sent to second connector 200.

[0109] In some embodiments, the third reset pin 373 of the root complex subsystem 370 is connected to the fourth reset pin 250 of the second connector 200 to transmit a reset signal.

[0110] It should be noted that the root complex subsystem 370 has eight third communication pins 371. In the four-channel operating mode, only four third communication pins 371 are used. The read and write signals of the remaining four third communication pins 371 that are not connected to the second connector 200 are left floating. The remaining three third reset pins 373 that are not connected to the second connector 200 are also left floating.

[0111] Understandably, with the combined effect of two clock signals, one reset signal, and one four-channel communication signal, stable link communication between the solid-state drive 500 and the root complex subsystem 370 can be achieved.

[0112] In some embodiments, the conversion module 300 is further provided with a second status indication interface 393, which is used to connect a second status indicator 394, which is used to indicate the transmission status of a four-channel communication signal.

[0113] like Figure 4 As shown, the second status indicator interface 393 is connected to the second status indicator 394. The second status indicator 394 lights up with different colors to indicate different signal transmission states. A PCIe×4 signal is transmitted between the solid-state drive 500 and the root complex subsystem 370. The second status indicator 394 indicates the transmission status of the PCIe×4 signal. The driving logic of the second status indicator 394 can also be stored in the firmware storage unit 340.

[0114] In some embodiments, the first connector 100 is provided with a first serial communication interface 160, the second connector 200 is provided with a second serial communication interface 260, and the conversion module 300 is provided with a third serial communication interface 303.

[0115] The first serial communication interface 160, the second serial communication interface 260 and the third serial communication interface 303 are connected to the system management bus, which is also connected to the external storage device 330.

[0116] The System Management Bus (SMBus) is a serial bus protocol used for communication between computer hardware components.

[0117] In this embodiment, the third serial communication interface 303 provided by the conversion module 300 can be a serial communication protocol interface (Inter-Integrated Circuit, I2C), which is connected to the external storage device 330 through the system management bus.

[0118] like Figure 2 As shown, the first serial communication interface 160, the second serial communication interface 260 and the third serial communication interface 303 are connected to the system management bus, and the external storage device 330 is also connected to the system management bus, so that the BMC of the storage device 400 can obtain the VPD information of the adapter board, the VPD information of the solid-state drive 500 and out-of-band management information, etc.

[0119] Understandably, the adapter board can also be configured with general purpose input / output (GPIO) interfaces.

[0120] In some embodiments, the first connector 100 is provided with a first general-purpose input / output interface 170, and the second connector 200 is provided with a second general-purpose input / output interface 270, and the first general-purpose input / output interface 170 is connected to the second general-purpose input / output interface 270.

[0121] The first general purpose input / output interface 170 outputs a level signal to the second general purpose input / output interface 270 so that the solid-state drive 500 can determine the type of device connected to the solid-state drive 500 based on the received level signal.

[0122] In this embodiment, the first general purpose input / output interface 170 of the first connector 100 is connected to the second general purpose input / output interface 270 of the second connector 200. When the storage device 400 is inserted into the solid-state drive 500 connected to the adapter board, the first general purpose input / output interface 170 can output a low level, and the second general purpose input / output interface 270 receives a low level, indicating that the host to which the solid-state drive 500 is inserted is the storage device 400, rather than a server product.

[0123] In some embodiments, the first connector 100 is provided with a first general-purpose input / output interface 170, and the conversion module 300 is provided with a third general-purpose input / output interface 304, wherein the first general-purpose input / output interface 170 is connected to the third general-purpose input / output interface 304.

[0124] The first general-purpose input / output interface 170 outputs a level signal to the third general-purpose input / output interface 304, so that the conversion module 300 runs the system firmware stored in the firmware storage unit 340 of the circuit system based on the received level signal.

[0125] In this embodiment, the first general-purpose input / output interface 170 of the first connector 100 is connected to the third general-purpose input / output interface 304 of the conversion module 300. When the storage device 400 is inserted into the solid-state drive 500 connected to the adapter board, the first general-purpose input / output interface 170 can output a low level. The third general-purpose input / output interface 304 receives the low level and runs the system firmware stored in the firmware storage unit 340, so that the endpoint subsystem 360 and the root complex subsystem 370 can operate according to the set port working mode.

[0126] In some embodiments, the first connector 100 is further provided with a first interface detection pin 180 and a first presence detection pin 190.

[0127] The signal of the first interface detection pin 180 can be an interface detection signal (IFDET), and the signal of the first presence detection pin 190 can be a presence signal (PRSNT).

[0128] In this embodiment, the first interface detection pin 180 is grounded, and the first presence detection pin 190 is left floating, indicating that the first connector 100 is connected to the storage device 400.

[0129] In some embodiments, the second connector 200 is further provided with a second interface detection pin 280 and a second presence detection pin 290.

[0130] The signal of the second interface detection pin 280 can be the IFDET signal, and the signal of the second presence detection pin 290 can be the PRSNT signal.

[0131] like Figure 2 As shown, the conversion module 300 is provided with a clock bus interface 307, and the clock generator 380 is connected to the clock bus interface 307. The clock bus interface 307 can be an I2C interface.

[0132] The clock generator 380 has a dual-channel clock output. The first clock output enable signal is grounded, indicating that the first clock output of the clock generator 380 is supplied to the root complex subsystem 370. The second clock output enable signal is connected to the second interface detection pin 280, which is grounded. When the adapter card is inserted into the solid-state drive 500, the second clock output enable signal is grounded, and the second clock of the clock generator 380 is supplied to the solid-state drive 500 through the second connector 200.

[0133] In actual operation, the second interface detection pin 280 is also connected to the fourth general-purpose input / output interface 374 of the conversion module 300 to send the IFDET signal of the solid-state drive 500 to the conversion module 300.

[0134] In this embodiment, the second presence detection pin 290 is left floating, indicating that the connected solid-state drive 500 is connected.

[0135] The adapter board of this application embodiment includes a first connector 100, a second connector 200, and a conversion module 300. By utilizing the reasonable configuration of hardware circuits and firmware such as the circuit system, endpoint subsystem 360, and root complex subsystem 370 of the conversion module 300, two PCIe×2 signals from the storage device 400 are converted into one PCIe×4 signal, thereby realizing communication between the storage device 400 and the single-port solid-state drive 500. This compensates for the functional defects of the single-port solid-state drive 500 and helps to improve the overall competitiveness of the single-port solid-state drive 500.

[0136] The adapter board provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An adapter board, characterized in that, include: The first connector connects to two device-end connectors of the storage device, the device-end connectors being used to transmit dual-channel communication signals; The second connector connects to the hard drive end connector of the solid-state drive, which is used to transmit four-channel communication signals. The conversion module includes a circuit system, an endpoint subsystem, and a root complex subsystem, wherein the endpoint subsystem is connected to the first connector, and the root complex subsystem is connected to the second connector. The conversion module is used to convert the two dual-channel communication signals input from the two device-end connectors to the first connector into a single four-channel communication signal, and then transmit the single four-channel communication signal to the hard disk connector through the second connector. The circuit system includes a power module, a clock input circuit, a reset circuit, a debug interface, and a firmware storage unit. The firmware storage unit is used to store system firmware, and the system firmware is used to configure the port operating modes of the endpoint subsystem and the root complex subsystem. The endpoint subsystem is provided with at least four second communication pins; When the endpoint subsystem is operating in a four-channel working mode, the four first communication pins of the first connector are connected one-to-one with the four second communication pins of the endpoint subsystem to transmit two dual-channel communication signals. The root complex subsystem is provided with at least four third communication pins; When the root complex subsystem is operating in four-channel mode, the four third communication pins of the root complex subsystem are connected one-to-one with the four fourth communication pins of the second connector to transmit one four-channel communication signal.

2. The adapter board according to claim 1, characterized in that, The power module includes a first step-down circuit, a second step-down circuit, and a third step-down circuit; The input terminal of the first step-down circuit is connected to the first main power pin of the first connector, the output terminal of the first step-down circuit is connected to the input terminal of the second step-down circuit, and the input terminal of the third step-down circuit is connected to the first main power pin. The first step-down circuit is used to convert the first power supply voltage provided by the first main power supply pin into a second power supply voltage, and output the second power supply voltage to the second step-down circuit. The second step-down circuit is used to convert the second power supply voltage into a third power supply voltage to power the conversion module. The third step-down circuit is used to convert the first power supply voltage into a fourth power supply voltage to power the conversion module. The fourth power supply voltage is lower than the third power supply voltage.

3. The adapter board according to claim 2, characterized in that, The first step-down circuit is also used to output a power status signal to the second step-down circuit to generate an enable signal for the second step-down circuit; The second step-down circuit is also used to output a power status signal to the third step-down circuit to generate an enable signal for the third step-down circuit.

4. The adapter board according to claim 2, characterized in that, The third step-down circuit is also used to output a power status signal to generate an external reset signal for the conversion module.

5. The adapter plate according to claim 2, characterized in that, The first auxiliary power pin of the first connector and the output terminal of the first step-down circuit are connected to an external storage device through a power redundancy switch. The power redundancy switch is used to convert the auxiliary power voltage provided by the first auxiliary power pin and the second power voltage into an external power voltage to power the external storage device, which is used to store product data.

6. The adapter plate according to any one of claims 1-5, characterized in that, The first main power pin of the first connector is connected to the second main power pin of the second connector; the first auxiliary power pin of the first connector is connected to the second auxiliary power pin of the second connector.

7. The adapter board according to claim 1, characterized in that, The two first clock pins of the first connector are connected one-to-one with the two second clock pins of the endpoint subsystem to transmit two clock signals; The two first reset pins of the first connector are connected one-to-one with the two second reset pins of the endpoint subsystem to transmit two reset signals.

8. The adapter board according to claim 1, characterized in that, The conversion module is also provided with two first status indicator interfaces. The first status indicator interfaces are used to connect to first status indicator lights. The two first status indicator lights are used to indicate the transmission status of the two dual-channel communication signals respectively.

9. The adapter board according to claim 1, characterized in that, Also includes: A clock generator, connected to the third clock pin of the root complex subsystem and the fourth clock pin of the second connector, the clock generator being used to generate two clock signals and transmit the two clock signals to the root complex subsystem and the second connector respectively; The third reset pin of the root composite subsystem is connected to the fourth reset pin of the second connector to transmit a reset signal.

10. The adapter board according to claim 1, characterized in that, The conversion module is also provided with a second status indication interface, which is used to connect a second status indicator light, and the second status indicator light is used to indicate the transmission status of a four-channel communication signal.

11. The adapter plate according to any one of claims 1-5, characterized in that, The first connector is provided with a first general-purpose input / output interface, and the second connector is provided with a second general-purpose input / output interface. The first general-purpose input / output interface is connected to the second general-purpose input / output interface. The first general-purpose input / output interface outputs a level signal to the second general-purpose input / output interface, so that the solid-state drive can determine the type of device connected to the solid-state drive based on the received level signal.

12. The adapter plate according to any one of claims 1-5, characterized in that, The first connector is provided with a first general-purpose input / output interface, and the conversion module is provided with a third general-purpose input / output interface. The first general-purpose input / output interface is connected to the third general-purpose input / output interface. The first general-purpose input / output interface outputs a level signal to the third general-purpose input / output interface, so that the conversion module runs the system firmware stored in the firmware storage unit of the circuit system based on the received level signal.

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