An in-board synchronization method and device based on RFSoC with digital function, a collection board card and a phased array radio telescope

Abstract

The application relates to the technical field of signal processing, and discloses an in-board synchronization method with a digital function based on an RFSoC, which comprises the following steps: in the case that a plurality of sampling channels on a collection board card are in a time lag mismatch state, if the plurality of sampling channels reach a delay synchronization state through delay distribution synchronization, triggering synchronization configuration is performed on the plurality of sampling channels; a first reference clock signal of a plurality of periods is received, if a preset signal change condition of the first reference clock signal is captured, periodic pulse triggering synchronization is performed on the plurality of sampling channels to ensure the synchronous execution of the digital function; and the plurality of sampling channels are subjected to synchronous phase locking. The method has the beneficial effect that, in the case that the sampling channels reach the delay synchronization state, the periodic pulse triggering synchronization of the sampling channels is performed by using the clock signal, the synchronous execution of the digital function by each sampling channel is ensured, the double synchronization of the sampling channels is realized, and the sampling channels are ensured to be in a high-precision synchronization state.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and in particular to an on-board synchronization method, device, acquisition board, and phased array radio telescope based on RFSoC with digital functions. Background Technology

[0002] A phased array system is an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array to precisely regulate the transmission and reception of electromagnetic waves. With its rapid development, phased array systems have played a crucial role in various fields, including radio astronomy, radar, ultrasonic imaging, and meteorological observation, and have broad application prospects. In a phased array system, each antenna element corresponds to a sampling channel, which are deployed on different acquisition boards. In some specialized acquisition boards, the sampling channels also possess certain digital functions for digital signal processing. However, in practice, the digital signal processing within the sampling channels is affected by phase errors, which places higher demands on the synchronization between the sampling channels.

[0003] In related technologies, the synchronization accuracy of on-board synchronization methods for acquisition boards with digital functions still needs to be improved. Summary of the Invention

[0004] This application provides an on-board synchronization method, device, acquisition board, and phased array radio telescope based on RFSoC with digital functions. When the sampling channel reaches a delayed synchronization state, the sampling channel is periodically pulse-triggered and synchronized using a clock signal, ensuring that each sampling channel executes digital functions synchronously, thereby achieving dual synchronization of the sampling channels and ensuring that the sampling channels are in a high-precision synchronization state.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, embodiments of this application provide an on-board synchronization method with digital functionality based on an RFSoC, the method comprising:

[0007] When multiple sampling channels on the acquisition board are in a time-delay mismatch state, if the multiple sampling channels achieve a delay synchronization state through delay allocation synchronization, the multiple sampling channels are triggered for synchronization configuration, so that the multiple sampling channels synchronously receive the first reference clock signal; wherein, the delay allocation synchronization is performed based on the first reference clock signal and the second reference clock signal, the first reference clock signal is used to set the delay measurement start reference for the multiple sampling channels in the delay allocation synchronization, and the second reference clock signal is used to provide the delay measurement observation window for the multiple sampling channels in the delay allocation synchronization;

[0008] Receive multiple cycles of the first reference clock signal; if a preset signal change of the first reference clock signal is detected, periodically pulse-triggered synchronization is performed on the multiple sampling channels to ensure the synchronous execution of the digital functions.

[0009] Synchronous phase locking is performed on the multiple sampling channels.

[0010] The on-board synchronization with digital functionality based on RFSoC proposed in this application first determines whether the sampling channel is in a time-delay mismatch state. If so, it performs delay allocation synchronization on the sampling channel to achieve a delayed synchronization state. Second, it configures the sampling channel for trigger synchronization, controlling the sampling channel to synchronously receive a first reference clock signal and periodically triggering synchronization based on the first reference clock signal to repeatedly align the phase of the sampling channel. Finally, it performs synchronization phase locking on the sampling channel. Compared with related technologies, this application performs dual synchronization on the sampling channel, not only ensuring that the sampling channel reaches a delayed synchronization state but also eliminating phase errors between sampling channels through periodic pulse trigger synchronization, thus ensuring a stable phase synchronization state. By performing dual synchronization on the sampling channel, the synchronization accuracy between sampling channels is effectively improved.

[0011] Optionally, receiving multiple cycles of the first reference clock signal, and if a preset signal change in the first reference clock signal is detected, periodically triggering synchronization of the multiple sampling channels includes:

[0012] For any one of the plurality of sampling channels, the first reference clock signal is subjected to signal change detection to obtain the reference clock change state;

[0013] If the preset signal change exists in the reference clock change state, determine the preset signal change of the first reference clock signal, and use the preset signal change as a trigger reference to perform repeated phase initialization on the multiple sampling channels.

[0014] The phase to be synchronized for each of the plurality of sampling channels is obtained, and phase compensation is performed on the plurality of sampling channels according to the phase to be synchronized, so that the phase of each of the plurality of sampling channels is aligned with the preset initial channel phase.

[0015] Using the preset signal change as a trigger reference, the multiple sampling channels are repeatedly phase aligned until the number of cycles of the preset signal change is captured reaches a preset cycle number threshold.

[0016] Optionally, the step of triggering synchronization configuration for the plurality of sampling channels includes:

[0017] Control the multiple sampling channels to synchronously stop receiving the first reference clock signal;

[0018] The initial phase of the plurality of sampling channels is set according to the preset initial channel phase;

[0019] The multiple sampling channels are controlled to synchronously begin receiving the first reference clock signal.

[0020] Optionally, before controlling the plurality of sampling channels to synchronously begin receiving the first reference clock signal, the method further includes:

[0021] The trigger signals of each of the plurality of sampling channels are all set to the first reference clock signal.

[0022] Optionally, after configuring the trigger synchronization of the plurality of sampling channels, the method further includes:

[0023] When the preset signal change is detected, the channel phase of the multiple sampling channels is initialized according to the preset initial channel phase.

[0024] Optionally, the preset signal change is the rising edge of a pulse in the first reference clock signal.

[0025] Optionally, the step of synchronizing phase-locking the plurality of sampling channels includes:

[0026] The multiple sampling channels are controlled to synchronously stop receiving the first reference clock signal.

[0027] Secondly, embodiments of this application provide an on-board synchronization device with digital functionality based on an RFSoC, the device comprising:

[0028] The trigger synchronization preparation module is used to configure the multiple sampling channels to receive a first reference clock signal synchronously when multiple sampling channels on the acquisition board are in a time-delay mismatch state, provided that the multiple sampling channels have reached a delay synchronization state through delay allocation synchronization. The delay allocation synchronization is performed based on the first reference clock signal and a second reference clock signal. The first reference clock signal is used to set a delay measurement start reference for the multiple sampling channels during delay allocation synchronization, and the second reference clock signal is used to provide a delay measurement observation window for the multiple sampling channels during delay allocation synchronization.

[0029] The pulse-triggered synchronization module is used to receive the first reference clock signal for multiple cycles. If a preset signal change of the first reference clock signal is detected, the module performs periodic pulse-triggered synchronization on the multiple sampling channels to ensure the synchronous execution of the digital functions.

[0030] A synchronous phase-locking module is used to synchronously lock the multiple sampling channels.

[0031] Thirdly, embodiments of this application provide an acquisition board with digital functions based on RFSoC, which performs on-board synchronization using the method described in any one of the above embodiments.

[0032] Fourthly, this application provides a phased array radio telescope, including the acquisition board described in any of the above embodiments. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0034] Figure 1 A step diagram of an on-board synchronization method with digital functionality based on RFSoC provided in an embodiment of this application;

[0035] Figure 2 This is a flowchart illustrating the steps of periodic pulse-triggered synchronization in an embodiment of this application;

[0036] Figure 3 This is a diagram illustrating the steps for triggering synchronization configuration in an embodiment of this application;

[0037] Figure 4 A block diagram of an on-board synchronization device with digital functionality based on RFSoC provided in this application embodiment;

[0038] Figure 5 This is a hardware block diagram of a digital acquisition board based on RFSoC in the embodiments of this application;

[0039] Figure 6 This is a clock tree structure diagram of the RFSoC-based data acquisition board with digital functionality in the embodiments of this application;

[0040] Figure 7 This application provides a schematic diagram of the structure of a computer device. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] A phased array system is an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array to precisely regulate the transmission and reception of electromagnetic waves. With its rapid development, phased array systems have played a crucial role in various fields, including radio astronomy, radar, ultrasonic imaging, and meteorological observation, and have broad application prospects. In a phased array system, each antenna element corresponds to a sampling channel, which are deployed on different acquisition boards. In some specialized acquisition boards, the sampling channels also possess certain digital functions for digital signal processing. However, in practice, the digital signal processing within the sampling channels is affected by phase errors, which places higher demands on the synchronization between the sampling channels.

[0043] Related technologies typically employ only a single synchronization method to synchronize sampling channels. For example, during signal acquisition, timing asynchrony between sampling channels can cause timing errors between sampled signals, thus affecting signal quality. Therefore, in this case, it is necessary to ensure that the sampling channels reach a delayed synchronization state to improve the timing consistency between sampled signals and enhance the quality of the sampled signals. In other cases, when obtaining and processing sampled signals, phase differences between sampling channels may adversely affect the signal processing results, leading to a reduction in signal quality. Therefore, in this case, it is necessary to ensure phase synchronization of the sampling channels to perform correct signal processing and improve the accuracy of the signal processing results. In real-world scenarios, timing asynchrony and phase differences may occur simultaneously between sampling channels, making it difficult to achieve stable and accurate synchronization between sampling channels using only a single synchronization method.

[0044] To address the aforementioned issues, this application provides an on-board synchronization method with digital functionality based on RFSoC, comprising: when multiple sampling channels on the acquisition board are in a time-delay mismatch state, if the multiple sampling channels achieve a delayed synchronization state through delay allocation synchronization, triggering synchronization configuration for the multiple sampling channels; receiving multiple cycles of a first reference clock signal, and if a preset signal change of the first reference clock signal is captured, periodically triggering synchronization for the multiple sampling channels to ensure the synchronous execution of digital functions; and performing synchronization phase locking on the multiple sampling channels.

[0045] The on-board synchronization method with digital functions based on RFSoC provided in this application first determines whether the sampling channel is in a time-delay mismatch state. If so, it performs delay allocation synchronization on the sampling channel so that the sampling channel reaches a delayed synchronization state. Second, it configures the sampling channel to be triggered for synchronization, controls the sampling channel to synchronously receive the first reference clock signal, and performs periodic pulse trigger synchronization on the sampling channel according to the first reference clock signal to repeatedly align the phase of the sampling channel. Finally, it performs synchronization phase locking on the sampling channel.

[0046] Compared with related technologies, this application implements dual synchronization for the sampling channels. This not only ensures that the sampling channels reach a delayed synchronization state, but also eliminates phase errors between sampling channels by periodically triggering synchronization with pulses, thus ensuring a stable phase synchronization state. This dual synchronization effectively improves the synchronization accuracy between sampling channels.

[0047] The on-board synchronization method with digital functionality based on RFSoC provided in this manual can be applied to any acquisition board within a phased array system. Phased array systems can be used in various fields, including radio astronomy, radar, ultrasonic imaging, and meteorological observation. In radio astronomy, phased array systems can be used to construct phased array radio telescopes, enabling high-speed, real-time, and synchronous acquisition and preprocessing of large-scale, wide-band radio frequency signals. It should be noted that this acquisition board includes digital functionality, enabling it to perform certain digital signal processing on the sampled signals.

[0048] According to an embodiment of this application, an embodiment of an on-board synchronization method with digital functions based on RFSoC is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Also, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0049] This embodiment provides an on-board synchronization method with digital functionality based on RFSoC, which can be used in the aforementioned acquisition board. (Refer to...) Figure 1 As shown, the method includes:

[0050] S100. When multiple sampling channels on the acquisition board are in a time-delay mismatch state, if the multiple sampling channels achieve a delay synchronization state through delay allocation synchronization, trigger synchronization configuration is performed on the multiple sampling channels so that the multiple sampling channels synchronously receive the first reference clock signal; wherein, the delay allocation synchronization is performed based on the first reference clock signal and the second reference clock signal. The first reference clock signal is used to set the delay measurement start reference for the multiple sampling channels in the delay allocation synchronization, and the second reference clock signal is used to provide the delay measurement observation window for the multiple sampling channels in the delay allocation synchronization.

[0051] S200. Receives multiple cycles of the first reference clock signal. If the preset signal change of the first reference clock signal is captured, the multiple sampling channels are periodically pulse-triggered for synchronization to ensure the synchronous execution of digital functions.

[0052] S300. Synchronize and phase-lock multiple sampling channels.

[0053] The time-delay mismatch state can be a situation where there is a difference in the delay values ​​between the sampling channels, causing the sampling channels to be unable to acquire signals synchronously. The cause of the sampling channels being in a time-delay mismatch state may be hardware delay or signal processing delay, etc. The delay synchronization state can be a situation where the sampling channels share the same target delay value, thereby enabling multi-channel synchronous signal acquisition through multiple sampling channels.

[0054] Delay allocation synchronization can be a process of allocating a target delay value to each sampling channel based on the delay values ​​of each sampling channel measured by a first reference clock signal and a second reference clock signal when the sampling channel is in a time-delay mismatch state. Delay allocation synchronization enables the sampling channels to share the same target delay value, achieving delay synchronization among the sampling channels and realizing multi-channel synchronous signal acquisition.

[0055] The first reference clock signal can be a reference clock signal with a specific clock frequency, used as a global reference clock to clock-align each sampling channel, so as to set the same delay value measurement benchmark for each sampling channel. The second reference clock signal can be a reference clock signal with the same frequency and constant phase difference as the first reference clock signal, used to clock-align the programmable logic area corresponding to each sampling channel, providing the same delay measurement observation window for each sampling channel, so as to synchronously control the delay value measurement of each sampling channel. It can be understood that, based on the cooperation between the first and second reference clock signals, the clock domain deviation that may occur during the delay value measurement process is effectively eliminated, improving the accuracy of the delay value measurement results. In addition, based on the first and second reference clock signals with the same frequency and constant phase difference, the delay value measurement of each sampling channel can be repeated, effectively improving the reliability of the delay value measurement results.

[0056] Specifically, the acquisition board is clock signal enabled, activating the first reference clock signal, the second reference clock signal, and the sampling reference clock signal. It should be noted that the sampling reference clock signal is used as the signal sampling reference clock for the sampling channels after on-board synchronization is completed, triggering each sampling channel to acquire synchronous signals. Next, the acquisition board undergoes a status self-check to determine if it is functioning correctly. This self-check may include module enable status checks, phase-locked loop status checks, power-on status checks, and channel enable status checks, ensuring that the modules and sampling channels on the acquisition board have a stable initial state, that there are no faults within the acquisition board, and that each sampling data channel can initiate the synchronization process. After clock signal enabling and status self-checks are completed, the delay values ​​for each sampling channel on the acquisition board are initialized.

[0057] Furthermore, when the sampling channels are in a time-delay mismatch state, delay allocation synchronization is performed on each sampling channel according to the first reference clock signal and the second reference clock signal, so that each sampling channel has the same target delay value, achieving a delay synchronization state, thereby realizing multi-channel synchronous signal acquisition. The process of determining whether the sampling channel is in a time-delay mismatch state may include: measuring the delay value of each sampling channel according to the first reference clock signal and the second reference clock signal to obtain the delay value of each sampling channel; if there is a difference between the delay values ​​of each sampling channel, it is determined that the sampling channel is in a time-delay mismatch state.

[0058] The process of measuring the delay value of each sampling channel may include: globally aligning each sampling channel with a first reference clock signal, and clock aligning the programmable logic portion of each sampling channel with a second reference clock signal, so that each sampling channel uses the same reference clock signal as the measurement benchmark; issuing delay value test commands to each sampling channel based on preset signal changes in the second reference clock signal, controlling each sampling channel to measure the delay value based on the preset signal changes in the first reference clock signal, and obtaining the delay value of each sampling channel; wherein, the preset signal changes in the first and second reference clock signals can be the rising or falling edge of a pulse signal, etc. It is understood that using the first and second reference clock signals to synchronously measure the delay value of each sampling channel reduces the timing errors that may occur when each sampling channel measures the delay value individually, and improves the accuracy of the delay value measurement results. Furthermore, using the first and second reference clock signals also enables automatic delay value measurement, eliminating the need for manual intervention by operators, reducing the influence of operator experience on the delay value measurement results, and improving the efficiency and accuracy of delay value measurement.

[0059] Based on this, the delay allocation synchronization process may include: performing distribution analysis on the delay values ​​of each sampling channel, determining the delay value that meets the preset delay synchronization requirement from all delay values, and performing redundancy processing on the delay value to obtain the delay value to be allocated; wherein, the preset delay synchronization requirement may be the maximum value, minimum value, average value, or median value among all delay values, and the redundancy processing may be adding a redundant delay period based on the delay value. For example, the preset delay synchronization requirement may be the maximum value among all delay values, and the redundant delay period added by the redundancy processing may be 16 clock cycles; based on the first reference clock signal, the delay value to be allocated is synchronously allocated to each sampling channel to set the target delay value of each sampling channel as the delay value to be allocated, so that each sampling channel achieves a delay synchronization state. Through delay allocation synchronization, the sampling channels share the same target delay value, and the sampling channels achieve a delay synchronization state, realizing multi-channel synchronous signal acquisition.

[0060] Furthermore, after the sampling channels reach a delayed synchronization state, a trigger synchronization configuration is applied to each sampling channel, enabling them to synchronously receive the first reference clock signal. Next, each sampling channel is controlled to stably receive the first reference clock signal for multiple cycles. Using a preset signal change in the first reference clock signal during each cycle as a trigger condition, each sampling channel is periodically pulse-triggered for synchronization, achieving phase synchronization. This ensures that each sampling channel can synchronously execute digital functions, reducing phase differences between multiple sampled signals. Understandably, in a phase-synchronized state, the sampled signals in each sampling channel possess phase consistency, eliminating errors between sampled signals from different channels and improving the observation accuracy based on multi-channel sampled signals. In addition, each sampling channel can output sampled signals with the same phase, allowing for correct superposition or interference between sampled signals, optimizing signal strength and accuracy at specific frequency points, and thus improving signal quality.

[0061] Furthermore, based on the phase synchronization of each sampling channel, the sampling channels are synchronized and phase locked to prevent the phase synchronization between sampling channels from being interfered with by environmental factors or hardware factors, ensuring that the phase synchronization can be maintained during subsequent synchronous signal acquisition and improving the synchronization between each sampling channel.

[0062] The on-board synchronization method with digital functions based on RFSoC provided in this embodiment first determines whether the sampling channel is in a time-delay mismatch state. If so, it performs delay allocation synchronization on the sampling channel so that the sampling channel reaches a delayed synchronization state. Second, it configures the sampling channel to be triggered for synchronization, controls the sampling channel to synchronously receive the first reference clock signal, and performs periodic pulse trigger synchronization on the sampling channel according to the first reference clock signal to repeatedly align the phase of the sampling channel. Finally, it performs synchronization phase locking on the sampling channel.

[0063] Compared with related technologies, this application implements dual synchronization for the sampling channels. This not only ensures that the sampling channels reach a delayed synchronization state, but also eliminates phase errors between sampling channels by periodically triggering synchronization with pulses, thus ensuring a stable phase synchronization state. This dual synchronization effectively improves the synchronization accuracy between sampling channels.

[0064] Reference Figure 2 As shown in one embodiment of this application, multiple cycles of a first reference clock signal are received. If a preset signal change of the first reference clock signal is captured, periodic pulse-triggered synchronization is performed on multiple sampling channels, including:

[0065] S210. For any one of the multiple sampling channels, perform signal change detection on the first reference clock signal to obtain the reference clock change state.

[0066] S220. In the case of a preset signal change in the reference clock change state, determine the preset signal change of the first reference clock signal, and use the preset signal change as a trigger reference to perform repeated phase initialization on multiple sampling channels.

[0067] S230. Obtain the phase to be synchronized for each of the multiple sampling channels, and perform phase compensation on the multiple sampling channels according to the phase to be synchronized, so that the phase of each of the multiple sampling channels is aligned with the preset initial channel phase.

[0068] S240. Using a preset signal change as a trigger reference, perform repeated phase alignment on multiple sampling channels until the number of cycles of the preset signal change is captured reaches a preset cycle number threshold.

[0069] The preset signal change condition can be a change in the signal characteristics of the first reference clock signal, which can include the signal level, frequency, amplitude, or phase. For example, the preset signal change condition can be a change in the level of the first reference clock signal from low to high.

[0070] Specifically, after receiving the first reference clock signal, each sampling channel performs change detection on the corresponding signal feature of the first reference clock signal based on the signal features set in the preset signal change situation, and obtains the reference clock change state of the first reference clock signal. The reference clock change state includes the change of the corresponding signal feature in the first reference clock signal over a period of time, and the duration of the reference clock change state is shorter than a single clock cycle of the first reference clock signal.

[0071] Furthermore, when a preset signal change occurs within the reference clock variation state, the preset signal change of the captured first reference clock signal is determined. The time point of the preset signal change is used as the trigger reference for each sampling channel, and the initial phase setting of each sampling channel is activated to initialize the phase of each sampling channel. It should be noted that by using multiple cycles of the first reference clock signal, the phase initialization of each sampling channel can be repeatedly performed, ensuring the accuracy of subsequent phase acquisition of each sampling channel. For example, the number of repetitions of phase initialization can be determined based on a preset cycle number threshold.

[0072] Furthermore, considering the potential phase differences between the sampling channels, phase acquisition is performed on each sampling channel to obtain its own phase to be synchronized. Based on the phase to be synchronized, the phase difference between the sampling channels is calculated, and each sampling channel is individually phase-set according to the phase difference to perform phase compensation, ensuring that the phase of each sampling channel is aligned with the preset initial channel phase. It can be understood that the preset initial channel phase can be the phase value of any sampling channel or a pre-defined phase value. By aligning the phase of each sampling channel, it is ensured that there will be no phase misalignment when the sampling channels are used for signal processing using digital functions, thus ensuring signal processing quality and improving the synchronization between sampling channels. The digital functions can be functions that perform digital processing on the sampled signal, such as digital quadrature demodulation.

[0073] Furthermore, the preset signal changes of the first reference clock signal in multiple clock cycles are acquired. These preset signal changes are used as the trigger reference for each sampling channel, activating the aligned phase settings of each sampling channel to achieve phase synchronization and further improve the phase synchronization between sampling channels. When the number of cycles in which the preset signal changes are captured reaches a preset cycle number threshold, it indicates that the phase synchronization between sampling channels has met the preset requirements, and repeated phase alignment stops.

[0074] In some embodiments, due to the introduction of digital functions, the signal flow of each sampling channel passes through both an analog processing domain and a digital processing domain. These two signal processing domains each correspond to clock signals with different processing frequencies, and there may be a phase difference between the analog processing clock in the analog processing domain and the digital processing clock in the digital processing domain. When each signal enters the digital processing domain from the analog processing domain, the phase difference between the analog and digital processing clocks will cause signal delay errors in different sampling channels, affecting the synchronization between the sampling channels. Therefore, during on-board synchronization processing, each sampling channel uses the same analog and digital processing clocks, and the relative phase of the analog and digital processing clocks is determined to ensure that each signal enters the digital processing domain at the same clock position.

[0075] Reference Figure 3 As shown, as one embodiment of this application, the trigger synchronization configuration for multiple sampling channels includes:

[0076] S110. Control multiple sampling channels to synchronously stop receiving the first reference clock signal.

[0077] S120. Set the initial phase of multiple sampling channels according to the preset initial channel phase.

[0078] S130. Control multiple sampling channels to synchronously start receiving the first reference clock signal.

[0079] Specifically, an API function is called in the programmable logic section of each sampling channel to disable the reference signal receiver for each sampling channel, causing the sampling channels to synchronously stop receiving the first reference clock signal. For example, for Xilinx's RFDCIP core, the API function called could be XRFdc_MTS_Sysref_Config. By controlling each sampling channel to synchronously stop receiving the first reference clock signal, false triggering of any sampling channel by the first reference clock signal is avoided, reducing phase interference between the sampling channels caused by the first reference clock signal.

[0080] Furthermore, the API function is called to set the initial phase of the sampling channels, ensuring that the initial phase of each sampling channel is the same before pulse triggering synchronization. For example, for Xilinx's RFDC IP core, the API function called could be XRFdc_SetMixerSettings.

[0081] Furthermore, the API function is invoked to enable the reference signal receivers for each sampling channel, allowing the sampling channels to synchronously begin receiving the first reference clock signal. For example, for Xilinx's RFDC IP core, the API function invoked could be XRFdc_MTS_Sysref_Config. By controlling each sampling channel to synchronously begin receiving the first reference clock signal, it is ensured that the first reference clock signal can simultaneously trigger each sampling channel for pulse-triggered synchronization, thereby improving the synchronization between sampling channels.

[0082] As one embodiment of this application, before controlling multiple sampling channels to synchronously start receiving the first reference clock signal, the method further includes:

[0083] S132. Set the trigger signals of each of the multiple sampling channels to the first reference clock signal.

[0084] Specifically, the API function is called to set the mixing trigger source of each sampling channel to the first reference clock signal. This allows each sampling channel to be triggered by a preset signal change in the first reference clock signal for periodic pulse-triggered synchronization. For example, for Xilinx's RFDC IP core, the API function called could be XRFdc_SetMixerSettings.

[0085] It should be noted that the trigger signal for all sampling channels is set to the first reference clock signal. When the first reference clock signal is received synchronously, the first reference clock signal will trigger the periodic pulse trigger synchronization, which reduces the timing error between sampling channels during the pulse trigger synchronization process and improves the synchronization between sampling channels.

[0086] As one embodiment of this application, after configuring the trigger synchronization of multiple sampling channels, the method further includes:

[0087] S140. When a preset signal change is detected, the channel phase of multiple sampling channels is initialized according to the preset initial channel phase.

[0088] Specifically, after setting the initial phase of each sampling channel to a preset initial channel phase, an API function is called to apply the initial phase setting, ensuring that the initial phase state of each sampling channel is the same before pulse triggering synchronization. For example, for Xilinx's RFDC IP core, the API function called could be XRFdc_ResetNCOPhase, used to reset the NCO initial phase of each sampling channel.

[0089] As one embodiment of this application, the preset signal change condition is the rising edge of the pulse in the first reference clock signal.

[0090] Specifically, the preset signal change condition can be a rising edge of a pulse in the first reference clock signal, indicating that the level of the first reference clock signal changes from low to high. In other embodiments, the preset signal change condition can be a change in the signal characteristics of the first reference clock signal, which may include the signal level, frequency, amplitude, or phase. It is understood that the preset signal change condition is obtained by detecting the reference clock change state of the first reference clock signal. The reference clock change state includes the changes in the corresponding signal characteristics of the first reference clock signal over a period of time, and the duration of the reference clock change state is shorter than a single clock cycle of the first reference clock signal.

[0091] As one embodiment of this application, synchronous phase locking of multiple sampling channels includes:

[0092] S310. Control multiple sampling channels to synchronously stop receiving the first reference clock signal.

[0093] Specifically, an API function is called in the programmable logic section of each sampling channel to disable the reference signal receiver for each sampling channel, causing the sampling channels to synchronously stop receiving the first reference clock signal and preventing the first reference clock signal from falsely triggering any sampling channel. For example, for Xilinx's RFDC IP core, the API function called could be XRFdc_MTS_Sysref_Config.

[0094] Understandably, once all sampling channels have reached phase synchronization, phase locking is applied to the sampling channels to prevent interference from environmental or hardware factors, ensuring that phase synchronization can be maintained during subsequent synchronous signal acquisition and improving the synchronization between sampling channels.

[0095] Accordingly, please refer to Figure 4 This application provides an on-board synchronization device with digital functionality based on an RFSoC, the device comprising:

[0096] The trigger synchronization preparation module 410 is used to configure multiple sampling channels to receive the first reference clock signal synchronously when multiple sampling channels on the acquisition board are in a time-delay mismatch state, and if multiple sampling channels achieve a delay synchronization state through delay allocation synchronization. The delay allocation synchronization is performed based on the first reference clock signal and the second reference clock signal. The first reference clock signal is used to set the delay measurement start reference for multiple sampling channels in the delay allocation synchronization, and the second reference clock signal is used to provide the delay measurement observation window for multiple sampling channels in the delay allocation synchronization.

[0097] The pulse-triggered synchronization module 420 is used to receive multiple cycles of the first reference clock signal. If the preset signal change of the first reference clock signal is captured, the multiple sampling channels are periodically pulse-triggered to synchronize, so as to ensure the synchronous execution of digital functions.

[0098] The synchronous phase-locking module 430 is used to synchronously lock the phases of multiple sampling channels.

[0099] In some alternative implementations, the pulse-triggered synchronization module 420 includes:

[0100] The signal change detection unit is used to detect signal changes in the first reference clock signal for any one of the multiple sampling channels to obtain the reference clock change state.

[0101] The signal capture and alignment unit is used to determine the preset signal change of the first reference clock signal when there is a preset signal change in the reference clock change state, and to perform repeated phase initialization on multiple sampling channels using the preset signal change as the trigger reference.

[0102] The signal phase compensation unit is used to acquire the phase to be synchronized of each of the multiple sampling channels, and to perform phase compensation on the multiple sampling channels according to the phase to be synchronized, so that the phase of each of the multiple sampling channels is aligned with the preset initial channel phase.

[0103] The periodic repetition processing unit is used to repeatedly phase align multiple sampling channels with a preset signal change condition as a trigger reference until the number of cycles of the preset signal change condition is captured reaches a preset number of cycles threshold.

[0104] In some alternative implementations, the trigger synchronization preparation module 410 includes:

[0105] The synchronous stop receiving unit is used to control multiple sampling channels to synchronously stop receiving the first reference clock signal.

[0106] The initial phase setting unit is used to set the initial phase of multiple sampling channels according to the preset initial channel phase.

[0107] The synchronous start receiving unit is used to control multiple sampling channels to synchronously start receiving the first reference clock signal.

[0108] In some optional implementations, the synchronization start receiving unit includes:

[0109] The trigger signal setting subunit is used to set the trigger signals of each of the multiple sampling channels to the first reference clock signal.

[0110] In some alternative implementations, the trigger synchronization preparation module 410 includes:

[0111] The phase initialization unit is used to initialize the channel phase of multiple sampling channels according to the preset initial channel phase when a preset signal change is detected.

[0112] In some alternative implementations, in the pulse-triggered synchronization module 420, the preset signal change is the rising edge of the pulse in the first reference clock signal.

[0113] In some alternative implementations, the synchronization phase-locking module 430 includes:

[0114] The phase-locking unit is used to control multiple sampling channels to synchronously stop receiving the first reference clock signal.

[0115] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0116] In this embodiment, the on-board synchronization device with digital functions based on RFSoC is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0117] Reference Figure 5 As shown, this application provides an RFSoC-based acquisition board with digital functionality, which performs on-board synchronization using the method described in any of the above embodiments.

[0118] The data acquisition board provided in this embodiment includes input interfaces, a clock management module, an RFSoC series FPGA processing chip, a DDR memory module, a power supply module, and output interfaces. The input interfaces include eight RF signal acquisition interfaces and two clock signal interfaces. The clock management module can be a single clock chip, connected to the clock signal interfaces, which receives an externally input 10MHz reference clock and generates various clock signals required for the acquisition board's operation. The RFSoC series FPGA processing chip integrates an RFDCIP core, capable of simultaneously performing analog-to-digital conversion or digital processing on the analog signals input from the eight RF signal acquisition interfaces. The DDR memory module expands the data storage capacity of the acquisition board. The power supply module includes a Core PWR and a PWR Conn, providing the voltage required for signal acquisition. The output interfaces include four QSFP28 optical ports and one GE Ethernet interface, with the QSFP28 optical ports offering a single-port communication rate of up to 100Gbps.

[0119] Reference Figure 6As shown, the acquisition board provided in this embodiment is designed with a synchronous clock tree based on a single clock chip. This synchronous clock tree includes a clock chip, a PL MMCM divider, an RF clock chip, and an RFDC IP core. The RFDC IP core contains multiple sampling channels, represented by ADC tiles. All sampling channels operate in the same mode and are configured with the same operating parameters. The clock chip, as the foundation of the synchronous clock tree, generates a homogeneous clock signal and sends it to multiple modules on the acquisition board, providing a synchronous clock foundation for each module. It can be understood that a single clock chip uniformly outputs the clock signal, reducing clock drift and errors between multiple clock signals and improving timing consistency. Furthermore, the single clock chip simplifies the hardware design of the acquisition board, reduces module complexity, and improves the hardware stability and ease of use of the acquisition board.

[0120] The PL MMCM frequency divider is used to divide the clock signal output by the clock chip, generating the ADC parallel data output clock AXIS_clock and the back-end signal processing clock USER_clock to control the output and processing of the sampled signals, ensuring synchronization between different sampled signals in the process. The PL MMCM frequency divider also includes clock frequency conversion, clock phase control, clock division and multiplication, and clock synchronization. It is understood that the sampled signals are synchronously output to the RFSoC FPGA processing chip on the acquisition board for synchronous signal processing. For example, the frequency of the ADC parallel data output clock AXIS_clock can be 250MHz, and the frequency of the back-end signal processing clock USER_clock can be 350MHz.

[0121] The RF clock chip receives the clock signal sent by the clock chip and, based on this clock signal, obtains a sampling reference clock signal to be synchronously sent to the RFDC IP core. This provides a synchronous clock basis for the sampling channels during signal acquisition, enabling the sampling channels to perform synchronous signal acquisition. After receiving the clock signal from the clock chip, the RF clock chip performs clock operations on the clock signal to obtain the sampling reference clock signal for transmission to the RFDC IP core. When the frequency of the sampling reference clock signal is outside the clock frequency range corresponding to the clock chip, the clock chip cannot directly generate a sampling reference clock signal for the RFDC IP core. Therefore, the RF clock chip needs to perform clock operations on the clock signal to generate a sampling reference clock signal that meets the actual requirements. For example, the clock operation can be clock frequency multiplication or clock phase adjustment, etc.

[0122] The RFDC IP core receives the synchronous sampling signal sent by the RF clock chip and internally distributes the sampling reference clock signal synchronously to multiple sampling channels, enabling all sampling channels to perform synchronous signal acquisition based on the sampling reference clock signal. The sampling channel can be an analog-to-digital converter (ADC) channel, which converts the analog signal obtained through signal acquisition into a digital signal for further signal processing and analysis.

[0123] In some embodiments, the RFDC IP core may have only a single input terminal, which can be the input terminal of a reference channel among multiple sampling channels. After receiving an external input signal, the reference channel internally distributes the input signal to the other sampling channels to operate according to the input signal. It is understood that the reference channel serves as the reference channel for all sampling channels and is active in subsequent synchronization processing and acquisition. Other sampling channels are synchronized with the reference channel, effectively improving the synchronization between sampling channels. Furthermore, a single input terminal reduces the hardware resources required to configure the RFDC IP core, lowers the complexity of module connection design on the acquisition board, and improves the integration of the acquisition board.

[0124] Among the aforementioned modules, the output of the clock chip is connected to the input of the RF clock chip, and the outputs of the RF clock chip and the clock chip are respectively connected to the input of the RFDC IP core. The input of the PL MMCM divider is connected to the output of the clock chip. The RFDC IP core receives a sampling reference clock signal from the RF clock chip based on its connection to the RF clock chip, and receives a first reference clock signal AMS_SYSREF and a second reference clock signal PL_SYSREF from the clock chip based on its connection to the clock chip. For example, the frequency of the sampling reference clock signal can be 4 GHz, the frequency of the first reference clock signal AMS_SYSREF can be 10 MHz, and the frequency of the second reference clock signal PL_SYSREF can be 10 MHz.

[0125] Before the sampling channels begin acquiring synchronization signals, the RFDC IP core receives the first reference clock signal AMS_SYSREF and the second reference clock signal PL_SYSREF. Using these two signals as reference clocks, the sampling channels are synchronized on-board according to their values. This is achieved by allocating delay values ​​to the sampling channels for synchronization. Furthermore, pulse-triggered synchronization is performed on the sampling channels based on the first reference clock signal AMS_SYSREF, thereby eliminating delay and phase errors between different sampling channels. This ensures timing alignment of multiple sampling channels and improves their synchronization consistency. It should be noted that both the first reference clock signal AMS_SYSREF and the second reference clock signal PL_SYSREF are generated by a clock chip, have the same clock frequency, and possess a constant phase difference.

[0126] In some embodiments, the pulse-triggered synchronization process includes: turning off the reference signal receivers of each sampling channel and stopping the reception of the first reference clock signal AMS_SYSREF; calling API functions to perform initial phase settings and application configuration updates for each sampling channel, and setting the mixing trigger source of each sampling channel to the first reference clock signal AMS_SYSREF; turning on the reference signal receivers of each sampling channel so that each sampling channel synchronously receives the first reference clock signal AMS_SYSREF; capturing multiple cycles of the first reference clock signal AMS_SYSREF, using the pulse signal of the first reference clock signal AMS_SYSREF in each cycle as a trigger signal to perform phase synchronization on each sampling channel to align the phases of each sampling channel; turning off the reference signal receivers of each sampling channel after the aforementioned multiple cycles of the first reference clock signal AMS_SYSREF, stopping the reception of the first reference clock signal AMS_SYSREF, to lock the phase settings of each sampling channel and ensure the phase synchronization state between sampling channels.

[0127] This application also provides a phased array radio telescope, including the acquisition board described in any of the above embodiments.

[0128] Please see Figure 7 , Figure 7This is a schematic diagram of a computer device according to an embodiment of this application. As shown in the figure, the computer device includes one or more processors 10, a memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components communicate with each other using different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0129] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0130] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0131] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0132] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0133] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0134] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0135] This application provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method of any embodiment of this application.

[0136] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

[0137] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0138] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0139] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0140] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0141] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0142] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for on-board synchronization with digital functionality based on RFSoC, characterized in that, The method includes: When multiple sampling channels on the acquisition board are in a time-delay mismatch state, if the multiple sampling channels achieve a delay synchronization state through delay allocation synchronization, the multiple sampling channels are triggered for synchronization configuration, so that the multiple sampling channels synchronously receive the first reference clock signal; wherein, the delay allocation synchronization is performed based on the first reference clock signal and the second reference clock signal, the first reference clock signal is used to set the delay measurement start reference for the multiple sampling channels in the delay allocation synchronization, and the second reference clock signal is used to provide the delay measurement observation window for the multiple sampling channels in the delay allocation synchronization; The system receives multiple cycles of the first reference clock signal. If a preset signal change condition of the first reference clock signal is captured, the system performs periodic pulse-triggered synchronization on the multiple sampling channels to ensure the synchronous execution of the digital functions. Specifically, for any of the multiple sampling channels, the system detects signal changes in the first reference clock signal to obtain a reference clock change state. If the preset signal change condition exists in the reference clock change state, the system determines that the preset signal change condition of the first reference clock signal has been captured. Using the preset signal change condition as a trigger reference, the system performs repeated phase initialization on the multiple sampling channels. The system obtains the phase to be synchronized for each of the multiple sampling channels and performs phase compensation on the multiple sampling channels according to the phase to be synchronized, so that the phase of each of the multiple sampling channels is aligned with the preset initial channel phase. Using the preset signal change condition as a trigger reference, the system performs repeated phase alignment on the multiple sampling channels until the number of cycles in which the preset signal change condition is captured reaches a preset number of cycles threshold. Synchronous phase locking is performed on the multiple sampling channels.

2. The method according to claim 1, characterized in that, The configuration for triggering synchronization of the multiple sampling channels includes: Control the multiple sampling channels to synchronously stop receiving the first reference clock signal; The initial phase of the plurality of sampling channels is set according to the preset initial channel phase; The multiple sampling channels are controlled to synchronously begin receiving the first reference clock signal.

3. The method according to claim 2, characterized in that, Before controlling the plurality of sampling channels to synchronously begin receiving the first reference clock signal, the method further includes: The trigger signals of each of the plurality of sampling channels are all set to the first reference clock signal.

4. The method according to claim 2, characterized in that, After configuring the trigger synchronization of the plurality of sampling channels, the method further includes: When the preset signal change is detected, the channel phase of the multiple sampling channels is initialized according to the preset initial channel phase.

5. The method according to claim 1, characterized in that, The preset signal change is the rising edge of the pulse in the first reference clock signal.

6. The method according to claim 1, characterized in that, The step of synchronizing and phase-locking the multiple sampling channels includes: The multiple sampling channels are controlled to synchronously stop receiving the first reference clock signal.

7. An on-board synchronization device with digital functionality based on RFSoC, characterized in that, The device includes: The trigger synchronization preparation module is used to configure the multiple sampling channels to receive a first reference clock signal synchronously when multiple sampling channels on the acquisition board are in a time-delay mismatch state, provided that the multiple sampling channels have reached a delay synchronization state through delay allocation synchronization. The delay allocation synchronization is performed based on the first reference clock signal and a second reference clock signal. The first reference clock signal is used to set a delay measurement start reference for the multiple sampling channels during delay allocation synchronization, and the second reference clock signal is used to provide a delay measurement observation window for the multiple sampling channels during delay allocation synchronization. A pulse-triggered synchronization module is used to receive multiple cycles of the first reference clock signal. If a preset signal change condition of the first reference clock signal is captured, the module performs periodic pulse-triggered synchronization on the multiple sampling channels to ensure the synchronous execution of the digital functions. Specifically, for any of the multiple sampling channels, signal change detection is performed on the first reference clock signal to obtain a reference clock change state. If the preset signal change condition exists in the reference clock change state, it is determined that the preset signal change condition of the first reference clock signal has been captured. Using the preset signal change condition as a trigger reference, the multiple sampling channels are repeatedly initialized with phase. The module obtains the phase to be synchronized for each of the multiple sampling channels and performs phase compensation on the multiple sampling channels according to the phase to be synchronized, so that the phase of each of the multiple sampling channels is aligned with the preset initial channel phase. Using the preset signal change condition as a trigger reference, the multiple sampling channels are repeatedly phase aligned until the number of cycles in which the preset signal change condition is captured reaches a preset number of cycles threshold. A synchronous phase-locking module is used to synchronously lock the multiple sampling channels.

8. A data acquisition board with digital functionality based on RFSoC, characterized in that, In-board synchronization is performed using the method described in any one of claims 1 to 6.

9. A phased array radio telescope, characterized in that, Includes the acquisition board described in claim 8.

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