Circuit and implementation method for sorting sequences according to index values in inverted order by bits

Abstract

The invention discloses a circuit for sequencing sequences according to index values in a bitwise reverse order and an implementation method, relates to the technical field of digital signal processing, and solves the problems of high hardware requirements, complex design and difficulty in determining processing time delay in the existing method for sequencing sequences according to index values in a bitwise reverse order based on a processor. The layer number is determined by the length of the input sequence, the input end with the minimum layer number receives the input sequence, and the output end with the maximum layer number sends the output sequence; each reverse order processing layer comprises a plurality of reverse order units, the number of the reverse order units is the same as the number of the layer, the input end with the largest number serves as the input end of the layer, and the output end with the smallest number serves as the output end of the layer; wherein the reverse order unit with the number j is used for processing an input sequence according to the length, averagely dividing the sequence into four sections according to the input sequence, keeping the positions of the head section and the tail section unchanged, and exchanging the middle two sections; layered reverse order processing is carried out through a simple circuit structure, and the problem is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and more particularly to a circuit and an implementation method for sorting a sequence in reverse bit order according to index values. Background Art

[0002] The Fast Fourier Transform (FFT) is one of the most important algorithms in digital signal processing, widely used in communications, audio processing, image processing, and other fields. The FFT core is the hardware circuit module that implements the FFT algorithm, and its design directly impacts system performance, power consumption, and resource utilization. In hardware implementation, the FFT core typically uses fixed-point data. Based on the classic Cooley-Tukey, Sande-Tukey, and improved algorithm designs, pipelined FFT circuits are widely used in real-time signal processing due to their excellent balance between data throughput and hardware resource consumption. However, in the pipeline architecture of FFT, the time-decimated FFT algorithm circuit represented by Cooley-Tukey requires that the sequence input be reversed bit by bit according to the sequence element index value before the butterfly operation, and the circuit outputs the FFT operation results in the normal order. On the other hand, the frequency-decimated FFT algorithm circuit represented by Sande-Tukey receives the sequence input in order for the butterfly operation, but the FFT operation result sequence output by the circuit is in the order of the sequence element index value reversed bit by bit. In order to correctly execute the FFT or process the FFT operation results, it is sometimes necessary to reverse the sequential input sequence or restore the reversed output sequence to the normal sequence. Most of the currently available reverse output solutions are based on processors such as CPUs and MCUs. Performing the reverse order processing in the CPU or MCU has high hardware requirements, complex design, and difficult to determine the processing delay.

[0003] Therefore, the present application provides a circuit and implementation method for sorting a sequence in reverse order according to index values ​​to solve the above problem. Summary of the Invention

[0004] The purpose of this application is to provide a circuit and implementation method for sorting a sequence in reverse order according to index values, so as to solve the problems of high hardware requirements, complex design, and difficult to determine processing delay in the existing processor-based implementation of bit-by-bit reverse order according to index values. This application uses a simple circuit structure to perform hierarchical reverse order processing, which can support pipeline processing, has a simple implementation structure, low hardware requirements, and can calculate the processing delay based on the length of the input sequence.

[0005] The present application first provides a circuit for sorting a sequence in reverse bit order according to an index value, comprising: Multi-layer reverse order processing layer. The number of layers of the reverse order processing layer is determined by the length of the input sequence. The input sequence, the number of layers of reverse processing is , is an integer greater than 1. Multiple layers of reversal processing layers are connected in order of layer numbers. The input end of the reversal processing layer with the smallest layer number receives the input sequence input in sequence, and the output end of the reversal processing layer with the largest layer number outputs the output sequence in bit-reversed order according to the index value.

[0006] Each reverse order processing layer includes multiple reverse order units, and the number of reverse order units is the same as the layer number of the reverse order processing layer. Multiple reverse order units are connected in order of number, and the input end of the reverse order unit with the largest number is used as the input end of the reverse order processing layer, and the output end of the reverse order unit with the smallest number is used as the output end of the reverse order processing layer; The reverse order unit is used to The length of the input sequence is processed and the sequence is evenly divided into 4 paragraphs, is a positive integer, keeping the sequence positions of the first and last segments unchanged, and swapping the sequence positions of the two middle segments.

[0007] In a possible implementation, the reverse order unit includes: two conditional multiplexers and a shift register; the length of the shift register is , is the number of the reversing processing unit; the conditional multiplexer is used to select, according to the control signal: connecting the input end of the shift register with the output end of the shift register, connecting the input end of the reversing processing unit with the output end of the reversing processing unit; or connecting the input end of the shift register with the input end of the reversing processing unit, and connecting the output end of the shift register with the output end of the reversing unit; the control signal is determined by the index value of the input sequence.

[0008] In one possible implementation, the control signal is the first bit in the input sequence index value, counted from low to high starting from 0. and When the control signal is 2'b10, the input end of the shift register is connected to the output end of the shift register, and the input end of the reversing processing unit is connected to the output end of the reversing processing unit; when the control signal is not 2'b10, the input end of the shift register is connected to the input end of the reversing processing unit, and the output end of the shift register is connected to the output end of the reversing unit.

[0009] In a possible implementation manner, the reversing unit includes: When the value is greater than the threshold, RAM resources are used to replace the shift register resources, and logic resources are used to replace the conditional multiplexer.

[0010] In one possible implementation, the processing delay of the circuit is: Shoot, among them The layer number of the reverse processing layer, The length of the input sequence is raised to the power of 2.

[0011] In a possible implementation, the reversal unit of each reversal processing layer is encapsulated as a module, and the module has an input end and an output end.

[0012] The present application also provides a method for sorting a sequence in reverse order according to the index value, which is based on the above circuit execution and includes: obtaining an input sequence, the length of the input sequence is , An integer greater than 1; the input sequence is connected in order of layer numbers The input sequence is input from the reverse order processing layer with the smallest layer number, and is converted into an output sequence from the reverse order processing layer with the largest layer number; in each reverse order processing layer, the input sequence is input into multiple reverse order units connected in numerical order, and the number of reverse order units is the same as the layer number of the reverse order processing layer, and the input sequence is input from the reverse order unit with the largest number and is output from the reverse order unit with the smallest number; In the reverse order unit, the input sequence starts with The length of the input is divided into equal parts according to the input order. 4 paragraphs, is a positive integer, keeping the sequence positions of the first and last segments unchanged, and swapping the sequence positions of the two middle segments.

[0013] In one possible implementation, In the reverse order unit, the input sequence starts with The length of the input is divided into equal parts according to the input order. 4 paragraphs, is a positive integer, keeping the sequence positions of the first and last segments unchanged, and swapping the sequence positions of the middle two segments; this is achieved by the following steps: extracting the control signal from the index value in the input sequence; selecting according to the control signal: taking the elements of the input sequence directly as the output of the reversal unit, and adjusting the length to Alternatively, pass the elements of the input sequence into a shift register of length The shift register is used, and the output of the shift register is taken as the output of the reversing unit.

[0014] In a possible implementation, extracting a control signal from an index value of an input sequence includes: extracting the first bit of the index value of the input sequence from the lowest to the highest, starting from 0. and bit as the control signal.

[0015] In a possible implementation, when the control signal is 2'b10, the elements of the input sequence are directly used as the output of the reversal unit, and the length is adjusted to The output of the shift register is used as input; when the control signal is not 2'b10, the elements of the input sequence are sent to the length of The shift register is used, and the output of the shift register is taken as the output of the reversing unit.

[0016] Compared with the prior art, the present application has the following beneficial effects: 1. Support for pipeline processing: The present application implements bit-reversal operations through layer-by-layer grading and sequential processing, supports pipeline operations and does not have blocking signals; 2. Simple interface structure: The present application only includes one input port and one output port. The input port receives an input sequence input in the order of index values, and the output port outputs an output sequence in bit-reversed order according to the index values. Compared with the implementation scheme based on CPU / MCU, the interface is greatly simplified, which can greatly improve the design flexibility; 3. Flexible design: The present application can select an integrated and packaged reverse processing layer module to construct a layered architecture according to the length of the input sequence, and flexibly adjust the layered architecture according to the change in the length of the input sequence, thereby improving the design flexibility; 4. Low consumption of hardware resources: The present application only involves shift register cache, conditional multiplexer, or RAM resources, logic resources, and the control signal is only two bits. Compared with the implementation scheme based on CPU / MCU, the hardware resources consumed are significantly reduced; 5. Fixed processing delay: The processing delay of the present application has a fixed one-to-one correspondence with the sequence length, which is convenient for timing design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings: Figure 1 A schematic diagram of a circuit for sorting a sequence in reverse bit order according to index values ​​provided in an embodiment of the present application; Figure 2 The numbers provided for the embodiments of this application Schematic diagram of the reverse order unit; Figure 3 A flowchart of a method for implementing a method of sorting a sequence in reverse order of index values ​​provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] Hereinafter, the terms "include" or "may include" as used in various embodiments of the present application indicate the presence of the claimed function, operation, or element, and do not limit the addition of one or more functions, operations, or elements. In addition, as used in various embodiments of the present application, the terms "include", "have" and their cognates are intended only to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be understood as first excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing or the possibility of adding one or more features, numbers, steps, operations, elements, components, or combinations of the foregoing.

[0019] In various embodiments of the present application, the expression "or" or "at least one of B or / and C" includes any or all combinations of the words listed simultaneously. For example, the expression "B or C" or "at least one of B or / and C" may include B, may include C, or may include both B and C.

[0020] The expressions used in the various embodiments of the present application (such as "first," "second," etc.) may modify the various components in the various embodiments, but may not limit the corresponding components. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are merely used to distinguish one element from other elements. For example, a first user device and a second user device refer to different user devices, even though both are user devices. For example, without departing from the scope of the various embodiments of the present application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0021] It should be noted that when a component is described as being “connected” to or “connected to” another component, the first component may be directly connected to the second component, and a third component may be “connected” between the first and second components. Conversely, when a component is described as being “directly connected” to or “directly connected to” another component, it can be understood that there is no third component between the first and second components.

[0022] The terms used in the various embodiments of the present application are only used for the purpose of describing specific embodiments and are not intended to limit the various embodiments of the present application. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise. Unless otherwise specified, all terms used herein (including technical terms and scientific terms) have the same meaning as those generally understood by those skilled in the art to which the various embodiments of the present application belong. Terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, unless clearly defined in the various embodiments of the present application.

[0023] In order to make the objectives, technical solutions and advantages of this application more clear, the present application is further described in detail below in conjunction with examples and drawings. The schematic implementation methods of this application and their descriptions are only used to explain this application and are not intended to limit this application.

[0024] See Figure 1 As shown, Figure 1 The schematic diagram of the circuit for sorting a sequence in reverse order according to the index value provided in the embodiment of the present application; the circuit for sorting a sequence in reverse order according to the index value comprises: a plurality of reverse order processing layers, the number of layers of the reverse order processing layers is determined by the length of the input sequence, and the length of the input sequence is , the number of layers in reverse order is , is an integer greater than 1, and multiple layers of reverse order processing layers are connected in order of layer numbers. The input end of the reverse order processing layer with the smallest layer number receives the input sequence input in sequence, and the output end of the reverse order processing layer with the largest layer number outputs the output sequence after bit-reversal according to the index value; each reverse order processing layer includes: multiple reverse order units, the number of reverse order units is the same as the layer number of the reverse order processing layer, and the multiple reverse order units are connected in order of numbering, the input end of the reverse order unit with the largest number serves as the input end of the reverse order processing layer, and the output end of the reverse order unit with the smallest number serves as the output end of the reverse order processing layer; wherein, number The reverse order unit is used to The length of the input sequence is processed and the sequence is evenly divided into 4 paragraphs, is a positive integer, keeping the sequence positions of the first and last segments unchanged, and swapping the sequence positions of the two middle segments.

[0025] Specifically, the circuit for sorting a sequence in reverse order according to the index value has the following functions: receiving an input sequence, processing the input sequence in reverse order according to the index value of the input sequence, and outputting a reordered output sequence. This circuit performs bit-reversal processing according to the index value for input sequences with a length of an integer power of 2. This circuit adopts a hierarchical structure and performs bit-reversal processing for sequential inputs of length The input sequence is divided into The layer reversal processing layer performs bit-by-bit reversal processing, and each layer of reversal processing layer is composed of several sequentially connected reversal units. The layers process the input of the layer in reverse order, starting from the The output of the layer reverse processing layer outputs the reverse order result, where the first layer( ) in the reverse order processing layer, including a total of Continuous reverse order units, reverse order processing units are numbered from The function of each reverse order unit is to receive the input sequence according to the processing length, divide the input sequence into 4 segments of the same length according to the input order, keep the sequence positions of the first and last segments unchanged, and swap the sequence positions of the two middle segments. In the reverse order processing layer, the ( ) reverse processing units, Processing length of the input sequence, the length of The sequence is divided into equal parts of length according to the input order The input sequence is processed through layers of reversal processing, and the final output sequence is a bitwise reversed sequence based on the index value. This satisfies the requirements of the classic Cooley-Tukey, Sande-Tukey, and improved algorithms for reversing the sequence elements based on the index value.

[0026] The improvement of the present application is that it provides a circuit that supports pipeline processing, has a simple structure, flexible design, and a fixed processing delay, and sorts a sequence in reverse bit order according to an index value. Specifically, the circuit of the present application adopts a multi-level reverse order processing architecture, and realizes bit-by-bit reverse order operation through layer-by-layer hierarchical processing. Each layer is composed of multiple sequentially connected reverse order units, which refines the hierarchical processing process. The circuit supports pipeline operation, and there is no blocking signal in the entire circuit design, thereby ensuring that when receiving continuous sequence input, bit-by-bit reverse order operation and sequence output can be carried out continuously, ensuring the stability and continuity of pipeline processing; the circuit of the present application has only one input end and one output end externally, and each layer of reverse order processing layer has one input end and one output end internally. Compared with the implementation solution based on CPU / MCU, the interface structure of the present application is simpler and more convenient to use; the circuit of the present application sets the number of reverse order processing layers according to the length of the input sequence, and can expand / reduce the reverse order processing layers at any time according to the change in the length of the input sequence, thereby improving design flexibility; the circuit of the present application realizes layered bit-by-bit reverse order operation through multiple sequentially connected reverse order units, and the processing delay of the circuit can be calculated according to the length of the input sequence, which is convenient for timing design.

[0027] See Figure 2 As shown, Figure 2 The numbers provided for the embodiments of this application In one possible implementation, the reversal unit includes two conditional multiplexers and a shift register; the length of the shift register is , is the number of the reversing processing unit; the conditional multiplexer is used to select, according to the control signal: connecting the input end of the shift register with the output end of the shift register, connecting the input end of the reversing processing unit with the output end of the reversing processing unit; or connecting the input end of the shift register with the input end of the reversing processing unit, and connecting the output end of the shift register with the output end of the reversing unit; the control signal is determined by the index value of the input sequence.

[0028] Furthermore, the control signal is the first bit in the input sequence index value bit counted from low to high starting from 0. and When the control signal is 2'b10, the input end of the shift register is connected to the output end of the shift register, and the input end of the reversing processing unit is connected to the output end of the reversing processing unit; when the control signal is not 2'b10, the input end of the shift register is connected to the input end of the reversing processing unit, and the output end of the shift register is connected to the output end of the reversing unit.

[0029] Specifically, the sequence position exchange function of the reverse unit is realized by combining the conditional multiplexer and the shift register according to the index value of the input sequence of the unit. Figure 2As shown, in the input sequence, the input element and the input element index value idx are synchronously input to the reverse processing unit, starting with Take the reverse order processing unit as an example, and take the first bit from low to high starting from 0 in the index value idx bit it receives. and bit as a control signal, when the and When the bits are high and low respectively (using HDL hardware description language as idx[j:j-1]=2'b10, 2'b10 means the control signal is a two-bit binary signal, and its specific value is binary 10), the length is The input end of the shift register selects its own output end, and the output end of the reverse unit selects its own input end. At this time, the input element is directly used as the output element; when the and When the level value of the bit does not meet the above conditions, the input end of the shift register selects the input end of the reversing unit, and the output end of the reversing unit selects the output end of the shift register. At this time, the input element enters the shift register and the output element is obtained from the shift register.

[0030] In a possible implementation manner, the reversing unit includes: When the value is greater than the threshold, RAM resources are used to replace the shift register resources, and logic resources are used to replace the conditional multiplexer.

[0031] Specifically, when the input sequence is too long, that is, When the value is too large, the delay caused by continuing to use the shift register and conditional multiplexer to form the reverse order unit is too high, so RAM resources and logic resources are used instead to implement the function of the reverse order unit.

[0032] It is understandable that the components used in the circuit of this application only involve shift registers and conditional multiplexers. When the input sequence is long, only RAM resources and logic resources are involved, and two-bit control signals are used, consuming only one LUT (lookup table) resource. Input sequence, reverse order only requires consumption Compared with the CPU / MCU-based implementation, the hardware resources consumed are significantly reduced.

[0033] In one possible implementation, the processing delay of the circuit is: Shoot, among them The layer number of the reverse processing layer, The length of the input sequence is raised to the power of 2.

[0034] Specifically, for Layer reverse order processing layer The delay of the conditional multiplexer at the input of the shift register does not affect the delay of data output and is not included in the data processing delay of the reverse order unit. The conditional multiplexer at the output of the reverse order unit is the necessary path for output data, so its delay is included in the data processing delay of the reverse order unit. Shift register cache, cache brings delay Shoot, so The processing delay of the reverse order unit is shoot.

[0035] Accordingly, The processing delay of the layer in reverse order processing layer is The total processing delay of the circuit that sorts the sequence in reverse order according to the index value is shoot.

[0036] It is understandable that there is a fixed one-to-one correspondence between the input sequence length and the processing delay, which facilitates timing design.

[0037] In a possible implementation, the reversal unit of each reversal processing layer is encapsulated as a module, and the module has an input end and an output end.

[0038] It can be understood that a standardized reversal processing layer can be implemented through encapsulation. When designing the number of reversal processing layers according to the power of the input sequence, the encapsulated reversal processing layers can be selected and connected in sequence to form a circuit that sorts the sequence in reverse order according to the index value. This circuit can adapt to the index-based reversal requirements of input sequences of different lengths without making large-scale design adjustments to the circuit structure, and has great design and application flexibility.

[0039] See Figure 3 As shown, Figure 3 The flowchart of the method for implementing the method of sorting a sequence in reverse order according to the index value provided in the embodiment of the present application is based on the circuit execution as described above, and the method includes: obtaining an input sequence, the length of the input sequence is , An integer greater than 1; the input sequence is connected in order of layer numbers The input sequence is input from the reverse order processing layer with the smallest layer number, and is converted into an output sequence from the reverse order processing layer with the largest layer number; in each reverse order processing layer, the input sequence is input into multiple reverse order units connected in numerical order, and the number of reverse order units is the same as the layer number of the reverse order processing layer, and the input sequence is input from the reverse order unit with the largest number and is output from the reverse order unit with the smallest number; In the reverse order unit, the input sequence starts with The length of the input is divided into equal parts according to the input order. 4 paragraphs, is a positive integer, keeping the sequence positions of the first and last segments unchanged, and swapping the sequence positions of the two middle segments.

[0040] In one possible implementation, In the reverse order unit, the input sequence starts with The length of the input is divided into equal parts according to the input order. 4 paragraphs, is a positive integer, keeping the sequence positions of the first and last segments unchanged, and swapping the sequence positions of the middle two segments; this is achieved by the following steps: extracting the control signal from the index value in the input sequence; selecting according to the control signal: taking the elements of the input sequence directly as the output of the reversal unit, and adjusting the length to Alternatively, the elements of the input sequence are fed into a shift register of length The shift register is used, and the output of the shift register is taken as the output of the reversing unit.

[0041] In a possible implementation, extracting a control signal from an index value of an input sequence includes: extracting the first bit of the index value of the input sequence from the lowest to the highest, starting from 0. and bit as the control signal.

[0042] Furthermore, when the control signal is 2'b10, the elements of the input sequence are directly used as the output of the reversal unit, and the length is adjusted to The output of the shift register is used as input; when the control signal is not 2'b10, the elements of the input sequence are sent to the length of The shift register is used, and the output of the shift register is taken as the output of the reversing unit.

[0043] It can be understood that the circuit and implementation method for sorting a sequence in reverse bit order according to index values ​​provided in the present application have the following effects: 1. Support for pipeline processing: The present application implements bit-reversal operations through layer-by-layer hierarchical and sequential processing, supports pipeline operation and does not have blocking signals; 2. Simple interface structure: The present application only includes one input port and one output port. The input port receives an input sequence input in index value order, and the output port outputs an output sequence in reverse bit order according to the index value. Compared with the CPU / MCU-based implementation solution, the interface is greatly simplified, which can greatly improve design flexibility; 3. Design flexibility: The present application can select an integrated packaged reverse processing layer module to construct a layered architecture based on the length of the input sequence, and flexibly adjust the layered architecture according to the change in the length of the input sequence, thereby improving design flexibility; 4. Low hardware resource consumption: The present application only involves shift register caches, conditional multiplexers, or RAM resources and logic resources, and has only two control signals, which significantly reduces the hardware resource consumption compared to the CPU / MCU-based implementation solution; 5. Fixed processing delay: The processing delay of the present application has a fixed one-to-one correspondence with the sequence length, which facilitates timing design.

[0044] Please refer to Tables 1 to 4. This application also provides specific application examples to introduce in detail the circuit and method provided in this application to achieve the entire process of outputting the input sequence in reverse bit order according to the index value.

[0045] Assume that the length of the input sequence to be processed is 8=2 3 , that is, taking N=3, the circuit includes N-1=2 layers of reverse order processing layers, numbered one and two. The input of the first layer of reverse order processing serves as the input of the entire circuit, and the output of the second layer of reverse order processing serves as the output of the entire circuit. The number of reverse order units in each layer of reverse order processing is consistent with the layer number. The input of the highest-numbered reverse order unit in each layer serves as the input of the layer, and the output of the lowest-numbered reverse order unit serves as the output of the layer. The input sequence to be processed is input from the reverse order unit numbered 1 in the first layer, and the output sequence is output from the reverse order unit numbered 1 in the second layer. The structural design of the reverse order processing layer is shown in Table 1.

[0046] Table 1 Structural design of reverse order processing layer

[0047] The correspondence between the reverse order unit numbers and the internal structures of the reverse order units is shown in Table 2. The reverse order units with the same numbers in different reverse order processing layers have the same internal structure, so they will not be described separately by layer.

[0048] Table 2 Correspondence between reverse order unit number and reverse order unit internal structure

[0049] Where idx represents the index value.

[0050] Each reversal unit uses two conditional multiplexers and one shift register to divide the input sequence into four equal segments according to the length of the sequence it processes. It then swaps the positions of the two middle segments before outputting them. Table 3 shows the processing results of an input sequence of length 8 after passing through each reversal layer.

[0051] Table 3 Processing results of the input sequence of length 8 after each layer of reverse processing

[0052] Table 4 gives the numbers as an example j =2. The data states of the input, shift register, and output of the reverse order unit at different clock beats. Where X represents the state when there is no valid data, and the output of the shift register is delayed by one beat compared to the internal state of the shift register.

[0053] Table 4 j =2 reverse order unit state table of each part under different clock beats

[0054] In this application example, the processing delay of the conditional multiplexer is 1 beat, and the sequence delay caused by the shift register buffer is the same as the length of the shift register. The circuit includes two layers of reverse order processing, the first layer includes one reverse order unit, the second layer includes two reverse order units, each reverse order unit includes two conditional multiplexers, and thus the entire circuit includes six conditional multiplexers.

[0055] In the entire circuit, the conditional multiplexer generates a total delay of 3 beats, and the shift register buffer generates a total delay of 4 beats, resulting in a total circuit delay of 4 + 3 = 7 beats. In terms of resource consumption, six conditional multiplexers and four storage cells for the shift register are used, resulting in minimal resource consumption.

[0056] The above specific implementation methods further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A circuit for sorting a sequence in reverse order according to index values, characterized in that: include: Multiple layers of reverse order processing layers, the number of layers of the reverse order processing layers is determined by the length of the input sequence, the length of the input sequence is , the number of layers of the reverse order processing layer is , is an integer greater than 1, and the multiple layers of the reversal processing layers are connected in order of layer numbers, the input end of the reversal processing layer with the smallest layer number receives the input sequence input in sequence, and the output end of the reversal processing layer with the largest layer number outputs the output sequence in bit-reversed order according to the index value; Each reversing processing layer includes: a plurality of reversing units, the number of the reversing units being the same as the layer number of the reversing processing layer, the plurality of reversing units being connected in order of number, the input end of the reversing unit with the largest number serving as the input end of the reversing processing layer, and the output end of the reversing unit with the smallest number serving as the output end of the reversing processing layer; Among them, No. The reverse order unit is used to The length of the input sequence is processed and the sequence is evenly divided into 4 paragraphs, is a positive integer, keeping the sequence positions of the first and last segments unchanged, and swapping the sequence positions of the two middle segments.

2. The circuit for sorting a sequence in reverse order according to an index value according to claim 1, wherein: The reverse order unit includes: two conditional multiplexers and a shift register; The length of the shift register is , The number of the reverse processing unit; The conditional multiplexer is used to select, according to the control signal, to: connect the input end of the shift register with the output end of the shift register, and connect the input end of the reversing processing unit with the output end of the reversing processing unit; or connect the input end of the shift register with the input end of the reversing processing unit, and connect the output end of the shift register with the output end of the reversing unit; The control signal is determined by the index value of the input sequence.

3. The circuit for sorting a sequence in reverse order according to index values ​​according to claim 2, wherein: The control signal is the number of bits in the input sequence index value from low to high starting from 0. and When the control signal is 2'b10, the input end of the shift register is connected to the output end of the shift register, and the input end of the reversing processing unit is connected to the output end of the reversing processing unit; when the control signal is not 2'b10, the input end of the shift register is connected to the input end of the reversing processing unit, and the output end of the shift register is connected to the output end of the reversing unit.

4. The circuit for sorting a sequence in reverse order according to index values ​​according to claim 2, wherein: The reverse order unit includes: When the value is greater than the threshold, RAM resources are used to replace the shift register resources, and logic resources are used to replace the conditional multiplexer.

5. The circuit for sorting a sequence in reverse order according to index values ​​according to claim 1, wherein: The processing delay of the circuit is: Shoot, among them The layer number of the reverse processing layer, The length of the input sequence is raised to the power of 2.

6. The circuit for sorting a sequence in reverse order according to index values ​​according to claim 1, wherein: The reversal unit of each reversal processing layer is encapsulated as a module, and the module has an input end and an output end.

7. A method for sorting a sequence in reverse order according to index values, characterized in that: Based on the implementation circuit according to any one of claims 1 to 6, the method includes: Get an input sequence, the length of the input sequence is , is an integer greater than 1; Input sequence input is connected in order of layer number In the reverse order processing layer, the input sequence is input from the reverse order processing layer with the smallest layer number, and is converted into an output sequence from the reverse order processing layer with the largest layer number; In each reverse order processing layer, the input sequence is input into multiple reverse order units connected in numerical order. The number of reverse order units is the same as the layer number of the reverse order processing layer. The input sequence is input from the reverse order unit with the largest number and output from the reverse order unit with the smallest number. Among them, in the number In the reverse order unit, the input sequence starts with The length of the input is divided into equal parts according to the input order. 4 paragraphs, is a positive integer, keeping the sequence positions of the first and last segments unchanged, and swapping the sequence positions of the two middle segments.

8. The method for implementing sorting a sequence in reverse order according to index values ​​according to claim 7, characterized in that: In the number In the reverse order unit, the input sequence starts with The length of the input is divided into equal parts according to the input order. 4 paragraphs, is a positive integer, keeping the sequence positions of the first and last segments unchanged, and swapping the sequence positions of the two middle segments; this is achieved by the following steps: Extract control signals from index values ​​in the input sequence; According to the control signal selection: the elements of the input sequence are directly used as the output of the reverse order unit, and the length is adjusted to Alternatively, the elements of the input sequence are fed into a shift register of length The shift register is used, and the output of the shift register is taken as the output of the reversing unit.

9. The method for implementing the reverse order sorting of a sequence according to index values ​​according to claim 8, characterized in that: Extract control signals from the index values ​​of the input sequence; including: Extract the index value bits from the input sequence from low to high starting from 0. and bit as the control signal.

10. The method for implementing sorting a sequence in reverse order according to index values ​​according to claim 9, characterized in that: When the control signal is 2'b10, the elements of the input sequence are directly used as the output of the reverse order unit and the length is adjusted to The output of the shift register is used as input; when the control signal is not 2'b10, the elements of the input sequence are sent to the length of The shift register is used, and the output of the shift register is taken as the output of the reversing unit.

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