Method and system for identifying internal configuration defects of siC mosfet device

Abstract

The application discloses a SiC MOSFET device internal structure defect identification method and system, relates to the technical field of semiconductor device defect detection and characterization, and comprises the following steps: defect accident tracing is performed on a SiC MOSFET device, and a multilayer defect tracing network is constructed; the device is measured in multiple modes, and measured characteristic data is obtained; on this basis, device layer, chip layer and lattice layer defect identification is performed, and first, second and third defect identification results are obtained; defect characteristic tracing correction is performed on the results, and a multilayer defect atlas is obtained. The application solves the technical problem that traditional detection means cannot comprehensively and accurately identify defects of each layer of the semiconductor device SiC MOSFET, resulting in incomplete and inaccurate data, and making it difficult to meet the accurate evaluation and reliable control of the defects, achieves comprehensive and accurate identification of defects of each layer of the SiC MOSFET, the data is comprehensive and accurate, and meets the technical effect of meeting the accurate evaluation and reliable control requirements of the defects.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device defect detection and characterization, in particular to a SiC MOSFET device internal structure defect identification method and system. BACKGROUND

[0002] SiC MOSFET, as a core device of wide bandgap semiconductor, is widely used in new energy, power electronics and other fields. Its internal structure defects directly affect the performance and reliability of the device, and accurate identification is crucial. In the prior art, single physical field testing, local structure analysis and other means are often used for defect detection. These methods play a certain role in simple structure devices or stable working conditions. However, with the increasing demand for device performance, these traditional techniques have limitations when applied to SiC MOSFET. Due to the multi-layer structure and multi-physical field coupling characteristics of the device layer, chip layer and lattice layer in the device, traditional methods cannot accurately identify defects in each layer, resulting in incomplete and inaccurate data, which cannot meet the needs of accurate evaluation and reliable control of defects. SUMMARY

[0003] The present application provides a SiC MOSFET device internal structure defect identification method and system to solve the technical problem that traditional detection methods cannot accurately identify defects in each layer of a semiconductor device SiC MOSFET, resulting in incomplete and inaccurate data, which cannot meet the needs of accurate evaluation and reliable control of defects.

[0004] In a first aspect, the present application provides a SiC MOSFET device internal structure defect identification method, which includes: performing multi-physical field coupling simulation defect accident tracing on a SiC MOSFET device, and constructing a multi-layer defect tracing network; performing multi-modal measurement on the SiC MOSFET device to obtain measured feature data; identifying device layer defects based on the measured feature data to obtain a first defect identification result; identifying chip layer defects based on the measured feature data to obtain a second defect identification result; identifying lattice layer defects based on the measured feature data to obtain a third defect identification result; and performing defect feature tracing correction on the first defect identification result, the second defect identification result and the third defect identification result based on the multi-layer defect tracing network to obtain a multi-layer defect atlas.

[0005] In a possible implementation, a three-dimensional reconstruction is performed on the SiC MOSFET device to obtain a transistor model; a multi-physical field coupling optimization is performed on the SiC MOSFET device to obtain a coupling field space; a device layer defect accident backtracking is performed on the transistor model according to the coupling field space to construct a device layer defect backtracking network; a chip layer defect accident backtracking is performed on the transistor model according to the coupling field space to construct a chip layer defect backtracking network; a lattice layer defect accident backtracking is performed on the transistor model according to the coupling field space to construct a lattice layer defect backtracking network; and the multi-layer defect backtracking network is generated according to the device layer defect backtracking network, the chip layer defect backtracking network, and the lattice layer defect backtracking network.

[0006] In a possible implementation, a multi-physical field operation record retrieval is performed on the SiC MOSFET device to obtain a running joint field set; a trigger credibility evaluation is performed on each running joint field in the running joint field set to obtain a field trigger credibility coefficient; the running joint field set is screened according to a trigger credibility threshold based on the field trigger credibility coefficient to obtain a credible joint field set; a pairwise twin evaluation is performed on the credible joint field set to obtain a twin evaluation matrix; and the coupling field space is generated by performing twin suppression optimization on the credible joint field set based on the twin evaluation matrix and according to a twin evaluation threshold.

[0007] In a possible implementation, a plurality of device layer defect accident simulations are respectively performed on the transistor model according to each coupling field in the coupling field space to obtain a plurality of defect accident simulation sets; a defect type identification is performed on the plurality of defect accident simulation sets to determine a plurality of accident defect type characteristics; an intermediate cause backtracking is performed on the plurality of accident defect type characteristics according to the plurality of defect accident simulation sets to obtain a plurality of defect intermediate causes; a basic cause backtracking is performed on the plurality of defect intermediate causes according to the plurality of defect accident simulation sets to obtain a plurality of defect basic causes; a plurality of device layer defect accident paths are constructed according to the plurality of accident defect type characteristics, the plurality of defect intermediate causes, and the plurality of defect basic causes, and the device layer defect backtracking network is built according to the plurality of device layer defect accident paths.

[0008] In a possible implementation, a device layer feature capture is performed according to the measured feature data to construct a device layer detection sequence; a plurality of device layer defect analysis models are obtained by supervising training of a plurality of learners according to a device layer detection sample set and a device layer defect analysis sample set; the device layer detection sequence is input into the plurality of device layer defect analysis models to obtain a plurality of device layer defect analysis results; and the first defect identification result is generated by confidence fusion according to the plurality of device layer defect analysis results.

[0009] In a possible implementation, the device layer defect tracing network is used to trace and correct defect features of the first defect identification result, to obtain a device layer defect correction result; the chip layer defect tracing network is used to trace and correct defect features of the second defect identification result, to obtain a chip layer defect correction result; the lattice layer defect tracing network is used to trace and correct defect features of the third defect identification result, to obtain a lattice layer defect correction result; and the device layer defect correction result, the chip layer defect correction result and the lattice layer defect correction result are used to construct the multi-level defect atlas.

[0010] In a possible implementation, the device layer defect tracing network is used to trace defect incident paths of the first defect identification result, to obtain a set of registered defect incident paths; the device layer defect tracing network is used to evolve defect incidents of a device layer detection sequence, to obtain a set of defect incident evolution paths; the set of registered defect incident paths is used to compensate and correct the first defect identification result, to obtain a first defect correction result; the set of defect incident evolution paths is used to feed back and correct the first defect identification result, to obtain a second defect correction result; and the first defect correction result and the second defect correction result are fused, to generate the device layer defect correction result.

[0011] In a possible implementation, a multi-modal detection factor is obtained, and the multi-modal detection factor includes an electrical mode, a thermal mode, an optical mode, a structural mode and an acoustic mode; the SiC MOSFET device is detected according to the multi-modal detection factor, to obtain a transistor detection data set; and the transistor detection data set is cleaned, to generate the measured feature data.

[0012] In a possible implementation, a multi-level defect early warning signal is generated according to the multi-level defect atlas.

[0013] In a second aspect of the present application, a SiC MOSFET device internal structure defect identification system is provided, which comprises: a multi-layer defect tracing network construction module, configured to perform multi-physical field coupling simulation defect accident tracing on a SiC MOSFET device, and construct a multi-layer defect tracing network; a measured characteristic data acquisition module, configured to perform multi-modal measurement on the SiC MOSFET device, and obtain measured characteristic data; a defect identification first result acquisition module, configured to perform device layer defect identification according to the measured characteristic data, and obtain a defect identification first result; a defect identification second result acquisition module, configured to perform chip layer defect identification according to the measured characteristic data, and obtain a defect identification second result; a defect identification third result acquisition module, configured to perform lattice layer defect identification according to the measured characteristic data, and obtain a defect identification third result; and a multi-layer defect atlas acquisition module, configured to perform defect characteristic tracing correction on the defect identification first result, the defect identification second result and the defect identification third result according to the multi-layer defect tracing network, and obtain a multi-layer defect atlas.

[0014] The one or more technical solutions provided in the present application have at least the following technical effects or advantages:

[0015] In the present application, the multi-physical field coupling simulation defect accident tracing is performed on the SiC MOSFET device to construct a multi-layer defect tracing network, the multi-modal measurement is performed on the device to obtain measured characteristic data, and after the device layer, chip layer and lattice layer defect identification, the defect characteristic tracing correction is performed on the identification results in combination with the multi-layer defect tracing network, so as to obtain a multi-layer defect atlas, accurately identify the internal structure defects of the device, make the SiC MOSFET device internal structure defect identification result more accurate and reliable, achieve the comprehensive and accurate identification of the defects of each layer of the SiC MOSFET, and achieve the technical effect of meeting the defect accurate evaluation and reliable control requirements with comprehensive and accurate data. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is a flowchart of the SiC MOSFET device internal structure defect identification method provided by the embodiments of the present application.

[0018] Figure 2 is a structural schematic diagram of the SiC MOSFET device internal structure defect identification system provided by the embodiments of the present application.

[0019] Explanation of reference signs: multi-layer defect traceability network construction module 1, measured feature data acquisition module 2, defect identification first result acquisition module 3, defect identification second result acquisition module 4, defect identification third result acquisition module 5, multi-layer defect atlas acquisition module 6. DETAILED DESCRIPTION

[0020] The application provides a SiC MOSFET device internal structure defect identification method and system, which is used to solve the technical problem that the traditional detection method cannot comprehensively and accurately identify defects of each layer of a semiconductor device SiC MOSFET, resulting in incomplete and inaccurate data, and being difficult to meet the accurate evaluation and reliable control of the defects.

[0021] The technical solutions in the embodiments of the application will be clearly and completely described in the specification of the application combined with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the application.

[0022] It should be noted that the terms "first", "second", etc. in the specification and the above drawings of the application are used to distinguish similar objects, and do not necessarily mean a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or server including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] Embodiment one, as shown in the SiC MOSFET device internal structure defect identification method, wherein the method comprises: Figure 1

[0024] Step A100: Multi-physical field coupling simulation defect accident traceability is performed on the SiC MOSFET device to construct a multi-layer defect traceability network.

[0025] In the embodiments of the application, the SiC MOSFET device is a metal-oxide-semiconductor field effect transistor with silicon carbide as the material, which has a multi-layer structure such as a device layer, a chip layer, a lattice layer, and has a multi-physical field coupling characteristic.

[0026] ​Specifically, the SiC MOSFET device is three-dimensionally reconstructed to obtain a transistor model, a multi-physical field coupling optimization is performed to obtain a coupling field space, and then the transistor model is traced back to defects of a device layer, a chip layer and a lattice layer based on the coupling field space to construct a tracing network of each layer, and finally a multi-layer defect tracing network is generated, and the specific steps are described in detail in A110-A160.

[0027] Step A200: Multi-modal measurement is performed on the SiC MOSFET device to obtain measured feature data.

[0028] Optionally, multi-modal detection factors including electrical, thermal and other modalities are obtained, and transistor detection data sets are obtained based on the device, and the measured feature data is generated after data cleaning, and the specific steps are described in detail in A210-A230.

[0029] Step A300: Defect identification of the device layer is performed according to the measured feature data to obtain a first defect identification result.

[0030] In the embodiments of the present application, the device layer is a level that contains key functional structures such as the gate, source, drain, oxide layer and interconnection layer of the SiC MOSFET device, and is the main structural layer for realizing the electrical function of the device, and the defects thereof will directly affect the electrical performance of the device.

[0031] In an embodiment of the present application, a detection sequence is constructed based on the device layer features captured from the measured feature data, a plurality of learners are trained with a sample set to obtain analysis models, and after a plurality of analysis results are obtained by inputting the sequence, confidence fusion is performed to generate the first defect identification result, and the specific steps are described in detail in A310-A340.

[0032] Step A400: Chip layer defect identification is performed according to the measured feature data to obtain a second defect identification result.

[0033] In the embodiments of the present application, the chip layer is a level that contains packaging and connection structures such as chip packaging, bonding wires and pads, and is responsible for the physical protection of the device and the connection with external circuits, and the defects thereof mainly involve packaging integrity and connection reliability.

[0034] Specifically, when the chip layer defect identification is performed based on the measured feature data, the same as steps A310-A340, first, the chip layer feature is captured to construct a detection sequence. Key features related to the chip layer are extracted from the measured feature data, including packaging stress distribution, bonding wire resistance, pad oxidation area ratio, chip edge cracking length, etc. According to the chip working time sequence, such as 0-20s, these features are collected every 0.5s to form a chip layer detection sequence containing multiple time points, which include stress features, bonding features, pad features and edge structure features.

[0035] Then, a plurality of learners are trained according to the chip layer detection sample set and the defect analysis sample set. The detection sample set contains 800 groups of data, 200 groups of package cracking, 250 groups of bonding failure, 150 groups of pad corrosion, and 200 groups of normal state. The defect analysis sample set corresponds to the defect type label of each group of data. Three kinds of learners are selected, including gradient boosting tree (tree number 50-100), K nearest neighbor (K value 5-10), and naive Bayes. The training set and the validation set are divided according to 7:3 for supervised training. Iteration is performed until the average accuracy of the validation set reaches more than 90%. Three chip layer defect analysis models are obtained, such as the gradient boosting tree with an identification accuracy of 93% for package cracking, the K nearest neighbor with an identification accuracy of 91% for bonding failure.

[0036] Then, the chip layer detection sequence is input into the plurality of analysis models, and each model outputs a corresponding defect analysis result. For example, after a certain sequence is input, the gradient boosting tree determines package cracking with a confidence of 0.85, the K nearest neighbor determines package cracking with a confidence of 0.78, and the naive Bayes determines bonding failure with a confidence of 0.82. A plurality of analysis results containing defect types and confidences are formed.

[0037] Finally, confidence fusion is performed according to the plurality of analysis results. The weights are set based on the model validation set accuracy, the gradient boosting tree is 0.4, the K nearest neighbor is 0.3, and the naive Bayes is 0.3. The weighted confidence of each defect type is calculated: package cracking is 0.85*0.4+0.78*0.3+0*0.3=0.574, bonding failure is 0*0.4+0*0.3+0.82*0.3=0.246, and the type corresponding to the highest value is taken as the result to generate the second defect identification result.

[0038] Through the above feature capturing, model training, result analysis and fusion steps, accurate identification of chip layer defects is realized, and the generated second defect identification result provides a reliable initial basis for subsequent correction based on the multi-layer defect tracing network.

[0039] Step A500: performing lattice layer defect identification according to the measured feature data to obtain a third defect identification result.

[0040] In the embodiments of the present application, the lattice layer is a crystal structure layer level of SiC MOSFET material, involving atomic arrangement, lattice structure and other microscopic crystal characteristics, and is a basic material layer of the device. Defects such as dislocations and vacancies will affect the intrinsic properties of the material.

[0041] Specifically, according to the measured characteristic data, the lattice layer defect recognition is performed, and the steps A310-A340 are the same. First, the lattice layer feature is captured to construct a detection sequence. The key features related to the lattice layer are extracted from the measured characteristic data, including the lattice distortion rate, the vacancy density, the dislocation density, and the grain boundary offset. These data are organized according to the spatial distribution characteristics of different regions of the lattice to construct a lattice layer detection sequence, which includes the distortion characteristics, the vacancy characteristics, the dislocation characteristics, and the grain boundary characteristics.

[0042] Then, the lattice layer detection sample set and the defect analysis sample set are used to train multiple learners. The detection sample set contains 600 groups of data, including 200 groups of dislocation defects, 150 groups of vacancy aggregation, 100 groups of grain boundary slip, and 150 groups of normal states. The defect analysis sample set corresponds to the defect type label of each group of data. Three kinds of learners are selected, including a deep belief network (3-layer hidden layer, node numbers are 64, 32, and 16), a random forest (tree depth 8-12, tree number 100), and an AdaBoost (base classifier is a decision tree, iteration number 50). The training set and the validation set are divided according to the ratio of 8:2 for supervised training. The iteration is performed until the average accuracy of the validation set is stable at more than 91%. Three lattice layer defect analysis models are obtained, such as the deep belief network for recognizing dislocation defects with an accuracy of 94%, and the random forest for recognizing vacancy aggregation with an accuracy of 92%.

[0043] Then, the lattice layer detection sequence is input into multiple analysis models, and each model outputs the corresponding defect analysis result. For example, after inputting a certain detection sequence, the deep belief network determines that it is a dislocation defect with a confidence of 0.89, the random forest determines that it is a dislocation defect with a confidence of 0.82, and the AdaBoost determines that it is a vacancy aggregation with a confidence of 0.78. Multiple analysis results including the defect type and the corresponding confidence are formed.

[0044] After that, the multiple analysis results are fused according to the confidence. The weights of the models on the validation set are set based on the accuracy, which are 0.4 for the deep belief network, 0.35 for the random forest, and 0.25 for the AdaBoost. The weighted confidence of each defect type is calculated: the dislocation defect is 0.89*0.4+0.82*0.35+0*0.25=0.645, the vacancy aggregation is 0*0.4+0*0.35+0.78*0.25=0.195, and the defect type corresponding to the highest value is taken as the final result to generate the third defect recognition result.

[0045] Through the above steps of feature capture, model training, result analysis, and fusion, the accurate recognition of the lattice layer defect is realized, and the third defect recognition result generated provides a reliable initial basis for the subsequent correction based on the multi-layer defect tracing network.

[0046] Step A600: Defect feature trace correction is performed on the defect identification first result, the defect identification second result and the defect identification third result according to the multi-layer defect trace network to obtain a multi-layer defect atlas.

[0047] Specifically, the multi-layer defect trace network is used to perform defect feature trace correction on the defect identification first, second and third results to obtain defect correction results of each layer, and a multi-layer defect atlas is constructed according to the defect correction results of each layer. Details are described in A610-A640.

[0048] Further, the step A100 in the method provided in the embodiments of the present application includes:

[0049] A110: A transistor model is obtained by performing three-dimensional reconstruction on the SiC MOSFET device.

[0050] A120: A coupled field space is obtained by performing multi-physical field coupling optimization on the SiC MOSFET device.

[0051] A130: A device layer defect trace network is constructed by performing device layer defect accident trace on the transistor model according to the coupled field space.

[0052] A140: A chip layer defect trace network is constructed by performing chip layer defect accident trace on the transistor model according to the coupled field space.

[0053] A150: A lattice layer defect trace network is constructed by performing lattice layer defect accident trace on the transistor model according to the coupled field space.

[0054] A160: The multi-layer defect trace network is generated according to the device layer defect trace network, the chip layer defect trace network and the lattice layer defect trace network.

[0055] Specifically, the transistor model is obtained by performing three-dimensional reconstruction on the SiC MOSFET device. First, a person skilled in the art obtains physical structure data of the device by using high-resolution imaging technology. For example, a scanning electron microscope (SEM) is used to scan the cross section of the device to obtain two-dimensional topographic images of key structures such as source, drain and gate, and to record parameters such as gate oxide layer thickness and source-drain spacing; at the same time, transmission electron microscopy (TEM) is used to observe the atomic arrangement of the lattice layer to obtain crystallographic data such as the lattice constant of hexagonal SiC.

[0056] Subsequently, the multi-dimensional physical structure data is imported into a three-dimensional modeling software, multi-layer two-dimensional images are integrated by an image stitching algorithm, and the spatial position relationship of each structure is located by using a feature matching technology. For example, the two-dimensional scanning data of the gate region is spatially aligned with the structure data of the source and drain, the three-dimensional distribution of the gate in the device layer is determined, and the relative position error of each structure in the model is ensured to be less than 0.5 μm.

[0057] During the modeling process, a person skilled in the art also needs to supplement details in combination with the design parameters of the device, such as the doping concentration distribution, the electrode material thickness, etc. For example, the doping concentration of the drift region is set according to the process documents formed during the design and manufacturing process of the SiC MOSFET device, and the model size is repeatedly calibrated by comparing with the actually measured device physical size, so that the key size deviation of the three-dimensional model is controlled within 3%, and finally a transistor model meeting the requirements is obtained.

[0058] Next, the SiC MOSFET device is subjected to a multi-physical field operation record retrieval to obtain a running joint field set, a trigger credibility evaluation is performed on each running joint field to obtain a field trigger credibility coefficient, a credible joint field set is obtained based on the coefficient and a trigger credibility threshold, a pairwise twin evaluation is performed on the credible joint field set to obtain a twin evaluation matrix, and finally a coupled field space is generated based on the matrix and a twin evaluation threshold. The specific steps are described in detail in A121-A125.

[0059] Then, according to each coupled field in the coupled field space, a plurality of device layer defect accident simulations are performed on the transistor model to obtain a defect accident simulation set, based on which the defect type characteristics are identified, the intermediate and basic causes are traced back, and a plurality of device layer defect accident paths are constructed in combination with these, and then a device layer defect tracing network is built. The specific steps are described in detail in A131-A135.

[0060] After that, according to each coupled field in the coupled field space, a chip layer defect accident is traced back to the transistor model, which is the same as steps A131-A135. It is assumed that the coupled field space contains 18 coupled fields, each corresponding to a specific combination of electric field, thermal field and stress field, such as an electric field strength of 5e5 V / m, a temperature of 85°C and a stress of 110 MPa. For each coupled field, 10 chip layer defect accident simulations are performed on the transistor model, and the simulation scenarios include chip package cracking, bond wire falling off, pad oxidation, etc. The chip surface temperature distribution, bond resistance, packaging stress change and other parameters are recorded each time, and 180 groups of data are generated from the 18 coupled fields, constituting a chip layer defect accident simulation set.

[0061] From the chip layer defect accident simulation set, the characteristic parameters of the defect type characteristics are extracted. For example, package cracking can be manifested as a sudden increase in chip edge stress exceeding 200 MPa, accompanied by a local temperature rise of more than 15°C; wire disconnection is accompanied by a sudden increase in bonding resistance from 0.02Ω to more than 5Ω. Through feature matching, it is determined that there are three typical defects in the chip layer, namely package cracking, bonding failure and pad corrosion, each of which corresponds to a clear stress, resistance or temperature change characteristic.

[0062] Based on the chip layer defect accident simulation set, the intermediate causes of each defect type characteristic are traced back. For example, the simulation data shows that before the package cracking occurs, the interface stress caused by the difference in the thermal expansion coefficient between the packaging material and the chip continues to rise, and the number of temperature cycles exceeds 500 times; the intermediate cause of the bonding failure is that the current density at the bonding site exceeds 1e4A / cm², causing local overheating.

[0063] Further trace the basic causes of the intermediate causes. Analysis of the simulation set shows that the basic cause of package cracking is improper selection of packaging materials; the basic cause of bonding failure is that the bonding process pressure is insufficient, resulting in a high initial value of the contact resistance. Accordingly, a chip layer defect accident path is constructed, such as improper material selection→ interface stress accumulation→ package cracking, forming multiple typical paths, and then a chip layer defect tracing network is built.

[0064] Subsequently, when tracing the lattice layer defect accidents of the transistor model, similarly to steps A131-A135, 18 coupling fields of the coupling field space are also used, and 10 times of lattice layer defect simulation are performed under each coupling field. The simulation scenarios include lattice dislocation, vacancy aggregation, grain boundary slip, etc., and parameters such as lattice distortion rate, carrier mobility, and defect density are recorded to generate 180 groups of lattice layer defect accident simulation sets.

[0065] From the lattice layer defect accident simulation set, the defect type characteristics are identified: for example, dislocation defects can cause a decrease in carrier mobility of more than 30% and a lattice distortion rate of more than 5%; vacancy aggregation is manifested as a 2-fold increase in leakage current compared to the normal state, with a defect density of >1e5 / cm². Through feature comparison, it is determined that there are two core defects in the lattice layer, namely dislocation and vacancy.

[0066] The intermediate causes of the lattice layer defects are traced back: dislocation defects occur before the local temperature of the lattice exceeds 180°C and the stress exceeds 150 MPa; the intermediate cause of vacancy aggregation is the abnormal atomic diffusion rate in the growth direction of the lattice. Further trace the basic causes: dislocations are caused by temperature fluctuations during crystal growth, and vacancy aggregation is caused by uneven impurity concentration during doping. Accordingly, a lattice layer defect accident path is constructed, such as temperature fluctuations→ local overheating of the lattice→ formation of dislocations, forming multiple typical paths, and building a lattice layer defect tracing network.

[0067] Finally, the device layer, chip layer, and lattice layer defect traceability networks are integrated, and the association relationship of each layer network is established. For example, lattice layer dislocations can cause local electric field concentration of the device layer gate oxide layer, and then trigger the gate short circuit; the chip layer bonding failure can aggravate the uneven current distribution of the device layer. By defining the causal association threshold of each layer defect, such as when the lattice dislocation density is greater than a certain value, the device layer leakage current abnormality probability is increased by a corresponding value, the three-layer network is connected into an organic whole, and a multi-layer defect traceability network is generated.

[0068] Through the simulation, identification, traceability, and path construction of the chip layer and lattice layer defects, and the integration of each layer network, the multi-layer defect traceability network generated completely covers the defect evolution path of different levels of devices and the association between levels, providing comprehensive network support for subsequent traceability correction of multi-level defect identification results.

[0069] Further, step A120 in the method provided in the embodiments of the application includes:

[0070] A121: performing multi-physical field operation record retrieval on the SiC MOSFET device to obtain an operation joint field set.

[0071] A122: performing trigger credibility evaluation according to each operation joint field in the operation joint field set to obtain a field trigger credibility coefficient.

[0072] A123: based on the field trigger credibility coefficients, performing trigger credibility threshold optimization screening on the operation joint field set to obtain a credible joint field set.

[0073] A124: performing pairwise twin evaluation according to the credible joint field set to obtain a twin evaluation matrix.

[0074] A125: based on the twin evaluation matrix, performing twin suppression optimization on the credible joint field set according to a twin evaluation threshold to generate the coupling field space.

[0075] In the embodiments of the application, the twin evaluation is an evaluation performed on each two operation joint fields in the credible joint field set in the process of constructing the coupling field space.

[0076] Optionally, to obtain the coupling field space by multi-physical field coupling optimization of the SiC MOSFET device, first, the multi-physical field operation records of the device under different working conditions need to be retrieved, including dynamic change data of physical fields such as electric field, thermal field, and stress field. For example, the electric field distribution, temperature field distribution, and mechanical stress data of the device under the rated voltage of 1200V and different load currents (5A, 10A, 15A) are collected, and an operation joint field set containing 80 different field combinations is formed by integration.

[0077] Then, trigger credible evaluation is performed on each running joint field in the running joint field set, and the frequency of each field in the set is taken as the trigger credibility coefficient. Assuming that in 80 groups of data, a joint field such as electric field intensity 6e5V / m + temperature 90℃ + stress 120MPa appears 12 times, and its trigger credibility coefficient is 12 / 80=0.15; another joint field appears 4 times, and the coefficient is 0.05.

[0078] Based on the trigger credibility coefficient of each field, the trigger credibility threshold is set to 0.1, and the joint field with a coefficient greater than or equal to 0.1 is screened out to form a credible joint field set. Assuming that the above 80 groups of data can retain 25 groups of joint fields that meet the conditions, the determination of the credible threshold is mainly based on the actual frequency of the running joint field and the demand for defect accident tracing of those skilled in the art, and the purpose is to screen joint fields with high enough frequency and representative for defect accident simulation.

[0079] Subsequently, pairwise twin evaluation is performed on the credible joint field set, and a twin evaluation matrix is generated by calculating the similarity of field strength distribution, temperature gradient and other characteristics. The element (i, j) in the matrix represents the similarity of the i th and j th joint fields, and the value range is 0-1. Specifically, for each joint field in the set, each group contains specific parameter distribution of electric field, thermal field, stress field and other multi-physical fields, and is compared with all other joint fields one by one. During the evaluation process, key characteristic parameters of each group of joint fields will be extracted, such as the spatial distribution peak value and gradient of electric field intensity, the isotherm distribution density of temperature field, the maximum stress value and distribution uniformity of stress field, etc. The matching degree of these key characteristic parameters is calculated to obtain the similarity of two joint fields. If the deviation of electric field peak value of two joint fields is less than 5%, the temperature gradient change trend coincides more than 90%, and the stress distribution uniformity difference is less than 10%, the similarity is close to 1; if the characteristic parameters differ significantly, such as the deviation of electric field peak value is more than 30% and the temperature gradient trend is completely opposite, the similarity is close to 0. The final twin evaluation matrix has the same dimension as the number of groups in the credible joint field set, such as 25 groups of joint fields corresponding to a 25x25 matrix. The element value in the i th row and j th column of the matrix represents the comprehensive similarity of the i th and j th joint fields, which provides a quantitative basis for subsequent screening of redundant fields and optimization of coupled field space based on the twin evaluation threshold.

[0080] Finally, the twin evaluation threshold is set to 0.8, and the credible joint field set is optimized by twin suppression. If the similarity of two joint fields is greater than or equal to 0.8, the more representative one of the two is retained and the redundancy is reduced. After optimization, the credible joint fields that meet the conditions are retained to generate the coupled field space.

[0081] Through the above steps, the screening and optimization of multi-physical field running data are realized, and an accurate and efficient coupled field space is obtained, which provides a reliable field basis for subsequent defect accident tracing based on transistor model at each layer.

[0082] Further, the method provided in the embodiments of the present application comprises the following step A130:

[0083] A131: According to each coupling field in the coupling field space, multiple device layer defect accident simulations are respectively performed on the transistor model to obtain each defect accident simulation set.

[0084] A132: According to each defect accident simulation set, defect type identification is performed to determine each accident defect type feature.

[0085] A133: According to each defect accident simulation set, intermediate cause tracing is performed on each accident defect type feature to obtain each defect intermediate cause.

[0086] A134: According to each defect accident simulation set, basic cause tracing is performed on each defect intermediate cause to obtain each defect basic cause.

[0087] A135: According to each accident defect type feature, each defect intermediate cause and each defect basic cause, multiple device layer defect accident paths are constructed, and the device layer defect tracing network is built according to the multiple device layer defect accident paths.

[0088] In the embodiments of the present application, the device layer defect accident refers to a defect related accident occurring in the device layer of the SiC MOSFET device, including the hierarchical defects of the structures such as gate, source, drain, oxide layer and interconnection layer, and specifically including gate oxide layer abnormality, gate short circuit, source-drain contact failure, interconnection layer fracture and the like.

[0089] Specifically, first, according to each coupling field in the coupling field space, device layer defect accident simulation is performed on the transistor model. For example, it is assumed that the coupling field space contains 18 coupling fields, each coupling field corresponds to a specific combination of electric field, thermal field and stress field, such as an electric field intensity of 6e5V / m, a temperature of 90℃ and a stress of 120MPa. For each coupling field, 10 device layer defect accident simulations are performed on the transistor model, and the simulation content covers scenarios such as gate oxide layer abnormality, gate short circuit and source-drain contact failure. Dynamic parameters such as drain current, gate voltage and temperature are recorded each time, thereby generating 10 sets of simulation data for each coupling field, and 180 sets of data for 18 coupling fields, constituting each defect accident simulation set.

[0090] Then, feature parameters are extracted from each defect accident simulation set, and defect types are identified by comparing the parameter change patterns of different simulation data. For example, abnormal gate oxide layer will show a characteristic of sudden increase of leakage current and sudden drop of gate voltage, and source-drain contact failure will show a characteristic of a sharp increase in on-resistance. After feature matching, the three types of device layer defect types are determined, which are gate oxide layer defect, electrode contact defect and interconnection layer fracture, and each type corresponds to a clear current-voltage change characteristic.

[0091] Based on each defect accident simulation set, the intermediate causes of the determined defect type characteristics are traced back. Taking the gate oxide layer defect as an example, it is found from the simulation data that before the occurrence of the defect, the local electric field strength exceeds 8e6V / m and the temperature is continuously higher than 150℃. These parameter abnormalities are the intermediate causes of the gate oxide layer defect. The intermediate causes of the electrode contact defect are the sudden increase of the contact resistance after the stage fluctuation of the contact resistance.

[0092] The basic causes of each defect are further traced back according to the intermediate causes of each defect. Analysis of the defect accident simulation set shows that the excessively high local electric field is caused by the unevenness of the gate edge due to the lithography process deviation, the excessively high temperature is caused by the unreasonable design of the device heat dissipation channel, and the fluctuation of the contact resistance is caused by the uneven thickness of the metallization layer, which are the basic causes of the corresponding defects.

[0093] Finally, according to the defect type characteristics of each accident, the intermediate causes of each defect and the basic causes of each defect, a device layer defect accident path is constructed. For example, the path of the gate oxide layer defect is lithography deviation → excessively high local electric field → sudden increase of leakage current, and the path of the electrode contact defect is uneven thickness of the metallization layer → fluctuation of the contact resistance → sudden increase of on-resistance. A plurality of typical paths are constructed. The device layer defect tracing network is built by integrating these paths, which contains the correlation of each path and the parameter threshold.

[0094] Through the above simulation identification and tracing and path construction steps, the device layer defect tracing network built clearly presents the complete evolution chain of the device layer defect from the cause to the characteristic, which provides a structured reference for the subsequent tracing and correction of the device layer defect identification result.

[0095] Further, step A300 in the method provided by the embodiment of the application includes:

[0096] A310: capturing device layer features according to the measured feature data, and constructing a device layer detection sequence.

[0097] A320: supervising and training a plurality of learners according to the device layer detection sample set and the device layer defect analysis sample set, to obtain a plurality of device layer defect analysis models.

[0098] A330: inputting the device layer detection sequence into the plurality of device layer defect analysis models, to obtain a plurality of device layer defect analysis results.

[0099] A340: performing confidence fusion according to the plurality of device layer defect analysis results to generate the first defect identification result.

[0100] Specifically, first, device layer feature capture is performed according to the measured feature data, and key features related to device layers, such as gate, oxide layer, source and drain, etc. are extracted from the multi-modal measured data. For example, the peak current and the on-resistance mutation value are extracted from the electrical modal data, the local temperature abnormal points of the device layer, such as the area exceeding 150°C, are extracted from the thermal modal data, and the edge distortion parameters of the gate edge, such as the edge unevenness > 2 μm, are extracted from the optical modal data. These features are organized according to the time sequence (such as 0-10s of device operation, collecting once every 0.1s) or spatial distribution (such as 5 monitoring points in the gate area) to construct a device layer detection sequence, which contains electrical, thermal, optical and structural features.

[0101] Then, when training the plurality of learners according to the device layer detection sample set and the defect analysis sample set, the sample set needs to cover various device layer defect cases. The detection sample set contains 1000 groups of detection sequences of normal devices and defective devices, including 200 groups of gate oxide layer defects, 300 groups of electrode contact failures, 250 groups of interconnection layer fractures, and 250 groups of normal states. The defect analysis sample set corresponds to the defect type label of each sequence. Three different learners are selected: random forest (tree depth 10-15), support vector machine (kernel function RBF), and convolutional neural network (3 layers of convolutional layers). Supervised training is adopted, and the training set and the validation set are divided in the ratio of 8:2. Iterative training is performed until the accuracy of the validation set is stable at more than 92%, and three device layer defect analysis models with different performances are obtained, such as the random forest contact failure identification accuracy of 95%, and the convolutional neural network oxide layer defect identification accuracy of 94%.

[0102] Then, the device layer detection sequence is input into the plurality of analysis models, and each model outputs a corresponding defect analysis result. For example, after inputting a certain detection sequence, the random forest model determines that it is an electrode contact failure with a confidence of 0.88, the support vector machine determines that it is an electrode contact failure with a confidence of 0.76, and the convolutional neural network determines that it is a gate oxide layer defect with a confidence of 0.91. These results contain the defect type and the corresponding confidence, forming a plurality of device layer defect analysis results.

[0103] Finally, according to the multiple analysis results, confidence fusion is performed, and a weighted fusion strategy is adopted, the weights are set based on the accuracy of the model on the verification set, the weight of the random forest is 0.35, the weight of the support vector machine is 0.25, and the weight of the convolutional neural network is 0.4. The weighted confidence of each defect type is calculated: the electrode contact is 0.88*0.35+0.76*0.25+0*0.4=0.468, the gate oxide layer defect is 0*0.35+0*0.25+0.91*0.4=0.364, and the defect type corresponding to the highest value is taken as the final result, and the first defect recognition result is generated.

[0104] Through the above feature capture, model training, result analysis and fusion steps, accurate identification of device layer defects is realized, and the first defect recognition result generated provides a reliable initial basis for subsequent correction based on the multi-layer defect tracing network.

[0105] Further, the method provided in the embodiment of the application comprises the following steps A600:

[0106] A610: According to the device layer defect tracing network, the first defect recognition result is corrected for defect feature tracing, and a device layer defect correction result is obtained.

[0107] A620: According to the chip layer defect tracing network, the second defect recognition result is corrected for defect feature tracing, and a chip layer defect correction result is obtained.

[0108] A630: According to the lattice layer defect tracing network, the third defect recognition result is corrected for defect feature tracing, and a lattice layer defect correction result is obtained.

[0109] A640: According to the device layer defect correction result, the chip layer defect correction result and the lattice layer defect correction result, the multi-layer defect atlas is constructed.

[0110] Specifically, according to the chip layer defect tracing network, the second defect recognition result is corrected for defect feature tracing, and steps A611-A615 are the same. First, the recognition result is corrected for defect accident path tracing, such as judging as package cracking. From the multiple paths of the chip layer defect tracing network, such as the package cracking path and the bonding failure path, the paths with a matching degree of more than 80% with the recognition result features (such as edge stress sudden increase and temperature abnormal rise) are selected to form a registered defect accident path set, which includes multiple package cracking related paths.

[0111] Then, according to the chip layer defect tracking network, the chip layer detection sequence is tracked, such as the encapsulation stress rising from 100 MPa to 250 MPa within 0-15 s, the bonding resistance rising from 0.02 Ω to 1 Ω, the defect accident evolution is simulated, and the possible development trend is predicted, such as the stress reaching 300 MPa within 8 s in the future, the encapsulation cracking length extending to 300 μm, and a defect accident evolution path set of multiple evolution paths is generated.

[0112] According to the registered defect accident path set, the second result of defect identification is compensated and corrected, and the intermediate causes (such as interface stress accumulation) and basic causes (such as the thermal expansion coefficient mismatch of encapsulation materials) recorded in the path are supplemented. If the original result does not mention these information, it is improved to form the first result of defect correction.

[0113] According to the defect accident evolution path set, the identification result is feedback corrected, and the feature change predicted by evolution, such as stress continues to rise, is adjusted. If the original confidence is 0.82 and the evolution coincidence degree reaches 90%, it is increased to 0.88 to generate the second result of defect correction. The two correction results are fused, the cause information and the adjusted confidence are retained, and the chip layer defect correction result is generated.

[0114] Then, the correction process of the third result of lattice layer defect identification is the same: according to the lattice layer defect tracking network, the identification result, such as the dislocation defect tracking registered defect accident path set, contains multiple dislocation paths with a matching degree of more than 85%; the lattice layer detection sequence is evolved and simulated, such as the lattice distortion rate rising from 2% to 6% within 0-12 s, and the carrier mobility decreasing by 25%; the future 6 s is predicted, the evolution path set is generated; the compensation correction is carried out, the intermediate causes such as local overheating and the basic causes such as crystal growth temperature fluctuation are supplemented, and the feedback correction is carried out, for example, the confidence is adjusted from 0.79 to 0.86, and the lattice layer defect correction result is obtained after fusion.

[0115] Finally, a multi-level defect map is constructed, the correction results of the device layer, the chip layer and the lattice layer are integrated, and the interlayer correlation is analyzed: for example, the lattice layer dislocation may cause local electric field concentration in the device layer, and the chip layer bonding failure may aggravate the uneven current distribution in the device layer. By defining the correlation threshold, such as the lattice dislocation density > corresponding value, the device layer leakage current abnormal probability is increased by a corresponding value, the defect information of each layer is organized according to the spatial distribution and causal relationship, and a multi-level defect map containing defect type, cause, evolution trend and interlayer correlation is formed.

[0116] Through the correction of the chip layer and the lattice layer defect identification results and the integration of the information of each layer, the multi-level defect map constructed comprehensively reflects the defect characteristics and correlation of each layer of the device, and provides complete visual basis for accurate defect analysis and early warning.

[0117] Further, the method provided in the embodiments of the present application includes the following step A610:

[0118] A611: According to the device layer defect tracking network, defect accident path tracking is performed on the defect identification first result to obtain a registered defect accident path set.

[0119] A612: According to the device layer defect tracking network, defect accident evolution is performed on the device layer detection sequence to obtain a defect accident evolution path set.

[0120] A613: According to the registered defect accident path set, compensation correction is performed on the defect identification first result to obtain a defect correction first result.

[0121] A614: According to the defect accident evolution path set, feedback correction is performed on the defect identification first result to obtain a defect correction second result.

[0122] A615: The defect correction first result and the defect correction second result are fused to generate the device layer defect correction result.

[0123] In one embodiment, first, according to the device layer defect tracking network, defect accident path tracking is performed on the defect identification first result. From the multiple device layer defect accident paths, such as gate oxide layer defect paths and electrode contact defect paths, which have been constructed in the network, paths matching the defect identification first result are matched, for example, paths determined as being related to gate oxide layer abnormalities. By calculating the similarity between the defect characteristics in the identification result, such as sudden increase in leakage current and sudden drop in gate voltage, and the type characteristics of the accident defects in each path, paths with a matching degree exceeding 85% are screened out to form a registered defect accident path set, which includes multiple paths highly related to gate oxide layer defects.

[0124] Then, according to the device layer defect tracking network, defect accident evolution is performed on the device layer detection sequence. The time sequence characteristics in the detection sequence, such as the increase of leakage current from 1 mA to 50 mA and the increase of temperature from 25 °C to 120 °C within 0-10 s, are input, and the defect evolution rules recorded in the network, such as the correlation between the increase of 10 mA of leakage current and the increase of 20 °C of temperature, are used to simulate the possible defect development paths of the sequence. For example, based on the current detection sequence, it is predicted that the leakage current will increase to 80 mA and the local electric field strength will reach 9e5 V / m within 5 s, and a defect accident evolution path set with multiple possible trends is generated.

[0125] Then, when compensating and correcting the first defect identification result according to the registration defect accident path set, the intermediate cause and the basic cause recorded in the path set, such as the local electric field being too high in the gate oxide layer defect path -> photolithography process deviation, are used to supplement the cause information not covered in the original identification result. If the original result only determines that the defect type is a gate oxide layer anomaly and does not mention the cause, the intermediate cause: local electric field intensity 8e6V / m; the basic cause: photolithography deviation 0.5μm, are supplemented to form the first corrected result of the defect.

[0126] Then, when the first defect identification result is fed back and corrected according to the defect accident evolution path set, the feature changes predicted based on the evolution path, such as the leakage current increasing to 80mA, are used to adjust the confidence of the original identification result. If the confidence of the original result on the gate oxide layer anomaly is 0.8, and the evolution path shows that the degree of agreement between the feature changes and the defect is 92%, the confidence is increased to 0.88, and possible misjudgments are corrected, such as excluding the possibility of an electrode contact defect, to generate the second corrected result of the defect.

[0127] Finally, when the first corrected result of the defect and the second corrected result of the defect are fused, a feature fusion strategy is used: the cause supplement information in the first result and the confidence adjustment in the second result are retained, and more accurate values are taken for repeated features, such as the temperature parameter taking the measured predicted value in the evolution path as the standard, to finally generate a device layer defect correction result containing the defect type, the cause, the confidence, and the evolution trend.

[0128] Through the above path tracing, evolution simulation, double correction and fusion steps, accurate correction of the device layer defect identification result is realized, and more accurate and comprehensive device layer defect information is provided for the construction of a multi-level defect map.

[0129] Further, the step A200 in the method provided by the embodiment of the application includes:

[0130] A210: Obtain a multi-modal detection factor, wherein the multi-modal detection factor includes an electrical mode, a thermal mode, an optical mode, a structural mode and an acoustic mode.

[0131] A220: Detect the SiC MOSFET device according to the multi-modal detection factor to obtain a transistor detection data set.

[0132] A230: Perform data cleaning on the transistor detection data set to generate the measured feature data.

[0133] Optionally, when the multi-modal detection factor is obtained, first, the specific detection parameters and means of each mode are determined. The specific detection parameters and means of the multi-modal detection factor are shown in Table 1.

[0134] Table 1: Multimodal detection factor detection parameter table

[0135]

[0136] When the SiC MOSFET device is detected according to the above-mentioned multimodal detection factor, a preset procedure needs to be performed. In the process of gradually increasing the gate voltage from 0 to 1200V, the drain current and the on-resistance are recorded every 10V, and a total of 120 groups of data are obtained; in the thermal mode, when the device works at the rated power, 10 minutes of continuous shooting are performed every second, and 600 frames of temperature distribution images are obtained; in the optical mode, the device surface is scanned in a range of 500x500μm, and 200 defect images are generated; in the structural mode, the device cross-section is photographed at three different positions, and 50 SEM images are obtained; in the acoustic mode, the device is scanned three times, and 30 groups of acoustic data are generated each time, and finally the transistor detection data set containing 120 groups of electrical data, 600 frames of thermal images, 200 optical images, 50 SEM images and 90 groups of acoustic data is formed.

[0137] Then, the transistor detection data set is cleaned, and corresponding measures are taken for different types of data. In the electrical data, the abnormal values caused by instantaneous instrument interference are removed, such as data in which the drain current suddenly exceeds 100mA, and the remaining valid data is retained; in the thermal image, the fuzzy frames with a clarity lower than the threshold, such as a pixel gray scale standard deviation <50, are deleted; the optical and SEM images are preprocessed by an image preprocessing algorithm, and the resolution is unified to 1024x1024 pixels, and the edge noise is removed; the acoustic data is filtered by a wavelet filtering algorithm to filter out low-frequency noise below 10MHz, and the signal-to-noise ratio is improved to more than 25dB. After cleaning, the measured feature data containing various valid data is generated.

[0138] Through the above steps, the multimodal detection data is systematically obtained and processed, and the generated measured feature data is complete and accurate, which provides reliable raw data support for subsequent defect recognition at the device layer, chip layer and lattice layer.

[0139] Further, step A600 in the method provided in the embodiment of the application comprises:

[0140] A710: generating a multi-level defect early warning signal according to the multi-level defect map. In one embodiment, when generating a multi-level defect early warning signal according to the multi-level defect map, first, the defect characteristics of the device layer, the chip layer, and the lattice layer in the map are quantitatively graded. For example, for the device layer, it is divided into three levels of slight (10-30 mA), medium (30-60 mA), and severe (>60 mA) according to the leakage current value; the chip layer is divided into three levels of low (<150 MPa), medium (150-250 MPa), and high (>250 MPa) according to the packaging stress; and the lattice layer is divided into three levels of low (<1e4 / cm²), medium (1e4-5e4 / cm²), and high (>5e4 / cm²) according to the dislocation density, and each level corresponds to a specific characteristic parameter threshold.

[0141] Then, the association rules between each level of defects and the early warning level are established. When a single level has a severe defect, such as a device layer leakage current of 70 mA, or two or more levels have a medium or higher defect, such as a chip layer stress of 200 MPa and a lattice layer dislocation density of 3e4 / cm², a high-level early warning is triggered; a single level of medium defect or multiple levels of slight defect triggers a medium-level early warning; only a single level of slight defect triggers a low-level early warning. At the same time, the early warning level is adjusted in combination with the interlayer association relationship. If the high-density dislocation of the lattice layer has caused a medium leakage current of the device layer, the early warning level is upgraded from the original medium level to the high level.

[0142] Subsequently, the future state is predicted based on the defect evolution path in the map. If the current device layer leakage current is 40 mA (medium), and the evolution path shows that it will rise to 65 mA (severe) within 10 hours, a high-level early warning is triggered in advance; if the chip layer stress is 180 MPa (medium), it is predicted that it will stabilize at 170 MPa within 24 hours, and the medium-level early warning is maintained.

[0143] Finally, an early warning signal containing specific information is generated: the level, type, current level, associated defects, prediction trend, and response suggestion of the defect. For example, a high-level early warning signal may be a device layer gate oxide layer defect with a leakage current of 68 mA, which is severe, associated with a lattice layer dislocation density of 6e4 / cm² (high), and predicted to reach 80 mA within 8 hours, suggesting that the gate oxide layer and lattice structure should be immediately shut down for detection.

[0144] Through quantitative grading, correlation analysis, and trend prediction of defects, the generated multi-level defect early warning signal can accurately reflect the severity and potential risk of defects at each level, providing a clear basis for timely maintenance and fault prevention of SiC MOSFET devices.

[0145] In summary, the SiC MOSFET device internal structure defect identification method provided by the embodiments of the present application has the following technical effects: the present application constructs a multi-layer defect tracing network by performing multi-physical field coupling simulation defect accident tracing on the SiC MOSFET device, obtains measured characteristic data by performing multi-modal measurement on the device, corrects the identification results by combining the multi-layer defect tracing network after performing defect identification on the device layer, chip layer and lattice layer, thereby obtaining a multi-level defect atlas, accurately identifying the internal structure defects of the device, making the SiC MOSFET device internal structure defect identification result more accurate and reliable, achieving comprehensive and accurate identification of defects of each layer of the SiC MOSFET, and achieving the technical effects of comprehensive and accurate data, meeting the requirements of accurate defect evaluation and reliable control.

[0146] Embodiment two, as shown in the same inventive concept as the preceding embodiment one, the present application embodiment provides a SiC MOSFET device internal structure defect identification system, the system comprises: Figure 2

[0147] A multi-layer defect tracing network construction module 1 is configured to perform multi-physical field coupling simulation defect accident tracing on the SiC MOSFET device and construct a multi-layer defect tracing network.

[0148] A measured characteristic data acquisition module 2 is configured to perform multi-modal measurement on the SiC MOSFET device and obtain measured characteristic data.

[0149] A defect identification first result acquisition module 3 is configured to perform device layer defect identification according to the measured characteristic data and obtain a defect identification first result.

[0150] A defect identification second result acquisition module 4 is configured to perform chip layer defect identification according to the measured characteristic data and obtain a defect identification second result.

[0151] A defect identification third result acquisition module 5 is configured to perform lattice layer defect identification according to the measured characteristic data and obtain a defect identification third result.

[0152] A multi-level defect atlas acquisition module 6 is configured to perform defect characteristic tracing correction on the defect identification first result, the defect identification second result and the defect identification third result according to the multi-layer defect tracing network and obtain a multi-level defect atlas.

[0153] Further, the multi-layer defect tracing network construction module 1 is configured to perform the following steps: ​

[0154] According to the SiC MOSFET device, a three-dimensional reconstruction is performed to obtain a transistor model; according to the SiC MOSFET device, a multi-physical field coupling optimization is performed to obtain a coupling field space; according to the coupling field space, a device layer defect accident trace is performed on the transistor model to construct a device layer defect trace network; according to the coupling field space, a chip layer defect accident trace is performed on the transistor model to construct a chip layer defect trace network; according to the coupling field space, a lattice layer defect accident trace is performed on the transistor model to construct a lattice layer defect trace network; and according to the device layer defect trace network, the chip layer defect trace network and the lattice layer defect trace network, the multi-layer defect trace network is generated.

[0155] Further, the multi-layer defect trace network construction module 1 is used to perform the following steps: a multi-physical field operation record retrieval is performed on the SiC MOSFET device to obtain a running joint field set; a trigger credibility evaluation is performed according to each running joint field in the running joint field set to obtain a field trigger credibility coefficient; based on the field trigger credibility coefficient, the running joint field set is screened according to a trigger credibility threshold optimization to obtain a credible joint field set; a pairwise twin evaluation is performed according to the credible joint field set to obtain a twin evaluation matrix; based on the twin evaluation matrix, the credible joint field set is optimized according to a twin evaluation threshold to generate the coupling field space.

[0156] Further, the multi-layer defect trace network construction module 1 is used to perform the following steps:

[0157] According to each coupling field in the coupling field space, a plurality of device layer defect accident simulations are respectively performed on the transistor model to obtain a plurality of defect accident simulation sets; a defect type identification is performed according to the plurality of defect accident simulation sets to determine a plurality of accident defect type characteristics; an intermediate cause trace is performed on the plurality of accident defect type characteristics according to the plurality of defect accident simulation sets to obtain a plurality of defect intermediate causes; a basic cause trace is performed on the plurality of defect intermediate causes according to the plurality of defect accident simulation sets to obtain a plurality of defect basic causes; a plurality of device layer defect accident paths are constructed according to the plurality of accident defect type characteristics, the plurality of defect intermediate causes and the plurality of defect basic causes, and the device layer defect trace network is built according to the plurality of device layer defect accident paths.

[0158] Further, the defect identification first result acquisition module 3 is configured to perform the following steps: capturing device layer features according to the measured feature data, constructing a device layer detection sequence; supervising training of a plurality of learners according to a device layer detection sample set and a device layer defect analysis sample set, to obtain a plurality of device layer defect analysis models; inputting the device layer detection sequence into the plurality of device layer defect analysis models, to obtain a plurality of device layer defect analysis results; performing confidence fusion according to the plurality of device layer defect analysis results, to generate the defect identification first result.

[0159] Further, the multi-level defect map acquisition module 6 is configured to perform the following steps:

[0160] According to the device layer defect tracing network, the defect identification first result is corrected for defect features, to obtain a device layer defect correction result; according to the chip layer defect tracing network, the defect identification second result is corrected for defect features, to obtain a chip layer defect correction result; according to the lattice layer defect tracing network, the defect identification third result is corrected for defect features, to obtain a lattice layer defect correction result; according to the device layer defect correction result, the chip layer defect correction result, and the lattice layer defect correction result, the multi-level defect map is constructed.

[0161] Further, the multi-level defect map acquisition module 6 is configured to perform the following steps:

[0162] According to the device layer defect tracing network, the defect identification first result is corrected for defect features, to obtain a device layer defect correction result; according to the chip layer defect tracing network, the defect identification second result is corrected for defect features, to obtain a chip layer defect correction result; according to the lattice layer defect tracing network, the defect identification third result is corrected for defect features, to obtain a lattice layer defect correction result; according to the device layer defect correction result, the chip layer defect correction result, and the lattice layer defect correction result, the multi-level defect map is constructed.

[0163] Further, the measured feature data acquisition module 2 is configured to perform the following steps:

[0164] A plurality of modal detection factors are obtained, including electrical modalities, thermal modalities, optical modalities, structural modalities, and acoustic modalities; the SiC MOSFET device is detected according to the plurality of modal detection factors, to obtain a transistor detection data set; the transistor detection data set is data cleaned, to generate the measured feature data.

[0165] Further, the multi-level defect map acquisition module 6 is configured to perform the following steps:

[0166] According to the multi-level defect map, a multi-level defect early warning signal is generated.

[0167] The SiC MOSFET device internal structure defect identification system provided in the embodiments of the present application can execute the SiC MOSFET device internal structure defect identification method provided in any of the embodiments of the present application, and has the corresponding function modules and beneficial effects of the execution method. Although the present application makes various references to certain modules in the system according to the embodiments of the present application, however, any number of different modules can be used and run on the user terminal and / or server, each unit and module included is only divided according to the function logic, but is not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific name of each functional unit is only for convenient mutual differentiation, and does not limit the protection scope of the present application.

[0168] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application. In some cases, the actions or steps described in the present application can be executed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.

Claims

1. A method for identifying internal structural defects of a SiC MOSFET device, characterized by, The method comprises: Multi-physical field coupling simulation defect accident tracing is performed on the SiC MOSFET device to construct a multi-layer defect tracing network; Multi-modal measurement is performed on the SiC MOSFET device to obtain measured characteristic data; According to the measured characteristic data, device layer defect identification is performed to obtain a first defect identification result; According to the measured characteristic data, chip layer defect identification is performed to obtain a second defect identification result; According to the measured characteristic data, lattice layer defect identification is performed to obtain a third defect identification result; According to the multi-layer defect tracing network, the first defect identification result, the second defect identification result and the third defect identification result are corrected for defect characteristics to obtain a multi-layer defect atlas; Multi-physical field coupling simulation defect accident tracing is performed on the SiC MOSFET device to construct a multi-layer defect tracing network, comprising: According to the SiC MOSFET device, a transistor model is reconstructed in three dimensions to obtain a transistor model; According to the SiC MOSFET device, multi-physical field coupling optimization is performed to obtain a coupling field space; According to the coupling field space, device layer defect accident tracing is performed on the transistor model to construct a device layer defect tracing network; According to the coupling field space, chip layer defect accident tracing is performed on the transistor model to construct a chip layer defect tracing network; According to the coupling field space, lattice layer defect accident tracing is performed on the transistor model to construct a lattice layer defect tracing network; According to the device layer defect tracing network, the chip layer defect tracing network and the lattice layer defect tracing network, the multi-layer defect tracing network is generated; Multi-modal measurement is performed on the SiC MOSFET device to obtain measured characteristic data, comprising: A multi-modal detection factor is obtained, which includes electrical, thermal, optical, structural and acoustic modalities; According to the multi-modal detection factor, the SiC MOSFET device is detected to obtain a transistor detection data set; The transistor detection data set is cleaned to generate the measured characteristic data.

2. The SiC MOSFET device internal configuration defect identification method according to claim 1, characterized by, According to the SiC MOSFET device, multi-physical field coupling optimization is performed to obtain a coupling field space, comprising: Multi-physical field operation record retrieval is performed on the SiC MOSFET device to obtain a combined field set; Trigger credibility evaluation is performed according to each operation combined field in the combined field set to obtain a field trigger credibility coefficient; Based on the field trigger credibility coefficient, the combined field set is screened according to a trigger credibility threshold to obtain a credible combined field set; Pairwise twin evaluation is performed according to the credible combined field set to obtain a twin evaluation matrix; Based on the twin evaluation matrix, the credible combined field set is optimized for twin suppression according to a twin evaluation threshold to generate the coupling field space.

3. The SiC MOSFET device internal configuration defect identification method according to claim 1, characterized by, According to the coupling field space, device layer defect accident tracing is performed on the transistor model to construct a device layer defect tracing network, comprising: Based on each coupling field in the coupling field space, the transistor model is subjected to multiple device layer defect accident simulations to obtain each defect accident simulation set. Based on the aforementioned defect accident simulation sets, defect type identification is performed, and the characteristics of each accident defect type are determined. Based on the simulated sets of each defect incident, the intermediate causes of each defect type are traced to obtain the intermediate causes of each defect. Based on the simulated accident set of each defect, the basic causes of each defect are traced back to the intermediate causes of each defect to obtain the basic causes of each defect. Based on the characteristics of each accident defect type, the intermediate causes of each defect, and the basic causes of each defect, multiple device layer defect accident paths are constructed, and based on the multiple device layer defect accident paths, the device layer defect tracing network is built.

4. The SiC MOSFET device internal configuration defect identification method according to claim 1, characterized by, Based on the measured feature data, device layer defects are identified to obtain a first result of defect identification, including: Based on the measured feature data, device layer feature capture is performed to construct a device layer detection sequence; Multiple learners are trained under supervision based on the device layer detection sample set and the device layer defect analysis sample set to obtain multiple device layer defect analysis models. The device layer detection sequence is input into the multiple device layer defect analysis models to obtain multiple device layer defect analysis results; The first result of defect identification is generated by performing confidence fusion based on the analysis results of the multiple device layer defects.

5. The SiC MOSFET device internal configuration defect identification method according to claim 1, characterized by, Based on the multi-layer defect tracing network, defect feature tracing correction is performed on the first defect identification result, the second defect identification result, and the third defect identification result to obtain a multi-layer defect map, including: Based on the device layer defect tracing network, the first result of defect identification is corrected by defect feature tracing to obtain the device layer defect correction result. Based on the chip-layer defect tracing network, the second result of defect identification is corrected by defect feature tracing to obtain the chip-layer defect correction result; Based on the lattice layer defect tracing network, the third result of defect identification is corrected by defect feature tracing to obtain the lattice layer defect correction result. The multi-level defect map is constructed based on the device layer defect correction results, the chip layer defect correction results, and the lattice layer defect correction results.

6. The SiC MOSFET device internal configuration defect identification method according to claim 5, characterized by, Based on the device layer defect tracing network, the first result of defect identification is corrected by defect feature tracing to obtain the device layer defect correction result, including: Based on the device layer defect tracing network, the first result of defect identification is traced for defect incident paths to obtain a registered defect incident path set. Based on the device layer defect tracing network, the device layer detection sequence is subjected to defect accident evolution to obtain a set of defect accident evolution paths; The defect identification first result is compensated and corrected according to the registration defect incident path set to obtain the defect correction first result; Based on the defect incident evolution path set, the first defect identification result is fed back and corrected to obtain the second defect correction result; The first defect correction result and the second defect correction result are combined to generate the device layer defect correction result.

7. The SiC MOSFET device internal configuration defect identification method according to claim 1, characterized by, Based on the multi-level defect map, a multi-level defect early warning signal is generated.

8. A system for identifying internal construction defects in a SiC MOSFET device, the system comprising: The system for implementing the SiC MOSFET internal structure defect identification method according to any one of claims 1-7 comprises: a multi-layer defect tracing network construction module for defect accident tracing of multi-physical field coupling simulation of the SiC MOSFET device, and construction of a multi-layer defect tracing network; a measured characteristic data acquisition module for multi-modal measurement of the SiC MOSFET device to obtain measured characteristic data; a defect identification first result acquisition module for device layer defect identification according to the measured characteristic data to obtain a defect identification first result; a defect identification second result acquisition module for chip layer defect identification according to the measured characteristic data to obtain a defect identification second result; a defect identification third result acquisition module for lattice layer defect identification according to the measured characteristic data to obtain a defect identification third result; a multi-layer defect atlas acquisition module for defect characteristic tracing correction of the defect identification first result, the defect identification second result and the defect identification third result according to the multi-layer defect tracing network to obtain a multi-layer defect atlas.

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