Dual-rail asynchronous pipelined puf circuit, chip, and method of generating a response

Abstract

This invention discloses a dual-track asynchronous pipelined PUF circuit, chip, and response generation method. The PUF circuit includes multiple sequentially connected single-stage components, terminal components, and D flip-flops. Each single-stage component includes two MUX components, two DI latches, two two-input OR gates, and a two-input C unit. The front-end inputs of the two MUX components in the single-stage component are dual-track signals, and the two-input OR gates are used to combine the feedback signals of the two MUX components into a response signal. The terminal component includes two MUX components, two sink components, and a two-input C unit. The front-end of the terminal component is connected to the back-end of the last single-stage component. The two sink components are respectively connected to the D and CLK terminals of the D flip-flops. The output signal of the two-input C unit in the terminal component serves as an enable signal. The dual-track asynchronous pipelined PUF circuit provided by this invention is based on asynchronous dual-track logic, achieving a delay-insensitive design. The addition of a pipeline mechanism to the PUF circuit significantly improves its throughput.

Description

Technical Field

[0001] This invention belongs to the field of PUF circuit design technology, specifically relating to a dual-track asynchronous pipeline PUF circuit, chip, and response generation method. Background Technology

[0002] Physically Unclonable Function (PUF) circuits are a security technology that uses unavoidable process variations introduced during chip manufacturing as a unique identifier (ID) for each chip. It maps an input signal to an output signal in an unpredictable manner to characterize its internal delay characteristics, distinguishing different instances and giving each chip a unique ID. Even if two PUF instances have the same structure, random variations due to process limitations will result in two different output signals. The input signal of a PUF circuit is typically called the excitation, and the output signal is called the response. The excitation and response are mutually exclusive, and the response is unique for each device, serving as its ID. This ID can be used to create authentication protocols, enhancing the security of IoT systems and reducing device costs by eliminating the need to store confidential information in non-volatile memory.

[0003] However, existing PUF circuits have the following shortcomings:

[0004] 1. Current mainstream PUF circuits rely on the precise delay difference of the signal path. Environmental fluctuations (such as temperature and voltage) can easily cause response drift, requiring complex error correction mechanisms to compensate for stability, but this will introduce additional delay and resource overhead. Moreover, there is currently a lack of PUF circuits that can be used in environments where delay changes are large, such as third-generation semiconductors.

[0005] 2. Traditional PUF circuits require serial operation or long delay chains to generate multi-bit responses (e.g., a ring oscillator PUF requires multiple oscillation cycles, and an arbiter PUF requires the time to complete the entire path to generate a single bit response), which limits throughput. Meanwhile, the bit width of current mainstream PUF circuits is often 125 bits, 256 bits, or even higher. Therefore, low-throughput PUF circuits cannot meet the needs of high-performance, high-concurrency scenarios such as the Internet of Things, edge computing, and high-throughput data centers.

[0006] 3. Linear PUF circuits, such as ring oscillator PUFs and arbitrator PUFs, are vulnerable to attackers who can collect challenge-response pairs to build mathematical models (such as machine learning) and predict responses. Summary of the Invention

[0007] To address the problems existing in the above-mentioned background technology, the purpose of this invention is to provide a dual-track asynchronous pipelined PUF circuit, chip, and response generation method. Based on asynchronous dual-track logic, it realizes a delay-insensitive design, and at the same time, it adds a pipeline mechanism to the PUF circuit, which greatly improves the throughput of the PUF circuit.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] A dual-track asynchronous pipelined PUF circuit includes multiple sequentially connected single-stage components, terminal components, and D flip-flops, wherein:

[0010] The single-level component includes: two MUX components, two DI latches, two two-input OR gates, and one two-input C unit. The front end of the two MUX components in the single-level component receives a dual-track signal, and the rear end of the two MUX components in the single-level component is connected to the DI latches respectively. The rear end of the two DI latches is connected to the front end of the two MUX components in the next level single-level component. The two-input OR gates are used to combine the feedback signals of the two MUX components to the input signal into a response signal. The two-input C unit in the single-level component is used to input the feedback signals of the two DI latches to the corresponding MUX components.

[0011] The terminal component includes two MUX components, two Sink components, and a two-input C unit. The front ends of the two MUX components in the terminal component are respectively connected to the rear ends of the two DI latches in the last stage single-level component. The rear ends of the two MUX components in the terminal component are respectively connected to the Sink components. The feedback signals of the two Sink components are respectively connected to the D terminal and CLK terminal of the D flip-flop. The two-input C unit in the terminal component is used to input the feedback signals of the two Sink components to the corresponding MUX components. At the same time, the output signal of the two-input C unit in the terminal component is used as an enable signal.

[0012] Furthermore, the dual-track signal has three values ​​for both input and output in the PUF circuit: NULL, DATA0, and DATA1. The input and output always maintain a "DATA-NULL-DATA" cycle, with each DATA value separated by NULL, ensuring that the two DATA values ​​do not overwrite each other.

[0013] Furthermore, the excitation input to the dual-track asynchronous pipeline PUF circuit is connected to the control ports of the two MUX components. By controlling the data paths of the two MUX components, the delay of the data path is changed, thereby achieving the selection of the delay path. The data path includes a cross path and a parallel path. When the control signal is DATA0, the data path is a cross path; when the control signal is DATA1, the data path is a parallel path.

[0014] Furthermore, in the single-stage component, when one DI latch receives DATA or NULL first, it outputs to the next-stage single-stage component. When both DI latches in a single-stage component receive DATA or NULL, they request NULL or DATA from the next-stage single-stage component. Therefore, the dual-track asynchronous pipelined PUF circuit can operate normally regardless of the delay difference between the two inputs DATA or NULL.

[0015] The present invention further provides a chip including the dual-track asynchronous pipeline PUF circuit.

[0016] This invention further provides a method for generating a response in a dual-track asynchronous pipelined PUF circuit, comprising the following steps:

[0017] Step 1: After circuit initialization, the first-stage single-level component inputs DATA and excitation, which are passed to the DI latch of this stage through the path selected by the excitation. When both DI latches of this stage receive DATA, they request NULL from the next higher-level single-level component and excitation.

[0018] Step 2: After receiving the DATA output from the first-level single-level component, the second-level single-level component repeats the process of the first-level single-level component processing DATA in Step 1. At the same time, the first-level single-level component starts processing NULL of the stimulus input. After receiving NULL, the first-level single-level component sets all the double-track paths of its level to NULL until the second-level single-level component finishes processing DATA, that is, after ensuring that the second-level single-level component has stored DATA in the DI latch of its level, the DI latch of the first-level single-level component will allow NULL to be written. Only then will the next round of input and the next round of stimulus be requested.

[0019] Step 3: After receiving the DATA output from the second-level single-level component, the third-level single-level component repeats the process of the first-level single-level component processing DATA in Step 1. At the same time, the second-level single-level component repeats the process of the first-level single-level component processing NULL in Step 2. The first-level single-level component then receives and processes the input and stimulus for the next round.

[0020] Compared with the shortcomings and deficiencies of existing technologies, the present invention has the following beneficial effects:

[0021] 1. The dual-track asynchronous pipelined PUF circuit provided by this invention is based on asynchronous dual-track logic, achieving a delay-insensitive design, and can operate normally even when delay varies greatly or cannot be calculated. Due to the special characteristics of the dual-track logic circuit, it can support four input modes depending on the different input data of the PUF circuit. Alternating between these modes can introduce non-linear factors into the PUF, increasing the difficulty of machine learning to crack it.

[0022] 2. This invention incorporates a pipeline mechanism into the PUF circuit, significantly improving its throughput. Compared to a PUF circuit without pipeline, the generation response time of the dual-track asynchronous pipelined PUF circuit is greatly shortened. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of the dual-track asynchronous pipeline PUF circuit provided in an embodiment of the present invention;

[0024] Figure 2 This is a single-level component routing diagram provided in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of signal transmission of a single-stage component provided in an embodiment of the present invention;

[0026] Figure 4 This is the workflow of a single-level component provided in the embodiments of the present invention;

[0027] Figure 5 This is a schematic diagram of the pipeline operation mechanism of the dual-track asynchronous pipeline PUF circuit provided in this embodiment of the invention;

[0028] In the diagram: 1. Single-stage component, 2. Terminal component, 3. D flip-flop, 4. MUX component, 5. DI latch, 6. OR gate, 7. C unit, 8. Sink component. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0030] like Figure 1 As shown, a dual-track asynchronous pipeline PUF circuit includes multiple stages of single-stage components 1, terminal components 2, and D flip-flops 3 connected in sequence. The rear end of the last stage single-stage component 1 is connected to the front end of the terminal component 2, and the rear end of the terminal component 2 is connected to the D flip-flop 3.

[0031] The single-level component 1 includes: two MUX components 4, two DI latches 5, two two-input OR gates 6, and a two-input C unit 7. The front end of the two MUX components 4 in the single-level component 1 receives a dual-track signal, and the rear end of the two MUX components 4 in the single-level component 1 is connected to the DI latches 5 respectively. The rear end of the two DI latches 5 is connected to the front end of the two MUX components 4 in the next level single-level component 1 respectively. The two-input OR gates 6 are used to combine the feedback signals of the two MUX components 4 to the input signal into a response signal. The two-input C unit 7 in the single-level component 1 is used to input the feedback signals of the two DI latches 5 to the corresponding MUX components 4.

[0032] The end component 2 includes two MUX components 4, two Sink components 8, and a two-input C unit 7. The front ends of the two MUX components 4 in the end component 2 are respectively connected to the back ends of the two DI latches 5 in the last stage single-stage component 1. The back ends of the two MUX components 4 in the end component 2 are respectively connected to the Sink components 8. The feedback signals of the two Sink components 8 are respectively connected to the D terminal and CLK terminal of the D flip-flop 3. The two-input C unit 7 in the end component 2 is used to input the feedback signals of the two Sink components 8 into the corresponding MUX components 4. At the same time, the output signal of the two-input C unit 7 in the end component 2 is used as an enable signal.

[0033] The function of MUX component 4 is to output the input signals of the corresponding ports according to the control signals and output request signals. In the initial state, the input signals, control signals and output signals are all NULL, and all request signals are 0; when the control signal is DATA0 (01), channel 0 of MUX component 4 is opened and the value of input port 0 is output; when the control signal is DATA1 (10), channel 1 of MUX component 4 is opened and the value of input port 1 is output; after DATA is output, the control signal and the input channel selected in the previous round will be input as NULL, thus making the output NULL.

[0034] The initial state of DI latch 5 is that the output is NULL and the feedback signal Ko is 0. When the request signal Ki is 0, it means that the next stage requests DATA from this stage DI latch 5. When the input becomes DATA and the request signal Ki=0, the output becomes DATA and the feedback signal Ko becomes 1, that is, it requests NULL from the next stage. When the input becomes NULL and the request signal Ki=1, the output becomes NULL and the feedback signal Ko becomes 0, that is, it requests DATA from the next stage.

[0035] The two-input OR gate 6 combines the feedback signals of the two MUX components 4 to the input signal into a response signal. When the response signal is 0, it indicates a request for DATA, and when it is 1, it indicates a request for NULL.

[0036] Unit 7 of C outputs 0 when all inputs are 0, outputs 1 when all inputs are 1, and keeps the output unchanged in other cases.

[0037] Combination Figure 1 Explain the working mechanism of the dual-track asynchronous pipeline PUF circuit:

[0038] An n-bit dual-track asynchronous pipelined PUF circuit requires n-1 single-stage components 1 and one terminal component 2 connected together. Due to manufacturing errors, the two data points in a single signal processing cycle experience different path delays, resulting in different transition times for the feedback signals of the two sink components 8 from 0 to 1. Consequently, the final output of the D flip-flop 3 is either 0 or 1. The output of cell 7 in terminal component 2 is used as an enable signal. This enable signal only changes from 0 to 1 after both data points in a cycle have reached the sink. Using the enable signal allows this PUF to be applied not only to synchronous circuits but also to clockless asynchronous circuits.

[0039] like Figure 1 The diagram shows an n-bit dual-track asynchronous pipeline PUF circuit that requires n-bit dual-track excitation inputs. The dual-track excitation input ports of n-1 single-stage components 1 are Challenge[0], Challenge[1], Challenge[2], ..., Challenge[n-2], and the dual-track excitation input port of the end component 2 is Challenge[n-1]. The excitation has three values: NULL (00), DATA0 (01), and DATA1 (10). The input needs to always maintain a "DATA-NULL-DATA" cycle.

[0040] Assuming that an n-bit dual-track asynchronous pipelined PUF circuit receives k responses from input excitation, a k x n matrix of excitation is required, where each element is a single-bit excitation. Existing pipelineless PUF circuits input excitation by inputting all the excitation Challenge[0][0.....n] from a given row, obtaining the response, and then inputting the next row of excitation Challenge[1][0.....n], until the last row of excitation Challenge[k][0.....n] is input, resulting in k responses. However, the dual-track asynchronous pipelined PUF circuit does not use rows and columns as units, but rather each single-bit excitation. When the m-th stage component 1 requests DATA from the excitation input port Challenge[m] for the xth time, Challenge[m] needs to input the single-bit excitation at position Challenge[x][m] in the excitation matrix as quickly as possible. If NULL is requested from Challenge[m], then NULL is input.

[0041] The input ports Input0 and Input1 of the dual-track asynchronous pipeline PUF circuit also have three possible values: NULL (00), DATA0 (01), and DATA1 (10). A "DATA-NULL-DATA" cycle must always be maintained. For each input, whether it is DATA0 or DATA1 will not affect the path traversed by the MUX component 4 and DI latch 5 under excitation control. However, within each MUX component 4 and DI latch 5, whether the input DATA is DATA0 or DATA1 will change the path of that DATA within the component; that is, the C unit 7 that bit value 1 must pass through will be different. Figure 1 In Mux component 4, the numbers 0 and 1 indicate that this component is a 2-to-1 input / output path controller. When the control signal is DATA0, path 0 is selected; when the control signal is DATA1, path 1 is selected. Therefore, based on the different inputs DATA0 and DATA1, even under the same set of stimuli, the final response will be different. There are four input combinations: {DATA0, DATA0}, {DATA0, DATA1}, {DATA1, DATA0}, and {DATA1, DATA1}. Figure 1 Input0 (01, 10) and Input1 (01, 10) represent the input combination of Input0 and Input1 as {DATA0, DATA1}. Therefore, four operating modes of the PUF circuit can be set according to the four input combinations, thereby increasing the difficulty of deciphering the PUF circuit.

[0042] Existing arbiter PUF circuits operate by inputting a set of stimuli (nbits) and input signals (typically from 0 to 1), receiving a response, and then resetting. That is, the stimuli and input signals are all reset to 0, ensuring that all signals in the entire PUF are 0 before starting the next set of stimuli and input signals. In contrast, the dual-track asynchronous pipeline PUF circuit of this invention operates with each stage's single-stage component 1 operating independently. After each stage's single-stage component 1 completes the x-th round of DATA stimuli and DATA input signals, it can immediately request NULL from the stimuli and the previous stage's single-stage component 1 for reset. After resetting, it requests DATA again from the stimuli and the previous stage's single-stage component 1, and can immediately begin executing the next set of stimuli and input signals.

[0043] For an n-bit PUF circuit, assuming the maximum delay for the execution and reset of a single-stage component 1 is w, the number of responses required is 2^n. A non-pipelined PUF circuit requires approximately w × n × 2^n time, while a pipelined PUF circuit only requires w × (2^n + n - 1). It can be seen that the pipelined PUF circuit can save approximately n times the time. Currently, most PUF circuits require an excitation bit width of 128 bits or 256 bits, meaning n is 128 or 256. Therefore, using a pipelined PUF circuit can save approximately a hundred times the time for generating the response sequence. In other words, the response generation time of the dual-track asynchronous pipelined PUF circuit of this invention is significantly shortened.

[0044] The dual-track signal has three input and output values ​​in the PUF circuit: NULL (00), DATA0 (01), and DATA1 (10). The input and output always maintain a "DATA-NULL-DATA" cycle, with the preceding and following DATA always separated by NULL, ensuring that the two DATA do not overwrite each other.

[0045] The input excitation in the PUF circuit is connected to the control ports of the two MUX components 4. By controlling the data paths of the two MUX components 4, the delay of the data path is changed, thus achieving delay path selection. The branching of single-stage component 1 is as follows: Figure 2 As shown, when the control signal is DATA0, the data path is a cross path; when the control signal is DATA1, the data path is a parallel path.

[0046] Signal transmission of single-stage component 1, such as Figure 3 As shown, the two MUX components 4 are MUX_0 and MUX_1, with input ports Input_0 and Input_1 respectively. The response signals of the two-input OR gate 6 are Input_0_ack and Input_1_ack respectively. The two DI latches 5 are DI_latch_0 and DI_latch_1 respectively. The feedback signals of DI_latch_0 and DI_latch_1 are Input_0_ack and Input_1_ack respectively. The output signal of the C unit 7 is Comp.

[0047] Combination Figure 4 The workflow of single-level component 1 is explained as follows:

[0048] Under initial conditions, the state of single-level component 1 is: Figure 4As shown in ①, the outputs of DI_latch_0 and DI_latch_1 are both NULL, and Input_0_ack and Input_1_ack are both 0 (when Input_0_ack is 0, it indicates a request for DATA; when it is 1, it indicates a request for NULL), requesting DATA from the upper level. The request signals of MUX_0 and MUX_1 are both 0. In actual operation, the request signal of MUX_0 is consistent with the signal value of Input_0_ack, and the request signal of MUX_1 is consistent with the signal value of Input_1_ack. In the design phase, it is assumed that the two input signals of single-level component 1 arrive and are output simultaneously. However, in actual production, the introduction of errors may lead to the two data inputs becoming asynchronous.

[0049] like Figure 4 As shown in Figure ②, assume that the input signal of Input_0 arrives at the current single-level component 1 before Input_1, and the input signal of Input_0 is DATA0, and the input stimulus is DATA0. The DATA0 input of Input_0 will reach DI_latch_1 through MUX_1. When the request signal Ki of DI_latch_1 is 0, the output becomes DATA0, and at the same time, the feedback signal Ko of DI_latch_1, that is, the DI_latch_1_ack signal, becomes 1; E in DI latch 5 represents that its output is NULL, and V represents that its output is DATA;

[0050] like Figure 4 As shown in ③, when DATA1 of Input_1 arrives, DATA1 will reach DI_latch_0 through MUX_0. When the request signal Ki of DI_latch_0 is 0, the output becomes DATA1. At the same time, the feedback signal Ko of DI_latch_0, that is, the DI_latch_0_ack signal, becomes 1. Since the two inputs of C unit 7 are 1 at the same time, the output signal Comp of C unit 7 becomes 1. Then Input_0_ack and Input_1_ack become 1, requesting NULL from the next level.

[0051] like Figure 4As shown in section ④, after the current level component 1 completes the DATA transmission, the input excitations of MUX_0 and MUX_1 become NULL, and the NULL transmission begins. Assuming the NULL input of Input_0 arrives first, it reaches DI_latch_1 through MUX_1. When the request signal Ki of DI_latch_1 is 1, the output becomes NULL, and the DI_latch_1_ack signal becomes 0. When the NULL input of Input_1 arrives, it will reach DI_latch_0 through MUX_0. When the request signal Ki of DI_latch_0 is 1, the output becomes NULL, and the DI_latch_0_ack signal becomes 0. Since both inputs of unit C 7 are 0, the output signal Comp of unit C 7 becomes 0, and Input_0_ack and Input_1_ack become 0, requesting DATA from the next higher level. At this time, level component 1 returns to... Figure 4 As shown in ①, one cycle is completed.

[0052] In single-stage component 1, when one DI latch 5 receives DATA or NULL first, it outputs to the next single-stage component 1. When both DI latches 5 in single-stage component 1 receive DATA or NULL, they request NULL or DATA from the next single-stage component 1. Therefore, the dual-track asynchronous pipelined PUF circuit can operate normally regardless of the delay difference between the two inputs DATA or NULL.

[0053] The dual-track asynchronous pipeline PUF circuit of the present invention can be packaged inside a chip to form a chip that realizes the function of a dual-track asynchronous pipeline PUF circuit.

[0054] The pipeline operation mechanism of the dual-track asynchronous pipeline PUF circuit is as follows: Figure 5 As shown, the method for generating the response is as follows:

[0055] Step 1, the state of the circuit after initialization is as follows: Figure 5 As shown in ①, the first-level single-stage component 1 receives DATA and a stimulus. Since the stimulus for this stage is DATA1, it is passed to the DI latch 5 of this stage through the stimulus selection path. When both DI latches 5 of this stage receive DATA, they request NULL from the next higher-level single-stage component 1 and the stimulus. Its state is as follows. Figure 5 As shown in ②;

[0056] Step 2: After receiving the DATA output from the first-level single-stage component 1, the second-level single-stage component 1 repeats the DATA processing process of the first-level single-stage component 1 in Step 1. Simultaneously, the first-level single-stage component 1 begins processing NULL values ​​for the stimulus input. Upon receiving a NULL value, the first-level single-stage component 1 sets all double-track paths in its current stage to NULL. This process continues until the second-level single-stage component 1 has finished processing the DATA, ensuring that the second-level single-stage component 1 has stored the DATA in its current stage's DI latch 5. Only then will the DI latch 5 of the first-level single-stage component 1 allow writing NULL values, and only then will it request the next round of input and the next round of stimulus. Its state is as follows: Figure 5 As shown in ③;

[0057] Step 3: After receiving the DATA output from the second-level single-level component 1, the third-level single-level component 1 repeats the process of the first-level single-level component 1 processing DATA in Step 1. Simultaneously, the second-level single-level component 1 repeats the process of the first-level single-level component 1 processing NULL in Step 2. The first-level single-level component 1 then receives and processes the input and stimulus for the next round, and its state is as follows. Figure 5 As shown in ④.

[0058] As mentioned in the pipeline operation mechanism above, for single-level component 1, it will only allow receiving NULL or DATA sent by the previous single-level component 1 after the next-level single-level component 1 has ensured that it has received DATA or NULL sent by its own single-level component 1. Therefore, the dual-track asynchronous pipeline PUF circuit itself can operate normally without assuming circuit delay, that is, it can always operate correctly regardless of how large the circuit delay is.

[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dual-track asynchronous pipeline PUF circuit, characterized in that, It includes multiple interconnected single-stage components, terminal components, and D flip-flops, wherein: The single-level component includes: two MUX components, two DI latches, two two-input OR gates, and one two-input C unit. The front end of the two MUX components in the single-level component receives a dual-track signal, and the rear end of the two MUX components in the single-level component is connected to the DI latches respectively. The rear end of the two DI latches is connected to the front end of the two MUX components in the next level single-level component. The two-input OR gates are used to combine the feedback signals of the two MUX components to the input signal into a response signal. The two-input C unit in the single-level component is used to input the feedback signals of the two DI latches to the corresponding MUX components. The terminal component includes: two MUX components, two Sink components, and a two-input C unit. The front ends of the two MUX components in the terminal component are respectively connected to the rear ends of the two DI latches in the last stage single-level component. The rear ends of the two MUX components in the terminal component are respectively connected to the Sink components. The feedback signals of the two Sink components are respectively connected to the D terminal and CLK terminal of the D flip-flop. The two-input C unit in the terminal component is used to input the feedback signals of the two Sink components to the corresponding MUX components. At the same time, the output signal of the two-input C unit in the terminal component is used as an enable signal. In the single-level component, when one DI latch receives DATA or NULL first, it outputs to the next level single-level component. When both DI latches in the single-level component receive DATA or NULL, they request NULL or DATA from the next level single-level component. In the dual-track asynchronous pipeline PUF circuit, the input excitation is connected to the control ports of the two MUX components. By controlling the data paths of the two MUX components, the delay of the data path is changed, thereby realizing the selection of the delay path. The data path includes cross paths and parallel paths.

2. The dual-track asynchronous pipeline PUF circuit as described in claim 1, characterized in that, The dual-track signal has three values ​​for both input and output in the PUF circuit: NULL, DATA0, and DATA1. The input and output always maintain a "DATA-NULL-DATA" cycle.

3. A chip, characterized in that, Includes the dual-track asynchronous pipeline PUF circuit as described in claim 1 or 2.

4. A method for generating a response in a dual-track asynchronous pipelined PUF circuit as described in claim 1 or 2, characterized in that, Includes the following steps: Step 1: After circuit initialization, the first-stage single-level component inputs DATA and excitation, which are passed to the DI latch of this stage through the path selected by the excitation. When both DI latches of this stage receive DATA, they request NULL from the next higher-level single-level component and excitation. Step 2: After receiving the DATA output from the first-level single-level component, the second-level single-level component repeats the process of the first-level single-level component processing DATA in Step 1. At the same time, the first-level single-level component starts processing the NULL of the stimulus input. After receiving NULL, the first-level single-level component sets all the double-track paths of its level to NULL. Only after the second-level single-level component finishes processing the DATA will the DI latch of the first-level single-level component allow NULL to be written, requesting the next round of input and the next round of stimulus. Step 3: After receiving the DATA output from the second-level single-level component, the third-level single-level component repeats the process of the first-level single-level component processing DATA in Step 1. At the same time, the second-level single-level component repeats the process of the first-level single-level component processing NULL in Step 2. The first-level single-level component then receives and processes the input and stimulus for the next round.

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