Logic layout method and device for elements in register transfer level schematic circuit diagram

Abstract

The invention provides a logic layout method and device for elements in a schematic diagram of a register transfer-level circuit, and the method comprises the steps: obtaining a plurality of elements of the register transfer-level circuit, and a connection relation between the plurality of elements; according to the connection relationship, distributing the plurality of elements into a mutually parallel multilayer structure; the plurality of elements in the multilayer structure serve as end points to form a plurality of multi-end wire nets. The multi-layer structure further comprises a plurality of virtual nodes, and the virtual nodes are used for realizing cross-layer connection among elements in the multi-end wire network; for each multi-end wire net, independently dividing the connection between the first element / virtual node related to the multi-end wire net and the second element / virtual node on the adjacent lower layer into directed edges; and determining global coordinates of the elements and the virtual nodes in each layer of structure by using a preset algorithm to obtain a physical layout of the plurality of elements. Therefore, the network intersection points in the RTL-level circuit schematic diagram can be effectively reduced, so that a better layout effect is obtained, and convenience is brought to a designer to use.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a method and apparatus for logically arranging components in a register transfer level circuit schematic. Background Art

[0002] Register Transfer Level (RTL) schematics are a graphical representation used to illustrate the data transfer and control logic within FPGA design circuits. Logic diagram automatic generation tools parse structural netlists or VHDL code and generate corresponding graphical representations based on the logical relationships and component connectivity information. Automatic component placement and automatic net routing are two of the most challenging aspects of automatic logic diagram generation. Effective layout ensures a clear schematic logic flow and minimizes net intersections, which is crucial for successful layout. Summary of the Invention

[0003] The embodiments of the present application provide a method and apparatus for logically arranging components in a register transfer level circuit schematic diagram, which can effectively reduce the number of wire network intersections in an RTL level circuit schematic diagram.

[0004] In a first aspect, an embodiment of the present application provides a method for logically placing components in a register transfer level circuit schematic, the method comprising:

[0005] Acquire multiple components, input ports, and output ports of a register transfer stage circuit, as well as connection relationships between the multiple components;

[0006] Abstract multiple components and their connection relationships into a directed acyclic graph;

[0007] Distributing multiple components into a mutually parallel multi-layer structure according to a directed acyclic graph; the connection relationships between the multiple components constitute multiple N-end wire nets due to the components being in the multi-layer structure, where N is an integer not less than 2; the multi-layer structure also includes multiple virtual nodes, which are used to implement cross-layer connections between components in the N-end wire net;

[0008] Merge multiple N-end nets with similar connection relationships to update the multiple N-end nets;

[0009] Split the updated multiple N-terminal network into M directed edges between components, where M is a natural number;

[0010] Determine the global coordinates of components / virtual nodes in each layer using a preset algorithm; the preset algorithm is used to reduce the crossing of directed edges;

[0011] Fine-tune component / virtual node coordinates based on global coordinates, as well as adjust the order of input and output ports to reduce routing corners.

[0012] Therefore, the present application proposes a method for the logical layout of components in an RTL-level circuit schematic diagram, by abstracting the netlist of the RTL-level circuit into a directed acyclic graph, and then layering it into a layered graph, merging the complex multi-terminal wire nets and dividing them between adjacent layers to simplify the subsequent sorting and coordinate allocation of components on each layer, thereby obtaining a logical layout result of components with reduced cross-talk.

[0013] In a second aspect, an embodiment of the present application provides a device for logically placing components in a register transfer level circuit schematic, the device comprising:

[0014] An acquisition module, configured to acquire a plurality of components, input ports, and output ports of a register transfer stage circuit, as well as connection relationships between the plurality of components;

[0015] A processing module, used for abstracting multiple components and the connection relationships between them into a directed acyclic graph;

[0016] The processing module is further configured to distribute the plurality of components into a mutually parallel multi-layer structure according to the directed acyclic graph; the connection relationship between the plurality of components constitutes a plurality of N-end wire nets due to the components being in the multi-layer structure, where N is an integer not less than 2; the multi-layer structure further includes a plurality of virtual nodes, the virtual nodes being configured to implement cross-layer connections between the components in the N-end wire nets;

[0017] The processing module is further configured to merge the N-end wire nets with similar connection relationships in the plurality of N-end wire nets to update the plurality of N-end wire nets;

[0018] The processing module is further configured to split the updated multiple N-terminal network into M directed edges between components, where M is a natural number;

[0019] The processing module is further used to determine the global coordinates of the components / virtual nodes in each layer structure using a preset algorithm; the preset algorithm is used to reduce the crossing of directed edges;

[0020] The processing module is also used to fine-tune the coordinates of components / virtual nodes based on global coordinates, and adjust the order of input ports and output ports to reduce wiring corners.

[0021] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A layered diagram of a directed acyclic graph provided by an embodiment of the present application is shown;

[0024] Figure 2 A flow chart of a method for logically arranging components in a register transfer level circuit schematic diagram provided by an embodiment of the present application is shown;

[0025] Figure 3 A schematic diagram of N-terminal network merging provided in an embodiment of the present application is shown;

[0026] Figure 4 A schematic diagram of cutting adjacent layer edges of an N-end wire mesh provided by an embodiment of the present application is shown;

[0027] Figure 5 A schematic diagram of global coordinate allocation of components and virtual nodes provided in an embodiment of the present application is shown;

[0028] Figure 6 A framework diagram of a method for logically arranging components in a register transfer level circuit schematic diagram provided by an embodiment of the present application is shown;

[0029] Figure 7 A schematic diagram of a logic layout device for components in a register transfer level circuit schematic provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0031] In the description of the embodiments of this application, any embodiment or design scheme using "exemplary," "for example," or "for example" should not be understood as being more preferred or advantageous than other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly identifying the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. The terms "include," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized. "Multiple" can mean one or more, where "multiple" means two or more.

[0033] In response to the problems in the prior art, an embodiment of the present application proposes a method for the logical layout of components in an RTL-level circuit schematic diagram. The method abstracts the netlist of the RTL-level circuit into a directed acyclic graph, and then layers it into a layered graph. The complex multi-terminal wire nets are merged and divided between adjacent layers to simplify the subsequent sorting and coordinate allocation of components on each layer, thereby obtaining a logical layout result of components with reduced cross-talk.

[0034] A directed acyclic graph (DAG) is a graph structure that represents logical relationships. The netlist of an RTL-level circuit includes multiple components, input ports, output ports, and their connections. When abstracting the RTL-level circuit netlist into a directed acyclic graph, the abstraction principle is to use nodes to represent components (such as registers, combinational logic units, etc.) in the RTL-level circuit schematic and edges to represent the flow of signals within the connection relationships. By abstracting the RTL-level circuit netlist into a DAG, the logical relationships between components can be more clearly represented, providing a foundation for subsequent logic layout optimization steps.

[0035] Figure 1 FIG shows a layered diagram of a directed acyclic graph provided by an embodiment of the present application. Figure 1 As shown in Figure 1, the DAG is layered into a 5-layer structure, from left to right, layer 1 → layer 5, which are parallel to each other. The DAG is obtained by abstracting the netlist of the RTL level circuit.

[0036] The components included in the RTL-level circuit netlist are distributed to different layers of the five-layer structure according to their connection relationships, resulting in a layered diagram. For example, components N1-N2 and N5 are distributed to layer 1, components N3-N4 are distributed to layer 3, and components N6-N7 are distributed to layer 5. In the layered diagram, square nodes represent the components included in the RTL-level circuit netlist.

[0037] The hierarchical structure also includes dummy nodes D1 to D7, which are represented by circular nodes. These dummy nodes are used to implement cross-layer connections between components. For example, components N1 and N3 are connected across layers through dummy node D1.

[0038] Elements and virtual nodes are collectively referred to as nodes in a hierarchical graph.

[0039] In the layered diagram, edges are used to represent the signal flow between multiple components, thereby describing the connection relationship between components.

[0040] like Figure 1As shown in the figure, in a layered diagram, multiple components have different orders and coordinates and are interconnected according to the connection relationships in the netlist, forming a specific logical layout. However, in complex RTL-level circuit schematics, the connection relationships between components are often intricate, which can lead to multiple intersections in the logical layout (for example, the directed edge formed by the connection between component N2 and virtual node D5 intersects with the directed edge formed by the connection between component N5 and virtual node D2). Excessive intersections lead to a cluttered layout and reduced visualization, making it difficult for developers to efficiently perform subsequent circuit optimization, simulation verification, and physical design.

[0041] Therefore, it is necessary to efficiently adjust the above order and coordinates based on the layered diagram to reduce intersections and obtain a more reasonable component logic layout result.

[0042] Based on the above, a logic layout method of components in a register transfer level circuit proposed in this application is introduced in detail.

[0043] Figure 2 The flowchart of the logic layout method of the components in the register transfer level circuit schematic diagram provided by the embodiment of the present application is shown. Figure 2 As shown, the method mainly includes the following execution steps:

[0044] Step S201 : Acquire multiple components, input ports, and output ports of a register transfer stage circuit, as well as connection relationships between the multiple components.

[0045] For example, the netlist of the RTL-level circuit is obtained to obtain information about multiple components included in the RTL-level circuit and the connection relationship between the multiple components. The netlist of the RTL-level circuit is usually generated from hardware description language code, such as Verilog or VHDL. Components are the basic units that make up the circuit, including registers, combinational logic units (such as adders, comparators, multiplexers, etc.), input and output ports, etc. The connection relationship describes the signal flow between components.

[0046] Step S202 : abstracting the multiple components and the connection relationships therebetween into a directed acyclic graph.

[0047] In one implementation, the netlist of the RTL-level circuit is abstracted into a directed acyclic graph, which is used to represent multiple components in the netlist and the connection relationships between them, thereby simplifying subsequent logic layout optimization operations.

[0048] Step S203, distribute multiple components into parallel multi-layer structures according to a directed acyclic graph; the connection relationship between the multiple components constitutes multiple N-end network because the components are in the multi-layer structure, where N is an integer not less than 2; the multi-layer structure also includes multiple virtual nodes, which are used to realize cross-layer connections between components in the N-end network.

[0049] For example, Figure 1 As shown, based on a directed acyclic graph, multiple components are distributed into parallel, multi-layered structures according to their connectivity, resulting in a layered graph. Within this layered structure, multiple components are connected across layers via virtual nodes. Components and virtual nodes are collectively referred to as nodes in the layered graph. Due to the multi-layer structure, the connections between components form an N-terminal network (N >= 2), also known as a multi-terminal network.

[0050] Step S204 : merging the N-end nets with similar connection relationships to update the N-end nets.

[0051] Preferably, complex N-end nets are merged. By merging N-end nets with the same components among multiple N-end nets, multiple merged N-end nets can be obtained. Weights are set for the merged N-end nets according to the number of merges to further simplify subsequent logic layout optimization operations.

[0052] Specifically, for N-end nets with the same components, multiple virtual nodes at the same layer that connect the same components are merged to obtain a merged N-end net, so as to simplify the net relationship of the register transfer level circuit netlist without losing the net connection information.

[0053] The updated multiple N-end nets include original N-end nets on which the merging operation is not performed and N-end nets obtained after merging.

[0054] Figure 3 FIG. 1 shows a schematic diagram of an N-terminal line network merging provided by an embodiment of the present application. Figure 3 As shown, based on Figure 1 The five-layer hierarchical structure shown depicts N-end nets T1 and T2, consisting of components N1-N3 and N5-N6 as endpoints. Components N1 and N2 are located in layer 1, component N3 is located in layer 2, and components N5 and N6 are located in layer 3. They are connected across layers in N-end net T1 via virtual node D1, and in N-end net T2 via virtual node D2. Virtual nodes D1 and D2 are located in layer 2. Component 4 constitutes a separate net.

[0055] like Figure 3 As shown, since each component can have multiple ports, although the N-end nets T1 and T2 include the same endpoints, the ports they use are different.

[0056] To simplify the optimization operation, the N-end nets T1 and T2 with the same components can be merged to obtain a corresponding N-end net. Figure 2 In the multi-terminal network T3, the specific port information of components N1-N3 and N5-N6 is omitted. Virtual nodes D1 and D2 are merged into the same virtual node D3.

[0057] Step S205 : splitting the updated multiple N-terminal nets into M directed edges between components, where M is a natural number.

[0058] Furthermore, the complex N-end network is divided between adjacent layers to further simplify subsequent logic layout optimization operations.

[0059] Specifically, for each N-terminal net, the connection between the first component / virtual node associated with the N-terminal net and the second component / virtual node in the adjacent lower layer is divided into directed edges, thereby splitting the N-terminal net between adjacent layers. This splitting operation avoids losing excessive net connections and simplifies multi-terminal nets.

[0060] Preferably, when executing something like Figure 3 The complex N-end network merge operation shown in the figure updates multiple N-end networks. For each N-end network, the connection between the first component / virtual node associated with that N-end network and the second component / virtual node in the adjacent lower layer is divided into directed edges. A directed edge is defined by two nodes and their connection relationship: the source node and the destination node.

[0061] Figure 4 Schematic diagram of cutting the adjacent layers of an N-end wire mesh provided by an embodiment of the present application is shown. Figure 4 As shown, Figure 2 The N-end network T3 shown in the figure can be split between adjacent layers in order of layers and within layers. For example, the N-end network T3 is first split between layers 1 and 2. Then, within layer 1, the directed edges between N1 and its adjacent lower layer nodes (N3 and D3) are first split according to the within-layer order.

[0062] like Figure 4 As shown, nodes N1~N2 and D3 have all realized the separate division of directed edges with the nodes in the lower layer. For any two adjacent layers of the N-end network, if the m nodes in the upper layer are connected to the n nodes in the lower layer, then the number of directed edges between the adjacent layers is m*n. Figure 4In layer1, there are two nodes N1 and N2 connected to two nodes N3 and D3 of layer2 respectively, so the number of directed edges between the two layers is 4.

[0063] Set the weight of the N-end network to the weight of the directed edge.

[0064] Therefore, by abstracting the netlist of the RTL-level circuit into a directed acyclic graph and then layering it into a layered graph, the complex N-terminal wire nets are merged and split between adjacent layers to simplify the subsequent instance / DummyNode sorting and coordinate allocation on each layer.

[0065] Step S206 , determining the global coordinates of the components / virtual nodes in each layer structure using a preset algorithm; the preset algorithm is used to reduce the crossing of directed edges.

[0066] Exemplarily, after determining the relative order of components and virtual nodes in each layer structure using the K-layer intersection minimization algorithm and the center of gravity algorithm, global coordinates are allocated to the components and virtual nodes in each layer structure based on the relative order to improve the efficiency of logic layout optimization.

[0067] The K-layer intersection minimization algorithm is a layout optimization method used to reduce the number of intersections between connecting lines on different layers. This method uses a swapping method to swap the positions of components or nodes on adjacent layers, calculate the number of intersections before and after the swap, and then select the layout with the fewer intersections. The K-layer intersection minimization algorithm is used to determine the relative order of components and virtual nodes within each layer. Unlike standard intersection minimization, K-layer intersection minimization unifies the relative order of all components on K layers, thus avoiding the problem of local or marginal layers affecting the global layout.

[0068] The centroid algorithm is a method that determines the position of a node or component in a layout based on its "center of gravity." The center of gravity can be understood as the "center position" of a node or component. By calculating the center of gravity of each node or component, its relative order in the layout can be optimized. After layering, a component is located in a certain layer (here, assuming it is layer n). This component is connected to components or virtual nodes on layers n-1 and n+1 via directed edges. The relative position distribution is determined by taking the average position of all components or virtual nodes connected to the component on the determined n-1 or n+1 layers.

[0069] Preferably, before globally assigning coordinates to components and virtual nodes, directed edge crossings are distinguished as follows: crossings are categorized into three types based on the two directed edges causing the crossing. If the crossing is caused by 0, 1, or 2 internal segments, the crossing type is 0, 1, or 2. An internal segment is a connection between two adjacent layer virtual nodes, that is, a directed edge between two adjacent layer virtual nodes. A connection indicates that it is part of a cross-layer edge. Cross-layer edge crossings can affect the aesthetics of routing and signal flow. A pre-set algorithm is also used to reduce crossings caused by internal segments.

[0070] Among them, because keeping the internal segments horizontal (equal vertical coordinates) will significantly improve the readability of the schematic diagram, intersection type 2 has been avoided when determining the relative order of components and virtual nodes in each layer structure. Therefore, in the coordinate allocation of subsequent components and virtual nodes, avoiding intersection type 1 is the main task.

[0071] By determining the relative order of components and dummy nodes within each layer, Type 2 intersections can be effectively avoided. This is because the K-layer intersection minimization algorithm determines the relative order of layers / DummyNodes on each layer. The goal of determining the relative order is to minimize network intersections and avoid crossovers between layers, specifically, crossovers between DummyNodes. This can significantly impact layout and routing visibility.

[0072] Exemplarily, after determining the relative order of the elements and virtual nodes in each layer structure, the following steps are performed to perform global coordinate allocation on the elements and virtual nodes:

[0073] First, for each component / virtual node, find its corresponding right neighbor in the adjacent lower layer based on the divided directed edges and their weights. Based on each component / virtual node and its right neighbor, divide all points representing components / virtual nodes in the directed acyclic graph into different sets, each defined as a block.

[0074] Specifically, try to select a right neighbor for each node in the lower layer. The selection rules are divided into two levels of priority. The first priority is the weight of the directed edge. The node is taken as the source node, and the directed edge with the largest weight is selected for the node. The target node of the directed edge is the right neighbor of the node; if there is at least one such directed edge, the second level of priority is to select the median friendly neighbor from at least one target node as the right neighbor of the node in the layer where at least one target node corresponding to at least one directed edge is located (that is, the lower layer of the node), in the inter-layer order from top to bottom.

[0075] Preferably, the maximum set of horizontally aligned points, that is, the connections of right-neighboring points, is defined as a Block. The rightmost node of the Block is called the root.

[0076] Therefore, for the case of complex network connections, some network connections are ignored according to the network weights and the median right neighbor of the point, so that the coordinate allocation result can better reflect the signal flow.

[0077] Figure 5 FIG. 1 shows a schematic diagram of global coordinate allocation of an element and a virtual node provided by an embodiment of the present application. Figure 5 As shown, continued Figure 4 For example, taking N1 as an example, the target node of the directed edge with a weight of 3, that is, node N3, is selected as N1's right neighbor according to the first priority. When there is at least one directed edge with the highest weight, taking N2 as an example, the median node in the layer, that is, node D3, is selected as N2's right neighbor according to the second priority.

[0078] According to the above global coordinate allocation method, all the points representing components / virtual nodes in the directed acyclic graph are divided into different blocks according to each component / virtual node and its right neighbor. Figure 5 As shown, Blocks 1 and 2 are finally obtained. Taking Block 1 as an example, Block 1 is a large set including nodes N1 and N3 and the target directed edge between them. N1 and N3 are horizontally aligned, and node N3 is the root node.

[0079] Secondly, the global coordinates of the rightmost node in the Block are determined in sequence according to the layer order of the Block and the layer order of the rightmost node in the Block. The global coordinates of the components in the Block are determined in sequence according to the layer order of the Block and the layer order of the rightmost node in the Block.

[0080] Specifically, a preset algorithm is used to determine the global coordinates of components and virtual nodes in multiple blocks. The global coordinate allocation rules include: assigning root coordinates to all roots based on their layer from right to left, and from top to bottom in relative position within the layer. The optional rule is to start from the rightmost layer of the schematic and work your way left, assigning reasonable coordinates to the root points on each layer from top to bottom according to the determined relative order; and, for non-root points in a block, assigning coordinates based on the root point of the block. The allocation rule is to calculate the coordinates from right to left, using the vertical coordinate of the right neighbor plus the port offset. The so-called port offset refers to the port position deviation of the net connection associated with the instance / dummynode represented by this point and the right neighbor respectively. Such adjustments will ensure that there are no unnecessary turns in the net connection.

[0081] Furthermore, the global coordinates of the nodes are obtained after merging multiple virtual nodes at the same layer, and the global coordinates of multiple virtual nodes at the same layer are determined. In order to simplify the abstraction of the netlist, the N-end wire nets with the same endpoints are merged. This process may cause the virtual nodes at the same layer to be merged into only one representative DummyNode. The merged multiple virtual nodes at the same layer are restored. Figure 3 For example, after determining the global coordinates of node D3, it is also necessary to determine the coordinates of virtual nodes D1 and D2 on the same layer based on the global coordinates.

[0082] In one implementation, the height attribute of the representative DummyNode is set to N times the height of the basic virtual node. During the assignment of DummyNode coordinates, the coordinates of multiple DummyNodes in the same layer are sequentially set from top to bottom according to the representative DummyNode coordinates.

[0083] Step S207 : fine-tuning the coordinates of the components / virtual nodes based on the global coordinates, and adjusting the order of the input ports and the output ports, so as to reduce wiring corners.

[0084] Finally, after using a preset algorithm to determine the global coordinates of the components and virtual nodes in each layer structure, the relative positions of the logical ports of the components are also adjusted to reduce the intersection caused by the order of the logical ports.

[0085] Specifically, all instances / DummyNodes are locally laid out. Globally allocating components can lead to issues such as overlapping components, unnecessary net bends, and wasted layout space. Therefore, component coordinates are fine-tuned. The adjustment rules include: fixing the left-layer components in units of two adjacent layers from left to right, and adjusting the right-layer components; and, when adjusting the right-layer components, dividing the space occupied by the right layer into tracks with fixed heights, with each track occupied by at most one component to ensure non-overlapping components; and, adjusting the relative positions of the input ports of the right-layer components according to the corresponding order of the left-layer nets to reduce crossovers caused by the port order.

[0086] In summary, the pre-defined algorithms include the K-layer intersection minimization algorithm and the centroid algorithm described above, as well as various rules used to determine the global coordinates of components and virtual nodes in each layer. The pre-defined algorithms are used to reduce the number of directed edge intersections, while the global coordinates are used to determine the logical layout of multiple components.

[0087] Therefore, the logical layout method of components in the RTL-level circuit schematic proposed in this solution has the following characteristics: This method is generally divided into two aspects: global layout and local layout. The overall layout allocates components to approximate positions based on the order of components on each layer and the relationship between wire nets. The local layout improves indicators such as intersections and wire net bending locally.

[0088] Based on the above, Figure 6 The following is a framework diagram of a logic layout method for components in a register transfer level circuit schematic diagram provided by an embodiment of the present application. Figure 6 As shown, the method mainly includes the following steps:

[0089] Step S601 : abstracting the netlist of the RTL level circuit into a layered graph.

[0090] To begin, the netlist of the RTL circuit is converted into a layer diagram, which is a graphical representation that shows the connections between different layers.

[0091] The basis for layering typically depends on the purpose and application scenario of the layering. Layering can be based on the functional modules of the circuit, with each module representing an independent functional unit. Layering can also be based on the hierarchical structure of logical expressions, for example, with the top layer representing the main logic and the lower layers representing the sub-logic. Layering can also be based on the direction of control signal flow, separating the control logic from the controlled logic.

[0092] The purpose of layering is to simplify the design, improve readability, optimize performance, reduce complexity, and meet specific design and manufacturing requirements. In practical applications, it may be necessary to consider multiple criteria for layering.

[0093] Step S602: Determine the relative order of instance / DummyNode on each layer.

[0094] Next, determine the relative order of instance / DummyNode in each layer. This helps optimize layout and signal transmission.

[0095] Step S603: Eliminate intersections of intersection type 1.

[0096] Eliminate specific types of intersections (intersection type 1) to reduce intersection points in the layout and improve layout clarity and efficiency.

[0097] Exemplarily, multiple N-end wire nets with similar connection relationships are merged to update the multiple N-end wire nets; the updated multiple N-end wire nets are respectively split into M element-to-element directed edges, where M is a natural number; a preset algorithm is used to determine the global coordinates of the elements / virtual nodes in each layer structure; the preset algorithm is used to reduce the crossing of directed edges.

[0098] Step S604: Horizontal alignment is performed in the form of Block.

[0099] Aligning elements horizontally in blocks helps keep the layout neat and consistent.

[0100] For example, based on the divided directed edges and their weights, the corresponding right neighbor is found for each component / virtual node in the adjacent lower layer. Based on each component / virtual node and its right neighbor, all points representing components / virtual nodes in the directed acyclic graph are divided into different sets and defined as a block.

[0101] Preferably, for each element / virtual node, its median right neighbor is used as the right neighbor; the maximum set of connections of horizontally aligned points, i.e., right neighbor points, is defined as a Block; and the rightmost node of the Block is called the root.

[0102] Step S605: determine the coordinates of the root node on each layer from the rightmost layer to the left.

[0103] Starting from the rightmost layer, determine the coordinates of the root node on each layer in turn. This helps determine the structure of the entire layout.

[0104] Step S606: Is the point in the traversal graph a root node?

[0105] Check whether each point in the graph is a root node. If yes, proceed to step S608; if not, proceed to step S607 to assign coordinates according to the relevant root node.

[0106] Step S607: Allocate coordinates of other nodes according to the relevant root node.

[0107] Based on the location of the root node, coordinates are assigned to other nodes in the RTL circuit.

[0108] Step S608: assigning coordinates to the virtual nodes merged during the N-end network merging process.

[0109] During the N-end network merging process, some virtual nodes on the same layer may be merged. This step is to assign coordinates to these merged virtual nodes.

[0110] Step S609: Adjust the logical port order of the component.

[0111] Adjust the logical port order of components to optimize layout.

[0112] Step S610: local layout based on the horizontal track.

[0113] Based on the horizontal track, local layout adjustments are made to optimize the overall layout.

[0114] Step S611, traverse all layers?

[0115] Check whether all layers have been traversed. If not, jump to step S610 and step S609 to continue processing; if yes, the coordinate allocation is completed.

[0116] Therefore, by performing coordinate allocation and layout optimization in the multi-layer structure of the RTL circuit, the clarity, efficiency and consistency of the layout can be ensured.

[0117] It is understandable that the size of the sequence number of each step in the above embodiment does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, in some possible implementations, the steps in the above embodiment can be selectively executed according to actual conditions, and can be partially executed or fully executed, which is not limited here. In addition, all or part of any features in the above embodiment can be freely and arbitrarily combined without contradiction. The combined technical solution is also within the scope of this application.

[0118] Figure 7 FIG. 1 shows a schematic diagram of a logic layout device for components in a register transfer level circuit schematic diagram provided by an embodiment of the present application. Figure 7 As shown, the logic layout device 700 includes:

[0119] The acquisition module 710 is configured to acquire multiple components, input ports, and output ports of a register transfer stage circuit, as well as connection relationships between the multiple components.

[0120] The processing module 720 is configured to abstract the multiple elements and the connection relationships therebetween into a directed acyclic graph.

[0121] The processing module 720 is also used to distribute multiple components into parallel multi-layer structures according to a directed acyclic graph; the connection relationship between the multiple components constitutes multiple N-end network because the components are in the multi-layer structure, where N is an integer not less than 2; the multi-layer structure also includes multiple virtual nodes, which are used to realize cross-layer connections between components in the N-end network.

[0122] The processing module 720 is further configured to merge the N-end nets with similar connection relationships among the multiple N-end nets to update the multiple N-end nets.

[0123] The processing module 720 is further configured to split the updated plurality of N-terminal nets into M directed edges between components, where M is a natural number.

[0124] The processing module 720 is further configured to determine the global coordinates of the components / virtual nodes in each layer structure using a preset algorithm; the preset algorithm is configured to reduce the crossing of directed edges.

[0125] The processing module 720 is further configured to fine-tune the coordinates of components / virtual nodes based on global coordinates, and adjust the order of input ports and output ports to reduce wiring corners.

[0126] Based on the method in the above embodiment, an embodiment of the present application provides an electronic device. The electronic device may include: at least one memory for storing a program; and at least one processor for executing the program stored in the memory. Wherein, when the program stored in the memory is executed, the processor is used to execute the method described in the above embodiment. Exemplarily, the electronic device may be a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, a server, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an artificial intelligence (AI) device, and the embodiment of the present application does not impose any special restrictions on the specific type of the electronic device.

[0127] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0128] It is understood that the various numerical numbers involved in the embodiments of the present application are only for the convenience of description and are not intended to limit the scope of the embodiments of the present application. It should be understood that in the embodiments of the present application, the order of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0129] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of this application in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of this application should be included in the scope of protection of this application.

Claims

1. A method for logically arranging components in a register transfer level circuit schematic, characterized in that: The method comprises: Acquire multiple elements, input ports, and output ports of a register transfer stage circuit, as well as connection relationships between the multiple elements; Abstracting the multiple elements and the connection relationships therebetween into a directed acyclic graph; The plurality of components are distributed into mutually parallel multi-layer structures according to the directed acyclic graph; the connection relationships between the plurality of components constitute a plurality of N-end wire nets due to the components being in the multi-layer structure, where N is an integer not less than 2; the multi-layer structure further includes a plurality of virtual nodes, the virtual nodes being used to implement cross-layer connections between components in the N-end wire nets; Merging the network with similar connection relationships among the plurality of N-end network to update the plurality of N-end network; Splitting the updated multiple N-terminal network into M element-to-element directed edges, where M is a natural number; Determining the global coordinates of the elements / virtual nodes in each layer structure using a preset algorithm; the preset algorithm is used to reduce the crossing of the directed edges; Fine-tuning the coordinates of the components / virtual nodes and adjusting the order of the input ports and output ports are performed based on the global coordinates to reduce wiring corners.

2. The method according to claim 1, characterized in that The method of determining the global coordinates of the components and virtual nodes in each layer structure by using a preset algorithm includes: The relative order of components and virtual nodes in each layer structure is determined using the K-layer intersection minimization algorithm and the center of gravity algorithm; Global coordinates are allocated to the elements and virtual nodes in each layer structure based on the relative order.

3. The method according to claim 1, characterized in that Merging the plurality of N-terminal nets with similar connection relationships includes: Merging N-end nets having the same components among the plurality of N-end nets; Setting weights for the N-end network obtained by merging according to the number of merging; The step of splitting the updated plurality of N-terminal network segments into M directed edges between components comprises: Separately dividing the connection between the first element / virtual node of the N-end network and the second element / virtual node of the adjacent lower layer into directed edges; The weight of the N-end network is set to the weight of the directed edge.

4. The method according to claim 3, characterized in that Merging the N-end nets having the same components among the plurality of N-end nets includes: For N-end nets with the same components, multiple virtual nodes at the same layer connecting the same components are merged to obtain a merged N-end net, so as to simplify the net relationship of the register transfer level circuit netlist without losing the net connection information.

5. The method according to claim 3, characterized in that The method of determining the global coordinates of the components and virtual nodes in each layer structure by using a preset algorithm includes: According to the divided directed edges and their weights, the corresponding right neighbor is found in the adjacent lower layer for each component / virtual node.

6. The method according to claim 5, characterized in that The method of determining the global coordinates of the components and virtual nodes in each layer structure by using a preset algorithm further includes: According to each component / virtual node and its right neighbor, all points representing components / virtual nodes in the directed acyclic graph are divided into different sets and defined as a Block.

7. The method according to claim 6, characterized in that According to each element / virtual node and its right neighbor, all points representing elements / virtual nodes in the directed acyclic graph are divided into different sets and defined as a Block, including: For each element / virtual node, take its median right neighbor as the right neighbor; The horizontally aligned points, that is, the maximum set of connections of the right neighboring points, are defined as a Block; the rightmost node of the Block is called the root.

8. The method according to claim 4, characterized in that The method further comprises: The merged multiple virtual nodes at the same layer are restored.

9. The method according to claim 1, characterized in that The crossing includes crossings caused by 0, 1 or 2 internal segments, where the internal segment is a connection composed of two adjacent layer virtual nodes; the connection indicates that it is part of a cross-layer edge, and the crossing of the cross-layer edge will affect the aesthetics of the wiring and the viewing of signal flow. The preset algorithm is also used to reduce crossings caused by internal segments.

10. A device for logically arranging components in a register transfer level circuit schematic, characterized in that: The device comprises: an acquisition module, configured to acquire a plurality of elements, input ports, and output ports of a register transfer stage circuit, and connection relationships between the plurality of elements; a processing module, configured to abstract the plurality of elements and the connection relationships therebetween into a directed acyclic graph; The processing module is further configured to distribute the plurality of components into mutually parallel multi-layer structures according to the directed acyclic graph; the connection relationships between the plurality of components constitute a plurality of N-end wire nets due to the components being in the multi-layer structure, where N is an integer not less than 2; the multi-layer structure further includes a plurality of virtual nodes, the virtual nodes being configured to implement cross-layer connections between components in the N-end wire nets; The processing module is further configured to merge the N-end wire nets having similar connection relationships among the multiple N-end wire nets to update the multiple N-end wire nets; The processing module is further configured to split the updated plurality of N-terminal network segments into M directed edges between components, where M is a natural number; The processing module is further configured to determine the global coordinates of the elements / virtual nodes in each layer structure using a preset algorithm; the preset algorithm is configured to reduce the crossing of the directed edges; The processing module is further configured to fine-tune the coordinates of the components / virtual nodes based on the global coordinates, and adjust the order of the input ports and the output ports, so as to reduce wiring corners.

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