An automated circuit board scoring method, apparatus, electronic device, and storage medium.

Abstract

This invention relates to an automated circuit board scoring method, apparatus, electronic device, and storage medium. The automated circuit board scoring method of this invention includes: extracting regions of interest (ROIs) from images of both sides of the circuit board, and performing circuit line segmentation and component identification on the ROIs of the motherboard on both sides respectively to obtain a circuit segmentation diagram and a component information diagram of the motherboard; sequentially extracting and erasing numbers from the circuit segmentation diagram of the motherboard to obtain the motherboard's numbering information and an optimized circuit segmentation diagram; performing solder joint identification and geometric recognition on the optimized circuit segmentation diagram of the motherboard to obtain solder joint, length, and width information of the motherboard respectively; associating the component information diagram with the solder joint information to generate a component-circuit line topology diagram; and performing a comprehensive scoring calculation on the solder joint, length, width information, and component-circuit line topology diagram to obtain a comprehensive score for the current motherboard. The automated circuit board scoring method of this invention effectively improves the granularity and accuracy of scoring.

Description

Technical Field

[0001] This invention relates to the technical field of circuit boards, and in particular to an automated scoring method, apparatus, electronic device, and storage medium for circuit boards. Background Technology

[0002] In today's electronic product design and manufacturing field, with the rapid development of technology and the ever-increasing market demands, automation and intelligence have become core trends in modern engineering design. For the design and production process of circuit boards, especially in education and engineering practice, evaluating circuit board quality is not only the job of teachers or experts, but also an important means of improving students' practical skills and reducing human error. Traditional manual grading methods require teachers or experts to check and score students' completed circuit board projects, which has drawbacks such as significant subjective judgment and excessive time consumption, making it difficult to meet the needs of large-scale evaluation.

[0003] Based on this, existing technologies extract and identify features from motherboard images, analyze electrical parameter data of motherboards, and use weighted algorithms to perform comprehensive scoring calculations on image features and electrical parameter features, thereby achieving automated scoring calculations for circuit boards.

[0004] However, existing technologies do not take into account the students' welding skills, especially the relationship between the solder joints and components, which makes the existing scoring system unable to effectively reflect the skill level shown by students during the welding process.

[0005] In summary, existing technologies for automated circuit board scoring suffer from insufficient granularity and accuracy. Summary of the Invention

[0006] Therefore, the purpose of this invention is to provide an automated scoring method for circuit boards.

[0007] An automated circuit board scoring method includes the following steps:

[0008] S1. Extract the region of interest (ROI) from the images of the front and back circuit boards to obtain the ROI regions of the motherboard on both sides.

[0009] S2. Perform circuit line segmentation and component identification on the front and back ROI areas of the motherboard to obtain the circuit segmentation diagram and component information diagram of the motherboard respectively.

[0010] S3. Sequentially extract and erase the circuit partition diagram of the motherboard by number to obtain the motherboard's numbering information and optimized circuit partition diagram;

[0011] S4. Perform solder joint identification and geometric identification on the optimized circuit segmentation diagram of the motherboard to obtain information on the solder joints, circuit line length, and circuit line width of the motherboard.

[0012] S5. Associate the component information diagram with the solder joint information to generate a component-circuit topology diagram;

[0013] S6. Perform a comprehensive score calculation on the solder joints, circuit line length, circuit line width information and component-circuit line topology to obtain the comprehensive score of the current motherboard;

[0014] S7. Based on the motherboard's serial number information, link the current motherboard's overall score with the student ID in the database to generate the final score report.

[0015] The automated circuit board scoring method described in this invention, compared with the prior art, identifies solder joints, geometric circuit lines, and components on both the front and back sides of the motherboard, and further associates solder joints, circuit line paths, and components to calculate corresponding scores. This objectively and comprehensively evaluates the student's technical level in the soldering process, thereby avoiding the subjectivity and crudeness of traditional methods and improving the granularity and accuracy of the comprehensive scoring.

[0016] Furthermore, the circuit line splitting includes the following sub-steps:

[0017] The ROI region of the reverse side of the motherboard is enhanced using an RGB exponential enhancement formula to obtain the enhanced ROI region of the reverse side of the motherboard; wherein the RGB exponential enhancement formula is expressed as follows:

[0018] V i,j = -2.0 × G i,j +B i,j +R i,j +10.0

[0019] In the formula, V i,j This represents the pixel value in the i-th row and j-th column of the enhanced reverse motherboard ROI region; G i,j B o,j and R o,j These are the pixel values ​​of the green, blue, and red channels in the i-th row and j-th column of the ROI area on the reverse side of the motherboard;

[0020] Next, global thresholding and local adaptive thresholding are applied to the enhanced reverse motherboard ROI region to obtain global circuit segmentation lines and local circuit segmentation lines.

[0021] Finally, the global circuit partition lines and local circuit partition lines are merged to obtain the circuit partition diagram of the motherboard;

[0022] The component identification process involves using an image recognition model to perform target detection on the front-facing motherboard ROI area, identifying the component type, component location, and component orientation within the motherboard ROI area, and obtaining a component information map.

[0023] Accordingly, this invention enhances the ROI region of the motherboard on the reverse side using the RGB exponential enhancement formula, significantly improving the contrast and clarity of the reverse image, making the subsequent extraction of solder joints and circuit lines more accurate; at the same time, it further utilizes image segmentation technology to extract the contours of solder joints and circuit lines from the reverse image through binarization, significantly improving the segmentation accuracy of the reverse motherboard circuit, thereby improving the ability to capture details during the scoring process.

[0024] Furthermore, by utilizing image recognition models to identify component types, locations, and orientations from the front of the motherboard, more comprehensive component information on the front of the circuit board can be obtained. This allows for more refined calculation methods during subsequent scoring, effectively improving the granularity and accuracy of the overall scoring.

[0025] Furthermore, the solder joint identification in step S4 includes the following sub-steps:

[0026] By identifying endpoints in the optimized circuit diagram of the motherboard, several solder joints can be extracted.

[0027] Next, based on the location of the solder joints, a clustering algorithm is used to cluster the solder joints in the circuit segmentation diagram, thereby grouping solder joints belonging to the same electrical connection into a group and obtaining several electrical networks;

[0028] Furthermore, the locations of solder joints and their corresponding clustering results are associated with the electrical network to obtain a solder joint-network mapping table;

[0029] Simultaneously, contour detection is performed on several solder joints to obtain their size and shape;

[0030] Finally, based on the solder joint-network mapping table, the size and shape of the solder joints are combined to form the solder joint information;

[0031] The geometric recognition in step S4 includes width calculation and length calculation; the width calculation includes the following sub-steps:

[0032] By segmenting the circuit lines in the optimized circuit diagram of the motherboard, several circuit lines are extracted.

[0033] Next, the orthogonal skeleton line algorithm is used to calculate the width of each circuit line to obtain the width information of the circuit line;

[0034] The length calculation includes the following sub-steps:

[0035] A skeleton extraction algorithm is used to extract the skeleton from the optimized circuit segmentation diagram of the motherboard, generating single-pixel skeletons of the circuit lines;

[0036] Pixel statistics are performed on the single-pixel skeleton of the circuit line, and the length information of the circuit line is obtained by combining the calibration data.

[0037] Accordingly, this invention effectively improves the identification accuracy of solder joint electrical networks by identifying the endpoints of solder joints in the optimized circuit segmentation diagram and classifying the solder joints in the circuit using a clustering algorithm. Furthermore, by mapping solder joints and electrical networks to form a solder joint-network mapping table, the electrical connection quality of the circuit can be evaluated more accurately, significantly improving the precision and accuracy of the evaluation.

[0038] Furthermore, by using the orthogonal skeleton line algorithm to calculate the width of the circuit lines and combining it with the skeleton extraction algorithm to calculate the length of the circuit lines, the evaluation accuracy of the circuit layout is effectively improved, and the rationality of the circuit line design and the soldering quality can be more accurately reflected in the scoring process.

[0039] Furthermore, the specific calculation method for the current motherboard's overall score is as follows:

[0040] overall score =w width ×W score +w length ×L score +w dot ×D score +w topology ×Topology score

[0041] In the formula, w width w length w dot and w topology These are the weighting factors for width score, length score, solder joint score, and topology result score, respectively; W score For width scoring, L score For length scoring, D score Indicates solder joint score, Topology score This indicates the score for the topology result.

[0042] Accordingly, this invention scores the results based on four aspects: width, length, solder joints, and topology. By assigning weights to each scoring factor, it ensures that each factor has a reasonable impact on the final score, thereby avoiding the problem of the scoring result being overly influenced by a single factor. This results in a more accurate reflection of the quality of circuit board design and soldering, and improves the objectivity and reliability of the overall scoring.

[0043] Furthermore, the specific calculation of the width score is expressed as follows:

[0044] W score =w avg ×width avg +w compliance ×width comp +w uniformity ×width uni

[0045] In the formula, w acg Weighting for the average width score; width avg The average width score is calculated as follows:

[0046]

[0047] In the formula, avg represents the average value of all circuit segments; w target The width represents the ideal width in the specification. max and width min These are the maximum and minimum widths allowed in the specification, respectively.

[0048] w compliance The weight representing the degree of conformity to the width specification; width comp The specific calculation method for the width specification compliance score is as follows:

[0049]

[0050] In the formula, width i Let N represent the width of the circuit line in the i-th segment, and let N represent the total number of circuit lines in the segment; I(·) is an indicator function, specifically expressed as:

[0051]

[0052] w uniformity For width uniformity weight; width uni The specific calculation method for width uniformity scoring is as follows:

[0053]

[0054] In the formula, σ w μ is the standard deviation of width. w Average width;

[0055] The specific calculation of the length score is as follows:

[0056]

[0057] In the formula, Ltotal L is the total length of the circuit lines. max and L min Used to indicate the maximum and minimum lengths allowed by the specification;

[0058] The specific calculation method for the solder joint score is as follows:

[0059]

[0060] In the formula, M represents the total number of actual solder joints obtained after solder joint identification; w size Indicates the weight of solder joint size; Size i The dimension score of the i-th solder joint is represented by the following calculation method:

[0061]

[0062] In the formula, d i d represents the actual area of ​​the i-th solder joint; d0 represents the ideal solder joint area; k represents the tolerance coefficient;

[0063] w shape Indicates the shape weight of the solder joint; Shape i The shape score of the i-th solder joint is represented as follows:

[0064]

[0065] In the formula, P i Let be the perimeter of the i-th weld point;

[0066] The specific calculation method for the topology result score is as follows:

[0067]

[0068] In the formula, P pin This indicates the degree of fit between the solder joint and the component lead, and its specific calculation is as follows:

[0069]

[0070] In the formula, N match Indicates the number of solder joints successfully associated; N total This indicates the preset number of pins for all components;

[0071] P pad This represents the proportion of solder joints connected to component pins out of the total number of solder joints. The specific calculation is as follows:

[0072]

[0073] In the formula, N usedIndicates the number of solder joints associated with the component pins; P trace This represents the proportion of solder joints that connect to the electrical network via circuit lines out of the total number of solder joints. The specific calculation is as follows:

[0074]

[0075] In the formula, N connect N represents the number of solder joints that connect to the electrical network via the circuit lines; totalPad This represents the total number of solder joints.

[0076] Based on this, the width scoring method described in this invention comprehensively evaluates the average width, width specification compliance, and width uniformity to fully reflect the compliance of circuit board trace widths. Therefore, by accurately calculating trace widths, this invention can effectively improve the accuracy of circuit design quality assessment and ensure that traces conform to design specifications.

[0077] Regarding length scoring, this invention utilizes a flexible scoring mechanism to calculate the difference between the total length of the circuit line and the specified length, enabling rapid and accurate identification of whether the length of the circuit line meets the design specifications, thus ensuring that the length of the circuit lines in the design conforms to the standard.

[0078] For solder joint scoring, this invention effectively quantifies students' soldering skill level by calculating the deviation between the solder joint size and the ideal size using an exponential decay formula. Simultaneously, it further assesses whether the solder joint shape conforms to specifications by using the ratio of the solder joint's perimeter to its area. Therefore, by comprehensively evaluating both size and shape, this invention can fully assess solder joint quality and ensure that the circuit board soldering quality meets standards.

[0079] For topology result scoring, the relationship between solder joints, components, and electrical networks is comprehensively analyzed by calculating the matching degree between solder joints and component pins, the connectivity between solder joints and electrical networks, and the proportion of solder joints used by component pins. This also allows for accurate judgment of the connectivity and functionality of circuit lines, avoiding functional defects caused by soldering errors or improper circuit line design, and providing more accurate feedback for the final evaluation of the circuit board.

[0080] In summary, this invention, through refined scoring of width, length, solder joints, and topology results, combined with rigorous calculation methods, ensures fine-grained and high-accuracy scoring, thereby effectively improving the ability to assess circuit board quality and reducing the influence of human intervention and subjective factors.

[0081] An automated circuit board scoring device includes a region of interest extraction unit, a motherboard information recognition unit, a motherboard number processing unit, a reverse motherboard information recognition unit, a front motherboard topology recognition unit, a comprehensive score calculation unit, and a score report generation unit.

[0082] The region of interest extraction unit is used to extract the region of interest from the images of the front and back circuit boards to obtain the ROI regions of the motherboard on the front and back sides.

[0083] The motherboard information identification unit is used to perform circuit line segmentation and component identification on the front and back ROI areas of the motherboard, respectively, to obtain the circuit segmentation diagram and component information diagram of the motherboard.

[0084] The motherboard numbering processing unit is used to extract and erase the numbers sequentially from the circuit partition diagram of the motherboard to obtain the motherboard's numbering information and optimized circuit partition diagram.

[0085] The reverse motherboard information recognition unit is used to perform solder joint recognition and geometric recognition on the optimized circuit segmentation diagram of the motherboard to obtain information on the solder joints, circuit line length and circuit line width of the motherboard.

[0086] The front motherboard topology identification unit is used to associate component information diagrams with solder joint information to generate a component-circuit topology diagram.

[0087] The comprehensive scoring calculation unit is used to perform comprehensive scoring calculation on solder joints, circuit line length, circuit line width information and component-circuit line topology diagram to obtain the comprehensive score of the current motherboard.

[0088] The rating report generation unit is used to associate the current motherboard's overall rating with the student ID in the database based on the motherboard's serial number information, and generate the final rating report.

[0089] To better understand and implement this invention, the following detailed description is provided in conjunction with the accompanying drawings. Attached Figure Description

[0090] Figure 1 A simplified structural diagram of the automated circuit board scoring device of the present invention;

[0091] Figure 2 This is a simplified flowchart illustrating the automated circuit board scoring method described in this invention. Detailed Implementation

[0092] To address the shortcomings of existing automated circuit board scoring technologies in terms of granularity and accuracy, this invention extracts Regions of Interest (ROIs) from images of both sides of the circuit board. Then, it performs circuit line segmentation and component identification on the ROIs of both sides of the motherboard, obtaining circuit segmentation diagrams and component information diagrams. Next, the circuit segmentation diagrams are sequentially numbered and then erased to obtain the motherboard's numbering information and an optimized circuit segmentation diagram. Then, solder joint identification and geometric recognition are performed on the optimized circuit segmentation diagram to obtain the solder joint, length, and width information of the motherboard. The component information diagram is then associated with the solder joint information to generate a component-circuit topology diagram. Finally, a comprehensive score is calculated based on the solder joint, length, and width information, as well as the component-circuit topology diagram, to obtain the overall score for the current motherboard. This score is then linked to student IDs in a database based on the motherboard's numbering information to generate the final scoring report.

[0093] Accordingly, this invention achieves a comprehensive evaluation of the soldering quality and structure of a circuit board by accurately extracting the Region of Interest (ROI) areas of both the front and back sides of the motherboard and performing solder joint and geometric recognition on the segmented circuit diagram of the back side. Furthermore, this invention associates solder joints with component pins to generate a component-circuit topology diagram. Based on this, and further combining the length, width, solder joint information, and comprehensive scoring of the topology diagram, this invention significantly improves the granularity and accuracy of automated scoring, ensuring more objective and reliable scoring results.

[0094] Based on the above design, this invention proposes an automated circuit board scoring method and an automated circuit board scoring device based on the method.

[0095] Please also refer to Figure 1 and Figure 2 , Figure 1 A simplified structural diagram of the automated circuit board scoring device of the present invention is shown. Figure 2 This is a simplified flowchart illustrating the automated circuit board scoring method described in this invention.

[0096] The automated circuit board scoring device includes a region of interest extraction unit 1, a motherboard information identification unit 2, a motherboard number processing unit 3, a reverse motherboard information identification unit 4, a front motherboard topology identification unit 5, a comprehensive scoring calculation unit 6, and a scoring report generation unit 7.

[0097] The region of interest extraction unit 1 is used to perform step S1: extract the region of interest from the images of the front and back circuit boards to obtain the ROI regions of the motherboard on the front and back sides.

[0098] Specifically, a fast segmentation model is used to extract the regions of interest (ROIs) from the images of the front and back circuit boards, respectively, and feature matching is performed on the extracted results to align the front and back circuit boards and obtain the ROI regions of the motherboard on both sides.

[0099] The fast segmentation model includes a region of interest extraction module and a feature alignment module.

[0100] The region of interest extraction module is used to extract effective regions from the images of the front and back of the circuit board to eliminate background interference and obtain images of the motherboard area on both sides. The effective regions include areas containing solder joints, components, component pins, and circuit lines, as well as areas related to electrical functions.

[0101] The feature alignment module is used to align and combine the motherboard endpoint features of the front and back motherboard area images to obtain the motherboard ROI regions of the front and back sides. Specifically, the alignment and combination involves comparing and matching the endpoint features in the front motherboard area image with the endpoint features in the back image one by one.

[0102] The motherboard information identification unit 2 is used to perform step S2: to perform circuit line segmentation and component identification on the front and back motherboard ROI areas respectively, and obtain the circuit segmentation diagram and component information diagram of the motherboard respectively.

[0103] Specifically, the circuit line splitting includes the following sub-steps:

[0104] The RGB exponential enhancement formula is used to enhance the ROI region of the motherboard on the reverse side, resulting in the enhanced ROI region. The RGB exponential enhancement formula is used to enhance the circuit line features in the image and reduce background interference, making the circuit lines more prominent. Its specific calculation is expressed as follows:

[0105] V i,j = -2.0 × G i,j +B i,j +R i,j +10.0

[0106] In the formula, V i,j This represents the pixel value in the i-th row and j-th column of the enhanced reverse motherboard ROI region; G i,j B i,j and R i,j These are the pixel values ​​of the green, blue, and red channels in the i-th row and j-th column of the ROI area on the reverse side of the motherboard.

[0107] Next, global thresholding and local adaptive thresholding are applied to the enhanced reverse motherboard ROI region to obtain global circuit segmentation lines and local circuit segmentation lines.

[0108] The global thresholding process involves selecting a pixel value threshold and filtering pixels in the entire enhanced reverse motherboard ROI area based on this threshold. Pixels below the threshold are classified as background and removed, while pixels above or equal to the threshold are classified as circuit dividing lines, thus obtaining global circuit dividing lines. Common global thresholding algorithms such as the Otsu algorithm can be used, but this invention does not limit the specific algorithm.

[0109] The local adaptive thresholding process uses a sliding window to adaptively filter the enhanced reverse motherboard ROI region. Thresholds below the mean of the sliding window are classified as background, while thresholds above or equal to the mean of the sliding window are classified as circuit dividing lines. A specific expression can be found in the following example:

[0110]

[0111] In the formula, I(i,j) represents a sliding window centered at pixel coordinates (i,j), and its size is generally 5×5 by default; mean() represents the average value of all pixels in the sliding window; C represents the threshold offset, which is a constant and can be adjusted according to specific needs. This invention does not specifically limit it.

[0112] Finally, the global circuit segmentation lines and local circuit segmentation lines are merged to obtain the circuit segmentation diagram of the motherboard.

[0113] The fusion process involves combining global or local circuit segmentation lines through intersection or union to more comprehensively represent the circuit lines on the circuit board and reduce erroneous segmentation caused by factors such as background noise and uneven lighting, thereby obtaining a circuit segmentation diagram of the motherboard.

[0114] Accordingly, the ROI region of the motherboard on the reverse side is segmented by global thresholding and local adaptive thresholding to generate a binary circuit segmentation diagram of the motherboard, and the clarity of the circuit lines is optimized, providing high-quality image data for subsequent circuit analysis and scoring.

[0115] The component identification process involves using an image recognition model to detect targets in the front-facing motherboard ROI area, identifying the component type, location, and orientation within the ROI area, thereby obtaining a component information map.

[0116] The image recognition model is a target detection model for identifying circuit board components. The target detection model can be selected from the YOLO (You Only Look Once) series. In order to correctly identify the component type, component position and component orientation, a front-facing circuit board image can be collected, and the components on the front-facing circuit board image can be labeled, labeled with position boxes and orientation labels to generate a component dataset. The target detection model can then be trained using the component dataset to form a target detection model that can be used to identify circuit board components.

[0117] Furthermore, the component types generally include resistors, capacitors, diodes, inductors, transistors, etc., and each component type typically has static pin information. Since different component versions may have different pin counts, this invention does not specifically limit the pin count for each component type. The component orientation can be identified through rotation-invariant convolution or YOLOv11's Oriented Bounding Box (OBB), and this invention does not impose specific limitations on this.

[0118] It should be noted that, given the variety of object detection models available, users can choose the appropriate object detection model based on their actual situation, such as Mask-RCNN, YOLOv4, YOLOv5, YOLOv7, ViTransformer, etc., or design and customize their own combined models. This invention does not impose any restrictions on the specific choice of model.

[0119] The motherboard numbering processing unit 3 is used to perform step S3: sequentially extracting and erasing numbers from the circuit partition diagram of the motherboard to obtain the motherboard's numbering information and optimized circuit partition diagram.

[0120] Specifically, the number extraction uses an optical character recognition (OCR) algorithm to perform character recognition on the circuit diagram of the motherboard in order to extract the motherboard's number information and the location area of ​​the number.

[0121] The optical character recognition algorithm is used to extract text information from images. It generally involves image preprocessing, rotation correction and region extraction, and character recognition of relevant regions to obtain character information and location regions. Its OCR technology can be Tesseract or EAST (Efficient and Accurate Scene Text Detector).

[0122] The erasure operation involves using an image restoration algorithm to fill holes, filter small-area noise, and separate adhesions between circuit lines in the numbered location area to obtain an optimized circuit segmentation diagram.

[0123] The image restoration algorithm fills in the numbered areas and then uses morphological operations to restore them, thereby ensuring that the circuit board area with the number removed is visually consistent with the surrounding circuit area, thus ensuring the continuity and consistency of the circuit lines and preventing abnormalities in subsequent scoring calculations.

[0124] Accordingly, the binarized circuit segmentation diagram was further optimized through number extraction and erasure operations to avoid interference from the numbering when analyzing the geometric features of the circuit in the subsequent process, thereby ensuring the integrity and analytical accuracy of the circuit lines.

[0125] The reverse motherboard information identification unit 4 is used to perform step S4: perform solder joint identification and geometric identification on the optimized circuit segmentation diagram of the motherboard to obtain information on the solder joints, circuit line length and circuit line width of the motherboard.

[0126] Specifically, the solder joint identification is performed by identifying endpoints in the optimized circuit segmentation diagram of the motherboard to extract several solder joints.

[0127] Since solder joints are generally located at the intersections or ends of circuit lines, the endpoint identification is generally achieved through image processing methods, such as connectivity analysis or edge detection, to determine the intersections or ends of circuit lines, thereby locating the solder joints.

[0128] Next, based on the location of the solder joints, a clustering algorithm is used to cluster the solder joints in the circuit segmentation diagram, thereby grouping solder joints belonging to the same electrical connection into a group and obtaining several electrical networks.

[0129] The clustering algorithm can be either K-means clustering or DBSCAN clustering; this invention does not specifically limit the choice of clustering algorithm. K-means clustering is suitable for situations where solder joints are relatively evenly distributed, while DBSCAN clustering is suitable for handling situations with more noise or more complex solder joint distributions, ensuring that solder joints in each electrical network can be identified.

[0130] Furthermore, the locations of solder joints and their corresponding clustering results are associated with the electrical network to obtain a solder joint-network mapping table.

[0131] The association refers to mapping the coordinates of each solder joint to its corresponding electrical network label. An example of the generated mapping table is: {solder joint coordinates: network label}.

[0132] Simultaneously, contour detection is performed on several solder joints to obtain their size and shape.

[0133] The contour detection process employs edge detection algorithms, such as Canny edge detection, to extract the edge information of the solder joint, thereby obtaining its shape contour. Then, morphological analysis or methods based on calibration data are used to identify the solder joint's dimensions, such as diameter, and its shape features, which are then used for subsequent quality assessment.

[0134] Finally, based on the solder joint-network mapping table, the size and shape of the solder joints are combined to form solder joint information.

[0135] The geometric recognition includes width calculation and length calculation; the width calculation is performed by segmenting the circuit lines in the optimized circuit partition diagram of the motherboard and extracting several circuit line segments.

[0136] The circuit line segmentation process uses connectivity analysis to divide the continuous circuit line into several segments according to preset segmentation rules. The start and end positions of each segment are clearly marked, thereby ensuring the uniformity of the segmented circuit line.

[0137] Next, the orthogonal skeleton line algorithm is used to calculate the width of each circuit line to obtain the width information of the circuit line.

[0138] The orthogonal skeleton line algorithm extracts the skeleton structure of the circuit line and calculates the distance to the nearest coordinate point based on the normal vector of the skeleton structure to obtain the width information of the circuit line.

[0139] The length calculation is performed by using a skeleton extraction algorithm to extract the skeleton from the optimized circuit segmentation diagram of the motherboard, generating a single-pixel skeleton of the circuit line.

[0140] Pixel statistics are performed on the single-pixel skeleton of the circuit line, and the length information of the circuit line is obtained by combining the calibration data.

[0141] The front motherboard topology identification unit 5 is used to perform step S5: associating the component information diagram with the solder joint information to generate a component-circuit line topology diagram.

[0142] Specifically, by matching the component type, component position, component orientation, and corresponding component pin and solder joint information in the component information diagram through position matching or orientation matching, the association between the components on the front motherboard and the solder joint positions on the back is established; then, in the form of components as nodes and electrical network connections as edges, the component-circuit topology diagram is constructed by combining the solder joint position contained in the solder joint information with the corresponding electrical network label.

[0143] Therefore, by establishing a mapping relationship between components and solder joints and organizing them into a topology diagram, the connection method of each component in the electrical network can be clearly presented, thus providing a basis for subsequent connectivity analysis or scoring calculation.

[0144] The comprehensive scoring calculation unit 6 is used to perform step S6: to perform comprehensive scoring calculation on solder joints, circuit line length, circuit line width information and component-circuit line topology diagram to obtain the comprehensive score of the current motherboard.

[0145] Specifically, the current motherboard's overall score includes a weighted sum of width score, length score, solder joint score, and topology result score.

[0146] The width score is calculated by performing average width calculation, width specification calculation, and width uniformity calculation on all segments of the circuit line in the circuit line width information, and then summing all the results with weights. The specific calculation expression is as follows:

[0147] W score =w vvg ×width avg +w compliance ×width comp +w uniformity ×width uni

[0148] In the formula, W score Score for width; w avg The weight for the average width score; this is a constant, defaulting to 0.4; width avg The average width score measures how close the average width of all circuit segments is to the ideal width in the specification, thereby determining whether the overall circuit design meets the expected width requirements. The specific calculation is as follows:

[0149]

[0150] In the formula, avg represents the average value of all circuit segments; w target The ideal width in the specification is a known value, set according to the requirements of the corresponding circuit board; this invention does not specifically limit it. max and width min These are the maximum and minimum widths allowed in the specification, which are known values. They are set according to the requirements of the corresponding circuit board, and are not specifically limited in this invention.

[0151] w compliance This represents the weight of width specification compliance; it is a constant with a default value of 0.4. comp The width specification compliance score is used to assess whether the circuit lines as a whole comply with the design specifications. The specific calculation method is as follows:

[0152]

[0153] In the formula, widthi Let N represent the width of the circuit line in the i-th segment, and let N represent the total number of circuit lines in the segment; I(·) is an indicator function, specifically expressed as:

[0154]

[0155] w uniformity This is the width uniformity weight, a constant, with a default value of 0.2; width uni Width uniformity is scored by measuring the ratio of the standard deviation of the circuit segment width to the average width, assessing the consistency of the circuit line width. The specific calculation is as follows:

[0156]

[0157] In the formula, σ w μ is the standard deviation of width. w This represents the average width.

[0158] The length score is calculated by segmenting the total length of the circuit line against the minimum and maximum lengths specified in the standard. Specifically, it is expressed as follows:

[0159]

[0160] In the formula, L score Score for length; L total L is the total length of the circuit lines. max and L min The maximum and minimum lengths allowed by the specification are known values ​​and are set according to the requirements of the corresponding circuit board. This invention does not specifically limit them.

[0161] The weld point scoring is calculated by evaluating the size and shape of the weld points to comprehensively assess whether the size of the weld points meets design requirements and whether the shape is close to the ideal form, thereby accurately reflecting the welding quality. The specific calculation is as follows:

[0162]

[0163] In the formula, D score Indicates the solder joint score; M represents the total number of actual solder joints obtained after solder joint identification; w size This indicates the solder joint size weight, which is a constant and defaults to 0.7; Size i This represents the dimensional score of the i-th solder joint, used to evaluate whether the dimensions of the solder joint meet the requirements. Its specific calculation is as follows:

[0164]

[0165] In the formula, d id0 represents the actual area of ​​the i-th solder joint, which is usually calculated based on calibration data; d0 represents the ideal solder joint area, which is determined according to design standards or ideal solder joint requirements; k represents the tolerance coefficient, which defaults to 0.2 and is used to adjust the tolerance range between the solder joint area and the ideal area.

[0166] w shaoe This represents the shape weight of the solder joint; it is a constant and defaults to 0.3. i This represents the shape score of the i-th solder joint, which is calculated by comparing the actual area of ​​each solder joint with the ideal solder joint area. The smaller the deviation, the higher the score. The specific calculation is as follows:

[0167]

[0168] In the formula, P i The perimeter of the i-th solder joint is obtained by calculating the edge pixel count of the solder joint using calibration data.

[0169] The topology result score is used to measure the connection quality between component pins and solder joints on the circuit board, the effective use of solder joints, and the connectivity of circuit lines. Its specific calculation is expressed as follows:

[0170]

[0171] In the formula, Topology score Indicates the topology result score; P pin This indicates the matching degree between solder joints and component pins, that is, the ratio of the number of successfully associated solder joints to the total number of component pins. The specific calculation is as follows:

[0172]

[0173] In the formula, N match The number of successfully associated solder joints is typically calculated from the matching degree between the component pin location and the solder joint location; N total This indicates the preset number of pins for all components, obtained from the component pin counts in the circuit design, typically the design standard or the actual number of components on the circuit board; P pad This indicates the proportion of solder joints associated with component pins out of the total number of solder joints. In other words, it checks whether each component pin is effectively connected to an actual solder joint. The specific calculation is as follows:

[0174]

[0175] In the formula, N used This indicates the number of solder joints associated with the component pins, used to calculate how many solder joints are actually connected to the component pins; M represents the total number of actual solder joints obtained after solder joint identification; P traceThis represents the proportion of solder joints that connect to the electrical network through the circuit lines out of the total number of solder joints. It is used to measure the connectivity of the circuit lines and the integrity of the electrical network. The specific calculation is as follows:

[0176]

[0177] In the formula, N connect N represents the number of solder joints that connect to the electrical network via the circuit lines; totalPad This represents the total number of solder joints on the circuit board.

[0178] Accordingly, the specific calculation method for the current motherboard's overall score is as follows:

[0179] overall score =w width ×W score +w length ×L score +w dot ×D score +w topology ×Topology score

[0180] In the formula, w width w length w dot and w topology These are the weighting factors for the width score, length score, solder joint score, and topology result score, respectively, with default values ​​of 0.3, 0.3, 0.2, and 0.2.

[0181] The rating report generation unit 7 is used to perform step S7: according to the motherboard's serial number information, the comprehensive rating of the current motherboard is associated with the student ID in the database to generate the final rating report, and the rating report is stored in the database according to the student ID.

[0182] The student ID is used to distinguish the circuit board works of different students and to ensure that the comprehensive score of each motherboard corresponds to the correct student. The student ID is stored in the database by default.

[0183] The scoring report includes the student's ID, the motherboard's serial number, the overall score of the current circuit board and each scoring item, feedback, and improvement suggestions; the scoring items include width score, length score, solder joint score, and topology result score.

[0184] Accordingly, the overall score of the main board is matched with the corresponding student records through data association to ensure the accuracy of the scoring results and the traceability of the data. Students can access their own scoring reports through the system portal, and teachers can also view and export the scoring reports of all students through the management backend.

[0185] Compared to existing technologies, this invention achieves a more comprehensive and detailed evaluation of the circuit board by separately identifying the images of the front and back sides of the circuit board. The image of the back side of the circuit board is used to identify solder joints and circuit lines, while the image of the front side focuses on the identification of components. This ensures that the details of every part are accurately captured.

[0186] Furthermore, by associating the component information on the front side with the solder joint information on the back side to form a topology diagram, the connection relationship between components and electrical networks can be clearly reflected through the topology diagram, thereby effectively improving the evaluation capability of circuit connectivity and greatly enhancing the accuracy and objectivity of the scoring results.

[0187] Ultimately, this invention incorporates multiple key factors into a comprehensive evaluation system by performing multi-dimensional and detailed scoring on solder joints, circuit line length, circuit line width, and topology diagrams. This enables a multi-faceted evaluation of circuit board quality, which not only improves the accuracy of the scoring but also ensures objectivity in the scoring process, reduces human bias, and further enhances the effectiveness of automated scoring.

[0188] Based on the same inventive concept, this application also provides an electronic device, which can be a server, desktop computing device, or mobile computing device (e.g., laptop computing device, handheld computing device, tablet computer, netbook, etc.) or other terminal device. The device includes one or more processors and a memory, wherein the processor is used to execute a program to implement the automated circuit board scoring method of the embodiments of the present invention; the memory is used to store a computer program executable by the processor.

[0189] Based on the same inventive concept, this application also provides a computer-readable storage medium corresponding to the aforementioned embodiments of the automated circuit board scoring method. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the steps of the automated circuit board scoring method described in any of the above embodiments.

[0190] This application may take the form of a computer program product implemented on one or more storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing program code. Computer storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information may be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to: phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0191] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and the present invention also intends to include these modifications and variations.

Claims

1. An automated circuit board scoring method, characterized in that, Includes the following steps: S1. Extract the region of interest (ROI) from the images of the front and back circuit boards to obtain the ROI regions of the motherboard on both sides. S2. Perform circuit line segmentation and component identification on the front and back ROI areas of the motherboard to obtain the circuit segmentation diagram and component information diagram of the motherboard respectively. S3. Sequentially extract and erase the circuit partition diagram of the motherboard by number to obtain the motherboard's numbering information and optimized circuit partition diagram; S4. Perform solder joint identification and geometric identification on the optimized circuit segmentation diagram of the motherboard to obtain information on the solder joints, circuit line length, and circuit line width of the motherboard. S5. Associate the component information diagram with the solder joint information to establish the association between the components on the front motherboard and the solder joint positions on the back. Using components as nodes and electrical network connections as edges, generate a component-circuit topology diagram by combining the solder joint positions contained in the solder joint information with their respective electrical network labels. S6. Perform a comprehensive score calculation on the solder joints, circuit line length, circuit line width information, and component-circuit line topology to obtain the comprehensive score of the current motherboard; the specific calculation method for the comprehensive score of the current motherboard is as follows: In the formula, , , and These are the weighting factors for width score, length score, solder joint score, and topology result score, respectively. Rate the width. Rate the length. Indicates the solder joint score. Indicates the score of the topology results; The specific calculation method for the topology result score is as follows: In the formula, This indicates the degree of fit between the solder joint and the component lead, and its specific calculation is as follows: In the formula, Indicates the number of solder joints successfully associated; This indicates the preset number of pins for all components; This represents the proportion of solder joints connected to component pins out of the total number of solder joints. The specific calculation is as follows: In the formula, Indicates the number of solder joints associated with the component pins; This represents the total number of actual solder joints obtained after solder joint identification. This represents the proportion of solder joints that are connected to the electrical network via circuit lines out of the total number of solder joints. The specific calculation is as follows: In the formula, This indicates the number of solder joints that connect to the electrical network via the circuit lines; This represents the total number of solder joints on the circuit board. S7. Based on the motherboard's serial number information, link the current motherboard's overall score with the student ID in the database to generate the final score report.

2. The automated circuit board scoring method according to claim 1, characterized in that, The circuit line splitting includes the following sub-steps: The ROI region of the reverse side of the motherboard is enhanced using an RGB exponential enhancement formula to obtain the enhanced ROI region of the reverse side of the motherboard; wherein the RGB exponential enhancement formula is expressed as follows: In the formula, This indicates the enhanced reverse side of the motherboard's ROI area. Line number The pixel values ​​of the column; and The first of each of the ROI areas on the reverse side of the motherboard Line number The pixel values ​​of the green, blue, and red channels of the column; Next, global thresholding and local adaptive thresholding are applied to the enhanced reverse motherboard ROI region to obtain global circuit segmentation lines and local circuit segmentation lines. Finally, the global circuit partition lines and local circuit partition lines are merged to obtain the circuit partition diagram of the motherboard; The component identification process involves using an image recognition model to perform target detection on the front-facing motherboard ROI area, identifying the component type, component location, and component orientation within the motherboard ROI area, and obtaining a component information map.

3. The automated circuit board scoring method according to claim 2, characterized in that, The solder joint identification in step S4 includes the following sub-steps: By identifying endpoints in the optimized circuit diagram of the motherboard, several solder joints can be extracted. Next, based on the location of the solder joints, a clustering algorithm is used to cluster the solder joints in the circuit segmentation diagram, thereby grouping solder joints belonging to the same electrical connection into a group and obtaining several electrical networks; Furthermore, the locations of solder joints and their corresponding clustering results are associated with the electrical network to obtain a solder joint-network mapping table; Simultaneously, contour detection is performed on several solder joints to obtain their size and shape; Finally, based on the solder joint-network mapping table, the size and shape of the solder joints are combined to form the solder joint information; The geometric recognition in step S4 includes width calculation and length calculation; the width calculation includes the following sub-steps: By segmenting the circuit lines in the optimized circuit diagram of the motherboard, several circuit lines are extracted. Next, the orthogonal skeleton line algorithm is used to calculate the width of each circuit line to obtain the width information of the circuit line; The length calculation includes the following sub-steps: A skeleton extraction algorithm is used to extract the skeleton from the optimized circuit segmentation diagram of the motherboard, generating single-pixel skeletons of the circuit lines; Pixel statistics are performed on the single-pixel skeleton of the circuit line, and the length information of the circuit line is obtained by combining the calibration data.

4. The automated circuit board scoring method according to claim 1, characterized in that, The specific calculation method for the width score is as follows: In the formula, Weights for the average width score; The average width score is calculated as follows: In the formula, This represents the average value of all segments of the circuit line; Indicates the ideal width in the specification; and These are the maximum and minimum widths allowed in the specification, respectively. The weight representing the degree of compliance with the width specification; The specific calculation method for the width specification compliance score is as follows: In the formula, Indicates the first The width of each segment of the circuit line, its Indicates the total number of circuit lines in the segment; For indicator functions, their specific representation is as follows: Weights for width uniformity; The specific calculation method for width uniformity scoring is as follows: In the formula, The standard deviation of width, Average width; The specific calculation of the length score is as follows: In the formula, This is the total length of the circuit lines; and Used to indicate the maximum and minimum lengths allowed by the specification; The specific calculation method for the solder joint score is as follows: In the formula, This represents the total number of actual solder joints obtained after solder joint identification. Indicates the weight of solder joint size; Indicates the first The dimensional score for each solder joint is calculated as follows: In the formula, Indicates the first The actual area of ​​each weld point; Indicates the area of ​​the ideal solder joint; Indicates the tolerance coefficient; Indicates the weight of the solder joint shape; Indicates the first The shape score for each solder joint is calculated as follows: In the formula, For the first The perimeter of each weld point.

5. An automated circuit board scoring device, characterized in that, It includes a region of interest extraction unit, a motherboard information recognition unit, a motherboard number processing unit, a reverse motherboard information recognition unit, a front motherboard topology recognition unit, a comprehensive score calculation unit, and a score report generation unit; The region of interest extraction unit is used to extract the region of interest from the images of the front and back circuit boards to obtain the ROI regions of the motherboard on the front and back sides. The motherboard information identification unit is used to perform circuit line segmentation and component identification on the front and back ROI areas of the motherboard, respectively, to obtain the circuit segmentation diagram and component information diagram of the motherboard. The motherboard numbering processing unit is used to extract and erase the numbers sequentially from the circuit partition diagram of the motherboard to obtain the motherboard's numbering information and optimized circuit partition diagram. The reverse motherboard information recognition unit is used to perform solder joint recognition and geometric recognition on the optimized circuit segmentation diagram of the motherboard to obtain information on the solder joints, circuit line length and circuit line width of the motherboard. The front motherboard topology identification unit is used to associate the component information diagram with the solder joint information, establish the association between the components on the front motherboard and the solder joint positions on the back, and generate a component-circuit topology diagram by combining the solder joint positions contained in the solder joint information with the corresponding electrical network labels, in the form of components as nodes and electrical network connections as edges. The comprehensive scoring calculation unit is used to perform comprehensive scoring calculations on solder joints, circuit line lengths, circuit line widths, and component-circuit line topology to obtain the comprehensive score of the current motherboard; the specific calculation method for the comprehensive score of the current motherboard is as follows: In the formula, , , and These are the weighting factors for width score, length score, solder joint score, and topology result score, respectively. Rate the width. Rate the length. Indicates the solder joint score. Indicates the score of the topology results; The specific calculation method for the topology result score is as follows: In the formula, This indicates the degree of fit between the solder joint and the component lead, and its specific calculation is as follows: In the formula, Indicates the number of solder joints successfully associated; This indicates the preset number of pins for all components; This represents the proportion of solder joints connected to component pins out of the total number of solder joints. The specific calculation is as follows: In the formula, Indicates the number of solder joints associated with the component pins; This represents the total number of actual solder joints obtained after solder joint identification. This represents the proportion of solder joints that are connected to the electrical network via circuit lines out of the total number of solder joints. The specific calculation is as follows: In the formula, This indicates the number of solder joints that connect to the electrical network via the circuit lines; This represents the total number of solder joints on the circuit board. The rating report generation unit is used to associate the current motherboard's overall rating with the student ID in the database based on the motherboard's serial number information, and generate the final rating report.

6. The automated circuit board scoring device according to claim 5, characterized in that, The circuit line splitting includes the following sub-steps: The ROI region of the reverse side of the motherboard is enhanced using an RGB exponential enhancement formula to obtain the enhanced ROI region of the reverse side of the motherboard; wherein the RGB exponential enhancement formula is expressed as follows: In the formula, This indicates the enhanced reverse side of the motherboard's ROI area. Line number The pixel values ​​of the column; and The first of each of the ROI areas on the reverse side of the motherboard Line number The pixel values ​​of the green, blue, and red channels of the column; Next, global thresholding and local adaptive thresholding are applied to the enhanced reverse motherboard ROI region to obtain global circuit segmentation lines and local circuit segmentation lines. Finally, the global circuit partition lines and local circuit partition lines are merged to obtain the circuit partition diagram of the motherboard; The component identification is achieved by using an image recognition model to perform target detection on the front-facing motherboard ROI area, identifying the component type, component location, and component orientation within the motherboard ROI area, and obtaining a component information map. The solder joint identification in the reverse motherboard information identification unit includes the following sub-steps: By identifying endpoints in the optimized circuit diagram of the motherboard, several solder joints can be extracted. Next, based on the location of the solder joints, a clustering algorithm is used to cluster the solder joints in the circuit segmentation diagram, thereby grouping solder joints belonging to the same electrical connection into a group and obtaining several electrical networks; Furthermore, the locations of solder joints and their corresponding clustering results are associated with the electrical network to obtain a solder joint-network mapping table; Simultaneously, contour detection is performed on several solder joints to obtain their size and shape; Finally, based on the solder joint-network mapping table, the size and shape of the solder joints are combined to form the solder joint information; The geometric recognition in the reverse motherboard information recognition unit includes width calculation and length calculation; the width calculation includes the following sub-steps: By segmenting the circuit lines in the optimized circuit diagram of the motherboard, several circuit lines are extracted. Next, the orthogonal skeleton line algorithm is used to calculate the width of each circuit line to obtain the width information of the circuit line; The length calculation includes the following sub-steps: A skeleton extraction algorithm is used to extract the skeleton from the optimized circuit segmentation diagram of the motherboard, generating single-pixel skeletons of the circuit lines; Pixel statistics are performed on the single-pixel skeleton of the circuit line, and the length information of the circuit line is obtained by combining the calibration data.

7. The automated circuit board scoring device according to claim 5, characterized in that, The specific calculation method for the width score is as follows: In the formula, Weights for the average width score; The average width score is calculated as follows: In the formula, This represents the average value of all segments of the circuit line; Indicates the ideal width in the specification; and These are the maximum and minimum widths allowed in the specification, respectively. The weight representing the degree of compliance with the width specification; The specific calculation method for the width specification compliance score is as follows: In the formula, Indicates the first The width of each segment of the circuit line, its Indicates the total number of circuit lines in the segment; For indicator functions, their specific representation is as follows: Weights for width uniformity; The specific calculation method for width uniformity scoring is as follows: In the formula, The standard deviation of width, Average width; The specific calculation of the length score is as follows: In the formula, This is the total length of the circuit lines; and Used to indicate the maximum and minimum lengths allowed by the specification; The specific calculation method for the solder joint score is as follows: In the formula, This represents the total number of actual solder joints obtained after solder joint identification. Indicates the weight of solder joint size; Indicates the first The dimensional score for each solder joint is calculated as follows: In the formula, Indicates the first The actual area of ​​each weld point; Indicates the area of ​​the ideal solder joint; Indicates the tolerance coefficient; Indicates the weight of the solder joint shape; Indicates the first The shape score for each solder joint is calculated as follows: In the formula, For the first The perimeter of each weld point.

8. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the computer program, it implements an automated circuit board scoring method as described in any one of claims 1-4.

9. A computer-readable storage medium storing computer-executable instructions, characterized in that, When the computer-executable instructions are executed by the processor, they implement an automated circuit board scoring method as described in any one of claims 1-4.

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