Chip surface defect visual detection method and system

Abstract

The invention discloses a chip surface defect visual detection method and system, and the method comprises the steps: carrying out the high-sensitivity imaging through the dynamic adaptation of a quantum imaging enhancement module to the surface reflectivity, and achieving the sparse efficient processing of a defect signal through the combination of event-driven vision and a pulse neural network; based on a risk thermodynamic diagram generated in real time, intelligently scheduling detection precision and speed resources, and utilizing multi-modal feature decoupling and a federal knowledge graph to accurately associate defects and process roots; the digital twinning module synchronously predicts a defect evolution path and drives online adjustment and optimization of process parameters, and meanwhile the dynamic compensation module corrects optical defocus in real time. According to the invention, full-detection coverage of nanoscale defects is realized, a defect transfer chain is actively blocked while the detection efficiency is improved, and the chip manufacturing yield and reliability are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of visual inspection, and in particular to a chip surface defect visual inspection method and system. Background Art

[0002] Currently, the semiconductor industry is moving towards smaller linewidths and higher integration. Micro- and nanoscale defects on chip surfaces, such as scratches, particle contamination, residues, etching anomalies, and metal layer defects, are increasingly impacting device performance and yield, driving the continuous evolution of surface inspection technology. Traditional manual visual inspection, while flexible, has long held a niche in early production. However, its low efficiency, susceptibility to subjective fatigue, and difficulty in accurate quantitative description have led to its gradual elimination in modern production lines.

[0003] Currently, mainstream inspection systems are primarily based on automated optical technology. Automated optical inspection (AOI), the most widely deployed system on production lines, relies on high-resolution CCD / CMOS cameras combined with multiple lighting strategies such as brightfield, darkfield, or differential interferometry for high-speed, contactless scanning. It relies on preset template comparison or algorithm-driven image processing technology for initial defect screening and is widely used in wafer manufacturing and packaging testing. For subtle defects at the submicron and even nanometer levels, such as extremely shallow scratches and tiny particles, laser scattering detection technology exploits the significant difference in laser scattering signals between defects and flat substrates for highly sensitive detection, making it particularly suitable for ultra-precision polished surfaces. When optical methods approach the physical diffraction limit, scanning electron microscopy (SEM), with its nanometer-level resolution, has become the gold standard for analyzing the morphology of key defects at deep submicron nodes. It reveals surface morphology and composition information through secondary electron or backscattered electron imaging and is often used as a tool for offline precision re-inspection and root-cause analysis. In addition, white light interferometry (WLI) and atomic force microscopy (AFM) provide sub-nanometer surface 3D topography through optical interference phase shift or probe mechanical feedback, respectively. Although limited in speed and expensive, they are indispensable for quantitative characterization of defects involving height and depth. However, current mainstream chip surface defect detection technologies still have significant limitations when facing increasingly stringent manufacturing requirements.

[0004] Therefore, it is necessary to improve the chip surface defect detection method and system in the prior art to solve the above problems. Summary of the Invention

[0005] The present invention overcomes the shortcomings of the existing technology and provides a chip surface defect visual detection method and system, aiming to solve the problems of limited optical resolution, low detection efficiency, difficulty in dealing with complex defects, and laser scattering relying on surface mirror reflection in the existing chip surface defect detection technology.

[0006] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a chip surface defect visual detection method, comprising:

[0007] S1. Obtaining raw defect data on the chip surface by dynamically adapting the chip surface reflectivity to the imaging method; wherein the imaging is obtained using a wavelength-tunable entangled light source array, and the raw defect data includes a raw defect point cloud image;

[0008] S2. After compressing the original defect data, a defect risk prediction heat map is generated, and detection resources are dynamically allocated to obtain secondary detection data;

[0009] S3. Perform multimodal feature decoupling on the secondary inspection data, integrate defect data from multiple production lines to build a global knowledge graph, and output instantaneous defect classification results and process correlation factors; wherein the multimodal feature decoupling includes separating the optical features, geometric features, and process features of the defects;

[0010] S4. Input the data of S1-S3 into the digital twin model, perform multi-physics field simulation, and output the dynamic prediction defect evolution path.

[0011] In a preferred embodiment of the present invention, in step S1, the wavelength-tunable entangled light source array includes entangled photon sources and compressed state lasers in the deep ultraviolet band and the near ultraviolet band; wherein the deep ultraviolet band has a wavelength of 180-200 nm and is used for highly reflective surfaces to break the diffraction limit, and the near ultraviolet band has a wavelength of 340-370 nm and is used for low-reflective surfaces to enhance the penetration of transparent films; the defect scattering signal of the entangled light source is enhanced by a quantum illumination protocol, and the noise suppression ratio of the compressed state laser is greater than 20 dB;

[0012] The chip surface reflectivity is measured using an InGaAs focal plane sensor, and the lighting mode is dynamically switched based on the reflectivity, including: quantum dark field illumination when the reflectivity is >0.7, quantum dark field superimposed structured light coding when the reflectivity is 0.3-0.7, and structured light coding combined with computational imaging when the reflectivity is <0.3;

[0013] The original defect point cloud image is output through Zernike phase space coding compressed sensing imaging with a resolution of 12-13nm.

[0014] In a preferred embodiment of the present invention, in step S2, the change in light intensity on the chip surface is captured based on event-driven dynamic visual sensing, the event-driven dynamic visual sensor has a response wavelength of 900-1700nm and a time resolution of 8-10μs; when the light intensity change on the chip surface ΔlogI>0.05, the original defect data of the changed area is transmitted; spatiotemporal filtering and pulse coding are performed in combination with a spiking neural network, and the original defect data is compressed, and the events within each 10ms window are converted into a 128-dimensional sparse pulse vector;

[0015] For the compressed defect data, the defect risk probability on the chip surface is predicted based on the AI ​​model to generate a defect risk prediction heat map.

[0016] In a preferred embodiment of the present invention, the method for dynamically allocating detection resources is: when the risk probability is greater than 0.8, a quantum super-resolution detection mode is used, with a resolution of 12-13nm and a speed of 1.5-2mm. 2 / s, when the risk probability is 0.3-0.8, the multi-spectral fusion mode is used, the resolution is 45-50nm, and the speed is 18-20mm 2 / s, when the risk probability is <0.3, the wide-field fast scanning mode is used, with a resolution of 150-200nm and a speed of 80-100mm 2 / s.

[0017] In a preferred embodiment of the present invention, in step S3: multimodal feature decoupling includes:

[0018] The defect feature extractor decouples optical features from geometric features and uses a neural network algorithm to extract corresponding features from the sparse pulse vector of S2 and the original defect point cloud image of S1;

[0019] The process correlation extractor extracts the latent variables of process parameters, and the encoder e(X 工艺 )=W e X 工艺 +b e , X 工艺 The input process parameter vector includes the key parameters in the manufacturing process, including photoresist thickness, etching rate, and annealing temperature, and the output latent variable z; decoder d(z) = W d z+b d , reconstructing process parameters W,b is the weight matrix and the bias vector for .

[0020] In a preferred embodiment of the present invention, in step S3, a global knowledge graph is constructed by integrating and constructing a federated defect knowledge graph:

[0021] Each production line k builds a knowledge subgraph G based on local defect data k ={T k ,R k}, where T k The triple set is (h, r, t), which represents the head entity, relation, and tail entity; R k is the relationship weight, which represents the confidence of the triple, calculated by the frequency of occurrence of the association in the local data;

[0022] Each production line aggregates knowledge subgraphs through federated learning to generate a global knowledge graph Among them, the total number of production lines is K, ωk is the weight of production line k, τ is the confidence threshold; is the process correlation factor, and the defect classification result is output through the classifier as the defect type probability distribution y.

[0023] In a preferred embodiment of the present invention, in step S4, the multi-physics field simulation includes: predicting the diffusion path of nanoparticles in high-temperature processes based on a thermal diffusion model; evaluating the expansion risk of chip scratches based on a stress intensity factor model; and simulating the dissolution of photoresist residues in a corrosive environment based on a dissolution rate model.

[0024] In a preferred embodiment of the present invention, through multi-physical field coupling simulation, the dynamic evolution state of chip defects is ultimately output, including: size change, position migration and type transformation. Combined with data-driven methods, the correlation between defect characteristics and process parameters is mined, model training is performed, and the defect evolution path under given process parameters is predicted.

[0025] In a preferred embodiment of the present invention, a pulse neural network integrates a memory and computing chip to perform synaptic weight calculations;

[0026] The input layer receives the DVS event stream (x, y, z, t, p), where t is the timestamp and p is the polarity;

[0027] The hidden layer is Among them, V mem is the membrane potential accumulation value, ω ij is the synaptic weight factor, τ is the time constant, t i ,t j is the event timestamp; when the membrane potential accumulation is less than 20% of the threshold, it is regarded as noise and the event is discarded.

[0028] In a preferred embodiment of the present invention, the process parameter correction instruction includes adjusting the etcher RF power, exposure dose, CMP equipment pressure and deposition equipment gas flow rate.

[0029] The present invention provides a chip surface defect visual detection system, including modules:

[0030] The quantum imaging enhancement module receives chip surface reflectivity data and generates a wavelength-tunable quantum entangled illumination signal. It dynamically switches the illumination mode based on real-time reflectivity and outputs compressed sensing imaging defect point cloud data.

[0031] The dynamic event processing module acquires the point cloud data from the quantum imaging module and captures the event stream of surface light intensity changes. It performs pulse neural network spatiotemporal filtering on the event stream to generate 128-dimensional sparse pulse coded data and transmits the risk heat map to the resource scheduling module.

[0032] The risk scheduling module receives the risk heat map from the dynamic event processing module, dynamically allocates detection parameters based on the risk value, and feeds back lighting mode instructions to the quantum imaging module;

[0033] The multimodal decoupling module integrates the point cloud data of the quantum imaging module and the pulse coded data of the dynamic event processing module. It decouples the optical, geometric and process characteristics of the defect through a multi-task framework and outputs the process correlation factors to the knowledge graph engine.

[0034] The federated knowledge construction module aggregates process-related factor data from multiple production lines, constructs a global defect knowledge graph, and provides the process-defect mapping relationship to the prediction module;

[0035] The digital twin prediction module synchronizes chip design parameters with real-time feature data from the multimodal decoupling module; calls the multi-physics simulation model to predict defect evolution paths, generates process parameter correction instructions, and transmits them to the process closed-loop control module;

[0036] The dynamic compensation module analyzes the defect point cloud data of the quantum imaging module, generates optical focal length compensation, and corrects the defocus error of the imaging module in real time;

[0037] The process closed-loop control module receives process correction instructions from the digital twin prediction module, converts parameter instructions into equipment control signals, and feeds back to the manufacturing production line in real time.

[0038] The present invention solves the defects existing in the background technology and has the following beneficial effects:

[0039] (1) The present invention provides a closed-loop controlled chip surface defect detection solution, which dynamically adapts the surface reflectivity through the quantum imaging enhancement module to perform high-sensitivity imaging, and combines event-driven vision and pulse neural networks to achieve sparse and efficient processing of defect signals; based on the real-time generated risk heat map, it intelligently schedules detection accuracy and speed resources, and uses multimodal feature decoupling and federated knowledge graphs to accurately associate defects with process roots; the digital twin module synchronously predicts the defect evolution path, achieves full inspection coverage of nano-level defects, actively blocks the defect transmission chain while improving detection efficiency, and significantly improves chip manufacturing yield and reliability.

[0040] (2) The present invention uses a wavelength-tunable quantum entangled light source array combined with a quantum illumination protocol, switches the illumination mode by dynamically adapting the chip surface reflectivity, and utilizes Zernike phase space compressed sensing imaging technology. This design breaks through the physical bottleneck of traditional optical detection limited by the Abbe diffraction limit, and significantly improves the signal-to-noise ratio capture capability of nano-scale defects, including: sub-surface residues, low-contrast scratches. Compared with the high missed detection rate of existing AOI or laser scattering technology for defects <100nm, this solution enables tiny defects to be stably detected on various surfaces such as metals and dielectrics, thereby preventing fatal defects from flowing into subsequent links at the source of detection, and directly improving the early yield control accuracy of chip manufacturing.

[0041] (3) The present invention captures surface light intensity transients through an event-driven dynamic vision sensor (DVS), and combines the spatiotemporal filtering and sparse coding technology of a pulse neural network to process only the defect signals in the changed area. At the same time, a dynamic resource scheduling mechanism based on a risk heat map is introduced to adaptively allocate high-precision mode, medium-efficiency mode or high-speed mode according to the predicted defect probability. This solves the contradiction between high resolution and full coverage in traditional technologies: while ensuring nanometer-level precision in high-risk areas, the detection speed for low-risk areas is greatly improved. Compared with the full-film low-speed scanning of SEM / AFM or the accuracy compromise solution of AOI, this system achieves the coordinated optimization of full inspection coverage and manufacturing efficiency, shortens the inspection cycle and releases production line capacity.

[0042] (4) The present invention fuses quantum point cloud and pulse coding data through a multimodal feature decoupler, uses a multi-task learning framework to separate the optical, geometric and process features of defects, and uses a meta-knowledge transfer engine to achieve rapid adaptation of defect patterns across scenarios. Combined with the global aggregation of multi-production line process correlation factors by the federated knowledge graph, the system can accurately trace the cause of defects. Compared with the high misjudgment rate and update lag of traditional rule bases or single production line models for complex defects, this solution establishes an evolvable defect-process correlation network, which not only improves the accuracy of defect classification, but also realizes targeted optimization of manufacturing parameters through process factor positioning, reducing re-judgment costs and scrap losses.

[0043] (5) The digital twin constructed by the present invention synchronizes chip design parameters with real-time detection data, and dynamically predicts the evolution path of defects in the process through multi-physics field simulation including: thermal diffusion, stress analysis, and chemical corrosion models. Compared with the limitations of existing technologies that can only identify the current defect morphology, the impact of defects on the reliability of the final device can be predicted in advance, and process correction instructions can be generated. This enables the manufacturing process to shift from passive detection to active prevention, and implements online optimization through process closed-loop control before defects cause chip failure, significantly reducing the failure rate of the later packaging link. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments described in the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive efforts.

[0045] Figure 1 is a flowchart of the steps of a chip surface defect detection method according to a preferred embodiment of the present invention;

[0046] Figure 2 This is an overall flow chart of chip surface defect detection according to a preferred embodiment of the present invention;

[0047] Figure 3 It is a digital twin flow chart of a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0049] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0050] Application Overview:

[0051] The defects of current chip surface defect detection technology restrict improvements in semiconductor manufacturing yield and reliability: 1. Optical resolution is limited by the Abbe diffraction limit, and the theoretical resolution in the visible light band is difficult to exceed 200nm. The detection capability of tiny defects <100nm, such as nanoparticles and shallow residues, is insufficient. Moreover, transparent film residues, low-contrast scratches, etc. are easily drowned out by noise due to weak scattering signals, resulting in a high missed detection rate. 2. High-resolution detection requires narrowing the field of view or extending the exposure time. Offline tools such as SEM and AFM point-by-point scanning are extremely inefficient, forcing production lines to choose between spot checks, reducing accuracy, or sacrificing coverage. This results in insufficient full inspection coverage, extended manufacturing cycles, and hindered production capacity release. 3. Traditional rules / shallow models are difficult to deal with complex defects such as random burrs and mixed contamination. Deep learning relies on massive labeled samples and updates lag, driving up re-judgment costs and scrap losses. 4. Laser scattering relies on surface specular reflection and is reflectivity-sensitive. Optical / SEMs require extremely short working distances, making them unable to cover high-aspect-ratio structures or warped wafers. This requires a combination of multiple instruments, increasing investment and management complexity. These defects collectively create a black box for detection, allowing fatal nanoscale defects to flow into the packaging process, increasing chip failure rates.

[0052] To solve the above problems, this application proposes a chip surface defect visual detection method and system, which dynamically adapts the surface reflectivity through a quantum imaging enhancement module to perform high-sensitivity imaging, and combines event-driven vision and pulse neural networks to achieve sparse and efficient processing of defect signals; based on the real-time generated risk heat map, it intelligently schedules detection accuracy and speed resources, and uses multi-modal feature decoupling and federated knowledge graphs to accurately associate defects with process roots; based on the digital twin module, it synchronously predicts the defect evolution path, drives online tuning of process parameters, and uses multi-physics field simulation to compensate for optical defocus in real time.

[0053] Exemplary methods:

[0054] like Figure 1 、 2 As shown, a chip surface defect visual detection method includes the following steps:

[0055] S1. Obtain the original defect data of the chip surface by dynamically adapting the imaging method of the chip surface reflectivity; in particular, use a wavelength-tunable entangled light source array to obtain imaging; specifically: deploy a wavelength-tunable entangled light source array, enhance the defect scattering signal through the quantum illumination protocol, dynamically switch the light illumination mode based on real-time feedback of the surface reflectivity, and combine Zernike phase space coding compressed sensing imaging to output the original defect data of the chip surface

[0056] S2. After compressing the original defect data, a defect risk prediction heat map is generated, and detection resources are dynamically allocated to obtain secondary detection data. Specifically, event-driven dynamic visual sensing is used to capture changes in light intensity on the chip surface. Spiking neural networks are used to implement spatiotemporal filtering and pulse coding compression processing. At the same time, detection resources are dynamically allocated based on the defect risk prediction heat map.

[0057] S3. Perform multimodal feature decoupling on the secondary inspection data, integrate defect data from multiple production lines to construct a global knowledge graph, and output instantaneous defect classification results and process correlation factors. Multimodal feature decoupling includes separating the optical, geometric, and process characteristics of defects. Specifically, a multimodal feature decoupler is used to process and decouple the data, and a meta-knowledge transfer engine is used to learn and adapt defect knowledge to construct a federated defect knowledge graph. The resulting output is the defect classification results and process correlation factors.

[0058] S4. Input the data of S1-S3 into the digital twin model, perform multi-physics field simulation, and output a dynamically predicted defect evolution path. Specifically, construct a digital twin model to synchronize design parameters and detection data, use multi-physics field simulation to predict the defect evolution path in real time, and establish a dynamic correlation model between defect characteristics and process parameters.

[0059] Finally, in order to further improve the system, a new control step S5 is added to generate process parameter correction instructions based on the twin traceability results, drive the online tuning of manufacturing equipment, and dynamically compensate the optical focal length based on the three-dimensional surface reconstruction data.

[0060] The wavelength-tunable entangled light source array is a special light source system that includes a wavelength-tunable entangled photon source and a compressed state laser. It dynamically outputs wavelength-tunable entangled photon pairs through electro-optical modulation. The reason for using this light source array is that it can cover high-reflection and low-reflection surfaces, thereby adapting to the detection needs of different chip surfaces, including: metal, dielectrics and photoresist. When detecting highly reflective surfaces, the appropriate wavelength can be selected to reduce reflection interference; when detecting low-reflective surfaces, the wavelength can be adjusted to enhance signal capture.

[0061] In step S1, the entanglement degree of the wavelength-tunable entangled light source array is ≥95%, and the photon flux is 10 11 -10 12 photons / s·mm 2The system comprises two entangled photon sources covering the deep ultraviolet and near ultraviolet bands, supplemented by a compressed state laser. The deep ultraviolet source operates at a wavelength of 180-200nm, suitable for highly reflective surfaces, breaking the optical diffraction limit and improving resolution. The near ultraviolet source operates at a wavelength of 340-370nm, suitable for low-reflective surfaces and enhancing the penetration of transparent films. The compressed state laser uses quantum compression technology to reduce light field noise, achieving a noise suppression ratio of >20dB and improving signal stability.

[0062] Traditional monochromatic light sources cannot take into account the defect excitation efficiency of different surfaces. However, the wavelength-tunable entangled light source can dynamically adapt to the light response characteristics of high and low reflective surfaces by covering multiple bands, ensuring the effective excitation of defect scattering signals.

[0063] The quantum illumination protocol is a signal enhancement technology based on the characteristics of quantum entanglement. The signal photon in the entangled photon pair illuminates the chip surface and interacts with the defects to produce scattered light; the idle photon is retained in the local detector. By measuring the quantum correlation between the scattered light and the idle photon, the interference of environmental noise on the signal can be suppressed, thereby extracting the weak defect scattering signal. Specifically, the core mechanism is Among them, ρ out is the final output quantum state, representing the signal actually measured in the quantum illumination system, ρ 缺陷 It is a quantum channel that describes the interaction between the chip surface defects and the environment; this channel will introduce noise or change the quantum state, simulating the effect of defects on quantum signals; ρ 纠缠 is the density matrix of the input entangled photon pairs.

[0064] Compared with traditional classical illumination technology, the quantum illumination protocol can improve the signal-to-noise ratio of defect scattering signals and simultaneously penetrate transparent films to detect subsurface defects underneath.

[0065] The chip surface reflectivity is measured using an InGaAs focal plane sensor and normalized;

[0066] When the reflectivity is greater than 0.7, the surface is highly reflective and quantum dark field illumination is used to suppress specular reflection using annular illumination, capturing only defect scattered light.

[0067] When the reflectivity is between 0.3-0.7, the surface is between a mirror surface and a rough surface. Quantum dark field annular illumination is used to suppress some of the mirror reflections, while superimposing structured light coding to enhance the scattered signal.

[0068] When the reflectivity is less than 0.3, the surface has low reflectivity. Structured light coding illumination combined with computational imaging is used to project sinusoidal stripes through a spatial light modulator. The computational imaging algorithm is used to reconstruct the details of the rough surface and compensate for the random distribution of scattered light caused by the uneven surface.

[0069] By dynamically adapting the surface characteristics and light source bands, the failure of detection under a single lighting mode on different surfaces is avoided, and the contrast of mirror surface defects and the resolution of rough surface details are improved.

[0070] The Zernike polynomial phase code is loaded into the spatial light modulator to encode the defect information on the chip surface into the Fourier domain of the optical system. x ||y-φx||2+λ||x||1, where φ is the Zernike basis measurement matrix, x is the sparse representation of the super-resolution image, y is the observation signal, and λ is the regularization parameter. In chip surface defect detection, it is used to reconstruct a high-resolution defect image from a small amount of observation data. The observation signal y is obtained and the sparsely represented defect image x is solved, thereby achieving high-precision detection of chip surface defects.

[0071] Output raw defect data, i.e., raw defect point cloud, including the three-dimensional coordinates (x, y, z) and signal-to-noise ratio labels of each defect, with a resolution of 12-13nm.

[0072] In step S2, an InGaAs-based dynamic vision sensor with a response wavelength of 900-1700nm is used, which complements the ultraviolet band of the quantum imaging module and expands the multispectral detection capability. The InGaAs-based dynamic vision sensor only triggers events for pixels whose light intensity changes on the chip surface exceed the threshold ΔlogI>0.05, and only transmits light intensity data in the changing area. Static areas indicate no defects and no data output. The time resolution is 8-10μs. The micro-defect signals generated by quantum illumination are mostly instantaneous pulses. DVS reduces the amount of data by ignoring the static background.

[0073] The pulse neural network integrates the Memristor storage and computing chip to perform synaptic weight calculations;

[0074] The input layer receives the DVS event stream (x, y, z, t, p), where t is the timestamp and p is the polarity;

[0075] The hidden layer is Among them, V mem is the membrane potential accumulation value, ω ij is the synaptic weight factor, τ is the time constant, t i ,t j is the event timestamp; when the membrane potential accumulation is less than 20% of the threshold, it is regarded as noise and the event is discarded.

[0076] The events in each 10ms window are converted into a 128-dimensional sparse pulse vector.

[0077] Dynamic resource allocation based on defect risk prediction heat map. Specifically, the original defect point cloud map output by S1 is used to predict the defect risk probability P of each area on the chip surface through a lightweight AI model. defect ,Using historical chip defect data as training data, a heat map is generated, where red is high risk, yellow is medium risk, and green is low risk;

[0078] Data layer:

[0079] Original defect point cloud: 3D coordinates, signal-to-noise ratio, size, and type of each defect;

[0080] Historical chip defect data: stores the defect distribution of chips in historical inspections, corresponding process parameters, and labels indicating the impact of defects on yield;

[0081] Feature extraction:

[0082] The following key features are extracted from the above data as model input:

[0083] Spatial characteristics: defect density, degree of defect spatial clustering, and distance from defects to critical functional areas;

[0084] Signal characteristics: defect confidence;

[0085] Process correlation characteristics: the matching degree between the process parameters of the current chip and the process parameters of historical high-risk defects;

[0086] Divide the chip surface into K grid areas, each grid is a graph node u k , the node feature is the fusion feature of the region They are defect density, clustering coefficient, average distance, average confidence, and process matching;

[0087] The spatial correlation features of the graph are extracted by two layers of GCN, and the hidden state update formula of node k is: in, is the hidden state of node k in the lth layer, N(k) is the neighbor set of node k, d k is the number of neighbors of node k, W (l) , b (l) is the weight matrix and bias of the lth layer, and σ is the activation function.

[0088] The model outputs the risk probability P for each node k defect .

[0089] When P defectWhen the value is >0.8, it is a high-risk area and the quantum super-resolution detection mode is called. The deep ultraviolet band entangled light source is combined with Zernike phase encoding to increase the resolution to 12-13nm and reduce the detection speed to 1.5-2mm. 2 / s;

[0090] When P defect When the range is 0.3-0.8, it is a medium-risk area and switches to multi-spectral fusion mode, combining ultraviolet and near-infrared data, with a resolution of 45-50nm and a speed of 18-20mm. 2 / s;

[0091] When P defect When the value is less than 0.3, it is a low-risk area. It adopts wide-field rapid scanning mode, uses structured light encoding in the near-infrared band, has a resolution of 150-200nm, and a speed of 80-100mm. 2 / s.

[0092] In step S3, the original defect point cloud data and pulse code event stream are received, and the data are fused. The multimodal hybrid feature X={X 光学 , X 几何 , X 工艺}, respectively, come from the sparse pulse data output by S2, the defect point cloud image output by S1, and the manufacturing process parameters;

[0093] The decoupling model structure adopts a multi-task learning framework and includes three sub-networks. The defect feature extractor is based on CNN+GNN to extract the optical and geometric features of the defects, which is similar to the S2 feature extraction step; the process association extractor is based on the autoencoder to extract the latent variables of the process parameters; the decoupling loss function constrains the independence of defect features and process features.

[0094] Among them, the process correlation extraction adopts self-encoding; the encoder e(X 工艺 )=W e X 工艺 +b e , X 工艺 The input process parameter vector includes the key parameters in the manufacturing process, including photoresist thickness, etching rate, and annealing temperature, and the output latent variable z; decoder d(z) = W d z+b d , reconstructing process parameters W,b is the weight matrix and the bias vector for .

[0095] Meta-knowledge migration engine construction:

[0096] Meta-knowledge K contains common defect patterns and is stored as transferable parameters are the weights of the optical and geometric feature extractors and the weight of the general defect classifier, respectively;

[0097] When adapting to new scenes, use a small number of newly labeled samples Among them, y (i) is the defect type label, is the defect content, N is the number of samples;

[0098] Fine-tuning the meta-parameters θ via the MAML algorithm meta to scene-specific parameters.

[0099] Each production line k builds a knowledge subgraph G based on local defect data k ={T k ,R k}, where T k The triple set is (h, r, t), which represents the head entity, relation, and tail entity; R k is the relationship weight, which represents the confidence of the triple, calculated by the frequency of occurrence of the association in the local data;

[0100] Each production line aggregates knowledge subgraphs through federated learning to generate a global knowledge graph Among them, the total number of production lines is K, ω k is the weight of production line k, τ is the confidence threshold; is the process-related factor,

[0101] The defect classification result is output through the classifier as the defect type probability distribution y.

[0102] like Figure 3 As shown, in step S4, the digital twin is a virtual mapping of the entire chip manufacturing process, which is constructed by real-time synchronization of design parameters and test data;

[0103] Access the chip design database to obtain the original design parameters, including transistor size, metal layer spacing, and material thermal expansion coefficient, as the initial state of the twin;

[0104] Receive the inspection data output by S1-S3 in real time and update the current manufacturing status of the twin;

[0105] Based on synchronized data, multi-physics simulation is used to simulate the evolution path of defects in the manufacturing process;

[0106] Predict the thermal diffusion behavior of nanoparticles in high-temperature processes and simulate defect diffusion: Where C is the particle concentration distribution, D 热 is the thermal diffusion coefficient, k is the thermal conductivity; by solving this equation, the diffusion path of the particles in the substrate is simulated and the size of the particles after diffusion is calculated;

[0107] Calculate the impact of chip warpage or film stress on the expansion of scratch defects: There is stress concentration at the scratch defect, and the stress intensity factor K in fracture mechanics is used to assess the expansion risk Where Y is the geometric correction factor, σ is the applied stress, and a is the initial length of the scratch. When K exceeds the fracture toughness of the material, the scratch will expand, and the simulation outputs the expansion direction and expansion amount.

[0108] Analyze the corrosion effect of etching solution or cleaning solution on residual photoresist, solve the dissolution equation by integration, simulate the change of photoresist residue over time, and the dissolution rate equation Where m is the mass of the photoresist, A is the surface area in contact with the solution; k 溶 is the dissolution rate constant, C 溶 is the solution concentration, and t is the contact time.

[0109] Through multi-physics field coupling simulation, the dynamic evolution state of the defect is finally output, including: size change, position migration and type transformation.

[0110] Combine data-driven methods to explore the relationship between defect characteristics and process parameters and conduct model training;

[0111] Extract process parameter feature X t , defect characteristics ΔD t , using a data-driven approach to model the dynamic relationship between process parameters and defect evolution in the form of ΔD t =f(X t )+ε t , where f is the correlation function, ε t is noise; the mean square error is used as the loss function to minimize the prediction error, so that the trained correlation model can predict the defect evolution path under given process parameters; the dynamic correlation model is used for real-time prediction and process optimization.

[0112] During the system improvement process, the defect evolution path is analyzed and equipment tuning instructions are generated: the etcher adjusts the RF power and exposure dose; the CMP equipment adjusts the pressure and dynamically compensates the gas flow; the deposition equipment modifies the gas flow rate to suppress scratches;

[0113] Dynamic compensation of optical focal length reconstructs the surface topography based on the defect point cloud output by S1, and adjusts the objective lens focal length in real time through the piezoelectric ceramic driver Where α is the focal length-curvature conversion coefficient, and S is the surface topography function (x, y, z).

[0114] Example systems:

[0115] A chip surface defect visual inspection system, comprising:

[0116] The quantum imaging enhancement module receives chip surface reflectivity data and generates a wavelength-tunable quantum entangled illumination signal. It dynamically switches the illumination mode based on real-time reflectivity and outputs compressed sensing imaging defect point cloud data.

[0117] The dynamic event processing module acquires the point cloud data from the quantum imaging module and captures the event stream of surface light intensity changes. It performs pulse neural network spatiotemporal filtering on the event stream to generate 128-dimensional sparse pulse coded data and transmits the risk heat map to the resource scheduling module.

[0118] The risk scheduling module receives the risk heat map from the dynamic event processing module, dynamically allocates detection parameters based on the risk value, and feeds back lighting mode instructions to the quantum imaging module;

[0119] The multimodal decoupling module integrates the point cloud data of the quantum imaging module and the pulse coded data of the dynamic event processing module. It decouples the optical, geometric and process characteristics of the defect through a multi-task framework and outputs the process correlation factors to the knowledge graph engine.

[0120] The federated knowledge construction module aggregates process-related factor data from multiple production lines, constructs a global defect knowledge graph, and provides the process-defect mapping relationship to the prediction module;

[0121] The digital twin prediction module synchronizes chip design parameters with real-time feature data from the multimodal decoupling module; calls the multi-physics simulation model to predict defect evolution paths, generates process parameter correction instructions, and transmits them to the process closed-loop control module;

[0122] The dynamic compensation module analyzes the defect point cloud data of the quantum imaging module, generates optical focal length compensation, and corrects the defocus error of the imaging module in real time;

[0123] The process closed-loop control module receives process correction instructions from the digital twin prediction module, converts parameter instructions into equipment control signals, and feeds back to the manufacturing production line in real time.

[0124] The above description is based on the ideal embodiment of the present invention. Based on the above description, relevant personnel can make various changes and modifications without departing from the technical scope of this invention. The technical scope of this invention is not limited to the content of the specification and must be determined according to the scope of the claims.

Claims

1. A chip surface defect visual detection method, characterized in that: Including steps: S1. Obtaining raw defect data on the chip surface by dynamically adapting the chip surface reflectivity to the imaging method; wherein the imaging is obtained using a wavelength-tunable entangled light source array, and the raw defect data includes a raw defect point cloud image; S2. After compressing the original defect data, a defect risk prediction heat map is generated, and detection resources are dynamically allocated to obtain secondary detection data; S3. Perform multimodal feature decoupling on the secondary inspection data, integrate defect data from multiple production lines to build a global knowledge graph, and output instantaneous defect classification results and process correlation factors; wherein the multimodal feature decoupling includes separating the optical features, geometric features, and process features of the defects; S4. Input the data of S1-S3 into the digital twin model, perform multi-physics field simulation, and output the dynamic prediction defect evolution path.

2. The chip surface defect visual detection method according to claim 1, characterized in that: In step S1, the wavelength-tunable entangled light source array includes entangled photon sources and compressed state lasers in the deep ultraviolet and near ultraviolet bands; the deep ultraviolet band has a wavelength of 180-200nm and is used for highly reflective surfaces to break the diffraction limit, and the near ultraviolet band has a wavelength of 340-370nm and is used for low-reflective surfaces to enhance the penetration of transparent films; the defect scattering signal of the entangled light source is enhanced through a quantum illumination protocol, and the noise suppression ratio of the compressed state laser is greater than 20dB; The chip surface reflectivity is measured using an InGaAs focal plane sensor, and the lighting mode is dynamically switched based on the reflectivity, including: quantum dark field illumination when the reflectivity is >0.7, quantum dark field superimposed structured light coding when the reflectivity is 0.3-0.7, and structured light coding combined with computational imaging when the reflectivity is <0.3; The original defect point cloud image is output through Zernike phase space coding compressed sensing imaging with a resolution of 12-13nm.

3. The chip surface defect visual detection method according to claim 1, characterized in that: In step S2, changes in light intensity on the chip surface are captured using event-driven dynamic visual sensing. The event-driven dynamic visual sensor has a response wavelength of 900-1700nm and a time resolution of 8-10μs. When the light intensity change on the chip surface ΔlogI>0.05, the original defect data of the changed area is transmitted. The original defect data is compressed by combining a spiking neural network for spatiotemporal filtering and pulse coding, and the events within each 10ms window are converted into a 128-dimensional sparse pulse vector. For the compressed defect data, the defect risk probability on the chip surface is predicted based on the AI ​​model to generate a defect risk prediction heat map.

4. The chip surface defect visual detection method according to claim 3, characterized in that: The method of dynamically allocating detection resources is: when the risk probability is greater than 0.8, quantum super-resolution detection mode is used, with a resolution of 12-13nm and a speed of 1.5-2mm. 2 / s, when the risk probability is 0.3-0.8, the multi-spectral fusion mode is used, the resolution is 45-50nm, and the speed is 18-20mm 2 / s, when the risk probability is <0.3, the wide-field fast scanning mode is used, with a resolution of 150-200nm and a speed of 80-100mm 2 / s.

5. The chip surface defect visual detection method according to claim 3, characterized in that: In step S3: multimodal feature decoupling includes: The defect feature extractor decouples optical features from geometric features and uses a neural network algorithm to extract corresponding features from the sparse pulse vector of S2 and the original defect point cloud image of S1; The process correlation extractor extracts the latent variables of process parameters, and the encoder e(X 工艺 )=W e X 工艺 +b e , X 工艺 The input process parameter vector contains the key parameters in the manufacturing process, including photoresist thickness, etching rate, and annealing temperature, and the output is the latent variable z; Decoder d(z)=W d z+b d , reconstructing process parameters W,b is the weight matrix and the bias vector for .

6. The chip surface defect visual detection method according to claim 1, characterized in that: In step S3, a global knowledge graph is constructed by integrating and building a federated defect knowledge graph: Each production line k builds a knowledge subgraph G based on local defect data k ={T k ,R k }, where T k The triple set is (h, r, t), which represents the head entity, relation, and tail entity; R k is the relationship weight, which represents the confidence of the triple, calculated by the frequency of occurrence of the association in the local data; Each production line aggregates knowledge subgraphs through federated learning to generate a global knowledge graph Among them, the total number of production lines is K, ω k is the weight of production line k, τ is the confidence threshold; is the process correlation factor, and the defect classification result is output through the classifier as the defect type probability distribution y.

7. The chip surface defect visual detection method according to claim 1, characterized in that: In step S4, the multi-physics field simulation includes: predicting the diffusion path of nanoparticles in high-temperature processes based on a thermal diffusion model; evaluating the expansion risk of chip scratches based on a stress intensity factor model; and simulating the dissolution of photoresist residues in a corrosive environment based on a dissolution rate model.

8. The chip surface defect visual detection method according to claim 1, characterized in that: Through multi-physics field coupling simulation, the dynamic evolution state of chip defects is ultimately output, including size change, position migration, and type transformation. Combined with data-driven methods, the correlation between defect characteristics and process parameters is explored, model training is performed, and the defect evolution path under given process parameters is predicted.

9. The chip surface defect visual detection method according to claim 3, characterized in that: The pulse neural network integrates storage and computing chips to perform synaptic weight calculations; The input layer receives the DVS event stream (x, y, z, t, p), where t is the timestamp and p is the polarity; The hidden layer is Among them, V mem is the membrane potential accumulation value, ω ij is the synaptic weight factor, τ is the time constant, t i ,t j is the event timestamp; when the membrane potential accumulation is less than 20% of the threshold, it is regarded as noise and the event is discarded.

10. A chip surface defect visual detection system based on a chip surface defect visual detection method according to any one of claims 1 to 9, characterized in that: Included modules: The quantum imaging enhancement module receives chip surface reflectivity data and generates a wavelength-tunable quantum entangled illumination signal. It dynamically switches the illumination mode based on real-time reflectivity and outputs compressed sensing imaging defect point cloud data. The dynamic event processing module acquires the point cloud data from the quantum imaging module and captures the event stream of surface light intensity changes. It performs pulse neural network spatiotemporal filtering on the event stream to generate 128-dimensional sparse pulse coded data and transmits the risk heat map to the resource scheduling module. The risk scheduling module receives the risk heat map from the dynamic event processing module, dynamically allocates detection parameters based on the risk value, and feeds back lighting mode instructions to the quantum imaging module; The multimodal decoupling module integrates the point cloud data of the quantum imaging module and the pulse coded data of the dynamic event processing module. It decouples the optical, geometric and process characteristics of the defect through a multi-task framework and outputs the process correlation factors to the knowledge graph engine. The federated knowledge construction module aggregates process-related factor data from multiple production lines, constructs a global defect knowledge graph, and provides the process-defect mapping relationship to the prediction module; Digital twin prediction module, synchronizing chip design parameters with real-time feature data from the multimodal decoupling module; Call the multi-physics simulation model to predict the defect evolution path, generate process parameter correction instructions and transmit them to the process closed-loop control module; Dynamic compensation module, which analyzes the defect point cloud data of the quantum imaging module; Generate optical focal length compensation and correct the defocus error of the imaging module in real time; The process closed-loop control module receives process correction instructions from the digital twin prediction module, converts parameter instructions into equipment control signals, and feeds back to the manufacturing production line in real time.

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