A semiconductor chip surface defect detection method and system

Abstract

The present application belongs to the technical field of semiconductor chip detection, and provides a semiconductor chip surface defect detection method and system, which comprises the following steps: collecting chip images of a semiconductor chip to integrate into a chip image sequence, identifying a suspected defect area in the chip image, matching the suspected defect area in the chip image sequence to obtain a matching group, judging whether the suspected defect area is a real defect area according to the matching group, if yes, intercepting the real defect area to obtain a defect image sequence, constructing and training a defect recognition model, identifying the surface defect type of the defect image sequence, and evaluating the accuracy of the identification, if the accuracy is low, triggering fusion defect review analysis, if the fusion defect review analysis is triggered, positioning an actual defect position area on the semiconductor chip according to the defect image sequence, collecting and processing to obtain fusion features of the actual defect position area, and identifying the actual surface defect type by using a graph neural network.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor chip detection, and in particular relates to a semiconductor chip surface defect detection method and system. BACKGROUND

[0002] As the core component of modern electronic devices, the quality of semiconductor chips directly determines the performance and reliability of electronic devices. During the manufacturing process of semiconductor chips, due to the complexity of production processes, purity requirements of raw materials, and slight fluctuations in production environment, various defects such as scratches, particle contamination, and lattice distortion may occur on the surface of the chip. These surface defects not only affect the electrical performance of the chip, leading to abnormal chip function, but also reduce the yield of the chip and increase the production cost. Therefore, accurate and efficient detection of surface defects of semiconductor chips is of great significance for ensuring chip quality, improving production efficiency, and reducing production cost.

[0003] In existing semiconductor chip surface defect detection methods, chip images are usually first collected, and then the images are analyzed to identify defect regions. However, due to the presence of natural textures on the chip surface, noise interference, and uneven illumination during image acquisition, misjudgment is likely to occur, which not only increases the amount of data for subsequent processing and reduces detection efficiency, but also may lead to a decrease in attention to real defect regions, affecting the accuracy of defect detection.

[0004] On the other hand, existing technologies also have certain limitations in surface defect type identification, with a prominent sample imbalance problem, which may cause traditional defect identification models to fail to fully learn the complex features of various defect types, thus reducing the accuracy of identification of some rare or complex defect types, and reducing the accuracy of defect type identification. The existing technology lacks effective review analysis mechanism, and for some complex defect conditions such as mixing of multiple defect types, similarity between defects and chip surface textures, etc., the existing technology is difficult to provide accurate defect type judgment, thereby affecting the comprehensive evaluation and processing of chip defects.

[0005] To solve the above problems, the present application proposes a semiconductor chip surface defect detection method and system. SUMMARY

[0006] In order to make up for the deficiencies of the prior art and solve at least one technical problem in the background art.

[0007] The technical solution adopted by the present application to solve the technical problem is: a semiconductor chip surface defect detection method, comprising:

[0008] Collecting chip images of semiconductor chips to integrate into a chip image sequence, and identifying suspected defect regions within the chip images;

[0009] Matching the suspected defect region in the chip image sequence to obtain a matching group, judging whether the suspected defect region is a real defect region according to the matching group, if yes, intercepting the real defect region to obtain a defect image sequence;

[0010] Constructing and training a defect recognition model, identifying the surface defect type of the defect image sequence, and evaluating the accuracy of the identification, if the accuracy is high, obtaining the actual surface defect type, if the accuracy is low, triggering fusion defect review analysis;

[0011] If the fusion defect review analysis is triggered, the actual defect position region is located on the semiconductor chip according to the defect image sequence, the fusion features of the actual defect position region are collected and processed, and the actual surface defect type is identified based on the fusion features using a graph neural network

[0012] The identification method of the suspected defect region is as follows:

[0013] A difference threshold value is set according to the pixel fluctuation range of the normal region on the surface of the semiconductor chip, a pixel point image difference value is obtained, if it is greater than the difference threshold value, a suspected defect mark is added to the pixel point, the pixel points with suspected defect marks adjacent in coordinates are integrated into the same suspected defect group, if the number of pixel points in the suspected defect group reaches a standard number, the region corresponding to the suspected defect group is judged as a suspected defect region;

[0014] The acquisition method of the pixel point image difference value is as follows:

[0015] A displacement parameter is set for the semiconductor chip to control the displacement of the semiconductor chip, a shooting parameter is set for the high-resolution industrial camera, chip images are collected by shooting during the displacement process, the chip images are preprocessed and integrated to obtain a chip image sequence;

[0016] A qualified chip sample is obtained, the same displacement parameter and shooting parameter are used for shooting and collection to obtain a standard chip image sequence, the chip image sequence and the standard chip image sequence are one-to-one corresponding and compared, and the pixel point image difference value of each pixel point is calculated through data processing;

[0017] The judgment method of whether the suspected defect region is a real defect region is as follows:

[0018] Each matching group is obtained, the number of suspected defect regions in the matching group and the number of all chip images in the chip image sequence are data processed to obtain the defect performance ratio of the matching group, if greater than or equal to a preset ratio standard, it is judged that the suspected defect regions in the matching group are all real defect regions;

[0019] The acquisition method of the matching group is as follows:

[0020] The suspected defect regions in each chip image in the chip image sequence are matched, and double matching constraint conditions including spatial displacement constraints and area change constraints are set;

[0021] For the first chip image in the chip image sequence, the suspected defect region is set as the matching starting point, any suspected defect region in the next chip image of the matching starting point is obtained, if the two suspected defect regions satisfy the double matching constraint conditions, they are divided into the same matching group, the matching starting point is changed to the suspected defect region with the latest time sequence in the matching group, and the matching is continued;

[0022] If none of the suspected defect regions in the next chip image of the matching starting point satisfies, the matching is performed in the next chip image, and after traversing the chip image sequence, the suspected defect region in the first chip image which is not included in any matching group is included in a matching group itself, if there is still a suspected defect region which is not included in a matching group, the chip image of the first suspected defect region is regarded as the first chip image in the chip image sequence, and the corresponding matching starting point is set for re-matching;

[0023] The judgment method of satisfying the double matching constraint conditions is:

[0024] In terms of spatial displacement constraints, the matching of the matching starting point and any suspected defect region in the next chip image in the chip image sequence is performed, the centroid coordinates of the two suspected defect regions in the corresponding chip image are obtained respectively and the Euclidean distance is calculated, the displacement distance range is calculated and set based on the displacement parameters of the semiconductor chip, and if the Euclidean distance falls within the displacement distance range, the spatial matching of the two suspected defect regions is judged;

[0025] In terms of area change constraints, for the two spatially matched suspected defect regions, the area change rate between the two suspected defect regions is calculated, and if it is less than the change threshold, it is judged that the two suspected defect regions are area matched, that is, the two suspected defect regions satisfy the double matching constraint conditions;

[0026] The evaluation method of the accuracy of the recognition is:

[0027] The surface defect types recognized by all defect images in the defect image sequence are obtained, the surface defect type with the largest number of defect images is obtained as the recognized surface defect type of the defect image sequence, the confidence corresponding to the recognized surface defect type is obtained for data processing to obtain the recognition confidence, and the number of defect images corresponding to the recognized surface defect type is obtained for data processing to obtain the recognition defect ratio;

[0028] If the recognition confidence and the recognition defect ratio of the defect image sequence both satisfy the accurate judgment condition, the accuracy of the recognition is high;

[0029] The identification mode of the surface defect type is as follows:

[0030] A convolutional neural network is used as a core model, a hierarchical feature extraction structure is designed according to the characteristics of the semiconductor chip defect image, and a defect recognition model is constructed and trained;

[0031] The defect recognition model is input with a defect image sequence, and a probability vector of the defect image is output, the maximum probability value in the probability vector is taken as a confidence degree, and the surface defect type corresponding to the confidence degree is the surface defect type of the defect image;

[0032] The acquisition mode of the fusion feature is as follows:

[0033] For the actual defect position area on the semiconductor chip, a high-resolution line scanning photoelectric sensor is used to perform raster scanning on the surface of the semiconductor chip in the actual defect position area, to obtain a photoelectric feature image, and a phased array ultrasonic detection system is used to perform point-by-point scanning on the actual defect area, to obtain an ultrasonic feature image of the actual defect position area;

[0034] The photoelectric feature image and the ultrasonic feature image collected are subjected to feature extraction, splicing and weighted fusion processing, to obtain the fusion feature.

[0035] A semiconductor chip surface defect detection system comprises the following modules:

[0036] A collection and preliminary screening module: chip images of a semiconductor chip are collected and integrated into a chip image sequence, and a suspected defect area in the chip image is identified;

[0037] A defect intercepting module: a matching group is obtained by matching the suspected defect area in the chip image sequence, and it is judged whether the suspected defect area is a real defect area according to the matching group, if yes, the real defect area is intercepted to obtain a defect image sequence;

[0038] A defect recognition module: a defect recognition model is constructed and trained, the surface defect type of the defect image sequence is identified, and the accuracy of the identification is evaluated, if the accuracy is high, the actual surface defect type is obtained, if the accuracy is low, fusion defect review analysis is triggered;

[0039] A fusion review module: if the fusion defect review analysis is triggered, the actual defect position area is located on the semiconductor chip according to the defect image sequence, fusion features of the actual defect position area are collected and processed, and the actual surface defect type is identified based on the fusion features by using a graph neural network.

[0040] The beneficial effects of the present application are as follows:

[0041] 1、The application can accurately distinguish real defects from misjudgment areas by matching and judging the suspected defect area in the chip image sequence, avoid treating non-defect areas as defects, reduce subsequent invalid analysis, improve overall detection efficiency, and at the same time, the real defect area is intercepted to form a defect image sequence, which provides targeted data for subsequent defect type identification, makes the identification process more focused, reduces the influence of interference factors, and ensures the accuracy and reliability of the identification result.

[0042] 2、The application has defect review analysis capability, which guarantees the comprehensiveness of the detection result, when the accuracy of the defect identification model is low, the fusion defect review analysis mechanism is triggered, the actual defect position area is located according to the defect image sequence, the fusion features are collected and processed, and the graph neural network is used for identification, which can fully excavate the multi-dimensional information of the defect, cope with complex defect conditions, effectively identify rare or complex defect types, avoid missed detection and false detection, and provide solid guarantee for semiconductor chip quality control. BRIEF DESCRIPTION OF DRAWINGS

[0043] The application will be further described below with reference to the accompanying drawings.

[0044] Figure 1 is a step flow chart of a semiconductor chip surface defect detection method according to an embodiment of the application;

[0045] Figure 2 is a system module architecture diagram of a semiconductor chip surface defect detection system according to an embodiment of the application. DETAILED DESCRIPTION

[0046] In order to make the technical means, creative features, purposes and effects realized by the application easy to understand, the application will be further described below with reference to the specific embodiments.

[0047] Embodiment 1:

[0048] Please refer to Figure 1 A semiconductor chip surface defect detection method according to an embodiment of the application, which includes the following steps:

[0049] S1: Collecting chip images of a semiconductor chip to integrate into a chip image sequence, and identifying suspected defect areas in the chip images;

[0050] The semiconductor chip is irradiated by a ring-shaped LED array light source, for each semiconductor chip to be detected, the same displacement parameters, including displacement path and displacement rate, are set for the semiconductor chip under the ring-shaped LED array light source, and the semiconductor chip is controlled to move according to the set displacement parameters, and the period during which each semiconductor chip to be detected moves according to the set displacement parameters is marked as the displacement collection period of the semiconductor chip;

[0051] A high-resolution industrial camera is used, shooting parameters are set for the high-resolution industrial camera, the shooting parameters including shooting frequency, shooting resolution, longitudinal distance between a shooting lens and a chip surface, and shooting lens focal length, so that the camera field of view of the high-resolution industrial camera can completely cover the chip surface detection area within the displacement collection period, within the displacement collection period, the semiconductor chip is shot by the high-resolution industrial camera according to the set shooting parameters, and a chip image of the semiconductor chip is obtained, and the time when the high-resolution industrial camera shoots is marked as a collection time;

[0052] Based on any semiconductor chip, the chip image shot within the corresponding displacement collection period is preprocessed including gray scale conversion, median filter denoising and image enhancement, to obtain a preprocessed chip image, and the preprocessed chip images at each collection time are integrated according to the time sequence to obtain a chip image sequence of the semiconductor chip;

[0053] A qualified chip sample that is from the same batch as the semiconductor chip to be detected, has undergone strict detection and has no defects is obtained, the same displacement parameters and shooting parameters are used to shoot the qualified chip sample to obtain a standard chip image, the standard chip image is also preprocessed including gray scale conversion, median filter denoising and image enhancement to obtain a preprocessed standard chip image, and the preprocessed standard chip images at each collection time are integrated according to the time sequence to obtain a standard chip image sequence;

[0054] The chip image sequence and the standard chip image sequence are corresponded one by one, for the corresponding chip image and standard chip image in the chip image sequence and the standard chip image sequence, the corresponding chip image and standard chip image are compared, and a suspected defect area is identified by calculating a pixel point image difference value, and the pixel point image difference value D(x, y) calculation formula is:

[0055] ;

[0056] Wherein, I(x, y) represents the pixel value of the pixel point of the chip image at coordinates (x, y), and L(x, y) represents the pixel value of the pixel point of the standard image at the corresponding coordinates;

[0057] According to the pixel fluctuation range of the normal area on the surface of the semiconductor chip, a difference threshold value is set, if the pixel point image difference value D(x, y) is greater than the set difference threshold value, a suspected defect mark is added to the pixel point, the pixel points with suspected defect marks adjacent to the coordinates are integrated into the same suspected defect group, and if the pixel point with the suspected defect mark is not integrated into any suspected defect group, the suspected defect mark of the pixel point is cleared;

[0058] The suspected defect group is analyzed, if the number of pixel points in the suspected defect group is less than the standard number, the suspected defect mark of the pixel point in the suspected defect group is cleared, otherwise, it is judged that the region corresponding to the suspected defect group is a suspected defect region;

[0059] The chip image in the chip image sequence is analyzed to obtain the suspected defect region of the chip image at each collection time;

[0060] It should be noted that the role of this step is to obtain the image sequence of the chip in the movement process by setting the fixed displacement parameter and the shooting parameter, ensure the complete coverage of the detection region, perform gray scale conversion, denoising and enhancement on the image, preliminarily screen out the suspected defect region through the pixel difference calculation with the standard image sequence, unify the displacement and shooting parameter, eliminate the interference of chip movement and view angle change, ensure the space-time consistency of the image sequence, realize the continuous coverage scanning of the chip surface by controlling the chip movement track and the shooting parameter, and solve the problem of insufficient view field in static shooting;

[0061] S2: The suspected defect region in the chip image sequence is matched to obtain a matching group, whether the suspected defect region is a real defect region is judged according to the matching group, if yes, the real defect region is intercepted to obtain a defect image sequence;

[0062] In the current displacement collection period, the suspected defect region of the chip image at each collection time in the chip image sequence is obtained and matched;

[0063] Specifically, a double matching constraint condition including a spatial displacement constraint and an area change constraint is set;

[0064] For any suspected defect region in the first chip image in the chip image sequence, the suspected defect region is taken as a matching starting point, in terms of the spatial displacement constraint, any suspected defect region in the next chip image of the matching starting point in the chip image sequence is obtained and matched with the suspected defect region of the matching starting point, and the centroid coordinates of the two suspected defect regions in the corresponding chip image are respectively obtained and The Euclidean distance of the two centroid coordinates is calculated , and the formula is:

[0065] ;

[0066] The displacement distance range is calculated and set based on the displacement parameter of the semiconductor chip, if the Euclidean distance of the two centroid coordinates falls within the displacement distance range, the spatial matching of the two suspected defect regions is judged;

[0067] In terms of the area change constraint, for the two suspected defect regions matched in space, the area change rate between the two suspected defect regions is calculated , the formula is:

[0068] ;

[0069] wherein, and respectively represent the number of pixel points in the two suspected defect areas;

[0070] If the area change rate calculated is less than the change threshold, it is judged that the two suspected defect areas are area-matched, that is, the two suspected defect areas satisfy the double matching constraint condition, the two suspected defect areas are divided into the same matching group, and the matching starting point is changed to the suspected defect area with the last time sequence in the matching group, and the matching is continued in the next chip image after the changed matching starting point;

[0071] If all suspected defect areas in the next chip image of the matching starting point in the chip image sequence do not satisfy the double matching constraint condition with the suspected defect area of the matching starting point, then the matching is performed with the suspected defect area of the matching starting point in the next chip image;

[0072] For each suspected defect area in the first chip image in the chip image sequence, matching is performed, and after traversing the entire chip image sequence, the suspected defect area in the first chip image which is not included in any matching group is included in a matching group by itself;

[0073] If there are still suspected defect areas which are not included in any matching group in the chip image sequence, the first chip image in which the suspected defect area which is not included in any matching group exists is regarded as the first chip image in the chip image sequence, a corresponding matching starting point is set, and re-matching is performed in all suspected defect areas which are not included in any matching group;

[0074] The entire chip image sequence is repeatedly traversed until all chip images are included in any matching group, and for each matching group, the number of suspected defect areas in the matching group is compared with the number of all chip images in the chip image sequence to obtain the defect appearance ratio of the matching group;

[0075] If the defect appearance ratio is less than a preset ratio standard, it is judged that the suspected defect areas in the matching group appear less frequently in the chip image sequence, which may be caused by accidental factors such as noise, light fluctuation and the like at the shooting moment, and thus the suspected defect areas in the matching group are all false defects caused by shooting errors;

[0076] If the defect appearance ratio is greater than or equal to the preset ratio standard, it is judged that the suspected defect areas in the matching group are all real defect areas;

[0077] For the obtained real defect area, a rectangular region is determined in the chip image corresponding to the real defect area, with the centroid of the real defect area as the center, the width of the rectangular region is set to 1.5 times the minimum circumscribed rectangle width of the real defect area, and the length-width ratio of the rectangular region is the same as that of the preset fixed size;

[0078] In the chip image, a rectangular region is intercepted, and the image in the rectangular region is enlarged to a preset fixed size by using bicubic interpolation, and the gray values of adjacent pixels are used to linearly interpolate and supplement the blurred or missing pixels that may occur during image enlargement, to obtain a defect image;

[0079] It should be noted that the length and width of the rectangular region are set to ensure that the intercepted image contains complete defect information and certain peripheral background information, which helps the defect recognition model to better learn the defect features in subsequent identification;

[0080] The defect images obtained by intercepting the real defect area in the matching group are integrated according to the time sequence to obtain a defect image sequence;

[0081] It should be noted that the purpose of this step is to establish the space-time correlation of different suspected defect areas through spatial displacement constraint and area change constraint, form a matching group, and distinguish real defects from shooting errors according to the matching group. Through double constraint conditions, more rigorous defect area correlation rules are constructed to improve the detection reliability of real defects, ensure the stable performance of the same defect at different collection times, realize the quantitative analysis of defect stability through the frequency of the matching group, avoid subjective judgment to exclude accidental factors, intercept the area containing defects and peripheral background and enlarge the preprocessing, and provide high-quality image input for subsequent identification;

[0082] S3: Construct and train a defect recognition model to identify the surface defect type of the defect image sequence and evaluate the accuracy of the identification. If the accuracy is high, the actual surface defect type is obtained. If the accuracy is low, a fusion defect review analysis is triggered;

[0083] A convolutional neural network (CNN) is used as the core model, a hierarchical feature extraction structure is designed for the characteristics of semiconductor chip defect images, and a defect recognition model is constructed;

[0084] Specifically, the defect recognition model includes an input layer, a feature extraction layer, and a feature fusion and classification layer.

[0085] The input layer inputs an image with a preset fixed size and a single-channel grayscale image data type;

[0086] The feature extraction layer comprises three convolutional layers, three batch normalization layers, and two pooling layers. Parameters are configured for the feature extraction layer as follows: Convolutional layer 1 uses 64 3×3 kernels with a stride of 1, padding of 1, and ReLU activation function to extract low-level features such as basic edges and corners of defective images. Convolutional layer 2 uses 128 3×3 kernels with the same configuration as convolutional layer 1 to extract mid-level features such as textures and patterns. Convolutional layer 3 uses 256 3×3 kernels with the same configuration as convolutional layer 1 to extract high-level features such as complex geometric structures. The normalization dimension of the batch normalization layer is set to the channel dimension to accelerate training convergence and alleviate gradient vanishing. The max pooling layer uses 2×2 pooling kernels with a stride of 2 to reduce feature dimensionality and enhance scale invariance.

[0087] The feature fusion and classification layer includes a global average pooling layer, a fully connected layer 1, a fully connected layer 2, and an output layer. The global average pooling layer is used to compress the defect image into a one-dimensional feature vector. The fully connected layer 1 has 1024 neurons and uses the ReLU activation function for non-linear feature transformation. The fully connected layer 2 has 512 neurons and uses the same activation function as the fully connected layer 1 to further fuse high-level features. The output layer has M neurons and uses the Softmax activation function to output a probability distribution vector.

[0088] A database of semiconductor chip surface defect images accumulated through historical inspections contains M types of surface defects, with the number of sample images for each type being [number missing]. , where i represents the number of the semiconductor chip surface defect type;

[0089] Each sample image is labeled with its corresponding defect type, and data augmentation is performed, including geometric transformation, photometric transformation, and noise injection, using weighted cross-entropy loss. As a loss function, it is used to solve the problem of imbalanced samples, and the formula is:

[0090] ;

[0091] in, This indicates the true label of the sample image n belonging to the surface defect type m. The true label is either 0 or 1. This represents the predicted probability of the surface defect identification model. The weights representing surface defect type m are:

[0092] ;

[0093] in, N represents the number of sample images for surface defect type m, and N represents the total number of sample images for all surface defect types.

[0094] In the training process, an Adam optimizer is used as an optimizer, a cosine annealing strategy is used for learning rate scheduling, a batch size, a training round number and an early stopping mechanism are set, a semiconductor chip surface defect image library is used to train the defect recognition model, and a trained defect recognition model is obtained.

[0095] The acquired defect image sequence is input into the trained defect recognition model, high-level feature maps are generated through convolution layers and pooling layers, a probability vector of the defect image is output through a full connection layer and a Softmax function, a surface defect type corresponding to a maximum probability value in the probability vector is taken as the surface defect type of the defect image, and the maximum probability value is taken as a confidence degree of the defect image being recognized as the corresponding surface defect type.

[0096] The surface defect types recognized by all defect images in the defect image sequence are acquired, a surface defect type with the largest number of defect images is taken as a recognized surface defect type of the defect image sequence, a confidence degree corresponding to the recognized surface defect type is summed and averaged to obtain a recognition confidence degree of the defect image sequence, and the number of defect images corresponding to the recognized surface defect type is acquired and is processed by ratio with the total number of all defect images in the defect image sequence to obtain a recognition defect ratio of the defect image sequence.

[0097] For any defect image sequence, if the recognition confidence degree of the defect image sequence is greater than a preset confidence standard, and the recognition defect ratio is greater than a preset recognition proportion standard, it is judged that the accuracy of recognition is high, and the recognized surface defect type is the actual surface defect type of the defect image sequence, otherwise, a fusion defect review analysis is triggered.

[0098] It should be noted that the role of this step is to design a hierarchical CNN network, extract multi-level features of the defect image, output a defect type probability distribution, realize fast classification of the defect image, reduce the cost of artificial detection, improve the recognition ability of the model to a few class defects through a weighted cross-entropy loss function, avoid the one-sidedness of a single index through a recognition confidence degree and a recognition defect ratio, balance the detection efficiency and accuracy, judge the reliability of the recognition result, and trigger a multi-modal review mechanism.

[0099] The technical scheme of the embodiment of the application is as follows: chip images of a semiconductor chip are acquired and integrated into a chip image sequence, suspected defect regions in the chip image are recognized, a matching group is obtained by matching the suspected defect regions in the chip image sequence, it is judged whether the suspected defect regions are real defect regions according to the matching group, if yes, a defect image sequence is obtained by intercepting the real defect regions, a defect recognition model is constructed and trained, the surface defect types of the defect image sequence are recognized, and the accuracy of recognition is evaluated, if the accuracy is high, an actual surface defect type is obtained, and if the accuracy is low, a fusion defect review analysis is triggered.

[0100] Example 2:

[0101] Please see Figure 1 As shown in the figure, the semiconductor chip surface defect detection method according to an embodiment of the present invention further includes the following steps:

[0102] S4: If the fusion defect verification analysis is triggered, the actual defect location area is located on the semiconductor chip according to the defect image sequence, the fusion features of the actual defect location area are collected and processed, and the actual surface defect type is identified by graph neural network based on the fusion features.

[0103] If the fusion defect verification analysis is triggered, the defect image sequence is obtained. Based on the coordinate information of the defect image in the chip image within the defect image sequence, the actual defect location region of the defect image sequence on the semiconductor chip is calculated.

[0104] For the actual defect location area on the semiconductor chip, a high-resolution line scan photoelectric sensor is used to perform a raster scan on the semiconductor chip surface of the actual defect location area. Each scan acquires one line of pixel information. The scan data is denoised in real time, and median filtering is used to remove salt-and-pepper noise to obtain the photoelectric feature image of the actual defect location area.

[0105] For the actual defect location area on the semiconductor chip, a phased array ultrasonic detection system is used. An ultrasonic coupling agent is applied to the chip surface to ensure effective propagation of sound waves. The phased array transducer scans the actual defect area point by point in C-scan mode, receives and records ultrasonic echo signals at different depth layers, and converts the ultrasonic echo signals into two-dimensional grayscale images through a time-depth conversion algorithm to obtain the ultrasonic feature image of the actual defect location area.

[0106] Feature extraction is performed on the acquired photoelectric feature images and ultrasonic feature images respectively, and a 128-dimensional feature vector is output. and ,Will and Concatenating the features along the channel dimension yields a 256-dimensional fused feature vector. ,Will and The inputs are given to independent fully connected layers with 128 neurons each, and the outputs are then weighted and fused to obtain the final result. The weights for the weighted fusion are determined through validation set optimization. and By splicing them together again, the fusion features are obtained. ;

[0107] Wherein, the history detection accumulated semiconductor chip surface defect fusion feature library is acquired, and corresponding defect type labeling is carried out, to obtain a training data set, and the training data set is divided into a training set and a verification set according to a ratio of 8:2;

[0108] The graph structure of the graph neural network is constructed, and the fusion feature is divided into a plurality of image blocks, each image block is taken as a graph node, the node feature of the graph node is the mean value of the pixel feature in the block, and the weight of the edge is According to the Euclidean distance between the graph nodes, the following is calculated:

[0109] ;

[0110] Wherein, , respectively, the node feature of the graph node a and the node feature of the graph node b, indicates the Euclidean distance;

[0111] The graph convolution network GCN is used for feature learning, and the actual defect position area fusion feature is input, after 3-layer graph convolution, global average pooling is performed on all node features, and the actual defect position is input into the Softmax layer to output the classification probability of each surface defect type;

[0112] The surface defect type with the maximum classification probability is acquired, if the classification probability is greater than a preset confidence standard, the surface defect type is judged as the actual surface defect type of the actual defect position, otherwise, manual review is triggered, and a signal is sent to the detection personnel terminal for manual identification;

[0113] It should be noted that the role of this step is to acquire the multi-modal feature image of the defect area through the photoelectric and ultrasonic sensors, utilize the graph neural network to process the spatial correlation of the cross-modal features, output the final defect classification result, solve the recognition difficulty of complex defects, integrate the surface and subsurface information, identify the deep defects that cannot be found by traditional single optical detection, capture the irregular spatial distribution characteristics of the defects through the graph node correlation of the image blocks, convert the spatial distribution of the chip surface defects into a graph structure, realize the feature learning of the non-Euclidean space through graph convolution, and break through the dependence of traditional CNN on the regular grid.

[0114] The technical scheme of the embodiment of the application is as follows: if the fusion defect review analysis is triggered, the actual defect position area is located on the semiconductor chip according to the defect image sequence, the fusion feature of the actual defect position area is acquired and processed, and the actual surface defect type is recognized based on the fusion feature by using the graph neural network.

[0115] Embodiment 3:

[0116] As Figure 2As shown, the semiconductor chip surface defect detection system comprises the following modules:

[0117] The acquisition and preliminary screening module integrates the chip images of the semiconductor chip into a chip image sequence, and identifies the suspected defect area in the chip image;

[0118] The defect extraction module matches the suspected defect area in the chip image sequence to obtain a matching group, judges whether the suspected defect area is a real defect area according to the matching group, and if so, extracts the real defect area to obtain a defect image sequence;

[0119] The defect recognition module constructs and trains a defect recognition model, recognizes the surface defect type of the defect image sequence, and evaluates the accuracy of the recognition, if the accuracy is high, the actual surface defect type is obtained, if the accuracy is low, the fusion defect review analysis is triggered;

[0120] The fusion review module positions the actual defect position area on the semiconductor chip according to the defect image sequence if the fusion defect review analysis is triggered, acquires and processes the fusion features of the actual defect position area, and identifies the actual surface defect type based on the fusion features using a graph neural network.

[0121] The basic principles, main features and advantages of the present application are shown and described above. It should be understood by those skilled in the art that the present application is not limited by the above embodiments, and the above embodiments and descriptions in the specification are only to illustrate the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the present application. The scope of protection of the present application is defined by the appended claims and their equivalents.

Claims

1. A method of detecting surface defects of a semiconductor chip, characterized by: The application comprises the following steps: Collecting chip images of a semiconductor chip to form a chip image sequence, and identifying suspected defect regions in the chip images; Matching the suspected defect regions in the chip image sequence to obtain a matching group, and determining whether the suspected defect regions are real defect regions according to the matching group, if so, intercepting the real defect regions to obtain a defect image sequence; The determination of whether the suspected defect regions are real defect regions is as follows: Obtaining each matching group, and performing data processing on the number of suspected defect regions in the matching group and the number of all chip images in the chip image sequence to obtain a defect proportion of the matching group, if the defect proportion is greater than or equal to a preset proportion standard, it is determined that all the suspected defect regions in the matching group are real defect regions; The matching group is obtained as follows: Matching the suspected defect regions of each chip image in the chip image sequence, and setting double matching constraint conditions including spatial displacement constraint and area change constraint; For the first chip image in the chip image sequence, setting a suspected defect region as a matching starting point, obtaining any suspected defect region in the next chip image of the matching starting point, if the two suspected defect regions satisfy the double matching constraint conditions, they are divided into the same matching group, the matching starting point is changed to the suspected defect region at the end of the time sequence in the matching group, and the matching is continued; If all the suspected defect regions in the next chip image of the matching starting point do not satisfy the double matching constraint conditions, the matching is continued in the next next chip image, and after traversing the chip image sequence, the suspected defect region in the first chip image that is not included in any matching group is included in a matching group by itself, if there is still a suspected defect region that is not included in a matching group, the chip image of the first suspected defect region is regarded as the first chip image in the chip image sequence, a corresponding matching starting point is set, and re-matching is performed; The judgment of whether the two suspected defect regions satisfy the double matching constraint conditions is as follows: In terms of spatial displacement constraint, the matching of the matching starting point and any suspected defect region in the next chip image in the chip image sequence is performed, the center coordinates of the two suspected defect regions in the corresponding chip images are obtained respectively, the Euclidean distance is calculated, the displacement distance range is calculated and set based on the displacement parameters of the semiconductor chip, and if the Euclidean distance falls within the displacement distance range, it is determined that the two suspected defect regions are spatially matched; In terms of area change constraint, for the two spatially matched suspected defect regions, the area change rate between the two suspected defect regions is calculated, and if the area change rate is less than a change threshold, it is determined that the two suspected defect regions are area-matched, that is, the two suspected defect regions satisfy the double matching constraint conditions; A defect recognition model is constructed and trained, the surface defect type of the defect image sequence is identified, and the accuracy of the identification is evaluated, if the accuracy is high, the actual surface defect type is obtained, if the accuracy is low, fusion defect review analysis is triggered; If the fusion defect review analysis is triggered, the actual defect position region on the semiconductor chip is located according to the defect image sequence, fusion features of the actual defect position region are collected and processed, and the actual surface defect type is identified based on the fusion features by using a graph neural network.

2. The method of claim 1, wherein the method further comprises: The identification of the suspected defect region is as follows: A difference threshold is set according to the pixel fluctuation range of the normal region on the surface of the semiconductor chip, a pixel point image difference value is obtained, if the pixel point image difference value is greater than the difference threshold, a suspected defect mark is added to the pixel point, and the pixel points with suspected defect marks adjacent to each other are integrated into a same suspected defect group, if the number of pixel points in the suspected defect group reaches a standard number, it is determined that the region corresponding to the suspected defect group is a suspected defect region.

3. The method of claim 2, wherein the step of detecting surface defects on the semiconductor chip comprises the steps of: The pixel point image difference value is obtained in the following manner: ​ A displacement parameter is set for the semiconductor chip to control the displacement of the semiconductor chip, a shooting parameter is set for the high-resolution industrial camera, chip images are collected by shooting during the displacement process, the chip images are preprocessed and integrated to obtain a chip image sequence; A qualified chip sample is obtained, the same displacement parameter and shooting parameter are used for shooting and collection to obtain a standard chip image sequence, the chip image sequence and the standard chip image sequence are corresponded and compared one by one, and the pixel point image difference value of each pixel point is calculated through data processing.

4. The method of claim 1, wherein the method further comprises: The accuracy of the evaluation and identification is obtained in the following manner: The surface defect types identified by all defect images in the defect image sequence are obtained, the surface defect type with the largest number of defect images is taken as the identified surface defect type of the defect image sequence, the confidence corresponding to the identified surface defect type is obtained for data processing to obtain the identification confidence, and the number of defect images corresponding to the identified surface defect type is obtained for data processing to obtain the identification defect ratio; If the identification confidence and the identification defect ratio of the defect image sequence both satisfy the accurate judgment condition, the accuracy of the identification is high.

5. The method of claim 4, wherein the step of detecting surface defects on the semiconductor chip comprises the steps of: The surface defect type is identified in the following manner: ​ A convolutional neural network is used as a core model, a hierarchical feature extraction structure is designed according to the characteristics of the semiconductor chip defect image, and a defect identification model is constructed and trained; The defect image sequence is input into the trained defect identification model, a probability vector of the defect image is output, the maximum probability value in the probability vector is taken as the confidence, and the surface defect type corresponding to the confidence is the surface defect type of the defect image.

6. The method of claim 1, wherein: The fusion feature is obtained in the following manner: For the actual defect position region on the semiconductor chip, a high-resolution line scanning photoelectric sensor is used to perform raster scanning on the surface of the semiconductor chip in the actual defect position region to obtain a photoelectric feature image, and a phased array ultrasonic detection system is used to perform point-by-point scanning on the actual defect region to obtain an ultrasonic feature image of the actual defect position region; The photoelectric feature image and the ultrasonic feature image collected are subjected to feature extraction, splicing and weighted fusion processing to obtain the fusion feature.

7. A system for detecting surface defects of a semiconductor chip, the system being configured to implement the method of any one of claims 1 to 6, characterized in that: The following modules are included: The chip image sequence is integrated into a chip image sequence, and the suspected defect region in the chip image is identified; The suspected defect region is matched in the chip image sequence to obtain a matching group, whether the suspected defect region is a real defect region is determined according to the matching group, if yes, the real defect region is intercepted to obtain a defect image sequence; Whether the suspected defect region is a real defect region is determined in the following manner: For each matched group, the number of suspected defect regions in the matched group is processed with the number of all chip images in the chip image sequence to obtain a defect representation ratio of the matched group, and if the defect representation ratio is greater than or equal to a preset ratio standard, the suspected defect regions in the matched group are all judged as real defect regions; The matched group is obtained in the following manner: Suspected defect regions of each chip image in the chip image sequence are matched, and double matching constraint conditions including a spatial displacement constraint and an area change constraint are set; For the first chip image in the chip image sequence, any suspected defect region in the next chip image of the matching starting point is obtained, and if the two suspected defect regions satisfy the double matching constraint conditions, they are divided into the same matched group, the matching starting point is changed to the suspected defect region at the end of the time sequence in the matched group, and the matching is continued; If all suspected defect regions in the next chip image of the matching starting point do not satisfy the double matching constraint conditions, the matching is continued in the next chip image, and after traversing the chip image sequence, the suspected defect region in the first chip image that is not included in any matched group is included in a matched group itself, and if there is still a suspected defect region that is not included in a matched group, the chip image of the first suspected defect region is regarded as the first chip image in the chip image sequence, and the corresponding matching starting point is set for re-matching; The judgment manner that the double matching constraint conditions are satisfied is as follows: In terms of the spatial displacement constraint, the matching of the matching starting point and any suspected defect region in the next chip image in the chip image sequence is obtained, the centroid coordinates of the two suspected defect regions in the corresponding chip image are obtained respectively, and the Euclidean distance is calculated, the displacement distance range is calculated and set based on the displacement parameter of the semiconductor chip, and if the Euclidean distance falls within the displacement distance range, the two suspected defect regions are judged to be spatially matched; In terms of the area change constraint, for the two spatially matched suspected defect regions, the area change rate between the two suspected defect regions is calculated, and if the area change rate is less than a change threshold, the two suspected defect regions are judged to be area-matched, that is, the two suspected defect regions satisfy the double matching constraint conditions; The defect identification module: a defect identification model is constructed and trained, the surface defect type of the defect image sequence is identified, and the accuracy of the identification is evaluated, if the accuracy is high, the actual surface defect type is obtained, if the accuracy is low, the fusion defect review analysis is triggered; The fusion review module: if the fusion defect review analysis is triggered, the actual defect position region on the semiconductor chip is located according to the defect image sequence, the fusion features of the actual defect position region are collected and processed, and based on the fusion features, the actual surface defect type is identified by using a graph neural network.

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