Compensation output circuit, display panel driving circuit, and display device

Abstract

This invention proposes a compensation output circuit, a driving circuit for a display panel, and a display device. The compensation output circuit includes a hysteresis circuit, a signal amplification circuit, and a compensation circuit. The hysteresis circuit delays the first common electrode voltage output by the power management integrated circuit, so that the first common electrode voltage and the second common electrode voltage are output synchronously. Simultaneously, the signal amplification circuit amplifies the delayed first common electrode voltage and outputs a target voltage to the compensation circuit. The compensation circuit generates a compensation voltage based on the target voltage and the feedback second common electrode voltage, and compensates the first common electrode. Through the hysteresis circuit and the signal amplification circuit, the first and second common electrode voltages are output synchronously to the compensation circuit for compensation processing, thereby avoiding voltage spikes and preventing screen flickering during power-on, and improving the display effect.

Description

Technical Field

[0001] This invention belongs to the field of display panel technology, and particularly relates to a compensation output circuit, a driving circuit for a display panel, and a display device. Background Technology

[0002] Display panels typically include an array substrate and a color filter substrate arranged opposite to each other, and a liquid crystal layer disposed between the array substrate and the color filter substrate. Common electrodes are respectively disposed on the color filter substrate and the array substrate. The common electrode on the color filter substrate and the pixel electrode on the array substrate form a liquid crystal capacitor, and the common electrode on the array substrate and the pixel electrode form a storage capacitor.

[0003] When driving a display panel, two corresponding common electrode voltage signals are typically output from two ports of the power management integrated circuit to the common electrode of the color filter substrate and the common electrode of the array substrate. The common electrode on the color filter substrate is prone to coupling with data lines and scan lines, causing disturbances in the common electrode voltage and resulting in screen flicker. Therefore, as... Figure 1 As shown, a compensation circuit is provided in the peripheral driving circuit to compensate the common electrode voltage on the color filter substrate. The compensation circuit obtains the common electrode voltage on the array substrate and the common electrode voltage output by the power management integrated circuit to the color filter substrate, and generates a compensation voltage to the common electrode on the color filter substrate, so that the common electrode voltage on the color filter substrate is stabilized at the target voltage.

[0004] Because the integrated circuits used in each port of the power management integrated circuit are different, such as Figure 2 As shown, the power-on timing of the two common electrode voltage signals may be different. Due to the existence of the compensation circuit, voltage spikes may appear on the common electrode voltage on the color filter substrate, which may lead to screen flickering when the display panel is turned on. Summary of the Invention

[0005] The purpose of this invention is to provide a compensation output circuit that solves the problems of voltage spikes and screen flickering during power-on caused by different timing of common electrode voltages in traditional compensation circuits.

[0006] A first aspect of the present invention provides a compensation output circuit connected to a power management integrated circuit. The first signal terminal of the power management integrated circuit is used to output a first common electrode voltage to the first common electrode of the color filter substrate of the display panel, and the second signal terminal of the power management integrated circuit is used to output a second common electrode voltage to the second common electrode on the array substrate of the display panel. The output time of the first common electrode voltage precedes the output time of the second common electrode voltage.

[0007] The compensation output circuit includes:

[0008] A hysteresis circuit is connected to the first signal terminal of the power management integrated circuit. The hysteresis circuit is used to delay the output of the first common electrode voltage so as to synchronize the output time of the first common electrode voltage with the output time of the second common electrode.

[0009] A signal amplification circuit is connected to the hysteresis circuit. The signal amplification circuit is used to amplify the delayed output first common electrode voltage to amplify the first common electrode voltage to the target voltage.

[0010] The compensation circuit is connected to the second common electrode, the signal amplification circuit, and the first common electrode, respectively. The compensation circuit is used to generate a compensation voltage based on the voltage of the second common electrode and the target voltage to compensate the first common electrode.

[0011] Optionally, the hysteresis circuit includes a Zener diode, a first resistor, and a second resistor;

[0012] The first end of the first resistor forms the input terminal of the hysteresis circuit, the second end of the first resistor is connected to the cathode of the Zener diode, the anode of the Zener diode is connected to the first end of the second resistor to form the output terminal of the hysteresis circuit, and the second end of the second resistor is grounded.

[0013] Optionally, the hysteresis circuit further includes a first capacitor and a second capacitor;

[0014] The first terminal of the first capacitor is connected to the cathode of the Zener diode, the first terminal of the second capacitor is connected to the anode of the Zener diode, and the second terminals of the first capacitor and the second capacitor are grounded.

[0015] Optionally, the signal amplification circuit includes a third resistor, a fourth resistor, and a first operational amplifier;

[0016] The non-inverting input terminal of the first operational amplifier constitutes the input terminal of the signal amplification circuit. The first terminal of the third resistor is grounded. The second terminal of the third resistor, the inverting input terminal of the first operational amplifier, and the first terminal of the fourth resistor are connected. The output terminal of the first operational amplifier and the second terminal of the fourth resistor are connected to constitute the output terminal of the signal amplification circuit.

[0017] Optionally, the signal amplification circuit further includes:

[0018] A bias voltage circuit is connected to the power supply terminal of the first operational amplifier. The bias voltage circuit is used to output a bias voltage to the first operational amplifier, and the bias voltage is equal to the target voltage.

[0019] Optionally, the bias voltage circuit includes a fifth resistor and an adjustable resistor;

[0020] The first end of the fifth resistor is used to input a positive voltage, and the second end of the fifth resistor and the first end of the adjustable resistor are connected to form the output terminal of the bias voltage circuit. The second end of the adjustable resistor is grounded.

[0021] Optionally, the compensation circuit includes a second operational amplifier, a sixth resistor, a seventh resistor, and a third capacitor;

[0022] The non-inverting input terminal of the second operational amplifier is connected to the output terminal of the signal amplification circuit. The first terminal of the third capacitor is connected to the second common electrode. The second terminal of the third capacitor is connected to the first terminal of the sixth resistor. The second terminal of the sixth resistor, the first terminal of the seventh resistor, and the inverting input terminal of the second operational amplifier are connected. The output terminal of the second operational amplifier, the second terminal of the seventh resistor, and the first common electrode are connected.

[0023] Optionally, the compensation output circuit further includes:

[0024] A switching circuit is connected between the first signal terminal of the power management integrated circuit and the compensation circuit. The switching circuit is turned on and off by a switching signal.

[0025] A second aspect of the present invention provides a driving circuit for a display panel, including a power management integrated circuit and a compensation output circuit as described above, wherein the power management integrated circuit is connected to the compensation output circuit.

[0026] A second aspect of the present invention provides a display device, including a display panel and a driving circuit for the display panel as described above, wherein the display panel is connected to the driving circuit for the display panel.

[0027] The beneficial effects of this invention compared to the prior art are as follows: The compensation output circuit includes a hysteresis circuit, a signal amplification circuit, and a compensation circuit. The hysteresis circuit delays the first common electrode voltage output by the power management integrated circuit, so that the first common electrode voltage and the second common electrode voltage are output synchronously. At the same time, the signal amplification circuit amplifies the delayed first common electrode voltage and outputs a target voltage to the compensation circuit. The compensation circuit generates a compensation voltage based on the target voltage and the feedback second common electrode voltage, and compensates the first common electrode. Through the hysteresis circuit and the signal amplification circuit, the first common electrode voltage and the second common electrode voltage are output synchronously to the compensation circuit for compensation processing, thereby avoiding voltage spikes and preventing screen flickering at startup, and improving the display effect. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the driving circuit of a traditional display panel;

[0029] Figure 2 This is a schematic diagram of the waveforms of the first common electrode voltage and the second common electrode voltage in a traditional power management integrated circuit.

[0030] Figure 3 This is a schematic diagram of the compensation output circuit and the driving circuit of the display panel provided in Embodiment 1 of the present invention;

[0031] Figure 4 This is a schematic diagram of the waveforms of each voltage signal in the compensation output circuit provided in Embodiment 1 of the present invention;

[0032] Figure 5 This is a schematic diagram of the first type of hysteresis circuit and signal amplification circuit provided in Embodiment 2 of the present invention;

[0033] Figure 6 This is a circuit diagram of the compensation circuit provided in Embodiment 2 of the present invention;

[0034] Figure 7 This is a second circuit diagram of the hysteresis circuit and signal amplification circuit provided in Embodiment 2 of the present invention;

[0035] Figure 8 This is a schematic diagram of the first waveform of each voltage signal in the compensation output circuit provided in Embodiment 2 of the present invention;

[0036] Figure 9 This is a third circuit diagram of the hysteresis circuit and signal amplification circuit provided in Embodiment 2 of the present invention;

[0037] Figure 10 This is a schematic diagram of the second waveform of each voltage signal in the compensation output circuit provided in Embodiment 2 of the present invention;

[0038] Figure 11 This is a fourth circuit diagram of the hysteresis circuit and signal amplification circuit provided in Embodiment 2 of the present invention;

[0039] Figure 12 This is a circuit diagram of the bias voltage circuit provided in Embodiment 2 of the present invention;

[0040] Figure 13 This is a schematic diagram of the structure of the compensation output circuit and the driving circuit of the display panel provided in Embodiment 2 of the present invention;

[0041] Figure 14 This is a schematic diagram of the driving circuit and display device of the display panel provided in Embodiments 3 and 4 of the present invention.

[0042] The figures in the diagram are labeled as follows:

[0043] 100. Driving circuit for display panel; 200. Display panel; 300. Chip-on film; 110. Compensation output circuit; 120. Power management integrated circuit; 210. First common electrode; 220. Second common electrode; 10. Hysteresis circuit; 20. Signal amplification circuit; 30. Compensation circuit; 40. Switching circuit; 21. Bias voltage circuit;

[0044] R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; Rx, adjustable resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; D1, Zener diode; U1, first operational amplifier; U2, second operational amplifier;

[0045] CFcom, first common electrode voltage; AVcom, second common electrode voltage; V1, output voltage of hysteresis circuit; Vout, target voltage; V0, compensation voltage; VCC, bias voltage; VAA, positive voltage; T0, preset duration. Detailed Implementation

[0046] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0048] Example 1

[0049] A first aspect of the present invention provides a compensation output circuit 110, such as... Figure 3As shown, the compensation output circuit 110 is connected to the power management integrated circuit 120. The first signal terminal of the power management integrated circuit 120 is used to output the first common electrode voltage CFcom to the first common electrode 210 of the color filter substrate of the display panel 200. The second signal terminal of the power management integrated circuit 120 is used to output the second common electrode voltage AVcom to the second common electrode 220 on the array substrate of the display panel 200. The array substrate is also provided with multiple data lines, scan lines and pixel units. The pixel unit includes a corresponding thin film transistor and a pixel electrode. The thin film transistor is connected to a corresponding data line and a scan line respectively. The scan line is used to input the line scan signal line by line. The data line is used to input the data signal. When the thin film transistor receives the line scan signal, it turns on and transmits the data signal to the pixel electrode. The pixel electrode and the first common electrode 210 on the color filter substrate form a liquid crystal capacitor. When the first common electrode voltage CFcom and the data signal are applied to the two ends respectively, the two form a driving voltage and drive the liquid crystal layer to deflect. The pixel electrode and the second common electrode 220 on the array substrate form a storage capacitor for storing the written data signal.

[0050] Because of the different internal integrated circuits of the power management integrated circuit 120, the output time of the first common electrode voltage CFcom is ahead of the output time of the second common electrode voltage AVcom. When the power is turned on, if the compensation signal is generated directly based on the first common electrode voltage CFcom and the second common electrode voltage AVcom, the compensation signal generated at this time is too large since the second common electrode voltage AVcom has not yet been input. When applied to the first common electrode 210, it will generate a voltage spike, resulting in an excessive driving voltage, which in turn causes the display panel 200 to flicker when it is turned on.

[0051] To address this problem, this embodiment proposes a compensation output circuit 110, comprising:

[0052] Hysteresis circuit 10 is connected to the first signal terminal of power management integrated circuit 120. Hysteresis circuit 10 is used to delay the output of the first common electrode voltage CFcom so as to synchronize the output time of the first common electrode voltage CFcom with the output time of the second common electrode 220.

[0053] The signal amplification circuit 20 is connected to the hysteresis circuit 10. The signal amplification circuit 20 is used to amplify the delayed output first common electrode voltage CFcom to amplify the first common electrode voltage CFcom to the target voltage Vout.

[0054] The compensation circuit 30 is connected to the second common electrode 220, the signal amplification circuit 20 and the first common electrode 210 respectively. The compensation circuit 30 is used to generate a compensation voltage V0 to compensate the first common electrode 210 based on the second common electrode voltage AVcom and the target voltage Vout.

[0055] In this embodiment, as Figure 4 As shown, upon power-on, the power management integrated circuit 120 first outputs the first common electrode voltage CFcom to the hysteresis circuit 10 and the first common electrode 210. The hysteresis circuit 10 delays the output of the first common electrode voltage CFcom, that is, it delays the power-on start point of the first common electrode voltage CFcom by a preset time T0, synchronizing the power-on start point of the first common electrode voltage CFcom with the power-on start point of the second common electrode voltage AVcom. At this time, the delayed first common electrode voltage CFcom is output to the signal amplification circuit 20. Since the hysteresis circuit 10 only delays the output of the first common electrode voltage CFcom, its voltage may be reduced. For example, the delayed output first common electrode voltage CFcom may be 650mV. In order to restore the voltage amplitude of the first common electrode voltage CFcom after passing through the hysteresis circuit 10 and make it reach the target voltage Vout, for example, 6.5V, the signal amplification circuit 20 amplifies the signal of the delayed output first common electrode voltage CFcom and restores the first common electrode voltage CFcom to the target voltage Vout.

[0056] Meanwhile, the power management integrated circuit 120 outputs the second common electrode voltage AVcom to the second common electrode 220. The compensation circuit 30 synchronously acquires the feedback second common electrode voltage AVcom and the target voltage Vout. The compensation circuit 30 generates a compensation voltage V0 based on the second common electrode voltage AVcom and the target voltage Vout. The compensation voltage V0 is output to the first common electrode 210 to compensate the first common electrode 210. This allows the first common electrode voltage CFcom to recover to the target voltage Vout when it is disturbed by the coupling of the data signal or the horizontal scanning signal, thus achieving a voltage stabilization effect. At the same time, the compensation voltage V0 generated by the two voltage signals synchronously output to the compensation circuit 30 will not fluctuate significantly, i.e., it will not generate voltage spikes, thus avoiding screen flickering during power-on of the display panel 200 and improving the display effect of the display panel 200.

[0057] The hysteresis circuit 10 can adopt corresponding switch, capacitor and other circuit structures, the signal amplification circuit 20 can adopt operational amplifier and other circuit structures, and the compensation circuit 30 can adopt operational amplifier, comparator and other circuit structures. The specific structure is not limited.

[0058] The beneficial effects of the present invention compared with the prior art are as follows: The compensation output circuit 110 includes a hysteresis circuit 10, a signal amplification circuit 20, and a compensation circuit 30. The hysteresis circuit 10 delays the first common electrode voltage CFcom output by the power management integrated circuit 120, so that the first common electrode voltage CFcom and the second common electrode voltage AVcom are output synchronously. At the same time, the signal amplification circuit 20 amplifies the delayed output first common electrode voltage CFcom and outputs the target voltage Vout to the compensation circuit 30. The compensation circuit 30 generates a compensation voltage V0 based on the target voltage Vout and the feedback obtained second common electrode voltage AVcom, and compensates the first common electrode 210. Through the hysteresis circuit 10 and the signal amplification circuit 20, the first common electrode voltage CFcom and the second common electrode voltage AVcom are output synchronously to the compensation circuit 30 for compensation processing, thereby avoiding voltage spikes and avoiding screen flickering at startup, and improving the display effect.

[0059] Example 2

[0060] In an alternative embodiment, such as Figure 5 As shown, the hysteresis circuit 10 includes a Zener diode D1, a first resistor R1, and a second resistor R2.

[0061] The first end of the first resistor R1 forms the input terminal of the hysteresis circuit 10, the second end of the first resistor R1 is connected to the cathode of the Zener diode D1, the anode of the Zener diode D1 is connected to the first end of the second resistor R2 to form the output terminal of the hysteresis circuit 10, and the second end of the second resistor R2 is grounded.

[0062] The signal amplification circuit 20 includes a third resistor R3, a fourth resistor R4, and a first operational amplifier U1;

[0063] The non-inverting input terminal of the first operational amplifier U1 forms the input terminal of the signal amplification circuit 20. The first terminal of the third resistor R3 is grounded. The second terminal of the third resistor R3, the inverting input terminal of the first operational amplifier U1, and the first terminal of the fourth resistor R4 are connected. The output terminal of the first operational amplifier U1 and the second terminal of the fourth resistor R4 are connected to form the output terminal of the signal amplification circuit 20.

[0064] like Figure 6 As shown, the compensation circuit 30 includes a second operational amplifier U2, a sixth resistor R6, a seventh resistor R7, and a third capacitor C3;

[0065] The non-inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the signal amplification circuit 20. The first terminal of the third capacitor C3 is connected to the second common electrode 220. The second terminal of the third capacitor C3 is connected to the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6, the first terminal of the seventh resistor R7, and the inverting input terminal of the second operational amplifier U2 are connected. The output terminal of the second operational amplifier U2, the second terminal of the seventh resistor R7, and the first common electrode 210 are connected.

[0066] In this embodiment, the reverse breakdown voltage regulation characteristic of Zener diode D1 is used to achieve signal delay, and the power-on start points of the first common electrode voltage CFcom and the second common electrode voltage AVcom are synchronized. When the first common electrode voltage CFcom is output first and starts to rise, when its voltage is less than the reverse breakdown voltage of Zener diode D1, Zener diode D1 is turned off and the anode voltage of Zener diode D1 is zero. After a preset time T0, the first common electrode voltage CFcom rises to the reverse breakdown voltage of Zener diode D1, and Zener diode D1 is turned on. At this time, the first common electrode voltage CFcom is divided by the first resistor R1, Zener diode D1 and the second resistor R2. The output voltage V1 of the hysteresis circuit 10 is less than the target voltage Vout of the first common electrode voltage CFcom.

[0067] The output voltage V1 of the hysteresis circuit 10 is output to the signal amplification circuit 20. The signal amplification circuit 20 consists of a first operational amplifier U1, a third resistor R3, and a fourth resistor R4. The first operational amplifier U1, the third resistor R3, and the fourth resistor R4 form a non-inverting amplifier circuit. The output voltage V1 of the hysteresis circuit 10 is output to the non-inverting input terminal of the operational amplifier. The amplification ratio of the signal amplification circuit 20 is 1 + (R4 / R3). By selecting the corresponding values ​​of the third resistor R3 and the fourth resistor R4, the output voltage V1 of the hysteresis circuit 10 can be amplified to the target voltage Vout of the first common electrode voltage CFcom, for example, 6.5V.

[0068] Meanwhile, the amplified target voltage Vout is output to the non-inverting input of the second operational amplifier U2 in the compensation circuit 30, and the second common electrode voltage AVcom on the second common electrode 220 is output to the third capacitor C3 in the compensation circuit 30. The third capacitor C3 blocks DC to prevent DC components from entering. The second common electrode voltage AVcom is coupled to the sixth resistor R6 through the third capacitor C3, and output to the inverting input of the second operational amplifier U2 through the sixth resistor R6. The compensation voltage V0 of the second operational amplifier U2 is Vout = (Vout - AVcom) * R7 / R6. When the first common electrode voltage CFcom is disturbed by data signal or line scanning signal coupling, due to the... The second common electrode 220 is positioned opposite to the first common electrode 210. The second common electrode voltage AVcom on the second common electrode 220 changes synchronously with the disturbance. For example, when the first common electrode voltage CFcom increases, the second common electrode voltage AVcom increases, the target voltage Vout remains unchanged, the compensation voltage V0 decreases, and the first common electrode voltage CFcom decreases. Similarly, when the first common electrode voltage CFcom decreases, the second common electrode voltage AVcom decreases, the target voltage Vout remains unchanged, the compensation voltage V0 increases, and the first common electrode voltage CFcom increases, thereby stabilizing the first common electrode voltage CFcom at the target voltage Vout and achieving negative feedback regulation.

[0069] By setting the Zener diode D1 and the first operational amplifier U1, the first common electrode voltage CFcom and the second common electrode voltage AVcom are synchronously output to the compensation circuit 30 for compensation processing, thereby avoiding voltage spikes and screen flickering during power-on, and improving the display effect.

[0070] In this case, the hysteresis effect of the Zener diode D1 is limited. For example, assuming the first common electrode voltage CFcom is 6.5V and the power-on time is 10ms, and the second common electrode voltage AVcom is 5.8V and the power-on time is 12ms, the power-on start point of the second common electrode voltage AVcom is delayed by 10ms compared to the first common electrode voltage CFcom. When using the Zener diode D1, the preset delay time T0 may only reach 5ms, which does not reach the expected 10ms.

[0071] Meanwhile, in addition to the different power-on start points causing voltage spikes, the first common electrode voltage CFcom and the second common electrode voltage AVcom may also have excessive voltage differences during the voltage rise process due to different voltage rise slopes, resulting in voltage spikes and screen flickering.

[0072] To improve the delay effect and avoid voltage spikes due to voltage rise slope issues, in an optional embodiment, such as Figure 7 and Figure 9As shown, the hysteresis circuit 10 also includes a first capacitor C1 and a second capacitor C2.

[0073] The first terminal of the first capacitor C1 is connected to the cathode of the Zener diode D1, the first terminal of the second capacitor C2 is connected to the anode of the Zener diode D1, and the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 are grounded.

[0074] In this embodiment, the first capacitor C1 and the first resistor R1 constitute an RC low-pass filter. The input first common electrode voltage CFcom is first charged through the first capacitor C1, such as... Figure 8 As shown, when the terminal voltage of the first capacitor C1 is charged to the reverse breakdown voltage of the Zener diode D1, the Zener diode D1 conducts. The first common electrode voltage CFcom is output to the signal amplification circuit 20 after being divided by the first resistor R1 and the second resistor R2. By setting an RC low-pass filter, part of the charging time is added as a delay time. By changing the size of the first capacitor C1, the time point at which the first common electrode voltage CFcom reaches the breakdown voltage can be changed, thereby realizing the regulation of the voltage start point.

[0075] After using an RC low-pass filter, the output voltage V1 of the hysteresis circuit 10 rises rapidly. Correspondingly, the target voltage Vout output by the signal amplification circuit 20 rises rapidly, which may cause an excessive voltage difference with the feedback-obtained second common electrode voltage AVcom, resulting in an excessive compensation voltage V0 and thus causing screen flickering.

[0076] Therefore, a second capacitor C2 is also provided across the second resistor R2. The second capacitor C2 and the second resistor R2 form a low-pass filter. The value of the second capacitor C2 can adjust the rate of change of the output voltage of the Zener diode D1. Figure 10 As shown, the output voltage V1 of the hysteresis circuit 10 is charged through the second capacitor C2, and the rate of change of the output voltage V1 is reduced so that its rate of change is close to the second common electrode voltage AVcom. This makes the voltage difference between the target voltage Vout after signal amplification and the feedback second common electrode voltage AVcom within a preset difference value, thereby avoiding the generation of a large compensation voltage V0 and preventing screen flicker, thus improving the display effect.

[0077] In this case, the output voltage V1 of the hysteresis circuit 10 may be too low. To achieve the target voltage Vout, the amplification ratio of the signal amplification circuit 20 can be set to a larger value. However, the maximum amplification value of the first operational amplifier U1 is equal to the magnitude of its bias voltage VCC. To ensure the output target voltage Vout, in an optional embodiment, such as... Figure 11 As shown, the signal amplification circuit 20 also includes:

[0078] The bias voltage circuit 21 is connected to the power supply terminal of the first operational amplifier U1. The bias voltage circuit 21 is used to output the bias voltage VCC to the first operational amplifier U1. The bias voltage VCC is equal to the target voltage Vout.

[0079] In this embodiment, the bias voltage VCC of the first operational amplifier U1 is adjusted to the target voltage Vout, and the amplification ratio of the signal amplification circuit 20 is set to reach a preset upper limit value. At this time, when the output voltage V1 of the hysteresis circuit 10 is large or small, the signal amplification circuit 20 can output the target voltage Vout after amplification.

[0080] The bias voltage circuit 21 can be selected from a corresponding voltage source, power conversion circuit, etc. In an optional embodiment, to simplify the circuit structure, such as... Figure 12 As shown, the bias voltage circuit 21 includes a fifth resistor R5 and an adjustable resistor Rx;

[0081] The first end of the fifth resistor R5 is used to input the positive voltage VAA. The second end of the fifth resistor R5 and the first end of the adjustable resistor Rx are connected to form the output end of the bias voltage circuit 21. The second end of the adjustable resistor Rx is grounded.

[0082] In this embodiment, the fifth resistor R5 and the adjustable resistor Rx constitute a voltage divider circuit. The size of the adjustable resistor Rx can be adjusted according to the size of the target voltage Vout, thereby dividing the voltage and outputting the target voltage Vout.

[0083] The adjustable resistor Rx can be composed of multiple resistor branches connected in parallel. Each resistor branch is turned on or off by a corresponding control signal, thereby generating an adjustable resistor Rx with a corresponding resistance value in parallel. Alternatively, a sliding rheostat can be used. The specific structure is not limited.

[0084] Furthermore, to enhance the versatility of the compensation output circuit 110, it is possible to select whether to perform a hysteresis output on the first common electrode voltage CFcom according to requirements. In one optional embodiment, such as... Figure 13 As shown, the compensation output circuit 110 also includes:

[0085] The switching circuit 40 is connected between the first signal terminal of the power management integrated circuit 120 and the compensation circuit 30. The switching circuit 40 is turned on and off by the switching signal.

[0086] In this embodiment, when there is a large time delay between the first common electrode voltage CFcom and the second common electrode voltage AVcom, and it is necessary to hysteresis output the first common electrode voltage CFcom, the off signal in the output switch signal is selected to control the switch circuit 40 to turn off. The first common electrode voltage CFcom is hysteresis output by the hysteresis circuit 10 and amplified by the signal amplification circuit 20 before being output to the compensation circuit 30 for signal compensation.

[0087] When the first common electrode voltage CFcom and the second common electrode voltage AVcom are synchronously powered on and output, and there is no need to hysteresis output of the first common electrode voltage CFcom, the conduction signal in the selected output switch signal controls the switch circuit 40 to conduct, and short-circuits the hysteresis circuit 10 and the signal amplification circuit 20. The compensation circuit 30 directly compares the first common electrode voltage CFcom and the feedback obtained second common electrode voltage AVcom, and generates a compensation voltage V0 to the first common electrode 210. The hysteresis circuit 10 and the signal amplification circuit 20 are reserved circuits, which can be selectively connected to the compensation circuit 30 and the power management integrated circuit 120 when needed.

[0088] By setting the switching circuit 40, it is possible to select whether to perform delayed output control and signal amplification on the first common trigger voltage CFcom, so as to meet different application scenarios.

[0089] The switching circuit 40 can be selected from switching devices with controlled on / off states, such as transistors or triodes, and the specific structure is not limited.

[0090] The switching circuit 40 can be connected to the corresponding port of the power management integrated circuit 120, or to other controllers, such as a timing controller. The timing controller outputs a corresponding switching signal to the switching circuit 40 according to the trigger signal, thereby controlling the switching circuit 40 to turn on and off accordingly.

[0091] Example 3

[0092] The present invention also proposes a driving circuit 100 for a display panel, such as... Figure 14 As shown, the driving circuit 100 of the display panel includes a power management integrated circuit 120 and a compensation output circuit 110. The specific structure of the compensation output circuit 110 is as described in the above embodiments. Since the driving circuit 100 of this display panel adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The power management integrated circuit 120 is connected to the compensation output circuit 110.

[0093] In this embodiment, the power management integrated circuit 120 is also connected to the first common electrode 210 and the second common electrode 220, and outputs the first common electrode voltage CFcom and the second common electrode 220 to the first common electrode 210 and the second common electrode 220 respectively. At the same time, the power management integrated circuit 120 also outputs the target voltage Vout to the compensation output circuit 110. The compensation output circuit 110 generates a compensation voltage V0 based on the target voltage Vout and the feedback obtained second common electrode voltage AVcom, and outputs it to the first common electrode 210 to realize the compensation of the first common electrode voltage CFcom, prevent signal disturbance from causing display abnormalities, and improve the display effect.

[0094] The driving circuit 100 of the display panel may also include a corresponding timing controller, a gate driving circuit and a source driving circuit. The gate driving circuit is used to output a row scanning signal and the source driving circuit is used to output a data signal.

[0095] The timing controller, power management integrated circuit 120, and compensation output circuit 110 can be mounted on the corresponding flexible circuit board. The flexible circuit board is connected to the display panel 200 through the flip-chip film 300. The flip-chip film 300 is provided with multiple transmission channels and source drive chips. The transmission channels can be used to transmit the common electrode voltage, control signals output by the timing controller to the gate drive circuit, and data signals.

[0096] Example 4

[0097] The present invention also proposes a display device, such as Figure 14 As shown, the display device includes a display panel and a driving circuit for the display panel. The specific structure of the driving circuit for the display panel is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The display panel is connected to the driving circuit for the display panel.

[0098] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A compensation output circuit, connected to a power management integrated circuit, characterized in that, The first signal terminal of the power management integrated circuit is used to output a first common electrode voltage to the first common electrode of the color filter substrate of the display panel, and the second signal terminal of the power management integrated circuit is used to output a second common electrode voltage to the second common electrode on the array substrate of the display panel. The output time of the first common electrode voltage precedes the output time of the second common electrode voltage. The compensation output circuit includes: A hysteresis circuit is connected to the first signal terminal of the power management integrated circuit. The hysteresis circuit is used to delay the output of the first common electrode voltage so as to synchronize the output time of the first common electrode voltage with the output time of the second common electrode. A signal amplification circuit is connected to the hysteresis circuit. The signal amplification circuit is used to amplify the delayed output first common electrode voltage to amplify the first common electrode voltage to the target voltage. The compensation circuit is connected to the second common electrode, the signal amplification circuit, and the first common electrode, respectively. The compensation circuit is used to generate a compensation voltage based on the voltage of the second common electrode and the target voltage to compensate the first common electrode. The hysteresis circuit includes a Zener diode, a first resistor, and a second resistor; The first end of the first resistor constitutes the input terminal of the hysteresis circuit, the second end of the first resistor is connected to the cathode of the Zener diode, the anode of the Zener diode is connected to the first end of the second resistor to constitute the output terminal of the hysteresis circuit, and the second end of the second resistor is grounded. The compensation output circuit also includes: A switching circuit is connected between the first signal terminal of the power management integrated circuit and the compensation circuit. The switching circuit is turned on and off by a switching signal.

2. The compensation output circuit as described in claim 1, characterized in that, The hysteresis circuit also includes a first capacitor and a second capacitor. The first terminal of the first capacitor is connected to the cathode of the Zener diode, the first terminal of the second capacitor is connected to the anode of the Zener diode, and the second terminals of the first capacitor and the second capacitor are grounded.

3. The compensation output circuit as described in claim 1, characterized in that, The signal amplification circuit includes a third resistor, a fourth resistor, and a first operational amplifier; The non-inverting input terminal of the first operational amplifier constitutes the input terminal of the signal amplification circuit. The first terminal of the third resistor is grounded. The second terminal of the third resistor, the inverting input terminal of the first operational amplifier, and the first terminal of the fourth resistor are connected. The output terminal of the first operational amplifier and the second terminal of the fourth resistor are connected to constitute the output terminal of the signal amplification circuit.

4. The compensation output circuit as described in claim 3, characterized in that, The signal amplification circuit also includes: A bias voltage circuit is connected to the power supply terminal of the first operational amplifier. The bias voltage circuit is used to output a bias voltage to the first operational amplifier, and the bias voltage is equal to the target voltage.

5. The compensation output circuit as described in claim 4, characterized in that, The bias voltage circuit includes a fifth resistor and an adjustable resistor; The first end of the fifth resistor is used to input a positive voltage, and the second end of the fifth resistor and the first end of the adjustable resistor are connected to form the output terminal of the bias voltage circuit. The second end of the adjustable resistor is grounded.

6. The compensation output circuit as described in claim 1, characterized in that, The compensation circuit includes a second operational amplifier, a sixth resistor, a seventh resistor, and a third capacitor; The non-inverting input terminal of the second operational amplifier is connected to the output terminal of the signal amplification circuit. The first terminal of the third capacitor is connected to the second common electrode. The second terminal of the third capacitor is connected to the first terminal of the sixth resistor. The second terminal of the sixth resistor, the first terminal of the seventh resistor, and the inverting input terminal of the second operational amplifier are connected. The output terminal of the second operational amplifier, the second terminal of the seventh resistor, and the first common electrode are connected.

7. A driving circuit for a display panel, characterized in that, It includes a power management integrated circuit and a compensation output circuit as described in any one of claims 1 to 6, wherein the power management integrated circuit is connected to the compensation output circuit.

8. A display device, characterized in that, It includes a display panel and a driving circuit for the display panel as described in claim 7, wherein the display panel is connected to the driving circuit for the display panel.

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