Signal identification circuit and system on chip

Abstract

The invention discloses a signal identification circuit and a system on chip, and relates to the technical field of signal identification. The circuit comprises N band-pass filtering units, N second logic gate units, N-1 first logic gate units and an identification unit, N is a positive integer larger than 2, and the N band-pass filtering units are connected with the N second logic gate units in a one-to-one correspondence mode. The ith first logic gate unit is connected with the ith band-pass filtering unit, the (i + 1) th band-pass filtering unit, the ith second logic gate unit and the (i + 1) th second logic gate unit, i is a positive integer larger than 0 and smaller than N, and the recognition unit is connected with the N second logic gate units. A to-be-recognized signal is input into the band-pass filtering unit, the first logic gate unit performs logical operation on a filtering result, the second logic gate unit performs logical operation on the output of the first logic gate unit and the filtering result, and the recognition unit obtains an identity recognition result of the to-be-recognized signal according to the output of the second logic gate unit. Therefore, resource waste can be avoided.

Description

Technical Field

[0001] The present invention relates to the field of signal recognition technology, and in particular to a signal recognition circuit and a system on chip. Background Art

[0002] In small-package on-chip systems, due to the limited number of pins, multiple unrelated or even mutually exclusive input signals often share the same input pin as the input source. Therefore, the identity information of the input signals needs to be identified.

[0003] In the related art, the system on chip inputs the signal to be identified into a plurality of bandpass filters with different effective frequency ranges, and determines the identity information of the signal to be identified based on the bandpass filters through which the signal to be identified passes.

[0004] However, in order to ensure recognition accuracy, the related art method for determining the identity information of the signal to be identified requires that the effective frequency ranges of different bandpass filters cannot overlap, resulting in fewer available windows within a certain frequency range and causing waste of resources. Summary of the Invention

[0005] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, a first object of the present invention is to provide a signal recognition circuit to avoid resource waste.

[0006] A second object of the present invention is to provide a system on chip.

[0007] To achieve the above objectives, an embodiment of the first aspect of the present invention provides a signal recognition circuit, comprising an identification unit, N bandpass filtering units, N-1 first logic gate units, and N second logic gate units, where N is a positive integer greater than or equal to 3, the N bandpass filtering units are connected to the N second logic gate units in a one-to-one correspondence, the i-th first logic gate unit is connected to the i-th bandpass filtering unit, the i+1-th bandpass filtering unit, the i-th second logic gate unit, and the i+1-th second logic gate unit, where i is a positive integer greater than 0 and less than N, and the identification unit is connected to the N second logic gate units; wherein the bandpass filtering unit is used to perform bandpass filtering on a received signal to be identified, and send the filtering result to the first logic gate unit and the second logic gate unit, the first logic gate unit is used to perform a first logic operation on the received signal, and the second logic gate unit is used to perform a second logic operation on the output signal of the first logic gate unit and the filtering result, and the identification unit is used to obtain an identity recognition result of the signal to be identified based on the output signals of the N second logic gate units.

[0008] In addition, the signal recognition circuit according to the embodiment of the present invention may also have the following additional technical features: According to one embodiment of the present invention, when the signal to be identified is a positive pulse width signal, the first logical operation is an exclusive OR operation, and the second logical operation is an AND operation; when the signal to be identified is a negative pulse width signal, the first logical operation is an exclusive OR operation, and the second logical operation is an OR operation.

[0009] According to one embodiment of the present invention, the upper limit of the effective frequency range of the i-1th band-pass filtering unit is the minimum frequency value of the center frequency window of the i-th band-pass filtering unit, and the lower limit of the effective frequency range of the i+1th band-pass filtering unit is the maximum frequency value of the center frequency window of the i-th band-pass filtering unit, wherein the center frequency window of the i-th band-pass filtering unit is a preset frequency window within the effective frequency range of the i-th band-pass filtering unit, and the effective frequency range of the i-th band-pass filtering unit is the frequency range in which the output signal strength of the i-th band-pass filtering unit is greater than a preset threshold.

[0010] According to one embodiment of the present invention, the identification unit is specifically used to: when a preset signal exists among the output signals of the N second logic gate units, obtain an identity identification result of the signal to be identified based on the target second logic gate unit that outputs the preset signal; when no preset signal exists among the output signals of the N second logic gate units, identify the signal to be identified as an invalid signal.

[0011] According to one embodiment of the present invention, the identification unit is further used to: when a preset signal exists in the output signals of N second logic gate units, determine the target bandpass filtering unit according to the target second logic gate unit, and query the preset bandpass filtering unit-signal identity correspondence table according to the target bandpass filtering unit to obtain the identity recognition result of the signal to be identified, wherein the target bandpass filtering unit is a bandpass filtering unit connected to the target second logic gate unit.

[0012] According to one embodiment of the present invention, the lower limit of the effective frequency range of the i-1th band-pass filtering unit is the maximum frequency value of the center frequency window of the i-th band-pass filtering unit, and the upper limit of the effective frequency range of the i+1th band-pass filtering unit is the minimum frequency value of the center frequency window of the i-th band-pass filtering unit, wherein the center frequency window of the i-th band-pass filtering unit is a preset frequency window within the effective frequency range of the i-th band-pass filtering unit, and the effective frequency range of the i-th band-pass filtering unit is the frequency range in which the output signal strength of the i-th band-pass filtering unit is greater than a preset threshold.

[0013] According to one embodiment of the present invention, the circuit further includes: N Schmitt units, the N Schmitt units are connected one-to-one with the N bandpass filtering units, and are connected one-to-one with the N second logic gate units, the first Schmitt unit is connected to the first first logic gate unit, the Nth Schmitt unit is connected to the N-1th first logic gate unit, the jth Schmitt unit is connected to the j-1th first logic gate unit and the jth first logic gate unit, where j is a positive integer greater than 1 and less than N; the Schmitt unit is used to perform a shaping operation on the output signal of the bandpass filtering unit, and send the shaping result to the first logic gate unit and the second logic gate unit.

[0014] According to one embodiment of the present invention, the circuit further includes: N registers, the N registers are connected to the N second logic gate units in a one-to-one correspondence, and the N registers are all connected to the identification unit, and the register is used to receive the output signal of the second logic gate unit when a trigger signal is received at the trigger end of the register, and output the output signal of the second logic gate unit to the identification unit.

[0015] According to one embodiment of the present invention, when the signal to be identified is a positive pulse width signal, the trigger end is the negative edge clock trigger end of the register, and the trigger signal is the falling edge of the signal to be identified; when the signal to be identified is a negative pulse width signal, the trigger end is the positive edge clock trigger end of the register, and the trigger signal is the rising edge of the signal to be identified. The circuit further includes: a buffer, which connects the trigger ends of N registers and the input pins of the signal identification circuit. The buffer is used to delay the signal to be identified and send it to the trigger end of the register when receiving the signal to be identified, so that the trigger signal in the signal to be identified triggers the register to receive the output signal of the second logic gate unit and outputs the output signal to the identification unit.

[0016] To achieve the above-mentioned object, a second embodiment of the present invention provides a system on chip, including the above-mentioned signal recognition circuit.

[0017] According to an embodiment of the present invention, a signal recognition circuit and a system on chip include N bandpass filtering units, N-1 first logic gate units, N second logic gate units and an identification unit, where N is a positive integer greater than or equal to 3, the N bandpass filtering units are connected to the N second logic gate units in a one-to-one correspondence, the i-th first logic gate unit is connected to the i-th bandpass filtering unit, the i+1-th bandpass filtering unit, the i-th second logic gate unit and the i+1-th second logic gate unit, i is a positive integer greater than 0 and less than N, and the identification unit is connected to the N second logic gate units; wherein the bandpass filtering unit is used to perform bandpass filtering on a received signal to be identified and send the filtering result to the second logic gate unit and the first logic gate unit, the first logic gate unit is used to perform a first logic operation on the received signal, the second logic gate unit is used to perform a second logic operation on the output signal of the first logic gate unit and the filtering result, and the identification unit is used to obtain an identity recognition result of the signal to be identified based on the output signals of the N second logic gate units. Thus, by providing the above-mentioned first logic gate unit and arranging the above-mentioned i-th first logic gate unit to connect to the i-th bandpass filter unit and the i+1-th bandpass filter unit, it is possible to distinguish between two situations: the signal to be identified is within the effective frequency range of one bandpass filter and the signal to be identified is within the effective frequency range of two bandpass filters, thereby supporting partial overlap of the effective frequency ranges of different bandpass filters, improving frequency band utilization, and avoiding waste of resources. Furthermore, by providing the above-mentioned second logic gate unit and arranging the i-th first logic gate unit to connect to the i-th second logic gate unit and the i+1-th second logic gate unit, since the second logic gate unit is connected to the bandpass filter unit in a one-to-one correspondence, the output signal of the first logic gate unit is converted into an output signal that corresponds to a one-to-one bandpass filter unit, so that the recognition unit can simply and directly determine which bandpass filter unit the signal to be identified has passed through based on the output of the second logic gate unit, thereby obtaining an identity recognition result of the signal to be identified.

[0018] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a structural diagram of a signal recognition circuit according to an embodiment of the present invention; Figure 2 is a circuit diagram of a signal recognition circuit according to an embodiment of the present invention; Figure 3 is a schematic diagram of the operation of a signal recognition circuit according to an embodiment of the present invention; Figure 4 FIG. 4 is a structural block diagram of a system on a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following describes a signal recognition circuit and a system-on-chip according to an embodiment of the present invention with reference to the accompanying drawings. The same or similar reference numerals throughout the description represent the same or similar components or components having the same or similar functions. The embodiments described with reference to the accompanying drawings are exemplary only and are not to be construed as limiting the present invention.

[0021] Figure 1 2 is a schematic structural diagram of a signal recognition circuit according to an embodiment of the present invention.

[0022] like Figure 1 As shown, the signal recognition circuit 100 includes: N band-pass filter units 101, N second logic gate units 102, N-1 first logic gate units 103 and an identification unit 108, N is a positive integer greater than or equal to 3, the N band-pass filter units 101 are connected to the N second logic gate units 102 in a one-to-one correspondence, the i-th first logic gate unit 103 is connected to the i-th band-pass filter unit 101, the i+1-th band-pass filter unit 101, the second output end of the i-th second logic gate unit 102 and the i+1-th second logic gate unit 102, i is a positive integer greater than 0 and less than N. The identification unit 108 is connected to N second logic gate units 102; wherein the bandpass filtering unit 101 is used to perform bandpass filtering on the received signal to be identified, and send the filtering result to the second logic gate unit 102 and the first logic gate unit 103, the first logic gate unit 103 is used to perform a first logic operation on the received signal, the second logic gate unit 102 is used to perform a second logic operation on the output signal of the first logic gate unit 103 and the filtering result, and the identification unit 108 is used to obtain an identity recognition result of the signal to be identified according to the output signals of the N second logic gate units 102.

[0023] It should be noted that Figure 1 The signal recognition circuit 100 further includes an input pin 104, and the signal to be recognized is input into the N band-pass filter units 101 through the input pin 104. In practical applications, it is not limited to the input pin 104, and it is only necessary to enable the signal to be recognized to be input into the N band-pass filter units 101 at the same time.

[0024] Specifically, in order to identify the identity of the signal to be identified, N band-pass filter units 101 are set in the signal identification circuit 100. Different band-pass filter units 101 have different effective frequency ranges. Therefore, when the same signal to be identified is input into the N band-pass filter units 101, different band-pass filter units 101 will have different filtering capabilities for the signal to be identified due to their different effective frequency ranges.

[0025] The above-mentioned effective frequency range refers to the frequency range in which the output signal strength of the band-pass filtering unit 101 is greater than a preset threshold value, and the above-mentioned preset threshold value refers to the signal strength threshold value at which the signal can be recognized by the subsequent circuit of the band-pass filtering unit 101. In other words, for the i-th band-pass filtering unit 101, if the frequency of the signal to be recognized is within the effective frequency range of the i-th band-pass filtering unit 101, then the signal to be recognized can be recognized by the subsequent circuit after passing through the i-th band-pass filtering unit 101; if the frequency of the signal to be recognized is not within the effective frequency range of the i-th band-pass filtering unit 101, then the signal to be recognized cannot effectively pass through the i-th band-pass filtering unit 101, that is, after the signal to be recognized passes through the i-th band-pass filtering unit 101, the signal strength will be attenuated to the point where it cannot be recognized by the subsequent circuit.

[0026] However, if only the bandpass filtering unit 101 is used, in order to ensure accurate recognition, the effective frequency ranges of the two bandpass filters need to be set to not overlap, resulting in low frequency band resource utilization.

[0027] Therefore, in order to avoid waste of resources, the above-mentioned signal recognition circuit 100 is designed to also include N second logic gate units 102 and N-1 first logic gate units 103, and the N band-pass filter units 101 are connected to the N second logic gate units 102 in a one-to-one correspondence, and the i-th first logic gate unit 103 is connected to the i-th band-pass filter unit 101, the i+1-th band-pass filter unit 101, the i-th second logic gate unit 102 and the i+1-th second logic gate unit 102.

[0028] The above N=3 is used as an example for explanation.

[0029] At this time, the first first logic gate unit 103 is connected to the first band-pass filtering unit 101, the second band-pass filtering unit 101, the first second logic gate unit 102 and the second second logic gate unit 102, the second first logic gate unit 103 is connected to the second band-pass filtering unit 101, the third band-pass filtering unit 101, the second second logic gate unit 102 and the third second logic gate unit 102. Since the N band-pass filtering units 101 are connected to the N second logic gate units 102 in a one-to-one correspondence, the first band-pass filtering unit 101 is connected to the first second logic gate unit 102, the second band-pass filtering unit 101 is connected to the second second logic gate unit 102, and the third band-pass filtering unit 101 is connected to the third second logic gate unit 102.

[0030] When a signal to be identified is input, the signal to be identified is simultaneously input to the first band-pass filtering unit 101 , the second band-pass filtering unit 101 , and the third band-pass filtering unit 101 .

[0031] At this time, when the frequency of the signal to be identified is only within the effective frequency range of the second band-pass filtering unit 101, the signal to be identified passes through the second band-pass filtering unit 101, but does not pass through the first band-pass filtering unit 101 and the third band-pass filtering unit 101, so that the input signal states of the first first logic gate unit 103 and the second first logic gate unit 103 are consistent, and thus the output signal states of the first first logic gate unit 103 and the second first logic gate unit 103 are consistent.

[0032] When the frequency of the signal to be identified is within the effective frequency range of the first band-pass filtering unit 101 and the second band-pass filtering unit 101, the signal to be identified will pass through the first band-pass filtering unit 101 and the second band-pass filtering unit 101, but will not pass through the third band-pass filtering unit 101, causing the output signal states of the first first logic gate unit 103 and the second first logic gate unit 103 to be inconsistent, thereby causing the output signal states of the first first logic gate unit 103 and the second first logic gate unit 103 to be consistent.

[0033] When the frequency of the signal to be identified is not within the range of the first band-pass filtering unit 101, the second band-pass filtering unit 101 and the third band-pass filtering unit 101, since no signal passes through the band-pass filtering unit 101, the output signal state of the first logic gate unit 103 is the state when no signal passes.

[0034] That is to say, by setting the above-mentioned first logic gate unit 103 and setting the above-mentioned i-th first logic gate unit 103 to connect the i-th band-pass filtering unit 101 and the i+1-th band-pass filtering unit 101, it is possible to distinguish between the two situations: the signal to be identified is within the effective frequency range of one band-pass filter and the signal to be identified is within the effective frequency range of two band-pass filters, thereby achieving partial overlap of the effective frequency ranges supporting different band-pass filtering units 101, thereby improving frequency band utilization and avoiding waste of resources.

[0035] However, since the first logic gate unit 103 does not correspond to the bandpass filter unit 101, if only the first logic gate unit 103 is used, even if it is known whether there is a signal passing through the bandpass filter unit 101 and how many bandpass filter units 101 the signal has passed through, it is difficult to determine which bandpass filter units 101 the signal to be identified has passed through, making it difficult to determine the identity of the signal to be identified.

[0036] Therefore, the above-mentioned second logic gate unit 102 is provided, and the i-th first logic gate unit 103 is provided to connect the i-th second logic gate unit 102 and the (i+1)-th second logic gate unit 102. Since the second logic gate unit 102 is connected to the bandpass filter unit 101 in a one-to-one correspondence, and when the first logic gate unit 103 outputs signals of different states, the signal states output by the second logic gate unit 102 will also be different. Therefore, by providing the second logic gate unit 102, while retaining the output signal state of the above-mentioned first logic gate unit 103, the output signal of the first logic gate unit 103 is converted into an output signal that corresponds one-to-one with the bandpass filter unit 101. This allows the identification unit 108 to simply and directly determine which bandpass filter unit 101 the signal to be identified has passed through based on the output of the second logic gate unit 102, thereby obtaining an identity recognition result for the signal to be identified.

[0037] As a specific embodiment, the settings of the above-mentioned second logic gate unit 102 and the first logic gate unit 103 can be set according to the type of the signal to be identified. When the signal to be identified is a positive pulse width signal, the first logic operation is an exclusive OR operation, and the second logic operation is an AND operation; when the signal to be identified is a negative pulse width signal, the first logic operation is an exclusive OR operation, and the second logic operation is an OR operation.

[0038] For example, when the signal to be identified is a positive pulse width signal, the second logic gate unit 102 includes an AND gate, and the first logic gate unit 103 includes an XOR gate; when the signal to be identified is a negative pulse width signal, the second logic gate unit 102 includes an OR gate, and the first logic gate unit 103 includes an XNOR gate.

[0039] The following describes the process in conjunction with a specific embodiment.

[0040] In this specific embodiment, when the above-mentioned first logic gate unit 103 is used to perform an exclusive OR operation on the signal input into the first logic gate unit 103, the second logic gate unit 102 is used to perform an AND operation on the signal input into the second logic gate unit 102. For example, the first logic gate unit 103 is an exclusive OR gate, the second logic gate unit 102 is an AND gate, the above-mentioned bandpass filter unit 101 is a bandpass filter, the above-mentioned signal to be identified is a positive pulse width signal, and N=3.

[0041] Specifically, if the above-mentioned signal to be identified is only within the effective frequency range of the second band-pass filtering unit 101, the signal to be identified only passes through the second band-pass filtering unit 101. Since the signal to be identified is a positive pulse width signal, when the signal to be identified is at a high level, the output signal of the second band-pass filtering unit 101 is a high level, and the output signals of the first band-pass filtering unit 101 and the second band-pass filtering unit 101 are both low levels. At this time, the first first logic gate unit 103 and the second first logic gate unit 103 will both output a high level due to different inputs, the first second logic gate unit 102 will output 0, the second second logic gate unit 102 will output 1, and the second second logic gate unit 102 will output 0.

[0042] If the above-mentioned signal to be identified is within the effective frequency range of the first band-pass filtering unit 101 and the second band-pass filtering unit 101, the signal to be identified passes through the first band-pass filtering unit 101 and the second band-pass filtering unit 101, but does not pass through the third band-pass filtering unit 101. When the signal to be identified is at a high level, the output signals of the first band-pass filtering unit 101 and the second band-pass filtering unit 101 are high levels, and the output signal of the third band-pass filtering unit 101 is low levels. At this time, the first first logic gate unit 103 will output a low level because the inputs are the same, the second first logic gate unit 103 will output a high level because the inputs are different, the first second logic gate unit 102 will output 0, the second second logic gate unit 102 will output 0, and the third second logic gate unit 102 will output 0.

[0043] If the above-mentioned signal to be identified is not within the effective frequency range of any of the three band-pass filtering units 101, the outputs of the three band-pass filtering units 101 are all 0, and the first first logic gate unit 103 and the second first logic gate unit 103 are both exclusive OR gates. Therefore, when the outputs of the three band-pass filtering units 101 are all 0, the two input ends of the first first logic gate unit 103 will both input 0, and the two input ends of the second first logic gate unit 103 will also input 0. In this case, the first first logic gate unit 103 and the second first logic gate unit 103 will both output a low level because of the same input, and then the three second logic gate units 102 will all output 0.

[0044] It can be seen that the second second logic gate unit 102 will output 1 only when the signal to be identified is only within the effective frequency range of the second band-pass filter unit 101. In other cases, the three second logic gate units 102 will all output 0. When the second second logic gate unit 102 outputs 1, it is determined that the signal to be identified has only passed through the second band-pass filter, thereby realizing the identification of the identity of the signal to be identified.

[0045] Thus, by providing the above-mentioned first logic gate unit 103 and arranging the above-mentioned i-th first logic gate unit 103 to connect to the i-th bandpass filter unit 101 and the i+1-th bandpass filter unit 101, it is possible to distinguish between the two situations where the signal to be identified is within the effective frequency range of one bandpass filter and the signal to be identified is within the effective frequency range of two bandpass filters, thereby supporting partial overlap of the effective frequency ranges of different bandpass filters, improving frequency band utilization, and avoiding waste of resources. In addition, by providing the above-mentioned second logic gate unit 102 and arranging the i-th first logic gate unit 103 to connect to the i-th second logic gate unit 102 and the i+1-th second logic gate unit 102, since the second logic gate unit 102 is connected to the bandpass filter unit 101 in a one-to-one correspondence, the output signal of the first logic gate unit 103 is converted into an output signal that corresponds to the bandpass filter unit 101 in a one-to-one manner, so that the recognition unit 108 can simply and directly determine which bandpass filter unit 101 the signal to be identified has passed through based on the output of the second logic gate unit 102, thereby obtaining an identity recognition result of the signal to be identified.

[0046] In some embodiments of the present invention, the upper limit of the effective frequency range of the i-1th band-pass filtering unit 101 is the minimum frequency value of the center frequency window of the i-th band-pass filtering unit 101, and the lower limit of the effective frequency range of the i+1th band-pass filtering unit 101 is the maximum frequency value of the center frequency window of the i-th band-pass filtering unit 101, wherein the center frequency window of the i-th band-pass filtering unit 101 is a preset frequency window within the effective frequency range of the i-th band-pass filtering unit 101, and the effective frequency range of the i-th band-pass filtering unit is the frequency range in which the output signal strength of the i-th band-pass filtering unit is greater than a preset threshold.

[0047] Among them, the upper limit of the above-mentioned effective frequency range is the maximum value of the effective frequency range of the band-pass filtering unit 101, that is, if the frequency of the signal to be identified is higher than the upper limit of the effective frequency range of the i-th band-pass filtering unit 101, the signal to be identified will not effectively pass through the i-th band-pass filtering unit 101, and the lower limit of the above-mentioned effective frequency range is the minimum value of the effective frequency range of the band-pass filtering unit 101, that is, if the frequency of the signal to be identified is lower than the lower limit of the effective frequency range of the i-th band-pass filtering unit 101, the signal to be identified will not effectively pass through the i-th band-pass filtering unit 101. After passing through the i-th band-pass filtering unit 101, the signal to be identified will be attenuated to the point where it cannot be recognized by the subsequent circuit.

[0048] Specifically, for each band-pass filtering unit 101, a center frequency window is set, and the center frequency window is within the effective frequency range of the band-pass filtering unit 101. Moreover, for the i-th band-pass filtering unit 101, the upper limit of the effective frequency range of the i-1-th band-pass filtering unit 101 is the minimum frequency value of the center frequency window of the i-th band-pass filtering unit 101, and the lower limit of the effective frequency range of the i+1-th band-pass filtering unit 101 is the maximum frequency value of the center frequency window of the i-th band-pass filtering unit 101.

[0049] At this time, referring to the above-mentioned first logic gate unit 103 being used to perform an exclusive OR operation on the signal input to the first logic gate unit 103, the second logic gate unit 102 is used to perform an AND operation on the signal input to the second logic gate unit 102. For example, the first logic gate unit 103 is an exclusive OR gate, the second logic gate unit 102 is an AND gate, the above-mentioned band-pass filter unit 101 is a band-pass filter, the above-mentioned signal to be identified is a positive pulse width signal, and in a specific embodiment of N=3, when the signal to be identified is within the center frequency window range of the second band-pass filter unit 101, the second second logic gate unit 102 outputs 1; when the signal to be identified is within the effective frequency range of the second band-pass filter unit 101 and is not within the center frequency range of the second band-pass filter unit 101, the three second logic gate units 102 will all output 0.

[0050] It can be seen that the above center frequency range is the valid signal frequency range of the signal to be identified, that is, when the frequency of the signal to be identified falls within the center frequency range of any bandpass filtering unit 101, the signal to be identified is a valid signal.

[0051] In some embodiments of the present invention, the lower limit of the effective frequency range of the i-1th band-pass filtering unit 101 is the maximum frequency value of the center frequency window of the i-th band-pass filtering unit 101, and the upper limit of the effective frequency range of the i+1th band-pass filtering unit 101 is the minimum frequency value of the center frequency window of the i-th band-pass filtering unit 101, wherein the center frequency window of the i-th band-pass filtering unit 101 is a preset frequency window within the effective frequency range of the i-th band-pass filtering unit 101, and the effective frequency range of the i-th band-pass filtering unit is the frequency range in which the output signal strength of the i-th band-pass filtering unit is greater than a preset threshold.

[0052] In some embodiments of the present invention, the identification unit 108 is specifically configured to: when a preset signal exists among the output signals of the N second logic gate units 102, obtain an identity identification result of the signal to be identified based on the target second logic gate unit 102 that outputs the preset signal; and when the preset signal does not exist among the output signals of the N second logic gate units 102, identify the signal to be identified as an invalid signal.

[0053] Continuing with the above-mentioned first logic gate unit 103 being used to perform an XOR operation on the signal input to the first logic gate unit 103, the second logic gate unit 102 is used to perform an AND operation on the signal input to the second logic gate unit 102. For example, the first logic gate unit 103 is an XOR gate, the second logic gate unit 102 is an AND gate, the above-mentioned bandpass filter unit 101 is a bandpass filter, the above-mentioned signal to be identified is a positive pulse width signal, and a specific embodiment of N=3 is described.

[0054] As shown above, when the signal to be identified is only within the effective frequency range of the second band-pass filter unit 101, the second second logic gate unit 102 will output 1. In other cases, all three second logic gate units 102 will output 0. In this case, the preset signal is 1. Therefore, when the signal to be identified is only within the effective frequency range of the second band-pass filter unit 101, the preset signal 1 is present in the output signals of the three second logic gate units 102, and the second second logic gate unit 102 that outputs the preset signal 1 is determined to be the target second logic gate unit 102. The identity recognition result is obtained based on this target second logic gate unit 102. In other cases, all three second logic gate units 102 will output 0. When the preset signal is not present in the output signals of the three second logic gate units 102, the signal to be identified is identified as an invalid signal.

[0055] In some embodiments of the present invention, the identification unit 108 is further used to: when a preset signal exists in the output signals of the N second logic gate units 102, determine the target band-pass filter unit 101 according to the target second logic gate unit 102, and query the preset band-pass filter unit 101-signal identity correspondence table according to the target band-pass filter unit 101 to obtain an identity recognition result of the signal to be identified, wherein the target band-pass filter unit 101 is the band-pass filter unit 101 connected to the target second logic gate unit 102.

[0056] Specifically, as described above, the upper limit of the effective frequency range of the i-1th band-pass filtering unit 101 is set to the minimum frequency value of the center frequency window of the i-th band-pass filtering unit 101, and the lower limit of the effective frequency range of the i+1th band-pass filtering unit 101 is set to the maximum frequency value of the center frequency window of the i-th band-pass filtering unit 101, or, the lower limit of the effective frequency range of the i-1th band-pass filtering unit 101 is set to the maximum frequency value of the center frequency window of the i-th band-pass filtering unit 101, and the upper limit of the effective frequency range of the i+1th band-pass filtering unit 101 is set to the minimum frequency value of the center frequency window of the i-th band-pass filtering unit 101.

[0057] However, in actual applications, when setting the band-pass filter unit 101, it cannot be guaranteed that the cutoff frequency of a band-pass filter unit 101 falls exactly on the boundary of the center frequency window of its adjacent band-pass filter unit 101. At this time, there will be a difference between the actual center frequency window of the band-pass filter unit 101 and its theoretical center frequency window. For example, assuming that theoretically the upper limit of the effective frequency range of the i-1th band-pass filter unit 101 is the frequency minimum value of the center frequency window of the i-th band-pass filter unit 101, but in fact the effective frequency range of the i-1th band-pass filter unit 101 is less than the center frequency window of the i-th band-pass filter unit 101. The upper limit is slightly smaller than the frequency minimum value of the center frequency window of the i-th band-pass filtering unit 101. If the signal to be identified falls within the frequency interval between the upper limit of the effective frequency range of the i-1-th band-pass filtering unit 101 and the frequency minimum value of the center frequency window of the i-th band-pass filtering unit 101, the signal to be identified can only pass through the i-th band-pass filtering unit 101, that is, the frequency interval between the upper limit of the effective frequency range of the i-1-th band-pass filtering unit 101 and the frequency minimum value of the center frequency window of the i-th band-pass filtering unit 101 will actually become the center frequency window of the i-th band-pass filtering unit 101.

[0058] At this time, in order to avoid the identity recognition error of the signal to be identified caused by the inconsistency between the actual center frequency window and the theoretical center frequency window, a bandpass filter unit 101-signal identity correspondence table is pre-set, that is, the identity of the signal to be identified is identified by the bandpass filter unit 101 through which the signal to be identified passes, thereby avoiding the identity recognition error of the signal to be identified caused by the inconsistency between the actual center frequency window and the theoretical center frequency window.

[0059] Continuing with the above-mentioned first logic gate unit 103 being used to perform an XOR operation on the signal input to the first logic gate unit 103, the second logic gate unit 102 is used to perform an AND operation on the signal input to the second logic gate unit 102. For example, the first logic gate unit 103 is an XOR gate, the second logic gate unit 102 is an AND gate, the above-mentioned bandpass filter unit 101 is a bandpass filter, the above-mentioned signal to be identified is a positive pulse width signal, and a specific embodiment of N=3 is described.

[0060] Specifically, a band-pass filter unit 101-signal identity correspondence table is pre-set, for example, the band-pass filter unit 101 of the first band-pass filter unit 101 is set to correspond to the first signal identity, the band-pass filter unit 101 of the second band-pass filter unit 101 corresponds to the second signal identity, and the band-pass filter unit 101 of the third band-pass filter unit 101 corresponds to the third signal identity. At this time, when the signal to be identified is only within the effective frequency range of the second band-pass filter unit 101, the second second logic gate unit 102 will output 1, and the second second logic gate unit 102 that outputs the preset signal 1 is determined to be the target second logic gate unit 102, and then the table is looked up to obtain the identity recognition result of the signal to be identified as the second signal identity.

[0061] In some embodiments of the present invention, the signal identification circuit 100 further includes: N Schmitt units, the N Schmitt units are connected one-to-one with the N bandpass filtering units 101, and are connected one-to-one with the N second logic gate units 102, the 1st Schmitt unit is connected to the 1st first logic gate unit 103, the Nth Schmitt unit is connected to the N-1th first logic gate unit 103, the jth Schmitt unit is connected to the j-1th first logic gate unit 103 and the jth first logic gate unit 103, where j is a positive integer greater than 1 and less than N; the Schmitt unit is used to perform a shaping operation on the output signal of the bandpass filtering unit 101, and send the shaping result to the second logic gate unit 102 and the first logic gate unit 103.

[0062] Specifically, due to the use of the bandpass filtering unit 101, the signal recognition circuit 100 can be applied to the case where the signal to be identified is an analog signal, and can also be applied to the case where the signal to be identified is a digital signal. In order to improve the signal recognition accuracy when the signal to be identified is an analog signal, a Schmidt unit is configured for each bandpass filtering unit 101, and the Schmidt unit is used to perform a shaping operation on the output signal of the bandpass filtering unit 101, and the analog signal output by the bandpass filtering unit 101 is converted into a digital signal, thereby further improving the accuracy of identity recognition of the signal to be identified.

[0063] In some embodiments of the present invention, the signal recognition circuit 100 further includes: N registers, the N registers are connected to the N second logic gate units 102 in a one-to-one correspondence, and the N registers are all connected to the recognition unit 108. The register is used to receive the output signal of the second logic gate unit 102 when the trigger signal is received at the trigger end of the register, and output the output signal of the second logic gate unit 102 to the recognition unit 108.

[0064] In some embodiments of the present invention, when the signal to be identified is a positive pulse width signal, the trigger end is the negative edge clock trigger end of the register, and the trigger signal is the falling edge of the signal to be identified; when the signal to be identified is a negative pulse width signal, the trigger end is the positive edge clock trigger end of the register, and the trigger signal is the rising edge of the signal to be identified. The signal identification circuit 100 also includes: a buffer, the buffer is connected to the trigger ends of N registers and the input pin 104 of the signal identification circuit 100, and the buffer is used to delay the signal to be identified and send it to the trigger end of the register when receiving the signal to be identified, so that the trigger signal in the signal to be identified triggers the register to receive the output signal of the second logic gate unit 102, and outputs the output signal to the identification unit 108.

[0065] Specifically, the input end of the above-mentioned signal recognition circuit 100 is set as an input pin 104. The signal to be recognized is not only input into the N bandpass filter units 101 through the input pin 104, but also input into the buffer through the input pin 104, and then input into the trigger end of the register after being buffered by the buffer.

[0066] The above-mentioned signal to be identified is also configured to include a trigger signal. When the signal to be identified is delayed and input to the register via the buffer, the trigger signal in the signal to be identified triggers the register to receive the output signal of the second logic gate unit 102 and output the output signal to the identification unit 108.

[0067] In some embodiments of the present invention, when the signal to be identified is a positive pulse width signal, the second logic gate unit 102 is used to perform an AND operation on the signal input to the second logic gate unit 102. For example, the second logic gate unit 102 can be set as an AND gate, and the first logic gate unit 103 is used to perform an XOR operation on the signal input to the first logic gate unit 103. For example, the first logic gate unit 103 can be set as an XOR gate, the trigger end is the negative edge trigger end of the clock of the register, and the trigger signal is the falling edge of the signal to be identified; when the signal to be identified is a negative pulse width signal, the second logic gate unit 102 is used to perform an OR operation on the signal input to the second logic gate unit 102. For example, the second logic gate unit 102 can be set as an OR gate, and the first logic gate unit 103 is used to perform an XOR operation on the signal input to the first logic gate unit 103. For example, the first logic gate unit 103 can be set as an XOR gate, the trigger end is the positive edge trigger end of the clock of the register, and the trigger signal is the rising edge of the signal to be identified.

[0068] The following describes the process in conjunction with a specific embodiment.

[0069] In this specific embodiment, the input signal can be a positive pulse width signal or a negative pulse width signal. The signal identification circuit 100 is a circuit in a system-on-chip (SoC), and thus the input end of the signal identification circuit 100 is an input pin 104 of the SoC. The bandpass filter unit 101 is a bandpass filter. N is a positive integer greater than 7.

[0070] When the signal to be identified is a positive pulse width signal, the second logic gate unit 102 is an AND gate, the first logic gate unit 103 is an XOR gate, the trigger end is the negative edge trigger end of the register clock, and the trigger signal is the falling edge of the signal to be identified.

[0071] At this time, see Figure 2 , using N bandpass filters and using Schmidt units for shaping, we get N preprocessed signals. Figure 2 In the figure, 107 is the buffer. In descending order, the bandpass filter unit 101, the Schmidt unit 105, and the register 106 in the first row are bandpass filter 1, Schmidt unit 1, and register 1, respectively. The bandpass filter unit 101, the Schmidt unit 105, and the register 106 in the second row are bandpass filter 2, Schmidt unit 2, and register 2, respectively. The bandpass filter unit 101, the Schmidt unit 105, and the register 106 in the third row are bandpass filter 3, Schmidt unit 3, and register 106, respectively. The bandpass filter unit 101, Schmitt unit 105, and register 106 in the i-th row are bandpass filter i, Schmitt unit i, and register i respectively; the bandpass filter unit 101, Schmitt unit 105, and register 106 in the second-to-last row are bandpass filter N-1, Schmitt unit N-1, and register N-1 respectively; the bandpass filter unit 101, Schmitt unit 105, and register 106 in the last row are bandpass filter N, Schmitt unit N, and register N respectively.

[0072] The relationship between the above bandpass filter and the target digital signal can be found in Figure 3 ,exist Figure 3 In the above, the boundary gain means that if the gain of the bandpass filter at a certain frequency is less than the boundary gain, the signal at this frequency cannot effectively pass through the bandpass filter.

[0073] Bandpass filters with adjacent passband frequencies can have smaller frequency spacing and larger frequency overlap, allowing the frequency at each filter's boundary gain to be close to the center frequency window of the adjacent filter. This increases the number of target digital signals allowed within a given frequency range.

[0074] To prevent the target digital signals corresponding to two bandpass filters with adjacent effective frequency ranges from being triggered or recognized simultaneously, a digital processing method is used. Preprocessed signal i is subjected to an exclusive-or operation with its adjacent preprocessed signals i-1 and i+1. If the exclusive-or results are all 1, it indicates that the signal to be recognized is within the center frequency window and pulse width window corresponding to target digital signal i. The input signal to be recognized is valid, enabling the relevant preprocessed signal to be sent to the data input of the register, and the data input of the i-th register receives a valid value of 1. If any of the exclusive-or results is 0, it indicates that the input signal to be recognized is not within the center frequency window and pulse width window corresponding to either target digital signal, but rather lies between the center frequency windows and pulse width windows corresponding to two adjacent bandpass filters. The signal to be recognized is determined to be invalid, and an invalid value of 0 is sent to the data input of the corresponding register. The pulse width window mentioned above is a window obtained based on the center frequency window.

[0075] After the input signal to be identified is connected to a first-level buffer 107, the output of which is connected to the negative-edge trigger terminal of each register. This ensures that the signal processing is complete before the falling edge of the signal reaches the register, and the register setup time is met. In this way, after the input pulse width ends and the delay is passed through buffer 107, the N registers can sample the N target digital signals. The sampling result is a level signal, which is friendly to low-frequency applications and low-power clockless modes.

[0076] When it is necessary to clear the target digital signal that was valid at the previous moment, it is sufficient to send a pulse width that is not within the specified frequency band.

[0077] When the signal to be identified is a negative pulse width signal, the second logic gate unit 102 is an OR gate, the first logic gate unit 103 is an XNOR gate, the trigger terminal is the positive edge trigger terminal of the register clock, and the trigger signal is the rising edge of the signal to be identified. At this time, the preset signal is 0.

[0078] In summary, the signal recognition circuit of an embodiment of the present invention includes N bandpass filtering units, N-1 first logic gate units, N second logic gate units and an identification unit, N is a positive integer greater than or equal to 3, the N bandpass filtering units are connected to the N second logic gate units in a one-to-one correspondence, the i-th first logic gate unit is connected to the i-th bandpass filtering unit, the i+1-th bandpass filtering unit, the i-th second logic gate unit and the i+1-th second logic gate unit, i is a positive integer greater than 0 and less than N, and the identification unit is connected to the N second logic gate units; wherein, the bandpass filtering unit is used to perform bandpass filtering on the received signal to be identified, and send the filtering result to the second logic gate unit and the first logic gate unit, the first logic gate unit is used to perform a first logic operation on the received signal, the second logic gate unit is used to perform a second logic operation on the output signal of the first logic gate unit and the filtering result, and the identification unit is used to obtain an identity recognition result of the signal to be identified based on the output signal of the N second logic gate units. Thus, by providing the above-mentioned first logic gate unit and arranging the above-mentioned i-th first logic gate unit to connect to the i-th bandpass filter unit and the i+1-th bandpass filter unit, it is possible to distinguish between two situations: the signal to be identified is within the effective frequency range of one bandpass filter and the signal to be identified is within the effective frequency range of two bandpass filters, thereby supporting partial overlap of the effective frequency ranges of different bandpass filters, improving frequency band utilization, and avoiding waste of resources. Furthermore, by providing the above-mentioned second logic gate unit and arranging the i-th first logic gate unit to connect to the i-th second logic gate unit and the i+1-th second logic gate unit, since the second logic gate unit is connected to the bandpass filter unit in a one-to-one correspondence, the output signal of the first logic gate unit is converted into an output signal that corresponds to a one-to-one bandpass filter unit, so that the recognition unit can simply and directly determine which bandpass filter unit the signal to be identified has passed through based on the output of the second logic gate unit, thereby obtaining an identity recognition result of the signal to be identified.

[0079] Furthermore, the present invention provides a system on chip.

[0080] Figure 4 FIG. 4 is a structural block diagram of a system on a chip according to an embodiment of the present invention.

[0081] like Figure 4 As shown, the system on chip 10 includes the above-mentioned signal recognition circuit 100 .

[0082] The system-on-chip of the embodiment of the present invention, through the signal recognition circuit of the above embodiment, by providing the above-mentioned first logic gate unit and arranging the above-mentioned first logic gate unit to connect to the i-th bandpass filter unit and the i+1-th bandpass filter unit, can distinguish between two situations: the signal to be recognized is within the effective frequency range of one bandpass filter and the signal to be recognized is within the effective frequency range of two bandpass filters, thereby supporting partial overlap of the effective frequency ranges of different bandpass filters, improving frequency band utilization, and avoiding waste of resources. Moreover, by providing the above-mentioned second logic gate unit and arranging the i-th first logic gate unit to connect to the i-th second logic gate unit and the i+1-th second logic gate unit, since the second logic gate unit is connected to the bandpass filter unit in a one-to-one correspondence, the output signal of the first logic gate unit is converted into an output signal that corresponds to the bandpass filter unit in a one-to-one correspondence, so that the recognition unit can simply and directly determine which bandpass filter unit the signal to be recognized has passed through based on the output of the second logic gate unit, thereby obtaining an identity recognition result of the signal to be recognized.

[0083] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0084] It should be understood that various components of the present invention may be implemented using hardware, software, firmware, or a combination thereof. In the aforementioned embodiments, multiple steps or methods may be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented using hardware, as in the other embodiments, any one or a combination of the following technologies known in the art may be used: a discrete logic circuit having logic gates for implementing logic functions on data signals, an application-specific integrated circuit having suitable combinational logic gates, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0085] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0086] In the description of this specification, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation on the present invention.

[0087] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0088] In the description of this specification, unless otherwise specified, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. For those skilled in the art, the specific meanings of the above terms in this invention can be understood according to specific circumstances.

[0089] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0090] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A signal recognition circuit, characterized in that: The circuit includes an identification unit, N band-pass filtering units, N-1 first logic gate units and N second logic gate units, N is a positive integer greater than or equal to 3, the N band-pass filtering units are connected to the N second logic gate units in a one-to-one correspondence, the i-th first logic gate unit is connected to the i-th band-pass filtering unit, the i+1-th band-pass filtering unit, the i-th second logic gate unit and the i+1-th second logic gate unit, i is a positive integer greater than 0 and less than N, and the identification unit is connected to the N second logic gate units; In which, the bandpass filtering unit is used to perform bandpass filtering on the received signal to be identified, and send the filtering result to the first logic gate unit and the second logic gate unit, the first logic gate unit is used to perform a first logic operation on the received signal, and the second logic gate unit is used to perform a second logic operation on the output signal of the first logic gate unit and the filtering result, and the identification unit is used to obtain the identity recognition result of the signal to be identified based on the output signals of N second logic gate units.

2. The signal recognition circuit according to claim 1, characterized in that: When the signal to be identified is a positive pulse width signal, the first logical operation is an exclusive OR operation, and the second logical operation is an AND operation; When the signal to be identified is a negative pulse width signal, the first logical operation is an exclusive OR operation, and the second logical operation is an OR operation.

3. The signal recognition circuit according to claim 1, characterized in that: The upper limit of the effective frequency range of the i-1th band-pass filtering unit is the minimum frequency value of the center frequency window of the i-th band-pass filtering unit, and the lower limit of the effective frequency range of the i+1th band-pass filtering unit is the maximum frequency value of the center frequency window of the i-th band-pass filtering unit, wherein the center frequency window of the i-th band-pass filtering unit is a preset frequency window within the effective frequency range of the i-th band-pass filtering unit, and the effective frequency range of the i-th band-pass filtering unit is the frequency range in which the output signal strength of the i-th band-pass filtering unit is greater than a preset threshold.

4. The signal recognition circuit according to claim 3, characterized in that: The identification unit is specifically used to: When a preset signal exists in the output signals of the N second logic gate units, obtaining an identity recognition result of the signal to be recognized according to the target second logic gate unit that outputs the preset signal; When there is no preset signal among the output signals of the N second logic gate units, it is identified that the signal to be identified is an invalid signal.

5. The signal recognition circuit according to claim 4, characterized in that: The identification unit is further configured to: When a preset signal exists in the output signals of the N second logic gate units, the target bandpass filter unit is determined according to the target second logic gate unit, and a preset bandpass filter unit-signal identity correspondence table is queried according to the target bandpass filter unit to obtain an identity recognition result of the signal to be identified, wherein the target bandpass filter unit is a bandpass filter unit connected to the target second logic gate unit.

6. The signal recognition circuit according to claim 1, characterized in that: The lower limit of the effective frequency range of the i-1th band-pass filtering unit is the maximum frequency value of the center frequency window of the i-th band-pass filtering unit, and the upper limit of the effective frequency range of the i+1th band-pass filtering unit is the minimum frequency value of the center frequency window of the i-th band-pass filtering unit, wherein the center frequency window of the i-th band-pass filtering unit is a preset frequency window within the effective frequency range of the i-th band-pass filtering unit, and the effective frequency range of the i-th band-pass filtering unit is the frequency range in which the output signal strength of the i-th band-pass filtering unit is greater than a preset threshold.

7. The signal recognition circuit according to claim 1, characterized in that: The circuit further comprises: N Schmitt cells, the N Schmitt cells are connected one-to-one with the N bandpass filter units, and are connected one-to-one with the N second logic gate units, the first Schmitt cell is connected to the first first logic gate unit, the Nth Schmitt cell is connected to the N-1th first logic gate unit, the jth Schmitt cell is connected to the j-1th first logic gate unit and the jth first logic gate unit, where j is a positive integer greater than 1 and less than N; The Schmitt unit is used to perform a shaping operation on the output signal of the bandpass filter unit, and send the shaping result to the first logic gate unit and the second logic gate unit.

8. The signal recognition circuit according to claim 1, characterized in that: The circuit further includes: N registers, N registers are connected one-to-one with N second logic gate units, and N registers are all connected to the identification unit. The register is used to receive the output signal of the second logic gate unit when the trigger signal is received at the trigger end of the register, and output the output signal of the second logic gate unit to the identification unit.

9. The signal recognition circuit according to claim 8, characterized in that: When the signal to be identified is a positive pulse width signal, the trigger end is a negative edge trigger end of the clock of the register, and the trigger signal is a falling edge of the signal to be identified; when the signal to be identified is a negative pulse width signal, the trigger end is a positive edge trigger end of the clock of the register, and the trigger signal is a rising edge of the signal to be identified. The circuit further includes: A buffer is connected to the trigger ends of the N registers and the input pins of the signal recognition circuit. The buffer is used to delay sending the signal to be recognized to the trigger end of the register when receiving the signal to be recognized, so that the trigger signal in the signal to be recognized triggers the register to receive the output signal of the second logic gate unit and output the output signal to the recognition unit.

10. A system on chip, characterized in that: The method comprises the signal recognition circuit according to any one of claims 1 to 9.

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