Reference clock frequency multiplication circuit and chip

Abstract

The present application relates to the technical field of analog integrated circuit, and discloses a reference clock frequency multiplication circuit and chip, the reference clock frequency multiplication circuit comprising: a phase detector, a charge pump, a loop filter, a voltage-controlled delay unit, a multi-phase injection locked ring oscillator and an edge combiner.The voltage-controlled delay unit, the phase detector, the charge pump and the loop filter constitute a multi-phase clock generator.The present application adopts the voltage-controlled delay unit to generate a multi-phase injection clock signal, and further adopts the multi-phase injection locked ring oscillator as the input clock source of the edge combiner to suppress the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit, so that a frequency multiplication clock signal with accurate duty ratio and low noise is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of analog integrated circuit technology, in particular to a reference clock frequency multiplication circuit and chip. BACKGROUND

[0002] The traditional clock frequency multiplication circuit is usually based on a phase-locked loop (PLL) structure, the basic structure of which includes a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider (1 / N), as shown in a of Figure 1 , the phase frequency detector is used to detect the phase error between the input reference clock and the feedback frequency-divided clock, the charge pump converts the phase error into a current, and the low-pass filter generates a control voltage. In combination with the frequency divider, this structure can generate a high-frequency clock by frequency multiplication of a low-frequency reference clock, and has the advantages of compact structure, stable operation and convenient frequency tuning. As shown in b of Figure 1 , the best loop bandwidth of the phase-locked loop can be approximately determined by the intersection of the loop module and the phase noise curve of the voltage-controlled oscillator. As can be seen, the jitter performance of the phase-locked loop is largely dependent on the noise of the voltage-controlled oscillator. However, different types of voltage-controlled oscillators have their own advantages and disadvantages in terms of power consumption, area, phase noise, tuning range and multi-phase clock generation. Compared with LC voltage-controlled oscillators, ring oscillators have the advantages of small area, wide tuning range and easy generation of multi-phase clock. The poor phase noise of the ring oscillator is mainly due to the accumulation of device noise. Therefore, a wider phase-locked loop loop bandwidth needs to be set to suppress the phase noise of the ring oscillator.

[0003] Compared with the phase-locked loop structure, the delay-locked loop has the advantages of wide frequency response range and low noise. In the traditional delay-locked loop structure, the phase error output by the delay-locked loop is difficult to be low due to circuit mismatch, and a duty cycle calibration circuit needs to be cascaded after the edge combiner, resulting in high cost.

[0004] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0005] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a reference clock frequency multiplication circuit and chip to solve the problem that the phase error output by the existing delay-locked loop is difficult to be low due to circuit mismatch, resulting in the need for a duty cycle calibration circuit cascaded after the edge combiner.

[0006] The technical solutions of the present application are as follows:

[0007] In a first aspect, the present application provides a reference clock frequency multiplication circuit, comprising:

[0008] a phase detector for detecting phase difference;

[0009] a charge pump connected with the phase detector, and a loop filter connected with the charge pump, the charge pump and the loop filter being configured to generate a control voltage according to a phase difference detection signal outputted by the phase detector;

[0010] a voltage controlled delay unit connected with the loop filter and the phase detector respectively, the voltage controlled delay unit being configured to access a reference clock and the control voltage and output a first multi-phase injection clock signal;

[0011] a multi-phase injection locked ring oscillator connected with the voltage controlled delay unit, the multi-phase injection locked ring oscillator being configured to access the control voltage and suppress phase error of the first multi-phase injection clock signal and output a second multi-phase injection clock signal;

[0012] an edge combiner connected with the multi-phase injection locked ring oscillator, the edge combiner being configured to generate a frequency multiplication clock through the second multi-phase injection clock signal.

[0013] Further provided in the present application, further comprising:

[0014] a first buffer connected between the voltage controlled delay unit and the phase detector;

[0015] a second buffer connected between the multi-phase injection locked ring oscillator and the edge combiner.

[0016] Further provided in the present application, the voltage controlled delay unit comprises a reference clock buffer and a voltage controlled delay line;

[0017] the reference clock buffer is connected with the voltage controlled delay line, and is configured to access a reference clock and convert the reference clock into a differential input signal inputted to the voltage controlled delay line;

[0018] the voltage controlled delay line is connected with the phase detector, and the voltage controlled delay unit is configured to access the differential input signal and output a first multi-phase injection clock signal to the phase detector and the multi-phase injection locked oscillator.

[0019] The further arrangement of the present application, the reference clock buffer comprises a plurality of cascaded first delay units, each of the first delay units outputs a differential clock signal, and the differential clock signals outputted by each of the first delay units collectively constitute the first multiphase injection clock signal.

[0020] The further arrangement of the present application, the first delay unit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a switched capacitor circuit, a fixed capacitor, a first variable capacitor and a second variable capacitor.

[0021] The input terminals of the first inverter and the second inverter are connected to the differential input signal, and the output terminals of the first inverter and the second inverter are respectively connected to the two output terminals of the voltage-controlled delay line.

[0022] The third inverter and the fourth inverter are connected across the two output terminals of the voltage-controlled delay line.

[0023] The fixed capacitor is connected across the two output terminals of the voltage-controlled delay line.

[0024] The first variable capacitor and the second variable capacitor are connected across the two output terminals of the voltage-controlled delay line.

[0025] The switched capacitor circuit is connected across the two output terminals of the voltage-controlled delay line, and the switched capacitor circuit is used to adjust the delay adjustment range of the first delay unit.

[0026] The further arrangement of the present application, the multiphase injection-locked ring oscillator comprises a plurality of cascaded second delay units and a first switch tube and a second switch tube connected to each of the second delay units.

[0027] The gate terminals of the first switch tube and the second switch tube are connected to the first multiphase injection clock signal, the drain terminal of the first switch tube is connected to the non-inverting terminal of the second delay unit, the source terminal of the first switch tube is grounded, the drain terminal of the second switch tube is connected to the inverting terminal of the second delay unit, and the source terminal of the second switch tube is grounded.

[0028] The output terminals of the second delay units are connected to the edge combiner, and the differential clock signals outputted by each of the second delay units collectively constitute the second multiphase injection clock signal.

[0029] The further arrangement of the present application, the phase detector comprises a first flip-flop, a second flip-flop, a first NOR gate and an inverter chain group.

[0030] The clock terminals of the first flip-flop and the second flip-flop are connected to the first multiphase injection clock signal.

[0031] An inverted output terminal of the first flip-flop and the second flip-flop is connected with an input terminal of the first NOR gate;

[0032] An output terminal of the first NOR gate is connected with an input terminal of the inverter chain group, and output terminals of the inverter chain group are respectively connected with reset terminals of the first flip-flop and the second flip-flop;

[0033] An output terminal of the first flip-flop outputs a first switch control signal, and an output terminal of the second flip-flop outputs a second switch control signal;

[0034] The first switch control signal and the second switch control signal constitute a phase difference detection signal output by the phase detector.

[0035] Further provided in the application, the charge pump comprises: a bias circuit, a first current mirror, a second current mirror, a normally-on path providing unit and a charge pump unit;

[0036] The bias circuit is connected with the first current mirror and the second current mirror and inputs a reference current, and is configured to provide a bias voltage for the first current mirror and the second current mirror;

[0037] The third current mirror is connected with the charge pump unit and inputs a power supply voltage, and is configured to provide an operating current for the charge pump unit;

[0038] The normally-on path providing unit is connected between the first current mirror and the third current mirror, and is configured to provide a normally-on path for the operating current of the charge pump unit;

[0039] The charge pump unit is connected between the first current mirror and the third current mirror, and is configured to generate a control voltage for the phase difference detection signal output by the phase detector.

[0040] Further provided in the application, the edge combiner comprises: a second NOR gate, a third NOR gate, a fourth NOR gate, a fifth NOR gate, a sixth NOR gate, a seventh NOR gate and an AND gate;

[0041] Input terminals of the second NOR gate, the third NOR gate, the fourth NOR gate and the fifth NOR gate input the second multi-phase injection clock signal;

[0042] Output terminals of the second NOR gate and the third NOR gate are respectively connected with input terminals of the sixth NOR gate, and output terminals of the fourth NOR gate and the fifth NOR gate are respectively connected with input terminals of the seventh NOR gate;

[0043] The output end of the sixth NOR gate and the output end of the seventh NOR gate are connected with the input end of the AND gate respectively, and the output end of the AND gate outputs a four times frequency clock.

[0044] In a second aspect, the present application further provides a chip comprising the reference clock frequency multiplication circuit as described above.

[0045] The reference clock frequency multiplication circuit comprises a phase detector for detecting phase difference; a charge pump and a loop filter, the charge pump being connected with the phase detector, the loop filter being connected with the charge pump, the charge pump and the loop filter being used for generating a control voltage according to a phase difference detection signal output by the phase detector; a voltage-controlled delay unit, the voltage-controlled delay unit being connected with the loop filter and the phase detector respectively, the voltage-controlled delay unit being used for inputting a reference clock and the control voltage and outputting a first multi-phase injection clock signal; a multi-phase injection locked ring oscillator, the multi-phase injection locked ring oscillator being connected with the voltage-controlled delay unit, the multi-phase injection locked ring oscillator being used for inputting the control voltage and suppressing phase error of the first multi-phase injection clock signal and outputting a second multi-phase injection clock signal; and an edge combiner, the edge combiner being connected with the multi-phase injection locked ring oscillator, the edge combiner being used for generating a frequency multiplication clock through the second multi-phase injection clock signal. The present application generates a multi-phase injection clock signal by using a voltage-controlled delay unit, and further uses a multi-phase injection locked ring oscillator as an input clock source of an edge combiner to suppress phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit, so that a frequency multiplication clock signal with accurate duty ratio and low noise is obtained. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only show some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained according to the structures shown in the drawings without any creative labor.

[0047] Figure 1 is a structure block diagram of a phase-locked loop and a phase noise characteristic diagram.

[0048] Figure 2 is a principle block diagram of the reference clock frequency multiplication circuit in the present application.

[0049] Figure 3 is a phase noise diagram of a delay-locked loop.

[0050] Figure 4is the circuit schematic and working timing chart of the phase detector in one embodiment of the present application.

[0051] Figure 5 is the working state chart and phase detection characteristic curve chart of the phase detector in one embodiment of the present application.

[0052] Figure 6 is the circuit schematic of the charge pump in one embodiment of the present application.

[0053] Figure 7 is the circuit schematic of the unit gain buffer constructed by rail-to-rail operational amplifier in one embodiment of the present application.

[0054] Figure 8 is the principle block diagram of the voltage controlled delay line and the circuit schematic of the first delay unit in one embodiment of the present application.

[0055] Figure 9 is the principle block diagram of the multiphase injection locked ring oscillator in one embodiment of the present application.

[0056] Figure 10 is the circuit schematic of the edge combiner in one embodiment of the present application.

[0057] Figure 11 is the tuning range chart of the reference clock frequency multiplication circuit in one embodiment of the present application.

[0058] Figure 12 is the phase noise chart of the reference clock frequency multiplication circuit in one embodiment of the present application.

[0059] Reference signs in the drawings: 1, phase detector; 2, charge pump; 21, bias circuit; 22, first current mirror; 23, second current mirror; 24, third current mirror; 25, always-on path providing unit; 26, charge pump unit; 3, loop filter; 4, voltage controlled delay unit; 41, reference clock buffer; 42, voltage controlled delay line; 421, first delay unit; 422, switched capacitor circuit; 5, multiphase injection locked ring oscillator; 51, second delay unit; 6, edge combiner; 7, first buffer; 8, second buffer. DETAILED DESCRIPTION

[0060] The present application provides a reference clock frequency multiplication circuit and chip, in order to make the purpose, technical scheme and effect of the present application more clear and definite, the present application is further explained in detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0061] In the embodiments and claims, the articles "a", "an" and "the" also include the plural, unless otherwise expressly specified by context. If it is stated herein that embodiments "comprise", "include", "have", "enter into" or "possess" something, then it is also possible that the embodiments can in fact include one or more of the features, integers, steps, operations, elements, components or combinations thereof, but not necessarily all of them.

[0062] It should further be understood that the word "comprise", "comprising", "comprises" and the like in this specification, particularly in the claims, specifies the presence of stated features, integers, steps, operations, elements, components and / or groups but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can also be present. In addition, the word "connected" or "coupled" as used herein can include wirelessly connected or wirelessly coupled. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] Those skilled in the art will understand that the terms used herein are not intended to limit the present application to a given aspect, but rather the terms are used in a generic sense to encompass the various aspects of the present application. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0064] In addition, the technical solutions among various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize the combination, and when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope required by the present application.

[0065] The inventor has found that different types of voltage-controlled oscillators have advantages and disadvantages in terms of power consumption, area, phase noise, tuning range and multi-phase clock generation. Compared with LC voltage-controlled oscillators, ring oscillators have the advantages of small area, wide tuning range and easy generation of multi-phase clocks; while LC voltage-controlled oscillators generally perform better in terms of phase noise and power consumption. It is generally difficult for these two structures to simultaneously meet the requirements of small area, low power consumption, low phase noise and multi-phase clock generation: the poor phase noise of ring oscillators is mainly due to the accumulation of device noise, and the large area of LC voltage-controlled oscillators is due to the large size of the inductor required. Therefore, a relatively wide phase-locked loop loop bandwidth needs to be set to suppress the phase noise of the voltage-controlled oscillator (especially the ring oscillator). Compared with traditional phase-locked loops, the clock generator based on a delay phase-locked loop has excellent jitter performance, and the output jitter can be approximately equal to the reference clock jitter. However, in the traditional delay phase-locked loop structure, the phase error of the delay phase-locked loop output is difficult to be low due to circuit mismatch, and a duty cycle calibration circuit needs to be cascaded after the edge combiner, resulting in high cost.

[0066] To solve the above technical problems, the application provides a reference clock frequency multiplication circuit and a chip, which adopts a delay phase-locked loop to generate a high-precision, low-noise multi-phase injection clock signal, and further adopts a multi-phase injection locked ring oscillator as an input clock source of an edge combiner to suppress the phase error of the multi-phase injection clock signal generated by the delay phase-locked loop, so as to obtain a frequency multiplication clock signal with accurate duty cycle and low noise.

[0067] Please refer to Figures 2 to 12 The application provides a preferred embodiment of a reference clock frequency multiplication circuit.

[0068] In some embodiments, as Figure 2As shown, the application provides a reference clock frequency multiplication circuit, which comprises a phase detector 1, a charge pump 2, a loop filter 3, a voltage controlled delay unit 4, a multi-phase injection locked ring oscillator 5 and an edge combiner 6. The phase detector 1 is used to detect phase difference; the charge pump 2 is connected with the phase detector 1, the loop filter 3 is connected with the charge pump 2, and the charge pump 2 and the loop filter 3 are used to generate a control voltage Vtune according to the phase difference detection signal output by the phase detector; the voltage controlled delay unit 4 is connected with the loop filter 3 and the phase detector 1 respectively, and the voltage controlled delay unit 4 is used to access the reference clock and the control voltage and output a first multi-phase injection clock signal; the multi-phase injection locked ring oscillator 5 is connected with the voltage controlled delay line 42, and the multi-phase injection locked ring oscillator 5 is used to access the control voltage, suppress the phase error of the first multi-phase injection clock signal and output a second multi-phase injection clock signal; the edge combiner 6 is connected with the multi-phase injection locked ring oscillator 5, and the edge combiner 6 is used to generate a frequency multiplication clock through the second multi-phase injection clock signal.

[0069] In the embodiment, the voltage controlled delay unit 4, the phase detector 1, the charge pump 2 and the loop filter 3 constitute a multi-phase clock generator. Wherein, the voltage controlled delay unit 4 accesses the reference clock generated by the crystal oscillator and converts the reference clock into a first multi-phase injection clock signal (differential signal) input to the phase detector 1. The phase detector 1 can detect the phase difference of the first multi-phase injection clock signal, and the charge pump 2 and the loop filter 3 generate a control voltage through the phase difference and input to the voltage controlled delay unit 4 and the multi-phase injection locked ring oscillator 5 respectively, so that the free running frequency of the multi-phase injection locked ring oscillator 5 is equal to the injection clock frequency when the delay locked loop is locked. The multi-phase injection locked oscillator can suppress the phase error after absorbing the first multi-phase injection clock, and then output a second multi-phase injection clock signal with higher precision to the edge combiner 6, and generate a frequency multiplication clock, for example, a four times frequency multiplication clock, by the edge combiner 6.

[0070] In the above technical solution, the structure combining the delay-locked loop and the multi-phase injection-locked ring oscillator 5 can break the compromise between phase accuracy and phase noise in the traditional injection-locked ring oscillator. The high-precision, low-noise multi-phase clock generated by the delay-locked loop has a wide frequency response range, can provide good clock jitter performance (the jitter accumulation in the open-loop voltage-controlled delay line is only limited to the delay line itself, and the phase noise transferred from the phase detector 1 and the charge pump 2 to the output is usually negligible due to the small gain of the delay-locked loop), the output jitter is approximately the reference clock jitter, and a large-area inductor is not needed. Through the clock synthesis by the edge combiner 6, a low-jitter, low-spur frequency multiplication clock can be generated, which has an advantage over the phase-locked loop or the multi-phase filter structure in low-frequency applications. Figure 3 The phase noise characteristics of the clock generator based on the delay-locked loop are shown, in which the cumulative phase noise related to the delay-locked loop and the phase noise introduced by the phase detector 1 and the charge pump 2 are very small. Although the structure has a certain jitter amplification effect at the out-of-band frequency, the amplitude is usually very small. Compared with the traditional phase-locked loop, the clock generator based on the delay-locked loop has excellent jitter performance, and the output jitter can be approximately equal to the reference clock jitter. Further, the multi-phase injection-locked ring oscillator 5 is introduced to effectively suppress the phase error, reduce the duty cycle variation of the output clock, obtain a high-precision multi-phase clock as the input clock source of the edge combiner 6, and generate a duty cycle accurate and low-noise frequency multiplication clock. This structure combining the delay-locked loop and the multi-phase injection-locked ring oscillator 5 can break the compromise between phase accuracy and phase noise in the traditional injection-locked ring oscillator, and a duty cycle calibration circuit is not needed after the edge combiner 6.

[0071] It should be understood that the phase accuracy of the multi-phase clock used as the injection signal in the multi-phase injection-locked ring oscillator 5 does not have to be too accurate. Since the working frequency is low and an eight-phase injection clock is needed, a larger area is needed if a multi-phase filter is used, and the mismatch will be larger. Therefore, the delay-locked loop is a very suitable multi-phase clock generation method.

[0072] In some embodiments, as shown in Figure 2 the reference clock frequency multiplication circuit further includes: a first buffer 7 and a second buffer 8. The first buffer 7 is connected between the voltage-controlled delay unit 4 and the phase detector 1; and the second buffer 8 is connected between the multi-phase injection-locked ring oscillator 5 and the edge combiner 6.

[0073] In the embodiment, the load of each stage output of the voltage-controlled delay unit 4 is not only the multi-phase injection-locked ring oscillator 5, but also a first buffer 7 for injecting the first buffer 7 into the phase detector 1. Meanwhile, in order to ensure the matching and symmetry of each stage of the voltage-controlled delay unit 4, a stage of the second buffer 8 is also cascaded at the non-phase-detection phase, i.e. the output of the multi-phase injection-locked ring oscillator 5. The first buffer 7 and the second buffer 8 are the same in structure.

[0074] In some embodiments, as shown by a in Figure 4 The phase detector 1 includes a first flip-flop DFF1, a second flip-flop DFF2, a first NOR gate NOR1 and a series of inverters constituting an inverter chain group Delay. The clock terminals of the first flip-flop DFF1 and the second flip-flop DFF2 are connected to the first multi-phase injection clock signal. The inverted output terminals of the first flip-flop DFF1 and the second flip-flop DFF2 are connected to the input terminals of the first NOR gate NOR1. The output terminal of the first NOR gate NOR1 is connected to the input terminal of the inverter chain group Delay, and the output terminals of the inverter chain group Delay are respectively connected to the reset terminals of the first flip-flop DFF1 and the second flip-flop DFF2. The output terminal of the first flip-flop DFF1 outputs a first switch control signal UP, and the output terminal of the second flip-flop DFF2 outputs a second switch control signal DN. The first switch control signal UP and the second switch control signal DN constitute the phase difference detection signal output by the phase detector 1.

[0075] In the embodiment, the phase detector 1 is a core module for realizing phase synchronization in a delay-locked loop. It generates a switch control signal UP / DN (a pulse signal) for switch control of the charge pump 2 by comparing the phase difference between the input signal CK1 and the input signal CK2. The phase detector 1 is composed of two rising edge triggered D flip-flops (i.e. the first flip-flop DFF1 and the second flip-flop DFF2) with reset terminals, a first NOR gate NOR1 and a series of odd-numbered inverters constituting an inverter chain group Delay which can realize reverse action. The inverter chain group Delay also serves as a delay of the reset signal, and the delay size is represented by td, which avoids the occurrence of glitches in the switch control signal UP / DN when the phase difference between the input signal CK1 and the input signal CK2 is small, so that the switch control signal UP / DN cannot be used as the switch control signal of the next stage charge pump 2.

[0076] The state of the phase detector 1 is triggered by the rising edges of the two input signals CK1 / CK2. The working principle and timing diagram are as shown in Figure 4As shown in b, input signal CK1 serves as a reference clock, and input signal CK2 is the clock signal delayed and adjusted by voltage-controlled delay line 42. When the rising edge of input signal CK2 arrives, the output of the second flip-flop DFF2 is set to a high level; when the rising edge of input signal CK2 arrives, the output of the first flip-flop DFF1 is set to a high level; when the outputs of both D flip-flops are both high, the reset terminals of both D flip-flops are set to a high level after a certain delay td, and the output terminals of both D flip-flops are simultaneously reset to a low level. The phase detection characteristic curve of the phase detector 1 is shown in Figure 1. Figure 5 As shown, its phase detection range is 4π. Figure 5 Middle ordinate This represents the average value of the voltage difference at the output terminals of phase detector 1. Figure 5 The horizontal axis Φ represents the phase difference between the two signals at the input of the phase detector.

[0077] In some embodiments, such as Figure 6 As shown, the charge pump 2 includes: a bias circuit 21, a first current mirror 22, a second current mirror 23, a normally open path providing unit 24, and a charge pump unit 25; the bias circuit 21 is connected to a reference current I_REF and is connected to the first current mirror 22 and the second current mirror 23 respectively, and the bias circuit 21 is used to provide bias voltage for the first current mirror 22 and the second current mirror 23; the third current mirror 24 is connected to a power supply voltage VDD and is connected to the charge pump unit 26, and the third current mirror 24 is used to provide operating current for the charge pump unit 26; the normally open path providing unit 25 is connected between the first current mirror 21 and the third current mirror 24, and the normally open path providing unit 25 is used to provide a normally open path for the operating current of the charge pump unit 26; the charge pump unit 26 is connected between the first current mirror 22 and the third current mirror 24, and the charge pump unit 26 is used to generate a control voltage from the phase difference detection signal output by the phase detector 1.

[0078] Specifically, the bias circuit 21 comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6. The first current mirror 22 comprises a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10. The second current mirror 23 comprises an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14. The third current mirror 24 comprises a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor M18. The always-on path providing unit 25 comprises a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, a twenty-second MOS transistor M22, a twenty-third MOS transistor M23, a twenty-fourth MOS transistor M24. The charge pump unit 26 comprises a twenty-fifth MOS transistor M25, a twenty-sixth MOS transistor M26, a twenty-seventh MOS transistor M27, a twenty-eighth MOS transistor M28, a twenty-ninth MOS transistor M29, a thirtieth MOS transistor M30, a thirty-first MOS transistor M31, a thirty-second MOS transistor M32, a thirty-third MOS transistor M33, a thirty-fourth MOS transistor M34, a thirty-fifth MOS transistor M35, and a thirty-sixth MOS transistor M36.

[0079] The first MOS M1 drain access reference current I_REF, the first MOS M1 source and the second MOS M2 drain connection, the second MOS M2 source ground, the first MOS M1 gate and the third MOS M3 gate connection, the second MOS M2 gate and the fourth MOS M4 gate connection, the third MOS M3 drain and the twelfth MOS M12 drain connection, the third MOS M3 source and the fourth MOS M4 drain connection, the fourth MOS M4 source ground; The fifth MOS M5 gate access power voltage VDD, the fifth MOS M5 drain and the fourteenth MOS M14 drain connection, the fifth MOS M5 source and the sixth MOS M6 drain connection, the twelfth MOS M12 drain and the third MOS M3 drain connection, The twelfth MOS M12 source and the eleventh MOS M11 drain connection, the twelfth MOS M12 gate and the fourteenth MOS M14 gate connection, the eleventh MOS M11 gate and the thirteenth MOS M13 gate connection, The eleventh MOS M11 source access power voltage, the thirteenth MOS M13 source access power voltage, the fourteenth MOS M14 drain and the fifth MOS M5 drain connection, The sixth MOS M6 source ground; The fifteenth MOS M15 source access power voltage, the fifteenth MOS M15 drain and the sixteenth MOS M16 source connection, the fifteenth MOS M15 gate and the seventeenth MOS M17 gate connection; The sixteenth MOS M16 drain and the nineteenth MOS M19 drain, the twentieth MOS M20 source connection, the sixteenth MOS M16 gate and the fourteenth MOS M14 gate and the eighteenth MOS M18 gate connection; The nineteenth MOS M19 gate access power voltage, the nineteenth MOS M19 source and the twenty-first MOS M21 drain connection, the twenty-first MOS M21 source and the twenty-third MOS M23 source connection, The twenty-first MOS M21 gate ground, the twenty-third MOS M23 gate ground;The drain of the twentieth MOS M20 is connected with the source of the twenty-second MOS M22, the gate of the twenty-second MOS M22 is connected with the power supply voltage, the drain of the twenty-second MOS M22 is connected with the drain of the twenty-fourth MOS M24, the gate of the twenty-fourth MOS M24 is connected with the power supply voltage, the source of the twenty-fourth MOS M24 is connected with the drain of the twenty-third MOS M23 and the drain of the seventh MOS M7; the common terminal of the nineteenth MOS M19 and the twenty-first MOS M21, the common terminal of the source of the twenty-first MOS M21 and the source of the twenty-third MOS M23, the common terminal of the twentieth MOS M20 and the twenty-second MOS M22, and the common terminal of the drain of the twenty-second MOS M22 and the drain of the twenty-fourth MOS M24 are connected; the gate of the seventh MOS M7 is connected with the drain of the third MOS M3 and the drain of the ninth MOS M9 respectively, the source of the seventh MOS M7 is connected with the drain of the eighth MOS M8, the gate of the eighth MOS M8 is connected with the gate of the sixth MOS M6 and the gate of the tenth MOS M10; the source of the ninth MOS M9 is connected with the drain of the tenth MOS M10, the source of the tenth MOS M10 is grounded, the drain of the ninth MOS M9 is connected with the drain of the twenty-ninth MOS M29, the source of the thirtieth MOS M30, the drain of the thirty-fifth MOS M35 and the source of the thirty-sixth MOS M36 respectively; the source of the seventeenth MOS M17 is connected with the power supply voltage, the gate of the seventeenth MOS M17 is connected with the gate of the fifteenth MOS M15, the drain of the seventeenth MOS M17 is connected with the source of the eighteenth MOS M18, the gate of the eighteenth MOS M18 is connected with the gate of the sixth MOS M6, the drain of the eighteenth MOS M18 is connected with the drain of the twenty-fifth MOS M25, the source of the twenty-sixth MOS M26, the drain of the thirty-first MOS M31 and the source of the twelfth MOS M12 respectively; the gate of the twenty-fifth MOS M25 is connected with the power supply voltage, the sixth level of the twenty-fifth MOS M25 is connected with the drain of the eighteenth MOS M18, the source of the twenty-fifth MOS M25 is connected with the drain of the twenty-seventh MOS M27, the gate of the twenty-seventh MOS M27 is grounded, the source of the twenty-seventh MOS M27 is connected with the source of the twenty-ninth MOS M29; the drain of the twenty-sixth MOS M26 is connected with the source of the twenty-eighth MOS M28, the drain of the twenty-eighth MOS M28 is connected with the drain of the thirtieth MOS M30.The common terminal of the source of the twenty-fifth MOS transistor M25 and the drain of the twenty-seventh MOS transistor M27, the common terminal of the drain of the twenty-sixth MOS transistor M26 and the source of the twenty-eighth MOS transistor M28, the common terminal of the source of the twenty-seventh MOS transistor M27 and the source of the twenty-ninth MOS transistor M29, the common terminal of the drain of the twenty-sixth MOS transistor M26 and the source of the twenty-eighth MOS transistor M28, and the common terminal of the drain of the twenty-eighth MOS transistor M28 and the drain of the thirtieth MOS transistor M30 are connected together; the common terminal of the source of the thirty-first MOS transistor M31 and the drain of the thirty-third MOS transistor M33, the common terminal of the source of the thirty-third MOS transistor M33 and the source of the thirty-fifth MOS transistor M35, the common terminal of the drain of the thirty-second MOS transistor M32 and the source of the thirty-fourth MOS transistor M34, and the common terminal of the thirty-fourth MOS transistor M34 and the thirty-sixth MOS transistor M36 are connected together.

[0080] In the embodiment, the charge pump 2 and the phase detector 1 cooperate to convert the switch control signal UP / DN at the output node of the phase detector 1 into an analog voltage or current input into the loop filter, and finally realize the phase synchronization of the two input clocks in the phase detector 1 by adjusting the phase of the voltage-controlled delay unit 4. It should be noted that some undesirable circuit effects, such as clock feedthrough, charge injection / sharing, etc., will seriously affect the performance of the charge pump 2 in the circuit design. The embodiment adopts a charge pump 2 with high current matching characteristics, and the structure thereof is as shown in the figure. Figure 6 INP / INPB is a pseudo-differential signal converted from the first switch control signal UP output by the phase detector 1, and INN / INNB is a pseudo-differential signal converted from the second switch control signal DN output by the phase detector 1.

[0081] The loop filter 3 is a loop capacitor C1. The charge pump 2 realizes the charging and discharging of the loop capacitor by outputting a switch pulse, so as to achieve the purpose of controlling the voltage across the loop capacitor C1.

[0082] In the circuit of the charge pump 2, the seventh MOS transistor M7 to the tenth MOS transistor M10 constitute a current mirror structure, and the fifteenth MOS transistor M15 to the eighteenth MOS transistor M18 constitute a current mirror structure. The first MOS transistor M1 to the sixth MOS transistor M6 and the eleventh MOS transistor M11 to the fourteenth MOS transistor M14 constitute a bias circuit, which can provide a bias voltage for the current mirror. The seventh MOS transistor M7 and the eighth MOS transistor M8, the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16, and the nineteenth MOS transistor M19 to the twenty-fourth MOS transistor M24 can provide a normally open path for the current of the charge pump 2, and can simultaneously improve the stability of the bias voltage. The ninth MOS transistor M9, the tenth MOS transistor M10, the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, the twenty-fifth MOS transistor M25 to the thirty-sixth MOS transistor M36 are used to realize the main function of the charge pump 2, wherein the ninth MOS transistor M9 and the tenth MOS transistor M10 and the seventeenth MOS transistor M17 and the eighteenth MOS transistor M18 constitute a current mirror structure, which provides a working current for the charge pump 2 when it works.

[0083] Among them, the first MOS transistor M1 to the fourth MOS transistor M4, the seventh MOS transistor M7 to the tenth MOS transistor M10, and the fifteenth MOS transistor M15 to the eighteenth MOS transistor M18 in the charge pump 2 are common-source common-gate structure current mirrors of low-voltage structure. The common-source common-gate structure current mirror has high output impedance, which can improve the current matching between the charging path and the discharging path in the charge pump 2. The output voltage range of the charge pump 2 is limited by the voltage drop on the current mirror. Therefore, this embodiment uses a common-source common-gate type current mirror based on a low-voltage architecture, which not only effectively reduces the voltage loss of the current mirror branch, but also further expands the output voltage interval of the charge pump 2 when it works by improving the output impedance of the current mirror.

[0084] In order to reduce the influence of charge injection and clock feedthrough effect, transmission gates are used as the structure for controlling the switch of the charge pump 2, such as the thirty-first MOS transistor M31 and the thirty-second MOS transistor M32, and the thirty-fifth MOS transistor M35 and the thirty-sixth MOS transistor M36. During the off process of the switch, the electrons in the N tube and the holes in the P tube in the transmission gate are released, and the sum of the equivalent currents of the two is zero, which suppresses the charge injection; by applying clock signals with opposite phases on the NMOS and PMOS devices, the coupling and interference of the two on the output node are offset, thereby realizing dynamic compensation of clock feedthrough. In order to solve the problem of charge sharing, a rail-to-rail operational amplifier is used to build a unit gain buffer, which is connected across the output nodes I_OUT and IOUT_DUM of the charge pump 2, and its equivalent circuit diagram is as follows: Figure 7As shown, the output node I_OUT is forced to be synchronous with IOUT_DUM by a negative feedback mechanism, thus effectively reducing charge sharing.

[0085] In some embodiments, as shown in FIG. 1, the voltage-controlled delay unit 4 comprises a reference clock buffer 41 and a voltage-controlled delay line 42; the reference clock buffer 41 is connected to the voltage-controlled delay line 42, and is configured to access a reference clock and convert the reference clock into a differential input signal input to the voltage-controlled delay line 42; the voltage-controlled delay line 42 is connected to the phase detector 1, and the voltage-controlled delay unit 4 is configured to access the differential input signal and output a first multiphase injection clock signal to the phase detector 1 and the multiphase injection-locked oscillator. Figure 2 Figure 8 In some embodiments, as shown in FIG. 1, the voltage-controlled delay line 42 comprises a plurality of cascaded first delay units 421, each of which outputs a differential clock signal, and the differential clock signals output by each of the first delay units 421 collectively constitute the first multiphase injection clock signal.

[0086] In some embodiments, as shown in FIG. 1, the voltage-controlled delay line 42 comprises a plurality of cascaded first delay units 421, each of which outputs a differential clock signal, and the differential clock signals output by each of the first delay units 421 collectively constitute the first multiphase injection clock signal.

[0087] In some embodiments, as shown in FIG. 1, the voltage-controlled delay line 42 comprises a plurality of cascaded first delay units 421, each of which outputs a differential clock signal, and the differential clock signals output by each of the first delay units 421 collectively constitute the first multiphase injection clock signal. Figure 8 In some embodiments, as shown in FIG. 1, the voltage-controlled delay line 42 comprises a plurality of cascaded first delay units 421, each of which outputs a differential clock signal, and the differential clock signals output by each of the first delay units 421 collectively constitute the first multiphase injection clock signal.

[0088] In some embodiments, as shown in FIG. 1, the voltage-controlled delay line 42 comprises a plurality of cascaded first delay units 421, each of which outputs a differential clock signal, and the differential clock signals output by each of the first delay units 421 collectively constitute the first multiphase injection clock signal.

[0089] Figure 8 ​​The first delay unit 421 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a switched capacitor circuit 422, a fixed capacitor C0, a first variable capacitor C2 and a second variable capacitor C3, as shown in FIG. 4B. The inputs of the first inverter INV1 and the second inverter INV2 are connected to the differential input signal, and the outputs of the first inverter INV1 and the second inverter INV2 are connected to the two outputs of the voltage-controlled delay line 42, respectively. The third inverter INV3 and the fourth inverter INV4 are connected in cross between the two outputs of the voltage-controlled delay line 42. The fixed capacitor is connected in cross between the two outputs of the voltage-controlled delay line 42. The first variable capacitor C2 and the second variable capacitor C3 are connected in cross between the two outputs of the voltage-controlled delay line 42. The switched capacitor circuit 422 is connected in cross between the two outputs of the voltage-controlled delay line 42, and is used to adjust the delay adjustment range of the first delay unit 421.

[0090] In this embodiment, the first inverter INV1 and the second inverter INV2 form a pair of large-size main inverters, and the third inverter INV3 and the fourth inverter INV4 form a pair of small-size cross-coupled inverters. The two pairs of inverters form a pseudo-differential delay unit based on cross-coupled inverters, which can output eight-phase clocks, i.e., DL0-DL315. The first inverter INV1 and the second inverter INV2 delay the input signals Vi_p and Vi_n (the input signals Vi_p and Vi_n include differential signals DL0 and DL180, differential signals DL225 and DL45, differential signals DL90 and DL270, DL180_DUM and DL0_DUM) to obtain output signals Vo_p and Vo_n. The third inverter INV3 and the fourth inverter INV4 are connected in cross between the two outputs of the voltage-controlled delay line 42 to ensure that the two output signals are differential signals. The switched capacitor circuit 422 uses three-bit switch control to expand the delay adjustment range of the pseudo-differential delay unit and avoid large phase errors caused by PVT (Process, Voltage, Temperature) variations. The continuous delay of the pseudo-differential delay unit is realized by the first variable capacitor C2, the second variable capacitor C3 and the fixed capacitor C0 connected in cross between the two outputs, wherein the control voltage Vtune is connected to the common terminal of the first variable capacitor C2 and the second variable capacitor C2.

[0091] The delay of each stage of the voltage-controlled delay line 42 is one-eighth of the clock period of 100 MHz (T100M / 8) in time domain and 45° phase shift in phase domain. In order to lock the delay of each stage to T100M / 8 through the delay-locked loop, a same delay unit (i.e. dummy delay unit in Figure 3 ) is connected after the last delay unit, and the output phase output differential signals DL0_DUM and DL180_DUM lagging one clock period compared with the differential signals DL0 and DL180 are used for phase detection, i.e. the input signals CK1 / CK2 are the differential signals DL0_DUM and DL180_DUM output by the voltage-controlled delay line 42 through the first buffer 7. Meanwhile, a buffer based on an inverter (i.e. the first buffer 7) is cascaded after each stage of the voltage-controlled delay line 42 to shape the output waveform into a square wave, and meanwhile the symmetry of each stage of the voltage-controlled delay line 42 is not destroyed.

[0092] In some embodiments, as shown by b in Figure 8 , the first inverter INV1 includes the thirty-seventh MOS transistor M37 and the thirty-eighth MOS transistor M38, the second inverter INV2 includes the thirty-ninth MOS transistor M39 and the fortieth MOS transistor M40. The third inverter INV3 includes the forty-first MOS transistor M41 and the forty-second MOS transistor M42, and the fourth inverter INV4 includes the forty-third MOS transistor M43 and the forty-fourth MOS transistor M44.

[0093] The gate of the thirty-seventh MOS transistor M37 and the thirty-eighth MOS transistor M38 is connected to the input signal Vi_p, the drain of the thirty-seventh MOS transistor M37 and the thirty-eighth MOS transistor M38 is connected to the output terminal of the voltage-controlled delay line 42, the source of the thirty-seventh MOS transistor M37 is connected to the power supply voltage, and the source of the thirty-eighth MOS transistor M38 is grounded. The gate of the thirty-ninth MOS transistor M39 and the fortieth MOS transistor M40 is connected to the input signal Vi_n, the drain of the thirty-ninth MOS transistor M39 and the fortieth MOS transistor M40 is connected to the output terminal, the source of the thirty-ninth MOS transistor M39 is connected to the power supply voltage, and the source of the fortieth MOS transistor M40 is grounded.

[0094] The gates of the forty-first MOSFET M41 and the forty-second MOSFET M42 are connected to the output terminal Vo_p, and the drains of the forty-first MOSFET M41 and the forty-second MOSFET M42 are connected to the output terminal Vo_n. The source of the forty-first MOSFET M41 is connected to the power supply voltage, and the source of the forty-second MOSFET M42 is grounded. The gates of the forty-third MOSFET M43 and the forty-fourth MOSFET M44 are connected to the output terminal Vo_n, and the drains of the forty-third MOSFET M43 and the forty-fourth MOSFET M44 are connected to the output terminal Vo_p. The source of the forty-third MOSFET M43 is grounded, and the source of the forty-fourth MOSFET M44 is grounded.

[0095] In some embodiments, such as Figure 9 As shown, the multiphase injection-locked ring oscillator 5 includes several cascaded second delay units 51 and a first switch Q1 and a second switch Q2 connected to each second delay unit 51; the gates of the first switch Q1 and the second switch Q2 are connected to the first multiphase injection clock signal, the drain of the first switch Q1 is connected to the non-inverting input of the second delay unit 51, the source of the first switch Q1 is grounded, the drain of the second switch Q2 is connected to the inverting input of the second delay unit 51, and the source of the second switch Q2 is grounded; the output of the second delay unit 51 is connected to the edge combiner 6; the differential clock signal output by each second delay unit 51 together constitutes the second multiphase injection clock signal.

[0096] In this embodiment, the second delay unit 51 has the same structure as the first delay unit 421, and the control voltage of the multiphase injection-locked ring oscillator 5 is connected to the control voltage in the delay phase-locked loop. The delay of the first delay unit 421 is equal to the delay of the second delay unit 51. The same delay unit and the same control voltage ensure that when the injection lock of the delay phase-locked loop occurs, the free oscillation frequency of the multiphase injection-locked ring oscillator 5 is equal to the injection clock frequency. In this embodiment, the first multiphase injection clock signal is input to the first switch Q1 and the second switch Q2. The differential signals of the first multiphase injection clock signal input to the first switch Q1 and the second switch Q2 are represented as INJ0 and INJ180, INJ225 and INJ45180, INJ90 and INJ270, and INJ315 and INJ135, respectively. The differential signals output by each stage of the second delay unit 51 are represented as R0_0 and R0_180, R0_225 and R0_45, R0_90 and R0_270, and R0_315 and R0_135. In one implementation, the input strength of the first multiphase injection clock signal is 0.3.

[0097] In some embodiments, as shown in Figure 10 The edge combiner 6 includes a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a fifth NOR gate NOR5, a sixth NOR gate NOR6, a seventh NOR gate NOR7, and an AND gate AND1. The inputs of the second NOR gate NOR2, the third NOR gate NOR3, the fourth NOR gate NOR4, and the fifth NOR gate NOR5 are connected to the second multi-phase injection clock signal. The outputs of the second NOR gate NOR2 and the third NOR gate NOR3 are connected to the inputs of the sixth NOR gate NOR6. The outputs of the fourth NOR gate NOR4 and the fifth NOR gate NOR5 are connected to the inputs of the seventh NOR gate NOR7. The outputs of the sixth NOR gate NOR6 and the seventh NOR gate NOR7 are connected to the inputs of the AND gate AND1, and the output of the AND gate AND1 outputs a four times frequency clock.

[0098] In this embodiment, the edge combiner 6 generates a high frequency output through edge detection and logical combination of multi-phase signals. In this embodiment, the edge combiner 6 is a circuit capable of raising the input signal frequency to four times, the first multi-phase injection clock signal is an eight-phase input signal including inputs V0, V225, V45, V180, V90, V315, V135, and V270, and the multi-stage logic gate is composed of a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a fifth NOR gate NOR5, a sixth NOR gate NOR6, a seventh NOR gate NOR7, and an AND gate AND1. As shown in Figure 9 The edge combiner 6 uses an eight-phase input signal and a multi-stage logic gate to achieve an efficient four times frequency function. As shown in Figure 9 The edges of the eight-phase output clock are evenly distributed on the time axis, ensuring that the pulse sequence of the logic gate does not overlap when performing edge combination. The input of the edge combiner 6 is the output of the previous-stage multi-phase injection locked ring oscillator 5, and the phase error of this set of eight-phase signals is less than 1°. After frequency multiplication, a 400MHz clock with a duty cycle of 50% is obtained.

[0099] To further illustrate the effect of the present application, simulation is performed according to Figure 2 The reference clock frequency multiplier designed in the present application is implemented based on COMS technology, and the low frequency part has a power supply voltage of 1V. To avoid the mismatch caused by PVT variation of the voltage-controlled delay line and the delay unit of the multi-phase injection locked ring oscillator, which leads to changes in the final output frequency and phase error, the low frequency ring oscillator designed in the present application expands the frequency range through a three-bit frequency control word. The frequency tuning range obtained through final simulation is as shown in Figure 11As shown, the lowest frequency is 89.7MHz and the highest frequency is 116.7MHz.

[0100] The phase noise of each module output obtained by the delay-locked loop, the multi-phase injection-locked ring oscillator and the edge combiner is as shown in the following table: Figure 12 As shown, in Figure 12 , DL represents the output signal of the first delay unit, CK_400M represents the output signal of the edge combiner, and RO represents the output signal of the second delay unit, wherein the voltage-controlled delay line only delays the reference signal, and thus the phase noise of the output increases with the increase of the number of delay stages, the phase noise of the multi-phase injection-locked ring oscillator follows the phase noise of DL135 / 315, and the phase noise of the edge-combined quadrupler for obtaining the 400MHz clock is improved by 20log(4) compared with the phase noise of the multi-phase injection-locked ring oscillator. The phase noise of the 400MHz clock at 1MHz frequency offset is-145.7dBc / Hz, and the jitter integrated from 10kHz to 40MHz is 149.7fs.

[0101] In some embodiments, the application also provides a chip comprising the reference clock frequency multiplication circuit as described above. Specifically, the reference clock frequency multiplication circuit is described above, and thus will not be described here again.

[0102] In summary, the reference clock frequency multiplication circuit and the chip provided by the application have the following beneficial effects:

[0103] In the multi-phase clock generation circuit, the coarse-precision multi-phase clock generator is used to generate the multi-phase injection signal, the delay-locked loop uses the injection-locked ring oscillator with high phase precision of the multi-phase output as the input clock source of the edge logic combiner, the duty cycle variation of the output clock can be reduced, the phase error of the multi-phase clock can be further suppressed to obtain the high-precision multi-phase clock, and the frequency multiplication clock is generated through the edge logic combiner. The structure of combining the delay-locked loop and the multi-phase injection-locked ring oscillator can break the compromise between the phase precision and the phase noise in the traditional injection-locked ring oscillator, and a duty cycle calibration circuit does not need to be cascaded after the edge combiner, thereby reducing the cost.

[0104] It should be understood that the application is not limited to the above examples, and those of ordinary skill in the art can make improvements or changes according to the above description, and all these improvements and changes shall fall within the protection scope of the appended claims of the application.

Claims

1. A reference clock frequency multiplier circuit, characterized in that, include: A phase detector used to detect phase differences; A charge pump and a loop filter are provided, wherein the charge pump is connected to the phase detector and the loop filter is connected to the charge pump. The charge pump and the loop filter are used to generate a control voltage based on the phase difference detection signal output by the phase detector. A voltage-controlled delay unit is provided, which is connected to the loop filter and the phase detector respectively. The voltage-controlled delay unit is used to receive the reference clock and the control voltage and output a first multiphase injection clock signal. A multiphase injection-locked ring oscillator is connected to the voltage-controlled delay unit. The multiphase injection-locked ring oscillator is used to receive the control voltage, suppress the phase error of the first multiphase injection clock signal, and output a second multiphase injection clock signal. An edge combiner, which is connected to the multiphase injection-locked ring oscillator, is used to generate a frequency-multiplied clock using the second multiphase injection clock signal; The voltage-controlled delay unit includes: a reference clock buffer and a voltage-controlled delay line; The reference clock buffer is connected to the voltage-controlled delay line. The reference clock buffer is used to receive a reference clock and convert the reference clock into a differential input signal, which is then input to the voltage-controlled delay line. The voltage-controlled delay line is connected to the phase detector, and the voltage-controlled delay unit is used to receive the differential input signal and output a first multiphase injection clock signal to the phase detector and the multiphase injection locked ring oscillator; The voltage-controlled delay line includes several cascaded first delay units, each of which outputs a differential clock signal. The differential clock signals output by each of the first delay units together constitute the first multiphase injection clock signal. The multiphase injection-locked ring oscillator includes a plurality of cascaded second delay units and a first switch and a second switch connected to each of the second delay units; The gates of the first switch and the second switch are connected to the first multiphase injection clock signal. The drain of the first switch is connected to the non-inverting input of the second delay unit. The source of the first switch is grounded. The drain of the second switch is connected to the inverting input of the second delay unit. The source of the second switch is grounded. The output of the second delay unit is connected to the edge combiner; the differential clock signal output by each of the second delay units together constitutes the second multiphase injection clock signal.

2. The reference clock frequency multiplier circuit according to claim 1, characterized in that, Also includes: A first buffer is connected between the voltage-controlled delay unit and the phase detector; A second buffer is connected between the multiphase injection-locked ring oscillator and the edge combiner.

3. The reference clock frequency multiplier circuit according to claim 1, characterized in that, The first delay unit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a switched capacitor circuit, a fixed capacitor, a first variable capacitor, and a second variable capacitor; The input terminals of the first inverter and the second inverter are connected to differential input signals, and the output terminals of the first inverter and the second inverter are respectively connected to the two output terminals of the voltage-controlled delay line; The third inverter and the fourth inverter are connected across the two output terminals of the voltage-controlled delay line; The fixed capacitor is connected across the two output terminals of the voltage-controlled delay line; The first variable capacitor and the second variable capacitor are connected across the two output terminals of the voltage-controlled delay line; A switched capacitor circuit is connected between the two output terminals of the voltage-controlled delay line, and the switched capacitor circuit is used to adjust the delay adjustment range of the first delay unit.

4. The reference clock frequency multiplier circuit according to claim 1, characterized in that, The phase detector includes: a first flip-flop, a second flip-flop, a first NOR gate and an inverter chain; The clock terminals of the first flip-flop and the second flip-flop are connected to the first multiphase injected clock signal; The inverted outputs of the first flip-flop and the second flip-flop are connected to the input of the first NOR gate; The output of the first NOR gate is connected to the input of the inverter chain, and the output of the inverter chain is connected to the reset terminals of the first flip-flop and the second flip-flop, respectively. The first flip-flop outputs a first switch control signal, and the second flip-flop outputs a second switch control signal. The first switch control signal and the second switch control signal constitute the phase difference detection signal output by the phase detector.

5. The reference clock frequency multiplier circuit according to claim 1, characterized in that, The charge pump includes: a bias circuit, a first current mirror, a second current mirror, a third current mirror, a normally open path providing unit, and a charge pump unit; The bias circuit is connected to a reference current and is connected to the first current mirror and the second current mirror respectively. The bias circuit is used to provide bias voltage to the first current mirror and the second current mirror. The third current mirror is connected to the power supply voltage and is connected to the charge pump unit. The third current mirror is used to provide operating current to the charge pump unit. The normally open path providing unit is connected between the first current mirror and the third current mirror, and the normally open path providing unit is used to provide a normally open path for the operating current of the charge pump unit. The charge pump unit is connected between the first current mirror and the third current mirror, and the charge pump unit is used to generate a control voltage from the phase difference detection signal output by the phase detector.

6. The reference clock frequency multiplier circuit according to claim 1, characterized in that, The edge combiner includes: a second NOR gate, a third NOR gate, a fourth NOR gate, a fifth NOR gate, a sixth NOR gate, a seventh NOR gate, and an AND gate; The input terminals of the second NOR gate, the third NOR gate, the fourth NOR gate, and the fifth NOR gate are connected to the second multiphase injected clock signal; The outputs of the second NOR gate and the third NOR gate are respectively connected to the input of the sixth NOR gate; the outputs of the fourth NOR gate and the fifth NOR gate are respectively connected to the input of the seventh NOR gate. The outputs of the sixth NOR gate and the seventh NOR gate are respectively connected to the input of the AND gate, and the output of the AND gate outputs a quadruple clock.

7. A chip, characterized in that, Includes the reference clock multiplier circuit as described in any one of claims 1-6.

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