FPGA-based miniaturized broadband signal generation in-band flatness compensation method

Abstract

The invention provides a miniaturized broadband signal generation in-band flatness compensation method based on an FPGA (Field Programmable Gate Array). The method specifically comprises the following steps of: dividing a signal bandwidth to be compensated into a sub-band set covering the whole bandwidth; inversing channel frequency response measured by a vector network analyzer VNA to obtain filter frequency response; obtaining a coefficient group of a complex coefficient filter through a maximum likelihood method; and storing the center frequency and the coefficient group of the complex coefficient filter in a coefficient register, and performing in-phase component compensation filtering and orthogonal component compensation filtering to complete full-compensation frequency band flatness compensation. According to the technical scheme, the problems that in-band flatness compensation precision is low and filtering time is long in the prior art are solved.

Description

Technical Field

[0001] The present invention relates to the field of signal processing, and in particular to a method for compensating for in-band flatness of a miniaturized broadband signal generator based on FPGA. Background Art

[0002] As the amount of information required to be transmitted increases, the bandwidth of signals generated is increasing, reaching the GHz level in ultra-wideband (UWB). Due to imperfect circuit matching or performance limitations of analog components, the flatness of in-band signals deteriorates, seriously affecting overall device performance indicators such as EVM.

[0003] In broadband signal generators, compensating for in-band signal power flatness is necessary to improve overall performance metrics such as EVM (Error Vector Magnitude). One approach uses traditional analog IF filtering for compensation. However, due to hardware limitations, this method can only compensate for narrow bandwidths and is inadequate for broadband compensation. Another approach uses general-purpose digital FIR filtering for compensation. However, achieving high-precision compensation requires extremely high-order filters, consuming significant FPGA multiplier resources and making it unsuitable for FPGA implementation in miniaturized measurement instruments.

[0004] Therefore, there is a need for an in-band flatness compensation method for a miniaturized broadband signal generator based on FPGA that can improve the in-band flatness compensation accuracy and reduce filtering time. Summary of the Invention

[0005] The main purpose of the present invention is to provide a method for in-band flatness compensation of a miniaturized broadband signal generator based on FPGA, so as to solve the problems of low in-band flatness compensation accuracy and long filtering time in the prior art.

[0006] To achieve the above object, the present invention provides a method for compensating for in-band flatness of a miniaturized broadband signal generator based on an FPGA, which specifically comprises the following steps:

[0007] S1, split the signal bandwidth to be compensated into a set of sub-bands covering the entire bandwidth.

[0008] S2, channel frequency response H measured by vector network analyzer VNA chan (ω k ) is inverted to obtain the filter frequency response.

[0009] S3, obtaining the coefficient group of the complex coefficient filter by the maximum likelihood method.

[0010] S4, storing the center frequency and the coefficient group of the complex coefficient filter in the coefficient register, and performing in-phase component compensation filtering and orthogonal component compensation filtering to complete the full compensation band flatness compensation.

[0011] Furthermore, step S1 divides the signal bandwidth to be compensated into a set of sub-bands covering the entire bandwidth, specifically:

[0012]

[0013] Wherein, BW is the bandwidth of the broadband signal to be compensated; BW i is the i-th sub-band, and L is the total number of sub-bands.

[0014] Furthermore, step S2 is specifically as follows:

[0015] S2.1, set the ideal frequency response to D(ω k ):

[0016]

[0017] Where τ0 is the average group delay.

[0018] S2.2, filter frequency response H vmcp (ω k ) is obtained by directly inverting:

[0019]

[0020] in, is the channel measurement frequency sampling point phase, N is the filter order, ω k is the angular frequency of the measurement frequency sampling point.

[0021] Furthermore, step S3 specifically includes the following steps:

[0022] S3.1, calculate the filter coefficients so that Established, where h n is the filter coefficient, and M is the number of channel frequency response sampling points.

[0023] S3.2, yes h n Component-wise partial derivative equation, we get:

[0024]

[0025] S3.3, use the maximum likelihood method to estimate the coefficient matrix A and then obtain the filter coefficient h:

[0026]

[0027] where ω1, ω2, ..., ω M is the angular frequency corresponding to the M measurement frequency sampling points, and N is the filter order.

[0028] Furthermore, in step S3.3 It is the coefficient matrix related to the filter order and the measurement frequency sampling point.

[0029] Furthermore, step S4 is specifically as follows:

[0030] The in-phase component compensation filtering is:

[0031]

[0032] The quadrature component compensation filtering is:

[0033]

[0034] Among them, "*" is the convolution operator symbol, is the complex coefficient h of the compensation filter of the ith sub-band i The real part of is the complex coefficient h of the compensation filter of the ith sub-band i The real part of I in is the in-phase component of the input signal, Q in is the quadrature component of the input signal, is the compensation filtering result of the in-phase component of the i-th sub-band, is the compensation filtering result of the orthogonal component of the i-th sub-band

[0035] The present invention has the following beneficial effects:

[0036] Compared with the currently used digital FIR intermediate frequency filtering method, the present invention optimizes the filter design method, reduces the difficulty of coefficient calculation, reduces the amount of calculation, and improves the calculation speed. While improving the compensation accuracy, it saves a large amount of multiplier resources, allowing miniaturized products to achieve flatness compensation for broadband and even ultra-wideband signals on ordinary FPGA chips, thereby reducing product costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0038] Figure 1 The present invention shows a flow chart of a method for compensating for in-band flatness of a miniaturized broadband signal generator based on FPGA.

[0039] Figure 2 The figure shows the effect of performing repetition filter compensation using the method provided by the present invention.

[0040] Figure 3 A comparison diagram before and after performing in-band flatness compensation using the method provided by the present invention is shown. DETAILED DESCRIPTION

[0041] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0042] like Figure 1 The method for compensating the flatness of a miniaturized broadband signal generator based on an FPGA specifically includes the following steps:

[0043] S1, split the signal bandwidth to be compensated into a set of sub-bands covering the entire bandwidth.

[0044] S2, channel frequency response H measured by vector network analyzer VNA chan (ω k ) is inverted to obtain the filter frequency response.

[0045] S3, obtaining the coefficient group of the complex coefficient filter by the maximum likelihood method.

[0046] S4, storing the center frequency and the coefficient group of the complex coefficient filter in the coefficient register, and performing in-phase component compensation filtering and orthogonal component compensation filtering to complete the full compensation band flatness compensation.

[0047] The host computer stores the estimated complex coefficient group of the compensation filter in the coefficient register, uses the sub-band center frequency as the pointer to address the coefficient register, and updates the filter coefficient in time to make the filter frequency response more consistent with the channel frequency response; during filtering, I im , Q in Corresponding to the real part and imaginary part of the filter and cross-filtering respectively, and then synthesizing them to output the final filtering compensation result.

[0048] Specifically, step S1 divides the signal bandwidth to be compensated into a set of sub-bands covering the entire bandwidth, and then integrates the results after processing to achieve a global high-precision processing effect.

[0049]

[0050] Wherein, BW is the bandwidth of the broadband signal to be compensated; BW i is the i-th sub-band, and L is the total number of sub-bands.

[0051] Specifically, step S2 is as follows:

[0052] S2.1, set the ideal frequency response to D(ω k ):

[0053]

[0054] Where τ0 is the average group delay.

[0055] S2.2, filter frequency response H vmcp (ω k ) is obtained by directly inverting:

[0056]

[0057] in, is the channel measurement frequency sampling point phase, N is the filter order, ω k is the angular frequency of the measurement frequency sampling point.

[0058] Specifically, step S3 includes the following steps:

[0059] S3.1, calculate the filter coefficients so that Established, where h n is the filter coefficient, and M is the number of channel frequency response sampling points.

[0060] To find the filter coefficient, we need Ask for h n The partial derivative of .

[0061] S3.2, yes h n Component-wise partial derivative equation, we get:

[0062]

[0063] S3.3, use the maximum likelihood method to estimate the coefficient matrix A and then obtain the filter coefficient h:

[0064]

[0065] where ω1, ω2, ..., ω M is the angular frequency corresponding to the M measurement frequency sampling points, and N is the filter order. Matrix operation is used to design filters, which effectively avoids tedious iterative calculations, improves calculation speed and reduces the amount of calculations.

[0066] Specifically, in step S3.3 It is the coefficient matrix related to the filter order and the measurement frequency sampling point.

[0067] Specifically, the filter uses a polyphase structure in which coefficients are pre-stored and addressed and read during operation, and the in-phase and quadrature components correspond to the real and imaginary parts of the coefficients respectively and cross-filter. Step S4 is specifically as follows:

[0068] The in-phase component compensation filtering is:

[0069]

[0070] The quadrature component compensation filtering is:

[0071]

[0072] Among them, "*" is the convolution operator symbol, is the complex coefficient h of the compensation filter of the ith sub-band i The real part of is the complex coefficient h of the compensation filter of the ith sub-band i The real part of I in is the in-phase component of the input signal, Q in is the quadrature component of the input signal, is the compensation filtering result of the in-phase component of the i-th sub-band, is the compensation filtering result of the orthogonal component of the i-th sub-band.

[0073] The host computer pre-stores the estimated complex coefficient group of the compensation filter in the coefficient register. As the signal bandwidth is extended, the sub-band is recursively pushed, the center frequency is shifted, the coefficient register address is incremented, and the filter coefficient is updated accordingly, so that the filter frequency response is more consistent with the channel frequency response. During filtering, I in Filter with the real part and imaginary part of the filter respectively, and Q in The real and imaginary parts of the filter are also filtered separately to output the final filter compensation result. Step S4 uses the sub-band center frequency as a pointer to address the coefficient register, and updates the filter coefficient in a timely manner following the migration of the center frequency. The in-phase and quadrature components of the signal are subjected to quasi-polyphase filtering in real time with the real and imaginary parts of the updated filter coefficients, that is, corresponding terms and cross-term filtering are performed separately to complete the full compensation band flatness compensation, improve the flatness compensation accuracy, reduce the consumption of FPGA multiplier resources, and reduce product cost.

[0074] The solution provided by the present invention is used to compensate the in-band flatness of a 120MHz bandwidth spectrum analyzer. 241 multi-tone signals with the same amplitude and interval of 0.5MHz pass through the channel. Affected by the in-band frequency response of the channel, the signal power is as follows: Figure 2 In the middle blue graph, the flatness of the signal power band is as follows Figure 3 Medium blue graph; This technical solution is used to compensate for the in-band signal flatness, and the signal power is as follows Figure 2The red graph in the figure shows the flatness of the signal power band. Figure 3 The red graphic in the

[0075] The present invention innovatively adopts a filtering compensation method based on complex coefficients. Table 1 shows the in-band flatness before and after compensation.

[0076] Table 1 In-band flatness before and after compensation

[0077] Maximum value / dBm Minimum value / dBm Maximum fluctuation value / dBm Before compensation 0.2818 -1.8627 2.1445 After compensation -0.0960 -0.2131 0.1171

[0078] The full-band passband capability of complex-coefficient filters expands the compensation bandwidth. During filter implementation, a novel polyphase-like FPGA structure with variable coefficients is proposed. This reduces the order of the compensation filter, enabling implementation with a limited number of FPGA multiplier resources. This improves the accuracy of in-band flatness compensation, reduces costs, and shortens filtering time. In summary, the solution provided by the present invention effectively achieves high-precision in-band flatness compensation for broadband signals while consuming a small amount of FPGA multiplier resources.

[0079] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A method for compensating for in-band flatness of a miniaturized broadband signal generator based on FPGA, characterized in that: The specific steps include: S1, split the signal bandwidth to be compensated into a set of sub-bands covering the entire bandwidth; S2, channel frequency response H measured by vector network analyzer VNA chan (ω k ) Inverse to obtain the filter frequency response; S3, obtaining the coefficient group of the complex coefficient filter by the maximum likelihood method; S4, storing the center frequency and the coefficient group of the complex coefficient filter in the coefficient register, and performing in-phase component compensation filtering and orthogonal component compensation filtering to complete the full compensation band flatness compensation.

2. The method for compensating for in-band flatness of a miniaturized broadband signal generator based on FPGA according to claim 1, wherein: Step S1 divides the signal bandwidth to be compensated into a set of sub-bands covering the entire bandwidth, specifically: Wherein, BW is the bandwidth of the broadband signal to be compensated; BW i is the i-th sub-band, and L is the total number of sub-bands.

3. The method for compensating for in-band flatness of a miniaturized broadband signal generator based on FPGA according to claim 1, wherein: Step S2 is specifically as follows: S2.1, set the ideal frequency response to D(ω k ): Where τ0 is the average group delay; S2.2, filter frequency response H comp (ω k ) is obtained by directly inverting: in, is the channel measurement frequency sampling point phase, N is the filter order, ω k is the angular frequency of the measurement frequency sampling point.

4. The method for compensating for in-band flatness of a miniaturized broadband signal generator based on FPGA according to claim 1, wherein: Step S3 specifically includes the following steps: S3.1, calculate the filter coefficients so that Established, where h n is the filter coefficient, M is the number of channel frequency response sampling points; S3.2, yes h n Component-wise partial derivative equation, we get: S3.3, use the maximum likelihood method to estimate the coefficient matrix A and then obtain the filter coefficient h: where ω1, ω2, ..., ω M is the angular frequency corresponding to the M measurement frequency sampling points, and N is the filter order.

5. The method for compensating for in-band flatness of a miniaturized broadband signal generator based on FPGA according to claim 4, wherein: In step S3.3 It is the coefficient matrix related to the filter order and the measurement frequency sampling point.

6. The method for compensating for in-band flatness of a miniaturized broadband signal generator based on FPGA according to claim 1, wherein: Step S4 is specifically as follows: The in-phase component compensation filtering is: The quadrature component compensation filtering is: Among them, "*" is the convolution operator symbol, is the complex coefficient h of the compensation filter of the ith sub-band i The real part of is the complex coefficient h of the compensation filter of the ith sub-band i The real part of I in is the in-phase component of the input signal, Q in is the quadrature component of the input signal, is the compensation filtering result of the in-phase component of the i-th sub-band, is the compensation filtering result of the orthogonal component of the i-th sub-band.

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