Synchronous acquisition and processing method and device of phased array system and electronic equipment

Abstract

The invention relates to the technical field of communication engineering, and discloses a synchronous acquisition and processing method of a phased array system, and the phased array system comprises a plurality of acquisition channels. Performing delay synchronization on each acquisition channel to achieve a preliminary synchronization state; when the acquisition channels reach the initial synchronization state and further phase synchronization needs to be carried out, inter-channel phase synchronization is carried out on the acquisition channels; aiming at the first synchronization consistency requirement, on the basis of enabling each acquisition channel to reach a preliminary synchronization state through delay synchronization, executing a first phase synchronization operation to reach a first phase synchronization state; and aiming at a second synchronization consistency requirement, on the basis of enabling each acquisition channel to reach a preliminary synchronization state through delay synchronization, executing a second phase synchronization operation so as to reach a second phase synchronization state. The method has the beneficial effects that targeted synchronous operation can be carried out on the acquisition channels, and the synchronization degree among the acquisition channels in the phased array system is remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of electronic and communication engineering technology, and in particular to a synchronous acquisition and processing method, device and electronic equipment for a phased array system. Background Art

[0002] To improve the accuracy of observations in fields such as radio astronomy, radar, ultrasonic imaging, and meteorological detection, conventional techniques typically increase the number of acquisition channels and synchronize signal reception and transmission across multiple channels to increase the amount of data collected and enhance the quality of the acquired signals. A phased array system is an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array to achieve precise control of electromagnetic wave transmission and reception. The number of acquisition channels within a phased array system can range from dozens to thousands, deployed on different acquisition boards. The synchronization between acquisition channels determines the accuracy of observations. However, in practice, synchronization between acquisition channels is affected by multiple factors, and a single synchronization solution cannot be suitable for all application scenarios.

[0003] In related technologies, the technical solutions for synchronous processing of phased array systems still need to be improved in terms of their pertinence to application scenarios. Summary of the Invention

[0004] The present application provides a synchronous acquisition and processing method, apparatus, and electronic equipment for a phased array system. According to the application scenario and corresponding synchronization consistency requirements of each acquisition channel in the phased array system, corresponding channel synchronization operations are performed on each acquisition channel, thereby enabling targeted synchronization operations on the acquisition channels and significantly improving the degree of synchronization between the acquisition channels in the phased array system.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, an embodiment of the present application provides a synchronous acquisition and processing method for a phased array system, wherein the phased array system includes multiple acquisition channels; the method comprises: Performing delayed synchronization on each acquisition channel so that all acquisition channels of the phased array system reach a preliminary synchronization state; When each acquisition channel reaches the preliminary synchronization state and needs further phase synchronization, inter-channel phase synchronization is performed on each acquisition channel; wherein: For the first synchronization consistency requirement, on the basis of enabling each acquisition channel to reach the preliminary synchronization state through the delayed synchronization, performing a first phase synchronization operation so that each acquisition channel reaches a first phase synchronization state corresponding to the first synchronization consistency requirement; In response to the second synchronization consistency requirement, on the basis of enabling each acquisition channel to reach the preliminary synchronization state through the delayed synchronization, a second phase synchronization operation is performed to enable each acquisition channel to reach the second phase synchronization state corresponding to the second synchronization consistency requirement; wherein, the second phase synchronization operation includes phase synchronization operation and iterative correction.

[0006] The synchronous acquisition and processing method for a phased array system proposed in the embodiment of the present application first performs delayed synchronization on each acquisition channel to ensure that the acquisition channels within the phased array system reach a preliminary synchronization state; and on this basis, for the acquisition channels that require further phase synchronization, corresponding phase synchronization operations are performed according to the synchronization consistency requirements, so that each acquisition channel reaches the phase synchronization state corresponding to the synchronization consistency requirements. Compared with related technologies, the present application determines the synchronization operation to be adopted based on the application scenario of each acquisition channel and the corresponding synchronization consistency requirements, and realizes targeted synchronization processing of the acquisition channels. This not only effectively reduces the synchronization cost consumed by the synchronization process of the phased array system and improves the synchronization efficiency, but also significantly improves the degree of synchronization between the acquisition channels, providing a reliable synchronization foundation for the application of the phased array system.

[0007] Optionally, the first phase synchronization operation is performed by the following steps: Calculating the phase information of each acquisition channel, and calculating the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel; Determine the channel phase adjustment value corresponding to each acquisition channel according to the inter-channel phase difference; The channel phase adjustment value is used to update the NCO initial phase of each acquisition channel to complete the first phase synchronization operation.

[0008] Optionally, the second phase synchronization operation is performed by the following steps: Calculating the phase information of each acquisition channel, and calculating the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel; Determining whether the inter-channel phase difference converges; If converged, ending the iterative correction process of the second phase synchronization operation; If convergence does not occur, determine the channel phase adjustment value corresponding to each acquisition channel based on the inter-channel phase difference; use the channel phase adjustment value to update the NCO initial phase of each acquisition channel; repeat the above steps of calculating phase information, inter-channel phase difference and convergence judgment until the inter-channel phase difference of each acquisition channel reaches a converged state.

[0009] Optionally, performing delay synchronization on each acquisition channel includes: Calculating the delay values ​​of the acquisition channels and unifying the delay values ​​of the acquisition channels to obtain a unified delay value; Delay configuration is performed on each acquisition channel according to the unified delay value to complete delay synchronization of each acquisition channel.

[0010] Optionally, the phased array system includes a timing control board, a frequency synthesis board, and an acquisition board; the timing control board is connected to the acquisition board via a first connection cable, and all first connection cables are required to be phase-stable and strictly of equal length; The frequency synthesis board is connected to the timing control board and the acquisition board through second connection cables. All second connection cables are required to be phase-stable and strictly of equal length.

[0011] Optionally, the frequency synthesis board sends a homologous, highly stable, and coherent reference clock signal to the timing control board and the acquisition board; the acquisition board includes the multiple acquisition channels; and the method further includes: Using the reference clock signal as a clock reference, a synchronization control pulse signal is sent to the acquisition board through the timing control board to trigger the phased array system to perform subsequent synchronization preprocessing of the signal.

[0012] Optionally, when the acquisition channel reaches a preset synchronization state, the synchronization process of the phased array system is ended, and the preset synchronization state includes the preliminary synchronization state; The acquisition board adopts a first type of board, which does not have a digital quadrature demodulation function, and the acquisition channels in the first type of board do not need to be further phase synchronized; The number of the first type of boards is N, where N is a positive integer.

[0013] Optionally, when the acquisition channel reaches a preset synchronization state, the synchronization process of the phased array system is ended, the preset synchronization state includes the preliminary synchronization state and a target phase synchronization state; the target phase synchronization state is a first phase synchronization state or a second phase synchronization state; The acquisition board adopts a second type of board, which has a digital quadrature demodulation function. The phase difference between the acquisition channels in the second type of board has not converged, and further phase synchronization is required. The number of the second type of boards is N, where N is a positive integer.

[0014] In a second aspect, an embodiment of the present application provides a synchronous acquisition and processing device for a phased array system, wherein the phased array system includes multiple acquisition channels; the device includes: A delay synchronization module is used to perform delay synchronization on each acquisition channel so that all acquisition channels of the phased array system reach a preliminary synchronization state; The inter-channel phase synchronization module is used to perform inter-channel phase synchronization on each acquisition channel when each acquisition channel reaches the preliminary synchronization state and needs further phase synchronization; wherein: a first phase synchronization unit, configured to, based on a first synchronization consistency requirement, perform a first phase synchronization operation so that each acquisition channel reaches a first phase synchronization state corresponding to the first synchronization consistency requirement, on the basis of enabling each acquisition channel to reach the preliminary synchronization state through the delayed synchronization; The second phase synchronization unit is used to perform a second phase synchronization operation based on the second synchronization consistency requirement, so that each acquisition channel reaches the second phase synchronization state corresponding to the second synchronization consistency requirement through the delayed synchronization; wherein the second phase synchronization operation includes phase synchronization operation and iterative correction.

[0015] In a third aspect, an embodiment of the present application provides an electronic device comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the method described in any one of the above embodiments by executing the computer instructions.

[0016] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to enable a computer to execute any one of the methods in the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1a A schematic diagram of a usage scenario of the synchronous acquisition and processing method for a phased array system provided in an embodiment of the present application; Figure 1b A diagram showing the steps of a synchronous acquisition and processing method for a phased array system provided in an embodiment of the present application; Figure 2 Schematic diagram of a synchronous control pulse signal including a synchronous pulse in an embodiment of the present application; Figure 3 This is a step diagram of the first phase synchronization operation in an embodiment of the present application; Figure 4 Schematic diagram of a synchronous control pulse signal including a phase sampling pulse in an embodiment of the present application; Figure 5 This is a step diagram of the second phase synchronization operation in an embodiment of the present application; Figure 6 This is a diagram of the steps of delay synchronization in an embodiment of the present application; Figure 7a This is a structural block diagram of the phased array system in an embodiment of the present application; Figure 7b This is a hardware block diagram of the frequency synthesis board in the embodiment of the present application; Figure 7c This is a hardware block diagram of the timing control board in an embodiment of the present application; Figure 8 This is a clock tree structure diagram on the acquisition board in the embodiment of the present application; Figure 9 Schematic diagram of a synchronous control pulse signal including a reset pulse in an embodiment of the present application; Figure 10 A module diagram of a synchronous acquisition and processing device for a phased array system provided in an embodiment of the present application; Figure 11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0020] To improve observation accuracy in fields such as radio astronomy, radar, ultrasonic imaging, and meteorological detection, conventional techniques typically increase the number of acquisition channels and synchronize signal reception and transmission across multiple channels to increase the amount of collected data and enhance signal quality. A phased array system is an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array to achieve precise control of electromagnetic wave transmission and reception. The number of acquisition channels within a phased array system can range from dozens to thousands, deployed on different acquisition boards. The synchronization between these channels determines the accuracy of observations. However, in practice, synchronization between acquisition channels is affected by multiple factors, and a single synchronization solution is not suitable for all application scenarios. The adaptability of synchronization solutions for phased array systems still needs to be improved.

[0021] Based on the above problems, the present application provides a synchronous acquisition and processing method for a phased array system, wherein the phased array system includes multiple acquisition channels; delayed synchronization is performed on each acquisition channel; when each acquisition channel reaches a preliminary synchronization state and needs further phase synchronization, inter-channel phase synchronization is performed on each acquisition channel; wherein: for a first synchronization consistency requirement, on the basis of enabling each acquisition channel to reach a preliminary synchronization state through delayed synchronization, a first phase synchronization operation is performed so that each acquisition channel reaches a first phase synchronization state; for a second synchronization consistency requirement, on the basis of enabling each acquisition channel to reach a preliminary synchronization state through delayed synchronization, a second phase synchronization operation is performed so that each acquisition channel reaches a second phase synchronization state.

[0022] This application also provides an embodiment of a synchronous acquisition and processing method for a phased array system. The usage scenario diagram of this embodiment is shown in FIG. Figure 1aAs shown. This embodiment is applicable to a phased array system, which includes a timing control board, an acquisition board, and a frequency synthesis board. The timing control board sends the synchronization control pulse signal to each RFSoC board via an SMA cable. All cables are required to be phase-stable, that is, the phase is stable, and the cables are strictly equal in length. The frequency synthesis board sends the same source and coherent 10MHz reference clock to each RFSoC board and the timing control board via an SMA cable. All cables are required to be phase-stable, that is, the phase is stable, and the cables are strictly equal in length. The PS end of the timing control board is also connected to the host computer via a gigabit network port. Figure 1a The dotted box in the figure represents the synchronization process performed on the acquisition board.

[0023] First, power on the phased array system for initialization. The frequency synthesizer board, without requiring a program to be loaded, continuously outputs a 10MHz reference clock signal, providing a highly stable, homogeneous, and coherent clock signal for the acquisition boards and timing control board. Each acquisition board performs its own initialization process, including program loading and clock module configuration. The timing control board also loads a program to complete power-on initialization.

[0024] Next, a synchronization calibration command is sent to the phased array system via the host computer. Upon receiving the synchronization calibration command, the PS terminal of the timing control board sends a synchronization control pulse signal to each acquisition board. Upon receiving the synchronization calibration command via the Gigabit Ethernet port, the PS terminal of each acquisition board initiates the synchronization process, calculates the delay value for each acquisition channel, and sends the delay value for all channels to the timing control board. The timing control board collects the delay values ​​of all acquisition channels and unifies them to obtain a unified delay value, recorded as T_total. The timing control board then sends this unified delay value to each acquisition board. Each acquisition board then configures the delay for each acquisition channel based on the received unified delay value, thereby achieving delay synchronization.

[0025] Next, the PL side of each acquisition board receives the synchronization control pulse signal sent by the timing control board and analyzes it to generate trigger pulses, including synchronization pulses, reset pulses, and phase sampling pulses. The synchronization pulse ensures alignment of the clock edges output by each acquisition board. The reset pulse is used for synchronization processing after data output in the acquisition board's RFdc IP core. The phase sampling pulse triggers phase synchronization or adaptive calibration. It should be noted that there are three usage scenarios for phased array systems, defined by the phase convergence threshold. In the first scenario, the acquisition board lacks digital functionality, and the phased array system performs demodulation on the analog side. This scenario has minimal requirements for channel synchronization consistency and only requires delay synchronization. In the second scenario, the acquisition board has digital functionality, and the phased array system performs digital quadrature demodulation on the acquisition board. This scenario has moderate requirements for channel synchronization consistency and, in addition to delay synchronization, requires phase synchronization, but does not require iterative phase correction. In the third usage scenario, the acquisition board has digital functions, and the phased array system performs digital orthogonal demodulation on the acquisition board. This usage scenario has the most stringent requirements for channel synchronization consistency. In addition to delay synchronization, phase synchronization is also required, and the phase needs to be iteratively corrected multiple times until the phase between the acquisition channels reaches a convergence state.

[0026] For example, the inter-channel phase convergence threshold for the first usage scenario may be 30°, and the synchronization process is completed when the inter-channel phase difference is less than 30°. The inter-channel phase convergence threshold for the second usage scenario may be 20°, and the synchronization process is completed when the inter-channel phase difference is less than 20°. The inter-channel phase convergence threshold for the third usage scenario may be 2°, and the synchronization process is completed when the inter-channel phase difference is less than 2°.

[0027] Phase synchronization can involve a single calculation and adjustment of the inter-channel phase difference, suitable for the second scenario. Each acquisition card's PS side calculates the phase information for each acquisition channel and sends it to the timing control board. The timing control board collects phase information from all channels in the phased array system and, based on the phase information of a selected reference channel, calculates the inter-channel phase difference. The resulting channel phase adjustment values ​​are then sent to each acquisition card. Based on the received channel phase adjustment values, the PS side of each acquisition card configures the initial phase update delay for each channel's NCO, completing the synchronization process for this scenario.

[0028] Phase-adaptive calibration can involve multiple iterations of inter-channel phase difference calculation and adjustment to keep the inter-channel phase difference within a preset range, thereby achieving phase convergence. Phase-adaptive calibration is applicable to the third use case. The PS side of each acquisition board calculates the phase information of each acquisition channel and sends it to the timing control board. The timing control board collects phase information from all channels in the phased array system and, based on the phase information of a selected reference channel, calculates the inter-channel phase difference. It then determines whether the inter-channel phase difference has converged. If so, phase-adaptive calibration ends. If not, it calculates a channel phase adjustment value based on the inter-channel phase difference and sends it to each acquisition board. The PS side of each acquisition board updates the initial NCO phase of each channel based on the received channel phase adjustment value. After the update, it recalculates the phase information of each acquisition channel and sends it to the timing control board. The timing control board collects phase information from all channels in the phased array system and, based on the phase information of a selected reference channel, calculates the inter-channel phase difference. It then determines whether the inter-channel phase difference has converged. Repeat the above process until the phase difference between channels converges.

[0029] The synchronous acquisition and processing method for a phased array system provided in the present application first performs delayed synchronization on each acquisition channel to ensure that the acquisition channels in the phased array system reach a preliminary synchronization state. On this basis, for acquisition channels that require further phase synchronization, corresponding phase synchronization operations are performed according to synchronization consistency requirements, so that each acquisition channel reaches a phase synchronization state corresponding to the synchronization consistency requirements.

[0030] Compared with related technologies, the present application judges the synchronization operation to be adopted according to the application scenario of each acquisition channel and the corresponding synchronization consistency requirements, and realizes targeted synchronization processing of the acquisition channels. It not only effectively reduces the synchronization cost consumed by the synchronization process of the phased array system and improves the synchronization efficiency, but also significantly improves the synchronization degree between the acquisition channels, providing a reliable synchronization foundation for the application of the phased array system.

[0031] The synchronous acquisition and processing method for a phased array system provided in this specification can be applied within a phased array system, which can be used in a variety of fields, including radio astronomy, radar, ultrasonic detection and imaging, and meteorological detection. In radio astronomy, the phased array system can be used to construct a phased array radio telescope, enabling high-speed, real-time, synchronous acquisition and preprocessing of large-scale, wide-band radio frequency signals. It is understood that, after adaptive modification, the synchronous acquisition and processing method for a phased array system provided in this specification can also be used to synchronously process other devices that acquire signals through multiple channels.

[0032] According to an embodiment of the present application, an embodiment of a method for synchronous acquisition and processing of a phased array system is provided. It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system, such as a set of computer-executable instructions, and although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown.

[0033] In this embodiment, a synchronous acquisition and processing method for a phased array system is provided, which can be used for the above-mentioned phased array system. Figure 1b As shown, the phased array system includes multiple acquisition channels; the method includes: S100. Delay synchronization is performed on each acquisition channel so that all acquisition channels of the phased array system reach a preliminary synchronization state.

[0034] S200. When each acquisition channel reaches a preliminary synchronization state and further phase synchronization is required, inter-channel phase synchronization is performed on each acquisition channel; wherein: S300. Based on the first synchronization consistency requirement, after each acquisition channel reaches a preliminary synchronization state through delayed synchronization, a first phase synchronization operation is performed to enable each acquisition channel to reach a first phase synchronization state corresponding to the first synchronization consistency requirement.

[0035] S400. In response to the second synchronization consistency requirement, on the basis of enabling each acquisition channel to reach a preliminary synchronization state through delayed synchronization, a second phase synchronization operation is performed to enable each acquisition channel to reach a second phase synchronization state corresponding to the second synchronization consistency requirement; wherein, the second phase synchronization operation includes phase synchronization operation and iterative correction.

[0036] The initial synchronization state can be a state where all acquisition channels within the phased array system are configured with the same delay value, ensuring that the acquisition channels are time-aligned and improving the timing synchronization of the phased array system during signal acquisition and processing. It is understood that after reaching the initial synchronization state, the acquired signals in each acquisition channel can simultaneously enter the ready-to-output state after the same delay value, thereby achieving synchronous output of multiple signals in the phased array system and significantly improving synchronization within the phased array system.

[0037] The first and second synchronization consistency requirements may be different synchronization thresholds for the synchronization consistency of each acquisition channel in a phased array system, where the synchronization threshold of the second synchronization consistency requirement may be higher than that of the first synchronization consistency requirement. In some embodiments, in addition to the first and second synchronization consistency requirements, a third synchronization consistency requirement may be provided, and the synchronization threshold of the third synchronization consistency requirement may be lower than that of the first synchronization consistency requirement. To illustrate the difference between the multiple synchronization consistency requirements, based on the clock cycle of the acquisition signal, the synchronization error between each acquisition channel is divided into an integer part comprising a complete clock cycle and a fractional part comprising a partial clock cycle. The first and second synchronization consistency requirements may focus on the fractional part of the synchronization error, while the third synchronization consistency requirement may focus on the integer part of the synchronization error. In some cases, the phase difference between the acquisition channels can directly meet the synchronization threshold of the third synchronization consistency requirement. For example, the synchronization threshold of the first synchronization consistency requirement may be a 20° inter-channel phase difference, the synchronization threshold of the second synchronization consistency requirement may be a 3° inter-channel phase difference, and the synchronization threshold of the third synchronization consistency requirement may be a 30° inter-channel phase difference.

[0038] The first phase synchronization operation may be a phase synchronization operation performed on each acquisition channel in accordance with a first synchronization consistency requirement, so that each acquisition channel reaches a first phase synchronization state. The first phase synchronization state may be a state in which all acquisition channels in a phased array system have the same phase, ensuring that each acquisition channel is aligned in phase. The degree of synchronization between the acquisition channels in the first phase synchronization state corresponds to a synchronization threshold of the first synchronization consistency requirement. Similarly, the second phase synchronization operation may be a phase synchronization operation performed on each acquisition channel in accordance with a second synchronization consistency requirement, so that each acquisition channel reaches a second phase synchronization state. The second phase synchronization state may be a state in which all acquisition channels in a phased array system have the same phase, ensuring that each acquisition channel is aligned in phase. The degree of synchronization between the acquisition channels in the second phase synchronization state corresponds to a synchronization threshold of the second synchronization consistency requirement.

[0039] Specifically, before starting the synchronization process for the phased array system, the system is powered on and initialized to ensure that it can operate normally and is ready for synchronization. After the power-on initialization is completed, a synchronization calibration command is sent to the system via the host computer to start the synchronization process for the phased array system.

[0040] It should be noted that multiple acquisition channels within a phased array system can be integrated onto one or more acquisition boards. Each acquisition board uses a single clock chip to construct a synchronous clock tree. Multiple clock signals sent within the synchronous clock tree synchronize the acquisition channels on the acquisition board. Therefore, the synchronicity between multiple clock signals within the synchronous clock tree has a significant impact on the synchronization process. For these reasons, within a phased array system, a synchronization control pulse signal containing synchronization pulses is sent to the acquisition board. These synchronization pulses trigger the clock chip on the acquisition board to synchronously reset the clock chip's multiple output pins, ensuring that the clock chip can synchronously output multiple clock signals, improving the synchronicity between the multiple clock signals, and providing a synchronization signal foundation for subsequent synchronization processes.

[0041] The synchronous control pulse signal may be a pulse signal containing different types of trigger pulses, which is used to trigger each acquisition channel to control each acquisition channel to perform synchronous processing, wherein different types of trigger pulses may correspond to different pulse widths. Figure 2 As shown, the synchronization pulse can be a trigger pulse whose pulse width meets the third pulse width condition. The third pulse width condition corresponds to a pulse width of 3 clock cycles. After receiving the synchronization pulse, the acquisition board triggers the clock chip to perform clock synchronization reset.

[0042] Furthermore, the synchronization error between the acquisition channels may include a delay error and a phase error, wherein the delay error may be the integer error that constitutes the synchronization error, and the phase error may be the fractional error that constitutes the synchronization error. It is understood that in order to minimize the synchronization error between the acquisition channels and improve the synchronization between the acquisition channels, delay synchronization of the acquisition channels is required under any synchronization consistency requirement to eliminate the impact of the delay error on the synchronization between the acquisition channels.

[0043] After the clock chip on the acquisition board is able to synchronously output multiple clock signals, it sends a synchronous analog-to-digital clock signal and a synchronous logic clock signal to each acquisition channel on the acquisition board through the clock chip. This delay synchronization is achieved through the synchronous analog-to-digital clock signal and the synchronous logic clock signal, ensuring that all acquisition channels on each acquisition board are configured with the same delay value, eliminating timing deviations between the acquisition channels, and achieving preliminary synchronization for all acquisition channels in the phased array system. It should be noted that both the synchronous analog-to-digital clock signal and the synchronous logic clock signal can be low-frequency clock signals. The synchronous analog-to-digital clock signal is used to align the clocks of the analog signal portion of the acquisition board, while the synchronous logic clock signal is used to align the clocks of the programmable logic portion of the acquisition board. Both the synchronous analog-to-digital clock signal and the synchronous logic clock signal have the same clock frequency, and the phase relationship between them is constant.

[0044] Furthermore, based on the initial synchronization state achieved by all acquisition channels, a determination is made as to whether each acquisition channel meets the synchronization consistency requirements corresponding to the current application scenario. If the current application scenario corresponds to the third synchronization consistency requirement, then each acquisition channel has achieved the required synchronization level for the current application scenario, and synchronization processing of the phased array system can be stopped. If the current application scenario corresponds to the first or second synchronization consistency requirement, and the synchronization states corresponding to the first and second synchronization consistency requirements also include corresponding phase synchronization states, then each acquisition channel has not achieved the required synchronization level for the current application scenario, and further phase synchronization is required.

[0045] When the current application scenario corresponds to the first synchronization consistency requirement, based on the first synchronization consistency requirement, a first phase synchronization operation is performed on each acquisition channel that has reached the preliminary synchronization state to align the acquisition channels in phase and eliminate the phase difference between the acquisition channels, so that each acquisition channel reaches the first phase synchronization state corresponding to the first synchronization consistency requirement.

[0046] When the current application scenario corresponds to the second synchronization consistency requirement, a second phase synchronization operation is performed on each acquisition channel that has reached the preliminary synchronization state, in accordance with the second synchronization consistency requirement, to align the phases of the acquisition channels, eliminate phase differences between the acquisition channels, and enable each acquisition channel to reach the second phase synchronization state corresponding to the second synchronization consistency requirement. The second phase synchronization operation includes a phase synchronization operation and iterative correction. It should be noted that, because the synchronization threshold of the second synchronization consistency requirement may be higher than the synchronization threshold of the first synchronization consistency requirement, after performing the phase synchronization operation on each acquisition channel, the acquisition channels may still not reach the second phase synchronization state corresponding to the second synchronization consistency requirement. Therefore, during the second phase synchronization operation, it is necessary to perform further iterative phase correction on each acquisition channel based on the phase synchronization operation. By repeatedly performing phase correction on each acquisition channel, the degree of synchronization between the acquisition channels is gradually improved, allowing each acquisition channel to reach the second phase synchronization state, achieving the degree of synchronization required by the current application scenario.

[0047] The synchronous acquisition and processing method for a phased array system provided in this embodiment first performs delayed synchronization on each acquisition channel to ensure that the acquisition channels in the phased array system reach a preliminary synchronization state. On this basis, for acquisition channels that require further phase synchronization, corresponding phase synchronization operations are performed according to synchronization consistency requirements, so that each acquisition channel reaches a phase synchronization state corresponding to the synchronization consistency requirements.

[0048] Compared with related technologies, the present application judges the synchronization operation to be adopted according to the application scenario of each acquisition channel and the corresponding synchronization consistency requirements, and realizes targeted synchronization processing of the acquisition channels. It not only effectively reduces the synchronization cost consumed by the synchronization process of the phased array system and improves the synchronization efficiency, but also significantly improves the synchronization degree between the acquisition channels, providing a reliable synchronization foundation for the application of the phased array system.

[0049] Reference Figure 3 As shown, as an embodiment of the present application, the first phase synchronization operation is performed by the following steps: S310. Calculate the phase information of each acquisition channel, and calculate the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel.

[0050] S320. Determine the channel phase adjustment value corresponding to each acquisition channel according to the phase difference between the channels.

[0051] S330. Use the channel phase adjustment value to update the NCO initial phase of each acquisition channel to complete the first phase synchronization operation.

[0052] Specifically, a synchronous control pulse signal containing a phase sampling pulse is sent to the acquisition board in the phased array system, and all acquisition channels on the acquisition board are triggered by the phase sampling pulse, so that each acquisition channel can calculate and feed back its own phase information to serve as the data basis for the first phase synchronization operation. After the phase information of all acquisition channels in the phased array system is obtained by calculation, a selected reference channel is determined from all acquisition channels, and the phase information of the selected reference channel is used as a reference to calculate the phase difference between the remaining acquisition channels and the selected reference channel, thereby obtaining the inter-channel phase difference between each acquisition channel and the selected reference channel. Figure 4 As shown, the phase sampling pulse can be a trigger pulse whose pulse width meets the first pulse width condition. The first pulse width condition corresponds to a pulse width of 1 clock cycle. After receiving the phase sampling pulse, the acquisition board triggers each acquisition channel to calculate the phase information.

[0053] Furthermore, based on the inter-channel phase difference, a phase compensation calculation is performed on each acquisition channel to determine a corresponding channel phase adjustment value for each acquisition channel. It will be appreciated that the channel phase adjustment value is used to align the phase information of each acquisition channel with the phase information of the selected reference channel, reducing the phase difference between each acquisition channel and the selected reference channel, thereby improving phase synchronization between all acquisition channels.

[0054] Furthermore, the channel phase adjustment value is used to update the initial phase of the numerically controlled oscillator (NCO) of each acquisition channel. The updated NCO initial phase is then triggered to take effect by the synchronized analog-to-digital clock signal, completing the first phase operation. It should be noted that before using the synchronized analog-to-digital clock signal to trigger and take effect, it is necessary to ensure that each acquisition channel can synchronously receive the synchronized analog-to-digital clock signal to reduce synchronization errors caused when the synchronized analog-to-digital clock signal triggers each acquisition channel. For this reason, the clock signal receiver of each acquisition channel is disabled, and each acquisition channel is controlled to synchronously stop receiving the synchronized analog-to-digital clock signal. The mixing trigger source of each acquisition channel is set to the synchronized analog-to-digital clock signal. After the setting is completed, the clock signal receiver of each acquisition channel is enabled, and each acquisition channel is controlled to synchronously begin receiving the synchronized analog-to-digital clock signal. This allows the synchronized analog-to-digital clock signal to synchronously trigger each acquisition channel, improving synchronization during the first phase synchronization operation.

[0055] In some embodiments, the process of triggering the updated NCO initial phase to take effect by the synchronized analog-to-digital clock signal may include: each acquisition channel performing pulse detection on the received synchronized analog-to-digital clock signal, triggering each acquisition channel based on the rising edge of the pulse signal in the synchronized analog-to-digital clock signal, thereby activating the NCO initial phase in each acquisition channel. Simultaneously, the number of pulse signal cycles is determined based on the rising edge of the pulse signal in the synchronized analog-to-digital clock signal. After detecting at least two pulse signal cycles, the NCO initial phase is determined to have been activated, the triggering process is terminated, and the first phase synchronization operation is completed. It will be understood that at this point, the degree of synchronization between the acquisition channels meets the synchronization threshold of the first synchronization consistency requirement, and each acquisition channel has reached the first phase synchronization state corresponding to the first synchronization consistency requirement.

[0056] Reference Figure 5 As shown, as an embodiment of the present application, the second phase synchronization operation is performed by the following steps: S410. Calculate the phase information of each acquisition channel, and calculate the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel.

[0057] S420. Determine whether the phase difference between channels converges.

[0058] S430. If converged, end the iterative correction process of the second phase synchronization operation.

[0059] S440. If convergence does not occur, determine the channel phase adjustment value corresponding to each acquisition channel based on the inter-channel phase difference; use the channel phase adjustment value to update the NCO initial phase of each acquisition channel; repeat the above steps of calculating phase information, inter-channel phase difference and convergence judgment until the inter-channel phase difference of each acquisition channel reaches a converged state.

[0060] Specifically, within the phased array system, a synchronization control pulse signal containing a phase sampling pulse is sent to an acquisition board. This phase sampling pulse triggers all acquisition channels on the acquisition board, enabling each acquisition channel to calculate and feedback its own phase information, which serves as the data basis for the first phase synchronization operation. After calculating the phase information of all acquisition channels in the phased array system, a reference channel is determined from among all acquisition channels. Using the phase information of the selected reference channel as a reference, the phase differences between the remaining acquisition channels and the selected reference channel are calculated to obtain the inter-channel phase differences between each acquisition channel and the selected reference channel.

[0061] In this embodiment, to determine whether the degree of synchronization between the acquisition channels meets the synchronization threshold of the second synchronization consistency requirement, the inter-channel phase difference is compared with the synchronization threshold of the second synchronization consistency requirement, and based on the comparison result, it is determined whether the inter-channel phase difference has converged. If the inter-channel phase difference of each acquisition channel does not exceed the synchronization threshold of the second synchronization consistency requirement, it is determined that the inter-channel phase difference has converged, and each acquisition channel has reached the second phase synchronization state corresponding to the second synchronization consistency requirement, and the iterative correction process of the second phase synchronization operation ends.

[0062] If the inter-channel phase difference between acquisition channels exceeds the synchronization threshold required for the second synchronization consistency, the inter-channel phase difference is considered non-convergent, and iterative phase correction is required for each acquisition channel. Based on the inter-channel phase difference, a phase compensation calculation is performed for each acquisition channel to determine the corresponding channel phase adjustment value. The channel phase adjustment value is used to update the initial NCO phase of each acquisition channel. The updated NCO initial phase is triggered by the synchronous analog-to-digital clock signal, completing the NCO initial phase update process.

[0063] It should be noted that before using the synchronous analog-to-digital clock signal for triggering, it is necessary to ensure that each acquisition channel can synchronously receive the synchronous analog-to-digital clock signal to reduce the synchronization error caused by the synchronous analog-to-digital clock signal triggering each acquisition channel. For this reason, the clock signal receiver of each acquisition channel is turned off, and each acquisition channel is controlled to synchronously stop receiving the synchronous analog-to-digital clock signal. The mixing trigger source of each acquisition channel is set to the synchronous analog-to-digital clock signal. After the setting is completed, the clock signal receiver of each acquisition channel is turned on, and each acquisition channel is controlled to synchronously start receiving the synchronous analog-to-digital clock signal. This allows the synchronous analog-to-digital clock signal to synchronously trigger each acquisition channel, improving the synchronization during the second phase synchronization operation.

[0064] In some embodiments, the process of triggering the updated NCO initial phase to take effect by the synchronous analog-to-digital clock signal may include: each acquisition channel performing pulse detection on the received synchronous analog-to-digital clock signal, triggering each acquisition channel based on the rising edge of a pulse signal in the synchronous analog-to-digital clock signal, thereby activating the NCO initial phase in each acquisition channel. Simultaneously, the number of pulse signal cycles is determined based on the rising edge of the pulse signal in the synchronous analog-to-digital clock signal. After detecting at least two pulse signal cycles, it is determined that the NCO initial phase has been updated, and the triggering process is stopped.

[0065] After the NCO initial phase is updated, the phase information calculation process for each acquisition channel is iteratively executed to determine whether the inter-channel phase difference between each acquisition channel and the selected reference channel has converged. It should be understood that the reference channel selected in each iteration is the same acquisition channel. If the inter-channel phase difference has not converged, it is necessary to further calculate the channel phase adjustment value corresponding to each acquisition channel to iteratively correct the NCO initial phase for each acquisition channel.

[0066] The iterative correction process can be expressed as follows: Where i is the number of the acquisition channel; k is the number of iterations; is the initial phase of the NCO of the i-th acquisition channel in the k-th iteration round; is the initial phase of the NCO of the i-th acquisition channel in the k-1-th iteration round; is the channel phase adjustment value for the i-th acquisition channel in the k-th iteration. The channel phase adjustment value can be calculated based on the inter-channel phase difference in the current iteration. Based on the NCO initial phase of the previous iteration, the channel phase adjustment value is used to correct the NCO initial phase for the current iteration. This ensures that the phase information obtained after digital quadrature demodulation for the i-th acquisition channel is closer to the phase information of the selected reference acquisition channel. The NCO initial phase is updated based on the channel phase adjustment value to perform phase correction on each acquisition channel, reducing or eliminating the phase error between the acquisition channel and the selected reference channel. By repeatedly calculating phase information, calculating inter-channel phase differences, and determining convergence, the phase information of all acquisition channels is ultimately aligned, improving phase synchronization between acquisition channels.

[0067] It is understandable that in any iterative round, if it is determined that the phase difference between channels has converged and each acquisition channel has reached the second phase synchronization state corresponding to the second synchronization consistency requirement, the iterative correction process of the second phase synchronization operation can be ended.

[0068] Reference Figure 6 As shown, as an embodiment of the present application, delay synchronization of each acquisition channel includes: S210. Calculate the delay value of each acquisition channel, and unify the delay values ​​of each acquisition channel to obtain a unified delay value.

[0069] S220. Perform delay configuration on each acquisition channel according to the unified delay value to complete delay synchronization of each acquisition channel.

[0070] Specifically, each acquisition channel is controlled to synchronously receive a synchronous analog-to-digital clock signal and a synchronous logic clock signal. The synchronous analog-to-digital clock signal is used to align the analog signal portion of the acquisition board, and the synchronous logic clock signal is used to align the programmable logic portion of the acquisition board. After the clocks are aligned, the programmable logic portion of the acquisition board issues a delay calculation instruction to each acquisition channel to calculate the delay value for each acquisition channel.

[0071] Furthermore, the delay values ​​of each acquisition channel are unified to obtain a unified delay value. In some embodiments, if the delay values ​​of each acquisition channel are equal, it means that each acquisition channel has been synchronized in terms of timing. At this time, the delay value shared between each acquisition channel is used as the unified delay value to ensure that each acquisition channel is in a preliminary synchronization state through delay configuration, thereby completing the delay synchronization of each acquisition channel. If there are differences between the delay values ​​of each acquisition channel, it means that delay synchronization is needed to reduce the timing deviation between each acquisition channel. At this time, the delay values ​​of each acquisition channel are screened, and the maximum delay value is selected from all delay values ​​as the target delay value, and redundant design is performed based on the target delay value to obtain a unified delay value. Exemplarily, the redundant design can be to add multiple clock cycles on the basis of the target delay value, and the number of added clock cycles can be 16.

[0072] Furthermore, after obtaining the unified delay value, the synchronous analog-to-digital clock signal is used as the clock reference, and the delay of each acquisition channel is configured according to the unified delay value, so that all acquisition channels are configured with the same unified delay value, eliminating the timing deviation between the acquisition channels, and all acquisition channels can reach a preliminary synchronization state.

[0073] As an embodiment of the present application, a phased array system includes a timing control board, a frequency synthesis board, and an acquisition board; the timing control board is connected to the acquisition board through a first connecting cable, and all first connecting cables are required to be phase-stable and strictly equal in length; the frequency synthesis board is connected to the timing control board and the acquisition board respectively through second connecting cables, and all second connecting cables are required to be phase-stable and strictly equal in length.

[0074] Reference Figure 7a As shown, the phased array system includes a timing control board, a frequency synthesis board and an acquisition board. The acquisition board is integrated with an acquisition channel, and the number of acquisition boards can be one or more. The output end of the frequency synthesis board is connected to the input end of the timing control board and the input end of the acquisition board respectively through a second connecting cable, and the output end of the timing control board is connected to the input end of the acquisition board through a first connecting cable. The timing control board and the acquisition board are connected in a DC coupling manner to reduce signal glitches and improve signal transmission quality. It should be noted that all first connecting cables are required to be phase-stable and strictly equal in length, so that the clock signals output by the frequency synthesis board to the timing control board and the acquisition board are in phase and stable. Similarly, all second connecting cables are required to be phase-stable and strictly equal in length, so that the clock signals output by the frequency synthesis board to the acquisition board are in phase and stable. The frequency synthesis board is used to generate a homologous, highly stable, and coherent reference clock signal, and output the reference clock signal to the timing control board so that the timing control board can synchronize and control the acquisition board according to the reference clock signal. The frequency synthesis board also sends the reference clock signal to the acquisition board, so that the acquisition board can use the reference clock signal as the signal input and output for synchronous processing. It can be understood that by outputting the clock signal through a single frequency synthesis board, the timing error between the clock signals generated by different clock sources is effectively reduced, and the timing consistency and stability between the multiple clock signals are improved. In addition, the single frequency synthesis board also simplifies the hardware design within the phased array system, reduces the hardware complexity of the phased array system, and improves the hardware stability and ease of use of the phased array system.

[0075] For example, referring to Figure 7b As shown, the frequency synthesis board can be a card that includes a rubidium atomic clock frequency standard source and two 1:16 frequency standard distributors. The rubidium atomic clock frequency standard source has GPS and Beidou satellite taming capabilities, receiving GPS and Beidou satellite signals and synchronizing the rubidium oscillator's output frequency to the clock signal of the GPS and Beidou satellite signals, thereby providing a high-precision time and frequency signal comparable to that of a cesium atomic clock. The clock signal output by the rubidium atomic clock frequency standard source passes through the two 1:16 frequency standard distributors to generate multiple clock signals, which provide stable reference clock signals for multiple acquisition boards, ensuring stable and synchronized operation of the acquisition boards.

[0076] The timing control board generates synchronization control pulse signals. After receiving the reference clock signal from the frequency synthesis board, it uses the reference clock signal as a clock reference to output synchronization control pulse signals to each acquisition board, controlling the acquisition board to perform corresponding operations. The timing control board connects to the acquisition board via a separate first connection cable for signal transmission. This effectively reduces the amount of wiring between the timing control board and the acquisition board, reduces the complexity of the phased array system, and thus improves the reliability of the phased array system.

[0077] For example, referring to Figure 7cAs shown, the timing control board can be a board including a Zynq SoC series FPGA module, a KU series pure PL FPGA module, and an input terminal. The input terminal is used to receive the reference clock signal output by the frequency synthesis board and send the reference clock signal to the Zynq SoC series FPGA module and the KU series pure PL FPGA module as a clock reference for both. The Zynq SoC series FPGA module is connected to a host computer or multiple acquisition boards to achieve signal data exchange with the host computer or multiple acquisition boards. For example, the Zynq SoC series FPGA module can be connected to the host computer or multiple acquisition boards via a PS-side gigabit network port. The KU series pure PL FPGA module has an output terminal connected to multiple acquisition boards, which is used to output a synchronization control pulse signal to each acquisition board using the reference clock signal as the clock reference to synchronize the acquisition boards. The Zynq SoC series FPGA module is connected to the KU series pure PL FPGA module. Based on the instructions issued by the host computer, a trigger signal is sent to the KU series pure PL FPGA module to trigger the KU series pure PL FPGA module to send a synchronous control pulse signal to the acquisition board.

[0078] The acquisition board is used to receive a reference clock signal and generate multiple clock signals for synchronous processing based on the reference clock signal through a clock chip, thereby realizing synchronous signal acquisition between multiple acquisition boards. The acquisition board includes a programmable logic part and a processing system part, wherein: the programmable logic part is provided with an RFDC IP core, and the RFDC IP core contains one or more acquisition channels for signal acquisition. The programmable logic part is also used to receive the synchronous control pulse signal output by the timing control board and parse the synchronous control pulse signal to determine the corresponding operation to be performed based on the trigger pulse contained therein. The processing system part can configure the clock signal of the acquisition board and start the required logic files by calling the API driver software. The processing system part is also used to receive information such as delay reference or channel phase obtained from the acquisition board. The processing system part exchanges information with the programmable logic part through the AXI interface and sends signal instructions to the programmable logic part.

[0079] Reference Figure 8As shown, a synchronous clock tree based on a single clock chip can be designed in the acquisition board. The hardware structure of this synchronous clock tree includes the clock chip, a PL MMCM divider, an RF clock chip, and an RFDC IP core. The RFDC IP core contains multiple acquisition channels, represented by ADC units. All acquisition channels operate in the same operating mode and are configured with the same operating parameters. The output of the clock chip is connected to the input of the RF clock chip. The output of the RF clock chip and the output of the clock chip are respectively connected to the input of the RFDC IP core. The input of the PL MMCM divider is connected to the output of the clock chip.

[0080] The clock chip, as the foundation of the synchronous clock tree, generates multiple clock signals from the same source and sends them to multiple modules on the acquisition board, providing clock references for each module. These multiple clock signals include the synchronization pulse period signal AMS_SYSREF and the logic pulse period signal PL_SYSREF. The clock chip connects to the RFDC IP core to transmit these signals to the RFDC IP core for delay and phase synchronization of each acquisition channel. For example, the frequency of the synchronization pulse period signal AMS_SYSREF and the logic pulse period signal PL_SYSREF can be 10 MHz.

[0081] As you can see, using a single clock chip to uniformly output multiple clock signals reduces clock drift and errors between them, improving the timing consistency of clock signals within the board. Furthermore, a single clock chip simplifies the hardware design on the acquisition board, reducing module complexity and improving the hardware stability and ease of use of the acquisition board.

[0082] The PL MMCM divider is used to divide the clock signal output by the clock chip to generate the ADC parallel data output clock AXIS_clock and the back-end signal processing clock USER_clock to control the output and processing of the acquisition signal and ensure the synchronization between different acquisition signals. The functions of the PL MMCM divider can also include clock frequency conversion, clock phase control, clock division and multiplication, and clock synchronization. It can be understood that the acquisition signal is synchronously output to the RFSoC FPGA processing chip on the acquisition board to perform signal processing on the acquisition signal. For example, the frequency of the ADC parallel data output clock AXIS_clock can be 250MHz, and the frequency of the back-end signal processing clock USER_clock can be 350MHz.

[0083] The RF clock chip receives the clock signal sent by the clock chip and, based on this clock signal, generates an acquisition clock signal for synchronous transmission to the RFDC IP core. This provides a synchronous clock foundation for the acquisition channels during signal acquisition, enabling synchronous signal acquisition. The RF clock chip generates the acquisition clock signal by performing clock operations on the clock signal. If the frequency of the acquisition clock signal falls outside the clock frequency range specified by the clock chip, the clock chip cannot directly generate the acquisition clock signal for the RFDC IP core. Clock operations must be performed on the clock signal by the RF clock chip to generate an acquisition clock signal that meets actual needs. Examples of clock operations include clock multiplication or clock phase adjustment.

[0084] The RFDC IP core receives the acquisition clock signal from the RF clock chip and distributes it to multiple acquisition channels, enabling synchronized signal acquisition across all channels. Each acquisition channel can be an analog-to-digital converter (ADC) unit, which converts analog signals into digital signals for further processing and analysis. For example, the acquisition clock signal frequency can be 4 GHz.

[0085] As an embodiment of the present application, a frequency synthesis board sends a homologous, highly stable, and coherent reference clock signal to a timing control board and an acquisition board; the acquisition board includes multiple acquisition channels; and the method further includes: S500. Using the reference clock signal as the clock reference, send a synchronization control pulse signal to the acquisition board through the timing control board to trigger the phased array system to perform subsequent synchronization preprocessing of the signal.

[0086] Specifically, the output of each acquisition channel on the acquisition board is connected to a signal processing unit. This unit contains multiple processing channels, each corresponding to the number of acquisition channels. To ensure that the clocks of each processing channel are consistent when the acquired signal enters the signal processing unit, the signal processing unit must also undergo subsequent synchronization preprocessing to synchronize the timing of the processing channels within the signal processing unit.

[0087] Furthermore, before the acquisition signal of each acquisition channel reaches the signal processing unit, a synchronization control pulse signal including a reset pulse is sent to the acquisition board, so that each processing channel in the signal processing unit can synchronously receive the synchronization control pulse signal. Pulse detection is performed on the synchronization control pulse signal, and after the trigger pulse is detected, the pulse width is measured, and the type of the trigger pulse is determined based on the measurement result. If the type of the trigger pulse is a reset pulse, each processing channel is triggered with the rising edge of the reset pulse as the reference point, and each processing channel is controlled to synchronously reset and align its own clock signal, so that the acquisition signal in each acquisition channel can be synchronously processed after entering the signal processing unit, thereby improving the synchronization between the acquisition signals. Figure 9 As shown, the reset pulse can be a trigger pulse whose pulse width meets the second pulse width condition. The second pulse width condition corresponds to a pulse width of 2 clock cycles. After receiving the reset pulse, the signal processing unit triggers each processing channel to perform subsequent synchronous preprocessing of the signal.

[0088] As an embodiment of the present application, when the acquisition channel reaches a preset synchronization state, the synchronization process of the phased array system is terminated, and the preset synchronization state includes a preliminary synchronization state; the acquisition board uses a first type of board, the first type of board does not have a digital orthogonal demodulation function, and the acquisition channel in the first type of board does not need to be further phase synchronized; the number of the first type of boards is N, where N is a positive integer.

[0089] Specifically, the acquisition cards in a phased array system can use Type 1 cards. Type 1 cards lack digital functionality and are unable to perform digital quadrature demodulation on the signals from each acquisition channel. Therefore, Type 1 cards place lower demands on phase synchronization between acquisition channels and typically meet the third synchronization consistency requirement, eliminating the need for further phase synchronization. The number of Type 1 cards can be one or more, with the specific number determined based on the actual application scenario.

[0090] Furthermore, for the first type of board that meets the third synchronization consistency requirement, since no further phase synchronization is required, its corresponding preset synchronization state only includes the preliminary synchronization state. When the first type of board reaches the preliminary synchronization state, the synchronization process of the phased array system is terminated.

[0091] As an embodiment of the present application, when the acquisition channel reaches a preset synchronization state, the synchronization process of the phased array system is terminated, the preset synchronization state includes a preliminary synchronization state and a target phase synchronization state; the target phase synchronization state is a first phase synchronization state or a second phase synchronization state; the acquisition board uses a second type of board, the second type of board has a digital orthogonal demodulation function, the inter-channel phase difference of each acquisition channel in the second type of board has not converged, and further phase synchronization is required; the number of the second type of board is N, and N is a positive integer.

[0092] Specifically, the acquisition cards in a phased array system can utilize Type II cards. These cards possess digital functionality and can perform digital quadrature demodulation on the signals collected from each acquisition channel. Therefore, Type II cards place relatively high demands on phase synchronization between acquisition channels, typically meeting either the first or second synchronization consistency requirements. Further phase synchronization is required for each acquisition channel. The number of Type II cards can be one or more, and the specific number can be determined based on the actual application scenario.

[0093] Furthermore, for the second type of board that meets the first synchronization consistency requirement, its corresponding preset synchronization state includes a preliminary synchronization state and a first phase synchronization state. When the second type of board reaches the preliminary synchronization state and the first phase synchronization state, the synchronization process of the phased array system ends. Similarly, for the second type of board that meets the second synchronization consistency requirement, its corresponding preset synchronization state includes a preliminary synchronization state and a second phase synchronization state. When the second type of board reaches the preliminary synchronization state and the second phase synchronization state, the synchronization process of the phased array system ends.

[0094] Accordingly, please refer to Figure 10 The embodiment of the present application provides a synchronous acquisition and processing device for a phased array system, wherein the phased array system includes multiple acquisition channels; the device includes: The delay synchronization module 1010 is used to perform delay synchronization on each acquisition channel so that all acquisition channels of the phased array system reach a preliminary synchronization state.

[0095] The inter-channel phase synchronization module 1020 is used to perform inter-channel phase synchronization on each acquisition channel when each acquisition channel reaches a preliminary synchronization state and needs further phase synchronization; wherein: The first phase synchronization unit 1030 is used to perform a first phase synchronization operation based on the first synchronization consistency requirement, so that each acquisition channel reaches the first phase synchronization state corresponding to the first synchronization consistency requirement after delaying synchronization to enable each acquisition channel to reach the preliminary synchronization state.

[0096] The second phase synchronization unit 1040 is used to perform a second phase synchronization operation based on the second synchronization consistency requirement, so that each acquisition channel reaches a second phase synchronization state corresponding to the second synchronization consistency requirement through delayed synchronization; wherein the second phase synchronization operation includes phase synchronization operation and iterative correction.

[0097] In some optional implementations, the first phase synchronization unit 1030 includes: The phase information unification subunit is used to calculate the phase information of each acquisition channel, and calculate the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel.

[0098] The phase adjustment determination subunit is used to determine the channel phase adjustment value corresponding to each acquisition channel according to the phase difference between channels.

[0099] The initial phase update subunit is used to update the NCO initial phase of each acquisition channel using the channel phase adjustment value to complete the first phase synchronization operation.

[0100] In some optional implementations, the second phase synchronization unit 1040 includes: The inter-channel phase difference calculation subunit is used to calculate the phase information of each acquisition channel, and calculate the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel.

[0101] The phase difference convergence judgment subunit is used to judge whether the phase difference between channels converges.

[0102] The convergence operation subunit is used to perform corresponding operations according to whether the phase difference between the channels converges. If converged, the iterative correction process of the second phase synchronization operation is terminated.

[0103] The non-convergence operation subunit is used to perform corresponding operations based on whether the inter-channel phase difference converges. If not, the channel phase adjustment value corresponding to each acquisition channel is determined based on the inter-channel phase difference; the channel phase adjustment value is used to update the NCO initial phase of each acquisition channel; and the above steps of calculating phase information, inter-channel phase difference and convergence judgment are repeated until the inter-channel phase difference of each acquisition channel reaches a converged state.

[0104] In some optional implementations, the inter-channel phase synchronization module 1020 includes: The delay value unification unit is used to calculate the delay value of each acquisition channel and unify the delay value of each acquisition channel to obtain a unified delay value.

[0105] The delay configuration unit is used to configure the delay of each acquisition channel according to the unified delay value to complete the delay synchronization of each acquisition channel.

[0106] In some optional embodiments, the phased array system includes a timing control board, a frequency synthesis board, and an acquisition board; the timing control board is connected to the acquisition board via a first connection cable, and all first connection cables are required to be phase-stable and strictly equal in length; The frequency synthesis board is connected to the timing control board and the acquisition board through second connection cables. All second connection cables are required to be phase-stable and strictly of equal length.

[0107] In some optional embodiments, the device further includes a synchronization preprocessing module, including: The synchronous reset alignment unit is used to use the reference clock signal as the clock reference and send a synchronous control pulse signal to the acquisition board through the timing control board to trigger the phased array system to perform subsequent synchronous preprocessing of the signal.

[0108] In some optional embodiments, when the acquisition channel reaches a preset synchronization state, the synchronization process of the phased array system is terminated, and the preset synchronization state includes a preliminary synchronization state; the acquisition board card adopts a first type of board card, the first type of board card does not have a digital orthogonal demodulation function, and the acquisition channel in the first type of board card does not need to be further phase synchronized; the number of the first type of board cards is N, where N is a positive integer.

[0109] In some optional embodiments, when the acquisition channel reaches a preset synchronization state, the synchronization process of the phased array system is terminated, the preset synchronization state includes a preliminary synchronization state and a target phase synchronization state; the target phase synchronization state is a first phase synchronization state or a second phase synchronization state; the acquisition board uses a second type of board, the second type of board has a digital orthogonal demodulation function, the phase difference between each acquisition channel in the second type of board has not converged, and further phase synchronization is required; the number of the second type of board is N, and N is a positive integer.

[0110] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0111] The synchronous acquisition and processing device of the phased array system in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0112] See also Figure 11 , Figure 111 is a structural diagram of an electronic device provided by an embodiment of the present application. As shown in the figure, the electronic device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the electronic device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple electronic devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 11 A processor 10 is taken as an example.

[0113] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0114] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0115] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0116] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0117] The electronic device further includes a communication interface 30 for the electronic device to communicate with other devices or a communication network.

[0118] The embodiments of the present application also provide a computer-readable storage medium. The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0119] The embodiments of the present application provide a computer program product comprising computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the method of any embodiment of the present application. Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

[0120] The systems, devices, modules, or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0121] For the convenience of description, the above devices are described as being divided into various units according to their functions. Of course, when implementing this application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0122] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0123] This application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate a device for implementing the functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0124] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0126] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0127] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0128] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

[0129] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A synchronous acquisition and processing method for a phased array system, characterized in that: The phased array system includes multiple acquisition channels; the method includes: Delay synchronization is performed on each acquisition channel so that all acquisition channels of the phased array system reach a preliminary synchronization state; When each acquisition channel reaches the preliminary synchronization state and needs further phase synchronization, inter-channel phase synchronization is performed on each acquisition channel; wherein: For the first synchronization consistency requirement, on the basis of enabling each acquisition channel to reach the preliminary synchronization state through the delayed synchronization, performing a first phase synchronization operation so that each acquisition channel reaches a first phase synchronization state corresponding to the first synchronization consistency requirement; In response to the second synchronization consistency requirement, on the basis of enabling each acquisition channel to reach the preliminary synchronization state through the delayed synchronization, a second phase synchronization operation is performed to enable each acquisition channel to reach the second phase synchronization state corresponding to the second synchronization consistency requirement; wherein, the second phase synchronization operation includes phase synchronization operation and iterative correction.

2. The method according to claim 1, characterized in that The first phase synchronization operation is performed by the following steps: Calculating the phase information of each acquisition channel, and calculating the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel; Determine the channel phase adjustment value corresponding to each acquisition channel according to the inter-channel phase difference; The channel phase adjustment value is used to update the NCO initial phase of each acquisition channel to complete the first phase synchronization operation.

3. The method according to claim 1, characterized in that The second phase synchronization operation is performed by the following steps: Calculating the phase information of each acquisition channel, and calculating the inter-channel phase difference between each acquisition channel and the selected reference channel based on the phase information of the selected reference channel; Determining whether the inter-channel phase difference converges; If converged, ending the iterative correction process of the second phase synchronization operation; If convergence does not occur, determine the channel phase adjustment value corresponding to each acquisition channel based on the inter-channel phase difference; use the channel phase adjustment value to update the NCO initial phase of each acquisition channel; repeat the above steps of calculating phase information, inter-channel phase difference and convergence judgment until the inter-channel phase difference of each acquisition channel reaches a converged state.

4. The method according to claim 1, wherein The delay synchronization of each acquisition channel includes: Calculating the delay values ​​of the acquisition channels and unifying the delay values ​​of the acquisition channels to obtain a unified delay value; Delay configuration is performed on each acquisition channel according to the unified delay value to complete delay synchronization of each acquisition channel.

5. The method according to claim 1, wherein The phased array system includes a timing control board, a frequency synthesis board, and an acquisition board; the timing control board is connected to the acquisition board via a first connection cable, and all first connection cables are required to be phase-stable and strictly of equal length; The frequency synthesis board is connected to the timing control board and the acquisition board through second connection cables. All second connection cables are required to be phase-stable and strictly of equal length.

6. The method according to claim 5, characterized in that The frequency synthesis board sends a homologous, highly stable and coherent reference clock signal to the timing control board and the acquisition board; the acquisition board includes the multiple acquisition channels; The method further comprises: Using the reference clock signal as a clock reference, a synchronization control pulse signal is sent to the acquisition board through the timing control board to trigger the phased array system to perform subsequent synchronization preprocessing of the signal.

7. The method according to claim 6, characterized in that When the acquisition channel reaches a preset synchronization state, ending the synchronization process of the phased array system, the preset synchronization state includes the preliminary synchronization state; The acquisition board adopts a first type of board, which does not have a digital quadrature demodulation function, and the acquisition channels in the first type of board do not need to be further phase synchronized; The number of the first type of boards is N, where N is a positive integer.

8. The method according to claim 6, characterized in that When the acquisition channel reaches a preset synchronization state, the synchronization process of the phased array system is terminated, wherein the preset synchronization state includes the preliminary synchronization state and the target phase synchronization state; The target phase synchronization state is the first phase synchronization state or the second phase synchronization state; The acquisition board adopts a second type of board, which has a digital quadrature demodulation function. The phase difference between the acquisition channels in the second type of board has not converged, and further phase synchronization is required. The number of the second type of boards is N, where N is a positive integer.

9. A synchronous acquisition and processing device for a phased array system, characterized in that: The phased array system includes multiple acquisition channels; the device includes: A delay synchronization module is used to perform delay synchronization on each acquisition channel so that all acquisition channels of the phased array system reach a preliminary synchronization state; The inter-channel phase synchronization module is used to perform inter-channel phase synchronization on each acquisition channel when each acquisition channel reaches the preliminary synchronization state and needs further phase synchronization; wherein: a first phase synchronization unit, configured to, based on a first synchronization consistency requirement, perform a first phase synchronization operation so that each acquisition channel reaches a first phase synchronization state corresponding to the first synchronization consistency requirement, on the basis of enabling each acquisition channel to reach the preliminary synchronization state through the delayed synchronization; The second phase synchronization unit is used to perform a second phase synchronization operation based on the second synchronization consistency requirement, so that each acquisition channel reaches the second phase synchronization state corresponding to the second synchronization consistency requirement through the delayed synchronization; wherein the second phase synchronization operation includes phase synchronization operation and iterative correction.

10. An electronic device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 8 by executing the computer instructions.

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