FPGA-based UDP protocol to multi-channel UART protocol conversion method and device

Abstract

This invention provides a method and apparatus for FPGA-based UDP protocol to multi-channel UART protocol conversion. The method includes: receiving and parsing UDP datagrams to obtain pseudo-header information and header information; performing data verification on the UDP datagrams based on the pseudo-header information and header information, and buffering the UDP datagrams according to the verification result to obtain UDP buffered data; parsing the UDP buffered data using application layer protocols to obtain application layer data; buffering the application layer data to obtain application layer buffered data; formatting the application layer buffered data into UART frames according to a preset UART frame encapsulation format to obtain UART data frames; searching a channel mapping table based on the header information to determine a set of UART channel IDs, and sending the UART data frames through the UART interface based on a dynamic priority arbitration mechanism, the set of UART channel IDs, and preset configuration parameters. The method and apparatus of this invention can perform multi-channel expansion to ensure the real-time performance and reliability of data transmission.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically, to an FPGA-based method, apparatus, electronic device, and computer-readable storage medium for converting UDP protocol to multi-channel UART protocol. Background Technology

[0002] Universal Asynchronous Receiver / Transmitter (UART) is a mature and reliable serial communication interface widely used in embedded systems, industrial control, and other fields. However, as application complexity increases, a single UART channel often cannot meet the concurrent communication needs of multiple devices or diverse data streams.

[0003] In existing technologies, multi-channel UART communication is mainly achieved through two methods: one is to use a hardware multiplexer to time-division multiplex a single UART physical channel. However, when the number of channels increases or the data rate is high, this method is prone to significant communication delays and efficiency reductions due to frequent switching. The other method is to directly integrate multiple independent UART controllers. Although this can provide true parallel communication, it significantly increases hardware costs, power consumption, and PCB area, limiting its application in resource-constrained embedded scenarios.

[0004] Meanwhile, the lack of an effective priority arbitration mechanism is another key issue when multiple channels simultaneously require data transmission. Existing solutions mostly employ simple polling or fixed-priority strategies. Polling mechanisms cannot guarantee the real-time performance of high-priority data, potentially causing delays in critical information; fixed-priority strategies lack flexibility, and low-priority channels may be unable to receive service for extended periods under sustained high load, leading to a "starvation" phenomenon. Existing mechanisms struggle to dynamically and adaptively adjust priorities based on data characteristics and system status.

[0005] Therefore, the existing technology lacks a method or device for converting UDP protocol to multi-channel UART protocol based on FPGA (Field Programmable Gate Array) that can perform multi-channel expansion and control multi-channel output data based on dynamic priority arbitration mechanism to ensure the real-time performance and reliability of data during transmission. Summary of the Invention

[0006] The purpose of this invention is to provide a method, apparatus, electronic device, and computer-readable storage medium for converting UDP protocol to multi-channel UART protocol based on FPGA, so as to solve the above-mentioned problems existing in related technologies.

[0007] According to a first aspect of the present invention, an FPGA-based method for converting UDP protocol to multi-channel UART protocol is provided, the method comprising:

[0008] Receive and parse UDP datagrams to obtain pseudo header information and header information;

[0009] Based on the pseudo header information and the header information, the UDP datagram is validated to obtain the validation result. Based on the validation result, the UDP datagram is cached to obtain UDP cached data.

[0010] The UDP cached data is parsed using application layer protocols to obtain the corresponding application layer data;

[0011] Cache the application layer data to obtain the application layer cached data;

[0012] According to the preset UART frame encapsulation format, the application layer cached data is formatted into UART frames to obtain UART data frames;

[0013] Based on the header information, the channel mapping table is searched to determine the UART channel ID set. Then, based on the dynamic priority arbitration mechanism, the UART data frame is sent through the corresponding UART interface according to the UART channel ID set and preset configuration parameters.

[0014] Optionally, the pseudo header information includes: source IP address, destination IP address, UDP protocol number and UDP length; the header information includes source port number, destination port number, total UDP length, data information and checksum.

[0015] Optionally, based on the pseudo header information and the header information, the UDP datagram is validated to obtain the validation result. Based on the validation result, the UDP datagram is then cached to obtain UDP cached data, including:

[0016] Data transmission verification is performed on UDP datagrams based on the pseudo header information and the header information;

[0017] If the data transmission verification result is a failure, the UDP datagram is discarded;

[0018] If the data transmission verification result is successful, perform cyclic redundancy check on the UDP datagram based on the pseudo header information and the header information.

[0019] If the cyclic redundancy check fails, the UDP datagram is discarded.

[0020] If the cyclic redundancy check (CRC) passes the check, the UDP datagram is cached in the first FIFO queue, and the UDP cached data is obtained.

[0021] Optionally, the UDP datagram is buffered in the first first-in-first-out queue. After obtaining the buffered UDP data, the process further includes:

[0022] Check if the first first-in-first-out queue is full;

[0023] If the first FIFO queue is full, discard new UDP buffered data.

[0024] Optionally, the application layer cached data is formatted into UART frames according to a preset UART frame encapsulation format to obtain a UART data frame, including:

[0025] Extract the command word field and length field from the application-layer cached data;

[0026] Add a 1-byte channel identifier prefix before the command word field;

[0027] A CRC16 checksum is generated based on the encapsulated data, which includes the source port number, destination port number, total UDP length, data information, and checksum.

[0028] The channel identifier prefix, command word field, length field, data information, and CRC16 checksum are encapsulated into a serial frame format to obtain a UART data frame. The UART data frame includes, in sequence, a start bit, a channel identifier prefix, a command word field, a length field, data information, a CRC16 checksum, and a stop bit.

[0029] Optionally, based on the header information, the channel mapping table is looked up to determine the UART channel ID set, and based on the dynamic priority arbitration mechanism, the UART data frame is sent through the corresponding UART interface according to the UART channel ID set and preset configuration parameters, including:

[0030] Based on the destination port number in the header information, look up the channel mapping table, determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set. The preset configuration parameters include basic priority, basic wait count and basic baud rate.

[0031] Detect the current request parameters of each UART channel in the UART channel ID set, where the current request parameters include the current wait count, the current channel baud rate, and the current pointer;

[0032] Calculate the effective priority for each UART channel in the UART channel ID set, where effective priority = base priority - wait boost value - baud rate boost value, wait boost value = current wait count / base wait count, and baud rate boost value = current channel baud rate / base baud rate.

[0033] Select the minimum value among the valid priorities corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer;

[0034] After identifying the target UART channel, the current pointer is reset to the target UART channel's channel ID incremented by 1, and the target UART channel's current wait count is reset to zero, awaiting the next round of priority arbitration.

[0035] According to a second aspect of the present invention, an FPGA-based UDP protocol to multi-channel UART protocol conversion device is provided. The device includes: a UDP protocol parsing module, a UDP verification module, a first buffer module, an application layer protocol parsing module, a second buffer module, a UART encapsulation module, and a channel management module; wherein,

[0036] The UDP protocol parsing module is used to receive and parse UDP datagrams to obtain pseudo header information and header information;

[0037] The UDP verification module is connected to the UDP protocol parsing module and is used to verify the UDP datagram based on the pseudo header information and the header information to obtain the verification result.

[0038] The first caching module and the UDP verification module are used to cache UDP datagrams based on the verification results to obtain UDP cached data.

[0039] The application layer protocol parsing module is connected to the first cache module and is used to parse the UDP cached data using the application layer protocol to obtain the corresponding application layer data.

[0040] The second caching module is connected to the application layer protocol parsing module and is used to cache application layer data to obtain application layer cached data.

[0041] The UART encapsulation module is connected to the second buffer module and is used to format the application layer buffer data into UART frames according to the preset UART frame encapsulation format to obtain UART data frames.

[0042] The channel management module is connected to the UDP protocol parsing module and the UART encapsulation module respectively. It is used to look up the channel mapping table based on the header information, determine the UART channel ID set, and send the UART data frame through the corresponding UART interface based on the dynamic priority arbitration mechanism, the UART channel ID set and the preset configuration parameters.

[0043] Optionally, the channel management module is further used for:

[0044] Based on the destination port number in the header information, look up the channel mapping table, determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set. The preset configuration parameters include basic priority, basic wait count and basic baud rate.

[0045] Detect the current request parameters of each UART channel in the UART channel ID set, where the current request parameters include the current wait count, the current channel baud rate, and the current pointer;

[0046] Calculate the effective priority for each UART channel in the UART channel ID set, where effective priority = base priority - wait boost value - baud rate boost value, wait boost value = current wait count / base wait count, and baud rate boost value = current channel baud rate / base baud rate.

[0047] Select the minimum value among the valid priorities corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer;

[0048] After identifying the target UART channel, the current pointer is reset to the target UART channel's channel ID incremented by 1, and the target UART channel's current wait count is reset to zero, awaiting the next round of priority arbitration.

[0049] According to a third aspect of the present invention, an electronic device is provided, comprising: a memory having a computer program stored thereon; and a processor for executing the computer program in the memory to implement the steps of any of the methods described above.

[0050] According to a fourth aspect of the present invention, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps of any of the methods described above.

[0051] This invention provides an FPGA-based method and apparatus for converting UDP protocol to multi-channel UART protocol. The method and apparatus receive and parse UDP datagrams to obtain pseudo-header information and header information. Based on the pseudo-header information and header information, the UDP datagrams are validated, and based on the validation result, the UDP datagrams are buffered to obtain UDP buffered data. The UDP buffered data is then parsed using application layer protocols to obtain application layer data. This application layer data is also buffered to obtain application layer buffered data. The application layer buffered data is formatted into UART frames according to a preset UART frame encapsulation format to obtain UART data frames. Based on the header information, a channel mapping table is searched to determine the UART channel ID set. Based on a dynamic priority arbitration mechanism, and according to the UART channel ID set and preset configuration parameters, the UART data frames are transmitted through the UART interface. This FPGA-based method and apparatus for converting UDP protocol to multi-channel UART protocol provides the ability to perform multi-channel expansion to ensure the real-time performance and reliability of data transmission.

[0052] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0053] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof. In the drawings:

[0054] Figure 1 A flowchart of the FPGA-based UDP protocol to multi-channel UART protocol conversion method provided by the present invention;

[0055] Figure 2 A structural block diagram of the FPGA-based UDP protocol to multi-channel UART protocol conversion device provided by the present invention;

[0056] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0057] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0058] It should be noted that in this invention, terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order; terms such as "S11," "S12," "S13," and "S14" are used to distinguish steps and should not be construed as performing method steps in a specific order or sequence; "multiple" includes two or more; when the following description relates to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0059] Exemplary methods

[0060] Figure 1 This is a flowchart illustrating the FPGA-based UDP protocol to multi-channel UART protocol conversion method provided by the present invention. Figure 1 As shown, the method includes:

[0061] Step S11: Receive and parse UDP datagrams to obtain pseudo header information and header information;

[0062] The pseudo header information includes: source IP address, destination IP address, UDP protocol number and UDP length; the header information includes source port number, destination port number, total UDP length, data information and checksum.

[0063] Optionally, before step S11 of the present invention, the method further includes: receiving target data and stripping the frame header from the target data to obtain network layer data;

[0064] The network layer data is parsed using network layer protocols, and the IP header is removed to obtain UDP datagrams.

[0065] Step S12: Perform data verification on the UDP datagram based on the pseudo header information and the header information, obtain the verification result, and cache the UDP datagram according to the verification result to obtain UDP cached data.

[0066] Specifically, step S12 may include:

[0067] Step S121: Perform data transmission verification on the UDP datagram based on the pseudo header information and the header information; wherein, the data transmission verification can be performed using existing checksum methods, and those skilled in the art can choose according to actual needs, without limitation here.

[0068] Step S122: If the data transmission verification result is that the verification fails, discard the UDP datagram;

[0069] Step S123: If the data transmission verification result is that the verification passes, perform cyclic redundancy check on the UDP datagram based on the pseudo header information and the header information; wherein, the cyclic redundancy check adopts the method in the prior art, and those skilled in the art can choose according to actual needs, and there is no limitation here.

[0070] Step S124: If the cyclic redundancy check result is a failure, discard the UDP datagram;

[0071] Step S125: If the cyclic redundancy check result is a pass, cache the UDP datagram in the first first-in-first-out queue to obtain the UDP cached data.

[0072] Optionally, after buffering the UDP datagram into the first first-in-first-out queue in step S125 and obtaining the buffered UDP data, the method further includes:

[0073] Check if the first first-in-first-out queue is full;

[0074] If the first FIFO queue is full, discard new UDP buffered data.

[0075] Step S13: Perform application layer protocol parsing on the UDP cached data to obtain the corresponding application layer data;

[0076] Step S14: Cache the application layer data to obtain application layer cache data;

[0077] Step S15: Format the application layer cached data into UART frames according to the preset UART frame encapsulation format to obtain UART data frames;

[0078] Optionally, step S15 specifically includes:

[0079] Extract the command word field and length field from the application-layer cached data;

[0080] Add a 1-byte channel identifier prefix before the command word field;

[0081] A CRC16 checksum is generated based on the encapsulated data, which includes the source port number, destination port number, total UDP length, data information, and checksum.

[0082] The channel identifier prefix, command word field, length field, data information, and CRC16 checksum are encapsulated into a serial frame format to obtain a UART data frame. The UART data frame includes, in sequence, a start bit, a channel identifier prefix, a command word field, a length field, data information, a CRC16 checksum, and a stop bit.

[0083] Step S16: Based on the header information, look up the channel mapping table, determine the UART channel ID set, and based on the dynamic priority arbitration mechanism, send the UART data frame through the corresponding UART interface according to the UART channel ID set and preset configuration parameters.

[0084] In an optional embodiment of the present invention, step S16 specifically includes:

[0085] Step S161: Based on the destination port number in the header information, look up the channel mapping table, determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set. The preset configuration parameters include basic priority, basic wait count and basic baud rate.

[0086] The number of UART channels can be flexibly set by those skilled in the art according to actual needs, and is not limited here. In this invention, the number of UART channels is preferably greater than or equal to 20.

[0087] In this invention, the channel ID and preset configuration parameters corresponding to the UART channel are pre-set, and those skilled in the art can flexibly set them according to actual needs, without limitation here.

[0088] Step S162: Detect the current request parameters of each UART channel in the UART channel ID set, wherein the current request parameters include the current wait count, the current channel baud rate, and the current pointer;

[0089] Step S163: Calculate the effective priority of each UART channel in the UART channel ID set, where effective priority = base priority - wait boost value - baud rate boost value, wait boost value = current wait count / base wait count, and baud rate boost value = current channel baud rate / base baud rate.

[0090] Step S164: Select the minimum value among the valid priorities corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer;

[0091] Step S165: After determining the target UART channel, reset the current pointer to the channel ID of the target UART channel and increment it by 1. At the same time, reset the current wait count of the target UART channel to zero and wait for the next round of priority arbitration.

[0092] To enable those skilled in the art to clearly understand this optional implementation, the present invention will be described in detail using an example of 4 UART channels, a base wait count of 100 clock cycles, and a base baud rate of 115200.

[0093] UART Channel 0: Base priority = 1, current channel baud rate = 115200, therefore, baud rate boost = current channel baud rate / base baud rate = 115200 / 115200 = 1;

[0094] UART Channel 1: Base priority = 2, current channel baud rate = 230400, therefore, baud rate boost = current channel baud rate / base baud rate = 230400 / 115200 = 2;

[0095] UART Channel 2: Base Priority = 0, Current Channel Baud Rate = 57600, Baud Rate Increase = Current Channel Baud Rate / Base Baud Rate = 57600 / 115200 = 0 (rounded to the nearest integer).

[0096] UART Channel 3: Base Priority = 3, Current Channel Baud Rate = 115200, Baud Rate Boost = Current Channel Baud Rate / Base Baud Rate = 115200 / 115200 = 1.

[0097] Initialization: Current wait count = 0, current pointer = 0.

[0098] Round 1: Calculate effective priority:

[0099] UART channel 0: Valid priority = 1-0-1 = 0;

[0100] UART Channel 1: Valid Priority = 2-0-2 = 0;

[0101] UART Channel 2: Valid Priority = 0-0-0 = 0;

[0102] UART channel 3: Effective priority = 3-0-1 = 2;

[0103] The lowest valid priority among the four UART channels is 0. Starting from the current pointer 0, UART channel 0 is found first, therefore, UART channel 0 is selected, and the current pointer moves to 1. Assume that sending data through UART channel 0 takes 80 clock cycles. During this time, the current wait count for the other channels increases by 80.

[0104] Second round: After UART channel 0 finishes sending data, priority arbitration is restarted.

[0105] UART Channel 0: Since UART Channel 0 was selected in the first round, its current waiting count = 0, so the effective priority of UART Channel 0 = 1-0-1 = 0;

[0106] UART Channel 1: Current wait count = 80, wait promotion value = current wait count / base wait count = 80 / / 100 = 0 (rounded down), so the effective priority of UART Channel 1 = 2 - 0 - 2 = 0;

[0107] UART Channel 2: Current wait count = 80, wait promotion value = current wait count / base wait count = 80 / / 100 = 0 (rounded down), so the effective priority of UART Channel 2 = 0 - 0 - 0 = 0;

[0108] UART channel 3: Current wait count = 80, wait promotion value = current wait count / base wait count = 80 / / 100 = 0 (rounded down), so the effective priority of UART channel 3 = 3 - 0 - 1 = 2;

[0109] The lowest valid priority among the four UART channels is 0. There are UART channels 0, 1, and 2. The current pointer is 1. Starting from 1, the first UART channel with a valid priority of 0 is UART channel 1. Therefore, UART channel 1 is selected, and the current pointer moves to 2. Assuming data is sent via UART channel 1, taking 40 clock cycles, the current wait count for the other UART channels increases by 40.

[0110] Third round: After UART channel 1 finishes sending data, priority arbitration is restarted.

[0111] UART channel 0: Current wait count = 0 + 40 = 40, wait promotion value = current wait count / base wait count = 40 / 100 = 0 (rounded to the nearest integer), so the effective priority of UART channel 0 = 1 - 0 - 1 = 0;

[0112] UART Channel 1: Since UART Channel 1 was selected in the second round, its current waiting count = 0, so the effective priority of UART Channel 1 = 2-0-2 = 0;

[0113] UART Channel 2: Current wait count = 80 + 40 = 120, wait promotion value = current wait count / base wait count = 120 / 100 = 1 (rounded to the nearest integer), so the effective priority of UART Channel 2 = 0 - 1 - 0 = -1;

[0114] UART channel 3: Current wait count = 80 + 40 = 120, wait promotion value = current wait count / base wait count = 120 / 100 = 1 (rounded to the nearest integer), so the effective priority of UART channel 3 = 3 - 1 - 1 = 1;

[0115] The lowest valid priority among the four UART channels is -1 (i.e., channel 2). The current pointer is 2. Starting from 2, the first UART channel with a valid priority of -1 is UART channel 2. Therefore, UART channel 2 is selected, and the current pointer moves to 3. Assuming data is sent via UART channel 2, taking 100 clock cycles, the current wait count for the other UART channels increases by 100.

[0116] Fourth round: UART channel 2 finishes sending data, and priority arbitration is restarted.

[0117] UART channel 0: Current wait count = 40 + 100 = 140, wait promotion value = current wait count / base wait count = 140 / 100 = 1 (rounded to the nearest integer), so the effective priority of UART channel 0 = 1 - 1 - 1 = -1;

[0118] UART Channel 1: Current wait count = 100, wait promotion value = current wait count / base wait count = 100 / 100 = 1, so the effective priority of UART Channel 1 = 2 - 1 - 2 = -1;

[0119] UART Channel 2: Since UART Channel 2 was selected in the third round, its current waiting count = 0, so the effective priority of UART Channel 2 = 0-0-0 = 0;

[0120] UART channel 3: Current wait count = 80 + 40 + 100 = 220, wait promotion value = current wait count / base wait count = 220 / 100 = 2, so the effective priority of UART channel 3 = 3 - 2 - 1 = 0;

[0121] The lowest valid priority among the four UART channels is -1 (UART channels 0 and 1). The current pointer is 3. Starting from 3, the first valid priority with -1 is UART channel 0. Therefore, UART channel 0 is selected, and the current pointer moves to 0.

[0122] To prevent a UART channel from waiting for too long, even if its base priority is low, its priority will gradually increase as the current wait count rises. Meanwhile, high-baud-rate UART channels have a fixed priority boost, thus receiving more service opportunities. This priority arbitration mechanism dynamically adjusts priorities and ensures fairness in data transmission across all UART channels, guaranteeing real-time performance and reliability during data transmission.

[0123] This invention discloses an FPGA-based UDP to multi-channel UART protocol conversion method. The method receives and parses UDP datagrams to obtain pseudo-header information and header information. Based on the pseudo-header information and header information, it performs data verification on the UDP datagrams and, based on the verification result, buffers the UDP datagrams to obtain UDP buffered data. It then performs application layer protocol parsing on the UDP buffered data to obtain application layer data. This application layer data is also buffered to obtain application layer buffered data. Following a preset UART frame encapsulation format, the application layer buffered data is formatted into UART frames to obtain UART data frames. Based on the header information, it searches a channel mapping table to determine the UART channel ID set and, based on a dynamic priority arbitration mechanism, transmits the UART data frames through the UART interface according to the UART channel ID set and preset configuration parameters. This FPGA-based UDP to multi-channel UART protocol conversion method provides multi-channel expansion and employs a dynamic priority arbitration mechanism to ensure the real-time performance and reliability of data transmission.

[0124] Exemplary device

[0125] Figure 2 This is a structural block diagram of the FPGA-based UDP protocol to multi-channel UART protocol conversion device provided by the present invention. Figure 2 As shown, the present invention also provides an FPGA-based UDP protocol to multi-channel UART protocol conversion device, which includes: a UDP protocol parsing module 21, a UDP verification module 22, a first buffer module 23, an application layer protocol parsing module 24, a second buffer module 25, a UART encapsulation module 26, and a channel management module 27; wherein,

[0126] UDP protocol parsing module 21 is used to receive and parse UDP datagrams to obtain pseudo header information and header information;

[0127] The UDP verification module 22 is connected to the UDP protocol parsing module 21 and is used to verify the UDP datagram based on the pseudo header information and the header information to obtain the verification result.

[0128] The first caching module 23 and the UDP verification module 22 are used to cache UDP datagrams according to the verification results to obtain UDP cached data.

[0129] The application layer protocol parsing module 24 is connected to the first cache module 23 and is used to parse the UDP cached data using the application layer protocol to obtain the corresponding application layer data.

[0130] The second caching module 25 is connected to the application layer protocol parsing module 24 and is used to cache application layer data to obtain application layer cached data.

[0131] UART encapsulation module 26 is connected to the second buffer module 25 and is used to format application layer buffer data into UART frames according to a preset UART frame encapsulation format to obtain UART data frames.

[0132] The channel management module 27 is connected to the UDP protocol parsing module 21 and the UART encapsulation module 26 respectively. It is used to look up the channel mapping table based on the header information, determine the UART channel ID set, and send the UART data frame through the corresponding UART interface based on the dynamic priority arbitration mechanism, the UART channel ID set and the preset configuration parameters.

[0133] Optionally, the UDP verification module 22 is specifically used for: performing data transmission verification on the UDP datagram based on the pseudo header information and the header information; if the data transmission verification result is a failure, discarding the UDP datagram; if the data transmission verification result is a success, performing cyclic redundancy check on the UDP datagram based on the pseudo header information and the header information; if the cyclic redundancy check result is a failure, discarding the UDP datagram; if the cyclic redundancy check result is a success, buffering the UDP datagram into the first first-in-first-out queue (i.e., the first buffer module 23).

[0134] At this point, the first caching module 23 is specifically used to: cache the UDP datagram according to the verification result to obtain UDP cached data;

[0135] Optionally, the apparatus of the present invention further includes: a cache state determination module (not shown in the figure), which is connected to the first first-in-first-out queue and is used to detect whether the first first-in-first-out queue is full; if the first first-in-first-out queue is full, new UDP cache data is discarded.

[0136] Optionally, the UART encapsulation module 26 is specifically used for:

[0137] Extract the command word field and length field from the application-layer cached data;

[0138] Add a 1-byte channel identifier prefix before the command word field;

[0139] A CRC16 checksum is generated based on the encapsulated data, which includes the source port number, destination port number, total UDP length, data information, and checksum.

[0140] The channel identifier prefix, command word field, length field, data information, and CRC16 checksum are encapsulated into a serial frame format to obtain a UART data frame. The UART data frame includes, in sequence, a start bit, a channel identifier prefix, a command word field, a length field, data information, a CRC16 checksum, and a stop bit.

[0141] Optionally, the channel management module 27 is further used for:

[0142] Based on the destination port number in the header information, look up the channel mapping table, determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set. The preset configuration parameters include basic priority, basic wait count and basic baud rate.

[0143] Detect the current request parameters of each UART channel in the UART channel ID set, where the current request parameters include the current wait count, the current channel baud rate, and the current pointer;

[0144] Calculate the effective priority for each UART channel in the UART channel ID set, where effective priority = base priority - wait boost value - baud rate boost value, wait boost value = current wait count / base wait count, and baud rate boost value = current channel baud rate / base baud rate.

[0145] Select the minimum value among the valid priorities corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer;

[0146] After identifying the target UART channel, the current pointer is reset to the target UART channel's channel ID incremented by 1, and the target UART channel's current wait count is reset to zero, awaiting the next round of priority arbitration.

[0147] It should be noted that, Figure 2 The device and Figure 1 The corresponding methods described can be explained by referring to each other. Furthermore... Figure 2 The device described can be implemented using a field-programmable gate array (FPGA).

[0148] This invention discloses an FPGA-based UDP-to-multichannel UART protocol conversion device. The UDP protocol parsing module receives and parses UDP datagrams, obtaining pseudo-header information and header information. The UDP verification module performs data verification on the UDP datagrams based on the pseudo-header information and header information, obtaining a verification result. A first buffer module buffers the UDP datagrams based on the verification result, obtaining UDP buffered data. An application layer protocol parsing module performs application layer protocol parsing on the UDP buffered data, obtaining the corresponding application layer data. A second buffer module buffers the application layer data, obtaining application layer buffered data. A UART encapsulation module formats the application layer buffered data into UART frames according to a preset UART frame encapsulation format, obtaining UART data frames. A channel management module looks up the channel mapping table based on the header information, determines the UART channel ID set, and, based on a dynamic priority arbitration mechanism, sends the UART data frames through the corresponding UART interface according to the UART channel ID set and preset configuration parameters. The FPGA-based UDP-to-multichannel UART protocol conversion device provided by this invention can perform multi-channel expansion and adopts a dynamic priority arbitration mechanism to ensure the real-time performance and reliability of data transmission.

[0149] Exemplary electronic devices

[0150] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. The electronic device can be any one or both of a first device and a second device, or a standalone device independent of them. This standalone device can communicate with the first and second devices to receive collected input signals from them. For example... Figure 3 As shown, the electronic device 30 includes one or more processors 31 and memory 32.

[0151] The processor 31 may be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0152] The memory 32 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 31 may execute the program instructions to implement the methods for determining the actual controller and / or other desired functions of the software programs of the various embodiments of this disclosure described above. In one example, the electronic device may also include an input device 33 and an output device 34, these components being interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0153] In addition, the input device 33 may also include, for example, a keyboard, a mouse, etc.

[0154] The output device 34 can output various information to the outside. The output device 34 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0155] Of course, for the sake of simplicity, Figure 3 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0156] Exemplary computer program products and storage media

[0157] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods for determining an actual controller according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0158] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0159] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods for determining an actual controller according to various embodiments of this disclosure as described in the "Exemplary Methods" section above.

[0160] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0161] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0162] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0163] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0164] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0165] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps are decomposable and / or recombinable. Such decomposition and / or recombination should be considered equivalent to the present disclosure. The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0166] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for converting UDP protocol to multi-channel UART protocol based on FPGA, characterized in that, The method includes: Receive and parse UDP datagrams to obtain pseudo header information and header information; Based on the pseudo header information and the header information, the UDP datagram is validated to obtain the validation result. Based on the validation result, the UDP datagram is cached to obtain UDP cached data. The UDP cached data is parsed using application layer protocols to obtain the corresponding application layer data; Cache the application layer data to obtain the application layer cached data; According to the preset UART frame encapsulation format, the application layer cached data is formatted into UART frames to obtain UART data frames; Based on the header information, the channel mapping table is searched to determine the UART channel ID set. Then, based on the dynamic priority arbitration mechanism, the UART data frame is sent through the corresponding UART interface according to the UART channel ID set and the preset configuration parameters. The step of looking up the channel mapping table based on the header information, determining the UART channel ID set, and sending the UART data frame through the corresponding UART interface based on the dynamic priority arbitration mechanism, according to the UART channel ID set and preset configuration parameters, includes: Based on the destination port number in the header information, look up the channel mapping table, determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set. The preset configuration parameters include basic priority, basic wait count and basic baud rate. Detect the current request parameters of each UART channel in the UART channel ID set, where the current request parameters include the current wait count, the current channel baud rate, and the current pointer; Calculate the effective priority for each UART channel in the UART channel ID set, where effective priority = base priority - wait boost value - baud rate boost value, wait boost value = current wait count / base wait count, and baud rate boost value = current channel baud rate / base baud rate. Select the minimum value among the valid priorities corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer; After identifying the target UART channel, the current pointer is reset to the target UART channel's channel ID incremented by 1, and the target UART channel's current wait count is reset to zero, awaiting the next round of priority arbitration.

2. The method according to claim 1, characterized in that, The pseudo header information includes: source IP address, destination IP address, UDP protocol number and UDP length; the header information includes source port number, destination port number, total UDP length, data information and checksum.

3. The method according to claim 1, characterized in that, The process of performing data verification on UDP datagrams based on pseudo-header information and header information, obtaining verification results, and then buffering UDP datagrams based on the verification results to obtain UDP buffered data includes: Data transmission verification is performed on UDP datagrams based on the pseudo header information and the header information; If the data transmission verification result is a failure, the UDP datagram is discarded; If the data transmission verification result is successful, perform cyclic redundancy check on the UDP datagram based on the pseudo header information and the header information. If the cyclic redundancy check fails, the UDP datagram is discarded. If the cyclic redundancy check (CRC) passes the check, the UDP datagram is cached in the first FIFO queue, and the UDP cached data is obtained.

4. The method according to claim 3, characterized in that, After buffering the UDP datagram into the first first-in-first-out queue and obtaining the buffered UDP data, the process further includes: Check if the first first-in-first-out queue is full; If the first FIFO queue is full, discard new UDP buffered data.

5. The method according to claim 1, characterized in that, The step of formatting the application layer cached data into UART data frames according to a preset UART frame encapsulation format includes: Extract the command word field and length field from the application-layer cached data; Add a 1-byte channel identifier prefix before the command word field; A CRC16 checksum is generated based on the encapsulated data, which includes the source port number, destination port number, total UDP length, data information, and checksum. The channel identifier prefix, command word field, length field, data information, and CRC16 checksum are encapsulated into a serial frame format to obtain a UART data frame. The UART data frame includes, in sequence, a start bit, a channel identifier prefix, a command word field, a length field, data information, a CRC16 checksum, and a stop bit.

6. A FPGA-based UDP protocol to multi-channel UART protocol conversion device, characterized in that, The device includes: a UDP protocol parsing module, a UDP verification module, a first buffer module, an application layer protocol parsing module, a second buffer module, a UART encapsulation module, and a channel management module; wherein, The UDP protocol parsing module is used to receive and parse UDP datagrams to obtain pseudo header information and header information; The UDP verification module is connected to the UDP protocol parsing module and is used to verify the UDP datagram based on the pseudo header information and the header information to obtain the verification result. The first caching module and the UDP verification module are used to cache UDP datagrams based on the verification results to obtain UDP cached data. The application layer protocol parsing module is connected to the first cache module and is used to parse the UDP cached data using the application layer protocol to obtain the corresponding application layer data. The second caching module is connected to the application layer protocol parsing module and is used to cache application layer data to obtain application layer cached data. The UART encapsulation module is connected to the second buffer module and is used to format the application layer buffer data into UART frames according to the preset UART frame encapsulation format to obtain UART data frames. The channel management module is connected to the UDP protocol parsing module and the UART encapsulation module respectively. It is used to look up the channel mapping table based on the header information, determine the UART channel ID set, and send the UART data frame through the corresponding UART interface based on the dynamic priority arbitration mechanism, the UART channel ID set and the preset configuration parameters. The channel management module is further used for: Based on the destination port number in the header information, look up the channel mapping table, determine the UART channel ID set, and obtain the channel ID and preset configuration parameters corresponding to each UART channel in the UART channel ID set. The preset configuration parameters include basic priority, basic wait count and basic baud rate. Detect the current request parameters of each UART channel in the UART channel ID set, where the current request parameters include the current wait count, the current channel baud rate, and the current pointer; Calculate the effective priority for each UART channel in the UART channel ID set, where effective priority = base priority - wait boost value - baud rate boost value, wait boost value = current wait count / base wait count, and baud rate boost value = current channel baud rate / base baud rate. Select the minimum value among the valid priorities corresponding to each UART channel in the UART channel ID set, and determine the target UART channel based on the current pointer; After identifying the target UART channel, the current pointer is reset to the target UART channel's channel ID incremented by 1, and the target UART channel's current wait count is reset to zero, awaiting the next round of priority arbitration.

7. An electronic device, characterized in that, include: A memory on which computer programs are stored; A processor for executing the computer program in the memory to implement the steps of the method according to any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the method described in any one of claims 1-5.

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