Dynamic random access memory device

Abstract

A dynamic random access memory device includes a substrate, a plurality of bit lines, a plurality of contacts, a dielectric layer, a plurality of memory node pads, and a capacitor structure. The bit lines are arranged on the substrate and comprise a plurality of first bit lines and a second bit line. The contacts are disposed on the substrate and alternately and separately disposed with the bit lines. The dielectric layer covers the contacts and the bit lines. The storage node pads are disposed within the dielectric layer and contact the contacts, respectively. The capacitor structure is arranged on the storage node bonding pad and comprises a plurality of first bottom electrode layers and at least one second bottom electrode layer located above the right vertical projection direction of the second bit line. Therefore, the dynamic random access memory device can achieve more optimized element efficiency.

Description

[0001] This application is a divisional application of Chinese patent CN202111452104.2, whose application date is December 1, 2021, and whose name is “Dynamic random access memory device and formation method thereof”. Technical Field

[0002] The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device including a dynamic random access memory. Background Art

[0003] As various electronic products continue to miniaturize, the design of semiconductor memory devices must also meet the requirements of high integration and density. Dynamic random access memory (DRAM) with a recessed gate structure is currently replacing planar gate DRAM, as it allows for a longer carrier channel length within the same semiconductor substrate, thereby reducing leakage in the capacitor structure.

[0004] Generally speaking, a dynamic random access memory (DRAM) with a recessed gate structure consists of a large number of memory cells clustered together in an array area to store information. Each memory cell may be composed of a transistor and a capacitor connected in series to receive voltage information from a wordline (WL) and a bitline (BL). To meet product requirements, the density of memory cells in the array area must continue to increase, resulting in increasing difficulty and complexity in the related manufacturing process and design. Therefore, existing technologies need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0005] One object of the present invention is to provide a dynamic random access memory device and a method for forming the same, wherein a storage node pad is formed on a substrate through a self-aligned double patterning process or a self-aligned reverse patterning process. In this way, the subsequently formed capacitor structure can include at least a portion of the capacitor being located on a dummy bit line, forming a dummy capacitor. Under this arrangement, a dynamic random access memory device can be formed while simplifying the manufacturing process, and the dummy capacitor can be isolated from the surrounding active components through the arrangement of the dummy capacitor, thereby achieving the effect of optimizing the overall device performance.

[0006] To achieve the above-mentioned purpose, one embodiment of the present invention provides a dynamic random access memory device, comprising a substrate, a plurality of bit lines, a plurality of contacts, a dielectric layer, a plurality of storage node pads, and a capacitor structure. The bit lines are arranged on the substrate, including a plurality of first bit lines and a second bit line, and the second bit line is arranged outside all the first bit lines. The contacts are arranged on the substrate and are arranged alternately and separately with the bit lines. The dielectric layer covers the contacts and the bit lines. The storage node pads are arranged in the dielectric layer and contact the contacts respectively. The capacitor structure is arranged on the storage node pads, including a plurality of first bottom electrode layers respectively located opposite to the storage node pads, and at least one second bottom electrode layer located above the positive vertical projection direction of the second bit line; the line width of the second bit line is greater than the line width of the first bit line.

[0007] To achieve the above-mentioned object, one embodiment of the present invention provides a dynamic random access memory device, comprising: a substrate having a plurality of insulating regions formed therein, the insulating regions defining a plurality of active regions; a plurality of bit lines disposed on the substrate, the plurality of bit lines extending along a first direction and separated from each other in a second direction, the first direction and the second direction being perpendicular to each other, the bit lines comprising a plurality of first bit lines and a second bit line disposed outside all of the first bit lines; a plurality of contacts disposed on the substrate and arranged alternately and separately from the bit lines; The bit lines respectively include a conductive layer and a cover layer stacked in sequence from bottom to top; a dielectric layer covering the contacts and above the bit lines; a plurality of storage node pads arranged in the dielectric layer and respectively contacting the contacts; and a capacitor structure arranged on the storage node pads, the capacitor structure including a plurality of first bottom electrode layers respectively corresponding to the storage node pads, and at least one second bottom electrode layer located above the positive vertical projection direction of the second bit line; the bottom surface of the at least one second bottom electrode layer directly contacts the dielectric layer, and the bottom surface completely overlaps with the dielectric layer.

[0008] To achieve the above-mentioned object, one embodiment of the present invention provides a dynamic random access memory device, comprising: a substrate having a plurality of insulating regions formed therein, the insulating regions defining a plurality of active regions; a plurality of bit lines disposed on the substrate, the plurality of bit lines extending respectively in a first direction and separated from each other in a second direction, the first direction and the second direction being perpendicular to each other, the bit lines comprising a plurality of first bit lines and a second bit line, the second bit line being disposed outside all of the first bit lines; a plurality of contacts disposed on the substrate and arranged alternately and separately from the bit lines; the bit lines respectively comprising a conductive layer and a capping layer stacked sequentially from bottom to top; a dielectric layer covering the contacts and the bit lines; a plurality of storage node pads disposed in the dielectric layer and respectively contacting the contacts; and a capacitor structure disposed on the storage node pads, the capacitor structure comprising a plurality of first bottom electrode layers respectively corresponding to the storage node pads, and at least one second bottom electrode layer located above a positive vertical projection direction of the second bit line; the at least one second bottom electrode layer directly contacting the capping layer of the second bit line.

[0009] To achieve the above-mentioned objective, one embodiment of the present invention provides a dynamic random access memory device, comprising: a substrate having a plurality of insulating regions formed therein, the insulating regions defining a plurality of active regions; a bit line disposed on the substrate, the bit line extending across the plurality of insulating regions and the plurality of active regions; the bit line comprising a conductive layer and a cap layer stacked sequentially from bottom to top; a dielectric layer covering the bit line; and a plurality of capacitor structures disposed on the bit line and the dielectric layer, wherein the plurality of capacitor structures each comprise a bottom electrode layer, and the bottom surfaces of at least three consecutively arranged bottom electrode layers are in direct contact with the dielectric layer and completely overlap with the dielectric layer.

[0010] To achieve the above-mentioned purpose, one embodiment of the present invention provides a dynamic random access memory device, comprising: a substrate, wherein a plurality of insulating regions are formed in the substrate, wherein the insulating regions define a plurality of active regions; a plurality of contacts, which are arranged separately on the substrate; a dielectric layer, which covers the contacts; a plurality of storage node pads, which are arranged in the dielectric layer and respectively contact the contacts; and a capacitor structure, which is arranged on the storage node pads, wherein the capacitor structure includes a plurality of first bottom electrode layers, which are respectively located opposite to the storage node pads and electrically connected to the storage node pads, and a second bottom electrode layer, which is located outside the remaining first bottom electrode layers, and the second bottom electrode layer is electrically insulated and isolated from the storage node pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 9 Schematic diagram of the steps of a method for forming a semiconductor memory device according to a first embodiment of the present invention, wherein:

[0012] Figure 1 is a schematic top view of a semiconductor memory device after bit lines are formed;

[0013] Figure 2 for Figure 1 Schematic diagram of the cross section along the tangent line A-A';

[0014] Figure 3 is a schematic top view of a semiconductor memory device after a self-aligned double patterning process is performed;

[0015] Figure 4 for Figure 3 Schematic diagram of the cross section along the tangent line A-A';

[0016] Figure 5 is a schematic cross-sectional view of a semiconductor memory device after forming a storage node pad;

[0017] Figure 6 is a schematic cross-sectional view of a semiconductor memory device after forming a stacked structure;

[0018] Figure 7 is a schematic cross-sectional view of a semiconductor memory device after forming a bottom electrode layer;

[0019] Figure 8 is a schematic cross-sectional view of a semiconductor memory device after forming a top electrode layer; and

[0020] Figure 9 Another cross-sectional schematic diagram of a semiconductor memory device after forming a top electrode layer.

[0021] Figure 10 FIG. 1 is a cross-sectional diagram of a semiconductor memory device according to a second embodiment of the present invention.

[0022] Figure 11 FIG. 1 is a schematic cross-sectional view of a semiconductor memory device according to a third embodiment of the present invention.

[0023] Figure 12 FIG. 1 is a cross-sectional view of a semiconductor memory device according to a fourth embodiment of the present invention. The reference numerals are described as follows:

[0024] 300, 400, 500, 600 semiconductor storage devices

[0025] 100 substrate

[0026] 101 Insulation Zone

[0027] 103 active area

[0028] 130 dielectric layer

[0029] 131 oxide layer

[0030] 133 Nitride layer

[0031] 135 oxide layer

[0032] 160 bit lines

[0033] 160a Bit line contact

[0034] 161 semiconductor layer

[0035] 162 First Line

[0036] 163 Barrier Layer

[0037] 164 Second bit line

[0038] 165 conductive layer

[0039] 167 cap layer

[0040] 170 spacer structure

[0041] 171 First spacer

[0042] 173 Second spacer

[0043] 175 Third interspace wall

[0044] 180 contacts

[0045] 182 First Contact

[0046] 184 Second contact

[0047] 210 Metal Layer

[0048] 211 Storage node pad

[0049] 221, 223 patterned mask

[0050] 230 dielectric layer

[0051] 240 Support layer structure

[0052] 241 First Support Layer

[0053] 242 First Opening

[0054] 243 Second Support Layer

[0055] 244 The Third Opening

[0056] 245 Third Support Layer

[0057] 246 Second Opening

[0058] 247 Fourth Support Layer

[0059] 250, 450, 550, 650 capacitor structures

[0060] 250a, 650a first capacitor

[0061] 250b, 450b, 550b, 650b second capacitor

[0062] 250c, 650c third capacitor

[0063] 251 bottom electrode layer

[0064] 253 capacitor dielectric layer

[0065] 255 top electrode layer

[0066] D1 First direction

[0067] D2 Second direction

[0068] D3 third direction

[0069] W1, W2 line width DETAILED DESCRIPTION

[0070] To help those skilled in the art further understand the present invention, several preferred embodiments of the present invention are listed below, along with the accompanying drawings, to provide a detailed description of the present invention's components and intended functions. Those skilled in the art can, without departing from the spirit of the present invention, refer to the following embodiments and replace, reorganize, or combine features from the various embodiments to create other embodiments.

[0071] Please refer to Figures 1 to 8 , which is a schematic diagram of the steps of the method for forming the semiconductor memory device 300 in the first embodiment of the present invention. First, Figure 1 As shown, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.) or a silicon-on-insulator (SOI) substrate. At least one insulating region 101 is formed in the substrate 100, such as a shallow trench isolation (STI), and a plurality of active areas (AA) 103 are defined on the substrate 100. Preferably, the active areas 103 extend parallel to each other and spaced apart from each other along a first direction D1, and are alternately arranged, wherein the first direction D1 intersects and is not perpendicular to the y-direction or the x-direction, for example. Figure 1In one embodiment, the insulating region 101 is formed by, for example, first forming a plurality of trenches (not shown) in the substrate 100 by etching, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride), but the present invention is not limited thereto.

[0072] In addition, a plurality of buried gates (not shown) may be formed in the substrate 100. The buried gates may extend parallel to each other along a direction (e.g., the y-direction) and cross the active region 103 to serve as buried word lines (BWL, not shown) of the semiconductor memory device 300. A plurality of bit lines 160 and a plurality of contacts 180 ( Figure 1 (not shown), the bit lines 160 extend in another direction perpendicular to the aforementioned direction (e.g., the x-direction) and intersect with the active area 103. Although the buried gates are not specifically depicted in the drawings of this embodiment, those skilled in the art will readily understand that, from a top view, the bit lines 160 extending in the x-direction should be perpendicular to the buried gates extending in the y-direction and intersect with both the active area 103 and the buried gates.

[0073] like Figure 1 As shown, the bit lines 160 further include a plurality of first bit lines 162 and at least one second bit line 164. The first bit lines 162 and the second bit lines 164 are, for example, respectively disposed in a memory cell region (not shown) and a peripheral region (not shown) of the semiconductor memory device 300, and may serve as normal bit lines (BLs) and dummy bit lines (dummy BLs), respectively. The second bit line 164 may be located on one side of all first bit lines 162, but is not limited thereto. It will be readily understood by those skilled in the art that, depending on actual device requirements, the memory cell region and the peripheral region may also have other configurations, resulting in other configurations of the first bit lines and the second bit lines, or other number of second bit lines. For example, in one embodiment, the semiconductor memory device preferably includes two second bit lines, one disposed on opposite sides (i.e., upper and lower sides) of all first bit lines 162 to isolate them from other external components. Furthermore, in this embodiment, the line width (e.g., the width in the y-direction) W2 of each second bit line 164 is preferably greater than the line width W1 of each first bit line 162, but the present invention is not limited thereto. In another embodiment, the second bit lines and the first bit lines may also have the same line width.

[0074] In detail, Figure 2As shown, each bit line 160 is formed on a substrate 100 in a spaced-apart manner and includes a semiconductor layer (e.g., polysilicon) 161, a barrier layer 163 (e.g., titanium and / or titanium nitride), a conductive layer 165 (e.g., a low-resistivity metal such as tungsten, aluminum, or copper), and a capping layer 167 (e.g., silicon oxide, silicon nitride, or silicon oxynitride), stacked in sequence. It should be noted that a portion of the first bit line 162 is formed on a dielectric layer 130 above the substrate 100. The dielectric layer 130 preferably has a composite layer structure, such as, but not limited to, an oxide layer 131-nitride layer 133-oxide layer 135 (oxide-nitride-oxide, ONO) structure. A bit line contact (BLC) 160a is further formed below the other portion of the first bit line 162, extending into the substrate 100 and directly contacting the substrate 100 (active area 103) below. Furthermore, the bit line contact 160a is, for example, formed integrally with the semiconductor layer 161 of the first bit line 162 of the other portion. Figure 2 As shown. On the other hand, each contact 180 is also formed on the substrate 100 in a spaced-apart manner and is alternately arranged with the bit lines 160. Furthermore, each contact 180 is insulated from each bit line 160 by a spacer structure 170. In one embodiment, the spacer structure 170 may selectively have a single-layer structure or a plurality of layers. Figure 2 The composite layer structure shown includes, for example, a first spacer 171 (e.g., comprising silicon nitride), a second spacer 173 (e.g., comprising silicon oxide), and a third spacer 174 (e.g., comprising silicon nitride) stacked in sequence, but is not limited thereto. Furthermore, the contact 180 further includes a plurality of first contacts 182 and a plurality of second contacts 184 arranged alternately with each other. These contacts 180 are disposed within the storage region of the semiconductor memory device 300 and directly contact the underlying substrate 100 (including the active region 103 and the insulating region 101) to serve as storage node contacts (SNCs) of the semiconductor memory device 300. In one embodiment, the contact 180 includes, for example, a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W).

[0075] Next, a plurality of storage node pads (SN pads) 211 are formed on the substrate 100. The formation of the storage node pads 211 is, for example, through a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but is not limited thereto. Figure 3 as well as Figure 4 As shown, a metal layer 210 is first formed above the contact 180 and the bit line 160. The metal layer 210 includes, for example, a low-resistance metal material such as aluminum, titanium, copper, or tungsten, preferably a metal material different from the contact 180, but not limited thereto. Then, at least two self-aligned double patterning processes are sequentially performed to form a plurality of patterned masks 221 extending in parallel along a second direction D2 on the metal layer 210, and a plurality of patterned masks 223 extending in parallel along a second direction D3 on the metal layer 210. The second direction D2 and the second direction D3 intersect with each other and are not perpendicular to the y direction or the x direction, for example, the angle between the second direction D2 or the second direction D3 and the y direction or the x direction is, for example, approximately 60 to 120 degrees. Figure 3 Then, the relative position of the storage node pad 211 is defined by the overlapping portion of the patterned mask 221 and the patterned mask 223, and a mask is formed as an etching mask to perform an etching process to pattern the metal layer 210 below. In this way, the storage node pad 211 can be formed, such as Figure 5 It should be noted that in this embodiment, by controlling the overlap between patterned mask 221 and patterned mask 223, storage node pad 211 is formed above contact 180 and bit line 160, selectively only above each first contact 182. In other words, storage node pad 211 is not formed above each second contact 184.

[0076] Subsequently, a capacitor structure 250 may be formed on the storage node pad 211 to directly contact and electrically connect the storage node pad 211 below. In one embodiment, the manufacturing process of the capacitor structure 250 includes but is not limited to the following steps. First, as shown in FIG. Figure 6As shown, a dielectric layer 230 and a supporting layer structure 240 are formed above the substrate 100. The dielectric layer 230 covers the contacts 180 (including the first contact 182 and the second contact 184) and the bit line 160. The thickness of the dielectric layer 230 is preferably greater than the thickness of the storage node pad 211, so that the storage node pad 211 can be located within the dielectric layer 230. The supporting layer structure 240, for example, includes at least one oxide layer and at least one nitride layer stacked alternately. In this embodiment, the supporting layer structure 240 includes, for example, a first supporting layer 241 (for example, comprising silicon oxide), a second supporting layer 243 (for example, comprising silicon nitride or silicon carbonitride), a third supporting layer 245 (for example, comprising silicon oxide), and a fourth supporting layer 247 (for example, comprising silicon nitride or silicon carbonitride), stacked in order from bottom to top, but the present invention is not limited thereto. Preferably, the first supporting layer 241 and the third supporting layer 245 can have a relatively large thickness, for example, approximately 5 to 10 times greater than the thickness of the other supporting layers (the second supporting layer 243 or the fourth supporting layer 247), but not limited thereto. This allows the overall thickness of the supporting layer structure 240 to reach approximately 1600 to 2000 angstroms, but not limited thereto. Those skilled in the art will appreciate that the specific number of oxide layers (such as the first supporting layer 241 or the third supporting layer 245) and nitride layers (such as the second supporting layer 243 or the fourth supporting layer 247) stacked is not limited to the aforementioned number and can be adjusted based on actual needs, such as 3, 4, or other numbers. Subsequently, a plurality of first openings 242, at least one second opening 246, and a plurality of third openings 244 are formed within the supporting layer structure 240, each of which sequentially penetrates the fourth supporting layer 247, the third supporting layer 245, the second supporting layer 243, the first supporting layer 241, and a portion of the dielectric layer 230. The first openings 242 and the third openings 244 are alternately arranged in the storage region, wherein the first openings 242 are respectively aligned with the storage node pads 211 (and the first contacts 182) located below, so that the top surfaces of the storage node pads 211 can be exposed from the first openings 242; the third openings 244 are respectively aligned with the second contacts 184 located below, but because the bottom surfaces of the third openings 244 are lower than the top surface of the dielectric layer 230 but do not penetrate the dielectric layer 230, only a portion of the dielectric layer 230 is exposed from the third openings 244. The second openings 246 are arranged outside all the first openings 242 and all the third openings 244, and are aligned with the second bit lines 164 located in the peripheral region. The second openings 246 also do not penetrate the dielectric layer 230, but only expose a portion of the dielectric layer 230, as shown in FIG. Figure 6 shown.

[0077] Then, if Figure 7As shown, a bottom electrode layer 251 is formed to fill the first opening 242, the third opening 244, and the second opening 246, respectively. The bottom electrode layer 251 comprises, for example, a low-resistance metal material such as aluminum, titanium, copper, or tungsten, preferably titanium, but not limited thereto. It should be noted that the bottom electrode layer 251 disposed in the first opening 242 is in direct contact with the storage node pad 211 below; while the bottom electrode layer 251 disposed in the third opening 244 and the second opening 246 is in direct contact with the dielectric layer 230, and is located directly above the second contact 184 and the second bit line 164, respectively. For example Figure 7 As shown, after the bottom electrode layer 251 is formed, an etching process is performed through a mask layer (not shown) to completely remove the oxide layer (such as the first supporting layer 241 or the third supporting layer 245) in the supporting layer structure 240, and partially remove the nitride layer (such as the second supporting layer 243 or the fourth supporting layer 247) in the supporting layer structure 240.

[0078] Subsequent, such as Figure 8 As shown, a capacitor dielectric layer 253 and a top electrode layer 255 are sequentially formed on the bottom electrode layer 251. Parts of the capacitor dielectric layer 253 and the top electrode layer 255 may be further filled between the remaining second support layer 243 and the fourth support layer 247, and between the remaining second support layer 243 and the dielectric layer 230. In one embodiment, the capacitor dielectric layer 253 comprises a high-k dielectric material selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), titanium oxide (TiO2), and zirconium oxide-aluminum oxide-zirconium oxide (ZAZ), preferably zirconium oxide-aluminum oxide-zirconium oxide; and the top electrode layer 255 comprises a low-resistance metal material such as aluminum, titanium, copper, or tungsten, preferably titanium, but not limited thereto.

[0079] In this way, the manufacturing process of the capacitor structure 250 is completed. The capacitor structure 250 includes a bottom electrode layer 251, a capacitor dielectric layer 253 and a top electrode layer 255 stacked in sequence, which can form a plurality of vertically extending capacitors 250a, 250b, and 250c. It should be noted that the capacitor structure 250 includes a plurality of first capacitors 250a and a plurality of third capacitors 250c. The first capacitors 250a and the third capacitors 250c are alternately and separately arranged to correspond to the first contact 182 and the second contact 184 respectively. Among them, each first capacitor 250a can be electrically connected to the transistor element (not shown) of the semiconductor memory device 300 through the storage node pad 211 below and the storage node plug (i.e., the first contact 182). Thereby, the first capacitor 250a can serve as the storage node (SN) of the semiconductor memory device 300, so that a good contact relationship can be maintained between the capacitor structure 250 and the transistor element. On the other hand, each third capacitor 250c does not have a storage node pad 211 disposed thereunder, and thus cannot be electrically connected to the storage node plug (i.e., contact 184) thereunder. The bottom surface of the third capacitor 250c (i.e., the bottom surface of the bottom electrode layer 251 that fills the second opening 246) only contacts the dielectric layer 230, thereby forming a disconnection and becoming a dummy storage node (dummy SN), isolating the adjacent storage nodes to maintain overall device performance. The bottom surface of the third capacitor 250c is lower than the top surface of the dielectric layer 230, as shown in FIG. Figure 8 shown.

[0080] It should also be noted that the capacitor structure 250 also includes at least one second capacitor 250b, under which there is also no storage node pad 211, and at least one second capacitor 250b is located outside all the first capacitors 250a and all the third capacitors 250c, facing the second bit line 164 located in the peripheral area. In this way, the bottom surface of at least one second capacitor 250b (i.e., the bottom surface of the bottom electrode layer 251 that fills the third opening 244) also directly contacts the dielectric layer 230 to form a short circuit, thereby becoming the virtual storage node to isolate the adjacent storage node. Although Figure 8 The cross-sectional diagram shown only depicts one second capacitor 250b located on the second bit line 164. However, those skilled in the art will readily appreciate that a cross-sectional diagram along other directions may show multiple second capacitors 250b located on the second bit line 164, such as a cross-sectional diagram along the extending direction of the second bit line 164. Figure 9Thus, the semiconductor memory device 300 of this embodiment can form a dynamic random access memory (DRAM) device, wherein at least one transistor element and at least one first capacitor 250a constitute a minimum component unit (memory cell) in a dynamic random access memory array to receive voltage information from the bit line 160 and the buried word line.

[0081] Thus, the semiconductor memory device 300 according to the first embodiment of the present invention is completed. According to the formation method of this embodiment, the storage node pad 211 is formed by controlling the overlap between the patterned mask 221 and the patterned mask 223, so that the storage node pad 211 is only disposed above the first contact 182 and not above the second contact 184. Thus, after forming the capacitor structure 250, a first capacitor 250a serving as a storage node and a second capacitor 250b and / or a third capacitor 250c serving as dummy storage nodes are formed. The storage node (i.e., the first capacitor 250a) is electrically connected to a transistor element (not shown) of the semiconductor memory device 300 via the underlying storage node pad 211 and the storage node plug (i.e., the first contact 182). However, the dummy storage nodes (i.e., the second capacitor 250b and / or the third capacitor 250c) do not have the storage node pad 211 disposed thereunder and are therefore unable to electrically connect to the underlying storage node plug (i.e., the second contact 184). The provision of the dummy storage nodes stabilizes and improves the performance of the storage nodes and isolates adjacent storage nodes to maintain the overall device performance of the semiconductor memory device 300.

[0082] In addition, those skilled in the art should be able to easily understand that, in order to meet the actual product requirements, the semiconductor memory device formed by the present invention and the method for forming the same may also have other aspects, not limited to the above. For example, the virtual storage node may also be selected to have other setting aspects. The following will further describe other embodiments or variations of the method for the semiconductor memory device in the present invention. And to simplify the description, the following description mainly details the differences between the various embodiments, and will not repeat the same parts. In addition, the same components in the various embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the various embodiments.

[0083] Please refer to Figure 10, which illustrates a schematic diagram of the steps of a method for forming a semiconductor memory device 400 according to a second embodiment of the present invention. The front-end formation steps of the semiconductor memory device 400 in this embodiment are generally the same as the front-end formation steps of the semiconductor memory device 300 in the first embodiment described above, and are not further described here. The primary difference between this embodiment and the first embodiment described above is that at least one second capacitor 450b penetrates the dielectric layer 230 and can directly contact the cap layer 167 of the second bit line 164.

[0084] Specifically, the formation method of this embodiment is to further control the etching process conditions when forming the opening in the support layer structure 240, so as to selectively make the second opening (not shown) corresponding to the second bit line 164 penetrate the dielectric layer 230 and stop at the top surface of the cap layer 167 of the second bit line 164. In this way, the cap layer 167 of the second bit line 164 can be exposed from the second opening. Subsequently, the bottom electrode layer 251, the capacitor dielectric layer 253 and the top electrode layer 255 are formed in sequence to form the following. Figure 10 In the illustrated capacitor structure 450, at least one second capacitor 450b extends into the dielectric layer 230 and directly contacts the top surface of the cap layer 167 of the second bit line 164 through the bottom electrode layer 251, corresponding to the second bit line 164 located in the peripheral region. Thus, the at least one second capacitor 450b only contacts the dielectric layer 230 and the cap layer 167, forming a disconnect circuit and thereby serving as the dummy storage node. With this configuration, the semiconductor memory device 400 of this embodiment can also form a dynamic random access memory device, isolating adjacent storage nodes through the second capacitor 450b and the third capacitor 250c to maintain overall device performance.

[0085] Please refer to Figure 11 , which illustrates a schematic diagram of the steps of a method for forming a semiconductor memory device 500 according to a third embodiment of the present invention. The steps for forming the front end of the semiconductor memory device 500 in this embodiment are generally the same as the steps for forming the front end of the semiconductor memory device 300 in the first embodiment described above, and are not further described here. The primary difference between this embodiment and the first embodiment described above is that at least one second capacitor 550b penetrates the dielectric layer 230 and further extends into a portion of the cap layer 167 of the second bit line 164.

[0086] In detail, the formation method of this embodiment is to further control the etching process conditions when forming the opening in the support layer structure 240, and selectively make the second opening (not shown) corresponding to the second bit line 164 pass through the dielectric layer 230 and the portion of the cap layer 167 of the second bit line 164, so that the second opening can extend into a portion of the cap layer 167. In other words, the bottom surface of the second opening can be lower than the top surface of the second bit line 164, and the portion of the cap layer 167 can be exposed from the second opening. Subsequently, the bottom electrode layer 251, the capacitor dielectric layer 253 and the top electrode layer 255 are formed in sequence to form the following. Figure 11 In the illustrated capacitor structure 550, at least one second capacitor 550b directly contacts the second bit line 164 located in the peripheral region, extending through its bottom electrode layer 251 into the portion of the cap layer 167. Thus, the bottom surface of the at least one second capacitor 550b (i.e., the bottom surface of the bottom electrode layer 251 that fills the second opening) can be lower than the top surface of the second bit line 164. The at least one second capacitor 550b only contacts the cap layer 167, forming a disconnection and thereby serving as the dummy storage node. With this configuration, the semiconductor memory device 500 of this embodiment can also form a dynamic random access memory device, isolating adjacent storage nodes through the second capacitor 550b and the third capacitor 250c to maintain overall device performance.

[0087] Please refer to Figure 12 , which illustrates a schematic diagram of the steps of a method for forming a semiconductor memory device 600 according to a fourth embodiment of the present invention. The steps for forming the front end of the semiconductor memory device 600 in this embodiment are generally the same as the steps for forming the front end of the semiconductor memory device 300 in the first embodiment, and are not further described herein. The primary difference between this embodiment and the first embodiment is that at least one second capacitor 650b is located simultaneously above a portion of the second bit line 164 and a portion of the contact 180.

[0088] In detail, Figure 12 As shown, the formation method of this embodiment is to form the storage node pads 211 so that each storage node pad 211 only partially overlaps the first contact 182 below, so as to gain a larger process space. Subsequently, the bottom electrode layer 251, the capacitor dielectric layer 253 and the top electrode layer 255 are formed in sequence to form the following. Figure 12The capacitor structure 650 shown. In this way, each storage node pad 211 can be simultaneously located above a portion of the first contact 182, the spacer structure 170 and a portion of the first bit line 162, and the subsequently formed first capacitor 650a can also be simultaneously located above a portion of the first contact 182, the spacer structure 170 and the first bit line 162, and the third capacitor 650c can be simultaneously located above a portion of the second contact 184, the spacer structure 170 and the first bit line 162. In addition, the second capacitor 650b located in the peripheral area can be simultaneously located above a portion of the second contact 184, the spacer structure 170 and the second bit line 164. It should be noted that in this embodiment, the etching process conditions can be further controlled to selectively allow the opening (not shown) located in the peripheral area to only penetrate a portion of the dielectric layer 230, so that the bottom surface of the second capacitor 650b (i.e., the bottom surface of the bottom electrode layer 251 that fills the opening) only contacts the dielectric layer 230, as shown in FIG. Figure 12 Under this configuration, the semiconductor memory device 600 of this embodiment can also form a dynamic random access memory device, and isolate the adjacent storage nodes through the second capacitor 650b and the third capacitor 650c to maintain the overall device performance.

[0089] In general, the present invention forms storage node pads on a substrate through a self-aligned double patterning process or a self-aligned reverse patterning process. By controlling the overlapping portions of the patterning masks, the storage node pads are formed only on a portion of the contacts. Thus, after forming the capacitor structure, a first capacitor that can serve as a storage node and a second capacitor that serves as a dummy storage node can be respectively formed. The storage node (i.e., the first capacitor) is electrically connected to a transistor element (not shown) of a semiconductor memory device through the storage node pad and storage node plug (i.e., the contact) below. The dummy storage node (i.e., the second capacitor) does not have a storage node pad disposed below it, but directly contacts a cap layer of a dummy bit line, and therefore cannot be electrically connected to the storage node plug (i.e., the contact). This isolates the adjacent storage nodes, thereby maintaining the overall device performance of the semiconductor memory device.

[0090] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A dynamic random access memory device, characterized in that: include: a substrate having a plurality of insulating regions formed therein, wherein the insulating regions define a plurality of active regions; a plurality of bit lines disposed on the substrate, the plurality of bit lines extending along a first direction and separated from each other in a second direction, the first direction and the second direction being perpendicular to each other, the bit lines comprising a plurality of first bit lines and a second bit line, the second bit line being disposed outside all of the first bit lines; a plurality of contacts disposed on the substrate and arranged alternately and separately from the bit lines; a dielectric layer covering the contacts and the bit lines; a plurality of storage node pads, disposed in the dielectric layer and respectively contacting the contacts; as well as a capacitor structure disposed on the storage node pad, the capacitor structure comprising a plurality of first bottom electrode layers respectively aligned with the storage node pads, and at least one second bottom electrode layer located above a positive vertical projection direction of the second bit line; The line width of the second bit line is greater than the line width of the first bit line.

2. The dynamic random access memory device according to claim 1, wherein: The bottom surface of the at least one second bottom electrode layer directly contacts the dielectric layer.

3. The dynamic random access memory device according to claim 1, wherein: The at least one second bottom electrode layer is simultaneously located above a portion of the contact and a portion of the second bit line in a positive vertical projection direction.

4. The dynamic random access memory device according to claim 1, wherein: The bit lines respectively include a conductive layer and a cap layer stacked in sequence from bottom to top, and the at least one second bottom electrode layer directly contacts the cap layer of the second bit line.

5. The dynamic random access memory device according to claim 1, wherein: A bottom surface of the at least one second bottom electrode layer is lower than a top surface of the second bit line.

6. The dynamic random access memory device according to claim 1, wherein: The capacitor structure also includes multiple third bottom electrode layers respectively corresponding to the contacts, the third bottom electrode layers directly contact the dielectric layer, the third bottom electrode layers and the first bottom electrode layers are alternately and separately arranged, and the bottom surface of the third bottom electrode layer is lower than the top surface of the dielectric layer.

7. The dynamic random access memory device according to claim 1, wherein: The second bit line crosses at least two of the active regions in the second direction.

8. A dynamic random access memory device, characterized in that: include: a substrate having a plurality of insulating regions formed therein, wherein the insulating regions define a plurality of active regions; a plurality of bit lines disposed on the substrate, the plurality of bit lines extending along a first direction and separated from each other in a second direction, the first direction and the second direction being perpendicular to each other, the bit lines comprising a plurality of first bit lines and a second bit line, the second bit line being disposed outside all of the first bit lines; a plurality of contacts disposed on the substrate and arranged alternately and separately from the bit lines; The bit lines respectively include a conductive layer and a cap layer stacked sequentially from bottom to top; a dielectric layer covering the contacts and the bit lines; a plurality of storage node pads, disposed in the dielectric layer and respectively contacting the contacts; as well as a capacitor structure disposed on the storage node pad, the capacitor structure comprising a plurality of first bottom electrode layers respectively aligned with the storage node pads, and at least one second bottom electrode layer located above a positive vertical projection direction of the second bit line; The bottom surface of the at least one second bottom electrode layer directly contacts the dielectric layer, and the bottom surface completely overlaps with the dielectric layer.

9. The dynamic random access memory device according to claim 8, wherein: The at least one second bottom electrode layer is simultaneously located above a portion of the contact and a portion of the second bit line in a positive vertical projection direction.

10. The dynamic random access memory device according to claim 8, wherein: The second bit line has a width greater than that of the first bit line, and the second bit line spans across at least two active regions in the second direction.

11. The dynamic random access memory device according to claim 8, wherein: The capacitor structure also includes multiple third bottom electrode layers respectively corresponding to the contacts, the third bottom electrode layers directly contact the dielectric layer, the third bottom electrode layers and the first bottom electrode layers are alternately and separately arranged, and the bottom surface of the third bottom electrode layer is lower than the top surface of the dielectric layer.

12. A dynamic random access memory device, characterized in that: include: a substrate having a plurality of insulating regions formed therein, wherein the insulating regions define a plurality of active regions; a plurality of bit lines disposed on the substrate, the plurality of bit lines extending along a first direction and separated from each other in a second direction, the first direction and the second direction being perpendicular to each other, the bit lines comprising a plurality of first bit lines and a second bit line, the second bit line being disposed outside all of the first bit lines; a plurality of contacts disposed on the substrate and arranged alternately and separately from the bit lines; The bit lines respectively include a conductive layer and a cap layer stacked sequentially from bottom to top; a dielectric layer covering the contacts and the bit lines; a plurality of storage node pads, disposed in the dielectric layer and respectively contacting the contacts; as well as a capacitor structure disposed on the storage node pad, the capacitor structure comprising a plurality of first bottom electrode layers respectively aligned with the storage node pads, and at least one second bottom electrode layer located above a positive vertical projection direction of the second bit line; The at least one second bottom electrode layer directly contacts the capping layer of the second bit line.

13. The dynamic random access memory device according to claim 12, wherein: The at least one second bottom electrode layer is simultaneously located above a portion of the contact and a portion of the second bit line in a positive vertical projection direction.

14. The dynamic random access memory device according to claim 12, wherein: A bottom surface of the at least one second bottom electrode layer is lower than a top surface of the second bit line.

15. The dynamic random access memory device according to claim 12, wherein: The second bit line has a width greater than that of the first bit line, and the second bit line spans across at least two active regions in the second direction.

16. The dynamic random access memory device according to claim 12, wherein: The capacitor structure also includes multiple third bottom electrode layers respectively corresponding to the contacts, the third bottom electrode layers directly contact the dielectric layer, the third bottom electrode layers and the first bottom electrode layers are alternately and separately arranged, and the bottom surface of the third bottom electrode layer is lower than the top surface of the dielectric layer.

17. A dynamic random access memory device, characterized in that: include: a substrate having a plurality of insulating regions formed therein, wherein the insulating regions define a plurality of active regions; a bit line disposed on the substrate, the bit line extending across the plurality of the insulating regions and the plurality of the active regions; The bit lines respectively include a conductive layer and a cap layer stacked sequentially from bottom to top; a dielectric layer covering the bit line; as well as Multiple capacitor structures are arranged on the bit line and the dielectric layer, wherein the multiple capacitor structures respectively include a bottom electrode layer, and the bottom surfaces of at least three consecutively arranged bottom electrode layers directly contact the dielectric layer and the bottom surfaces completely overlap with the dielectric layer.

18. The dynamic random access memory device according to claim 17, wherein: The bottom surface of the bottom electrode layer of the at least one capacitor structure is lower than the top surface of the dielectric layer.

19. The dynamic random access memory device according to claim 17, wherein: The bottom electrode layer of at least one of the capacitor structures directly contacts the capping layer of the bit line.

20. The dynamic random access memory device according to claim 17, wherein: The bottom surface of the bottom electrode layer of at least one of the capacitor structures is lower than the top surface of the bit line.

21. A dynamic random access memory device, characterized in that: include: a substrate having a plurality of insulating regions formed therein, wherein the insulating regions define a plurality of active regions; a plurality of contacts disposed separately on the substrate; a dielectric layer covering the contacts; a plurality of storage node pads, disposed in the dielectric layer and respectively contacting the contacts; as well as A capacitor structure is arranged on the storage node pad, and the capacitor structure includes multiple first bottom electrode layers respectively located on the storage node pad and electrically connected to the storage node pad, and a second bottom electrode layer located on the outside of the remaining first bottom electrode layers, and the second bottom electrode layer is electrically insulated and isolated from the storage node pad.

22. The dynamic random access memory device according to claim 21, wherein: Also includes: A plurality of bit lines are arranged on the substrate, and the plurality of bit lines extend along a first direction respectively and are separated from each other in a second direction. The first direction and the second direction are perpendicular to each other. The bit lines include a plurality of first bit lines and a second bit line, and the second bit line is arranged outside all the first bit lines.

23. The dynamic random access memory device according to claim 22, wherein: The second bottom electrode layer is located above the second bit line in a positive vertical projection direction.

24. The dynamic random access memory device according to claim 22, wherein: The second bit line has a width greater than that of the first bit line, and the second bit line spans across at least two active regions in the second direction.

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