Groove filling method based on groove capacitor and groove capacitor structure
By combining step-by-step filling with high-temperature processes, the problems of pattern cracks and wafer warpage in high-density and high-integration trench filling are solved, device performance is improved and abnormal problems are avoided.
Patent Information
- Application Number
- CN202510931548.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-07
- Publication Date
- 2025-10-03
AI Technical Summary
During the trench filling process of high-density and high-integration, abnormal problems such as pattern cracks and wafer warping are prone to occur, affecting subsequent processes.
A step-by-step filling method is adopted to define the thickness relationship between the layer group structure and the layer structure in the trench, combined with high-temperature process and in-situ P activation, to deposit and release the polysilicon layer, avoiding pattern cracks and wafer warping.
It solves the problems of pattern cracks and wafer warpage during the trench filling process, improves the overall performance of the device, and avoids the occurrence of abnormal problems.
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Figure CN120751709A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor device manufacturing, and in particular relates to a trench filling method based on a trench capacitor and a trench capacitor structure. Background Art
[0002] Silicon capacitor devices achieve high-density capacitance while making the size of silicon capacitor devices smaller by designing high-density integrated graphics and high aspect ratio trenches. This is very different from the planar design of traditional MOSCAP (metal oxide semiconductor capacitors).
[0003] While high-density, highly integrated trench designs achieve high capacitance density for silicon capacitors, they also introduce challenges. For example, during and after trench filling, issues such as pattern cracking and wafer warpage often occur, impacting subsequent processes such as photolithography and etching.
[0004] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention
[0005] The object of the present invention is to provide a trench filling method and a trench capacitor structure based on a trench capacitor, which can solve abnormal problems such as pattern cracks and wafer warping that occur during the trench filling process.
[0006] In order to achieve the above object, a specific embodiment of the present invention provides the following technical solutions:
[0007] A trench filling method based on trench capacitance, comprising:
[0008] Providing a semiconductor substrate having a trench formed thereon;
[0009] forming an electrode-dielectric stacking layer group on the surface of the semiconductor substrate and the inner wall of the trench, wherein the electrode-dielectric stacking layer group does not completely fill the trench, and a gap communicating with the outside is retained in the trench;
[0010] forming a layer structure on the electrode-dielectric stacked layer group, wherein the layer structure fills the gap and closes the groove;
[0011] The electrode-dielectric stacking layer is deposited in the groove with a thickness H of p1 , the maximum width W of the groove t , the maximum width W of the gap in the groove g The following relationship is satisfied: 2*H p1 =W t -W g .
[0012] In one or more embodiments of the present invention, after the layer structure is filled until the trench is closed, the layer structure is continuously deposited.
[0013] In one or more embodiments of the present invention, the electrode-dielectric stacked layer is deposited in the trench with a thickness H of p1 The total deposition thickness of the layer structure H p4 The ratio ranges from 0.3 to 1.8; and / or,
[0014] The electrode-dielectric stacked layer is deposited in the trench with a thickness H p1 The maximum width W of the gap in the groove g The ratio between the range is between 0.4 and 10.1; and / or,
[0015] The layer structure is deposited on the surface of the semiconductor substrate to a thickness H p3 The maximum width W of the gap in the groove g The ratio ranges from 0.6 to 4.9.
[0016] In one or more embodiments of the present invention, the total deposition thickness H of the layer structure is P4 The deposition thickness H of the layer structure in the trench p2 , the layer structure is deposited on the surface of the semiconductor substrate to a thickness H p3 , the deposition thickness H of the electrode-dielectric stack group p1 , the maximum width W of the groove t , the maximum width W of the gap in the groove g The following relationship is satisfied: 2H p2 =W g ;H P4 =H p2 +H p3 ;H p4 =1 / 2(W t -2*H p1 )+H p3 .
[0017] In one or more embodiments of the present invention, the total deposition thickness H of the layer structure is P4 Greater than or equal to 250nm and less than or equal to 550nm.
[0018] In one or more embodiments of the present invention, the maximum width W of the gap in the groove is g The range is 50nm-400nm.
[0019] In one or more embodiments of the present invention, after forming the electrode-dielectric stacking layer group, the method further includes: performing high-temperature annealing on the electrode-dielectric stacking layer group;
[0020] The annealing temperature ranges from 700° C. to 1250° C., and / or the annealing time ranges from 30 seconds to 1 hour.
[0021] In one or more embodiments of the present invention, the electrode-dielectric stacked layer group includes an electrode layer and a dielectric layer that are stacked; and the layer structure includes a polysilicon layer or an insulating layer.
[0022] In one or more embodiments of the present invention, the layer structure includes a polysilicon layer, and the polysilicon layer is formed using a high temperature process;
[0023] The temperature range for forming the polysilicon layer is 500° C. to 650° C.
[0024] In one or more embodiments of the present invention, a semiconductor substrate is provided, wherein a trench is formed on the semiconductor substrate, specifically comprising:
[0025] providing a semiconductor substrate, and forming an initial trench on the semiconductor substrate;
[0026] The surface of the semiconductor substrate and the inner wall of the initial trench are repaired by thermal oxidation.
[0027] In one or more embodiments of the present invention, thermally oxygenating the surface of the semiconductor substrate and the inner wall of the initial trench comprises:
[0028] At a high temperature (700° C. to 1000° C.), in a mixed gas environment of hydrogen, oxygen, and HCl, a thermal oxide layer is formed on the surface of the semiconductor substrate and the inner wall of the initial trench while removing metal impurities;
[0029] The thermal oxide layer is removed by a wet method.
[0030] A trench capacitor structure is manufactured using the above trench capacitor-based trench filling method.
[0031] The trench capacitor structure includes:
[0032] a semiconductor substrate having a trench formed thereon;
[0033] an electrode-dielectric stacking layer group formed on the surface of the semiconductor substrate and the inner wall of the trench, wherein the electrode-dielectric stacking layer group does not completely fill the trench, and a gap communicating with the outside is retained in the trench;
[0034] a layer structure formed on the electrode-dielectric stacked layer group, the layer structure filling the gap and closing the groove;
[0035] The electrode-dielectric stacking layer is deposited in the groove with a thickness H of p1 , the maximum width W of the groove t , the maximum width W of the gap in the groove g The following relationship is satisfied: 2*H p1 =W t -W g .
[0036] In one or more embodiments of the present invention, the electrode-dielectric stacked layer is deposited in the trench with a thickness H of p1 The total deposition thickness of the layer structure H p4 The ratio ranges from 0.3 to 1.8; and / or,
[0037] The electrode-dielectric stacked layer is deposited in the trench with a thickness H p1 The maximum width W of the gap in the groove g The ratio between the range is between 0.4 and 10.1; and / or,
[0038] The maximum width W of the gap in the groove g is in the range of 50 nm to 400 nm; and / or,
[0039] The total deposited thickness H of the layer structure P4 greater than or equal to 250 nm and less than or equal to 550 nm; and / or,
[0040] The electrode-dielectric stacked layer group includes an electrode layer and a dielectric layer that are stacked; and the layer structure includes a polysilicon layer or an insulating layer.
[0041] Compared with the prior art, the trench filling method and trench capacitor structure based on the present invention can solve abnormal problems such as pattern cracks and wafer warping that occur during the trench filling process by filling the trench in steps.
[0042] The trench filling method and trench capacitor structure based on the present invention limit the thickness relationship between the layer group structure and the layer structure in the trench during the trench filling process, so that abnormal problems such as pattern cracks and wafer warping will not occur after the trench is filled.
[0043] The trench filling method and trench capacitor structure based on the trench capacitor of the present invention improve the overall performance of the device by overfilling. At the same time, the ratio of the thickness of the overfilled layer structure to the thickness of the layer structure in the trench is limited. While improving the device performance, abnormal problems such as pattern cracks and wafer warping will not occur.
[0044] The trench filling method and trench capacitor structure based on the trench capacitor of the present invention directly deposit the polysilicon layer by adopting a high-temperature process, and perform in-situ P activation while depositing the polysilicon layer, and release stress while depositing. This can avoid sudden changes in the grains of the polysilicon layer during the subsequent annealing process, which can avoid generating large stress and causing abnormal problems such as pattern cracks and wafer warping. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0046] Figure 1 FIG1 is a process flow chart of a trench filling method based on trench capacitors according to an embodiment of the present invention;
[0047] Figure 2a to Figure 2f FIG. 1 is a schematic diagram of the steps of a trench filling method based on trench capacitors according to an embodiment of the present invention. DETAILED DESCRIPTION
[0048] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0049] As mentioned in the background, existing high-density, highly integrated trench designs, while achieving high-density capacitance for silicon capacitors, also present certain challenges. For example, during and after trench filling, issues such as pattern cracking and wafer warpage often occur, impacting subsequent processes such as photolithography and etching.
[0050] In order to solve the above technical problems, the present invention provides a trench filling method and trench capacitor structure based on trench capacitors. By filling the trenches in steps, abnormal problems such as pattern cracks and wafer warping that occur during the trench filling process can be solved.
[0051] like Figure 1 As shown, the trench filling method based on trench capacitor of the present invention specifically includes the following steps:
[0052] S1, providing a semiconductor substrate, on which a trench is formed.
[0053] S2, forming an electrode-dielectric stacking layer group on the surface of the semiconductor substrate and the inner wall of the trench, wherein the electrode-dielectric stacking layer group does not completely fill the trench, and a gap communicating with the outside is retained in the trench.
[0054] S3, forming a layer structure on the electrode-dielectric stacked layer group, wherein the layer structure fills the gap and closes the groove.
[0055] S4, after filling the layer structure until the trench is closed, continue depositing the layer structure.
[0056] The deposition thickness of the electrode-dielectric stack in the trench is H p1 , the maximum width of the groove W t , the maximum width of the gap in the groove W g The following relationship is satisfied: 2*H p1 =W t -W g The total deposition thickness of the layer structure H P4 , the deposition thickness of the layer structure in the trench H p2 , the deposition thickness H of the layer structure deposited on the surface of the semiconductor substrate p3 , the deposition thickness H of the electrode-dielectric stack p1 , the maximum width of the groove W t , the maximum width of the gap in the groove W g The following relationship is satisfied: 2H p2 =W g ;H P4 =H p2 +H p3 ;H p4 =1 / 2(W t -2*H p1 )+H p3 .
[0057] Preferably, the electrode-dielectric stacking layer is deposited to a thickness H in the trench. p1 The total deposition thickness H of the layer structure p4 The ratio range is between 0.3 and 1.8.
[0058] Preferably, the electrode-dielectric stacking layer is deposited to a thickness H in the trench. p1 The maximum width of the gap in the groove W g The ratio ranges from 0.4 to 10.1.
[0059] Preferably, the thickness of the layer structure deposited on the surface of the semiconductor substrate is H p3 The maximum width of the gap in the groove W g The ratio ranges from 0.6 to 4.9.
[0060] The trench filling method and trench capacitor structure based on the trench capacitor of the present invention can solve abnormal problems such as pattern cracks and wafer warpage that occur during the trench filling process by filling the trench in steps; by limiting the thickness relationship between the layer group structure and the layer structure in the trench during the trench filling process, abnormal problems such as pattern cracks and wafer warpage will not occur after the trench is filled; by overfilling, the overall performance of the device is improved, and at the same time, the ratio of the thickness of the overfilled layer structure to the thickness of the layer structure in the trench is limited, so that while improving the performance of the device, abnormal problems such as pattern cracks and wafer warpage will not occur.
[0061] In the prior art, a method for forming trenches on a semiconductor substrate (silicon substrate) is usually to directly use photoresist as a mask to etch deeper trenches. However, directly using photoresist as a mask to etch deeper trenches may result in insufficient selectivity and the desired depth cannot be etched.
[0062] In step S1 of the present invention, the etching depth of the deep trench is increased by depositing a hard mask 21 on the surface of the semiconductor substrate 10. The semiconductor substrate 10 is generally a silicon substrate.
[0063] like Figure 2a As shown, a hard mask 21 is first deposited on the surface of the semiconductor substrate 10. After the hard mask 21 is deposited, a photoresist 22 is coated on the surface of the hard mask 21. Using the photoresist 22 as a mask, an initial trench pattern 11a is formed on the photoresist 22 through exposure and development processes. A conventional etching process is then used to transfer the initial trench pattern 11a on the photoresist 22 to the hard mask 21, thereby etching the openings in the hard mask 21.
[0064] Exemplarily, the hard mask 21 is SiO 2 or SiN deposited by a plasma enhanced device, and the thickness of the hard mask is controlled to be between 1 μm and 2 μm.
[0065] like Figure 2b As shown, after the opening etching on the hard mask 21 is completed, the semiconductor substrate 10 is continuously subjected to an etching-while-deposition process using the Bosch process to achieve etching of an initial trench 11b with a high aspect ratio on the semiconductor substrate 10. The Bosch process is a deep silicon etching technology used in microelectromechanical systems (MEMS) manufacturing and is capable of achieving deep silicon etching structures with high aspect ratios (up to 30:1 or higher).
[0066] It is understandable that the trench in an ideal trench capacitor structure is completely vertical. However, during the specific process implementation, due to the influence of the photolithography process, the accuracy of the etching equipment, etc., the actually formed trench is not completely vertical and generally has a morphology that is wide at the top and narrow at the bottom.
[0067] In the present invention, between step S1 and step S2, a step of repairing the surface of the semiconductor substrate and the inner wall of the initial trench by thermal oxidation is also included.
[0068] like Figure 2c and Figure 2d As shown, after the initial groove 11b is formed, a mixed gas such as hydrogen, oxygen, and HCl is introduced at a high temperature (usually 700°C to 1000°C) using a furnace tube device to react the surface silicon of the semiconductor substrate 10 to form a SiO2 thermal oxide layer 30. During the thermal oxidation process, HCl undergoes a replacement reaction with impurities on the surface of the semiconductor substrate 10 to remove surface metal impurities. The thermal oxide layer 30 is then removed using a wet solution such as BOE or DHF to expose a silicon surface with low roughness and low metal contamination, forming a groove 11. The thermal oxidation repair process and the replacement reaction of HCl gas can facilitate the filling of subsequent layer groups and layer structures, thereby improving the performance of the manufactured trench capacitor.
[0069] It should be noted that if thermal oxidation repair is performed, the maximum groove width W defined in the present invention is t , which is the width of the trench top after removing the thermal oxide layer 30. If thermal oxide repair is not performed, the maximum trench width Wt defined in the present invention is the initial trench top width.
[0070] In step S2 of the present invention, after the thermal oxidation repair process, an electrode-dielectric stacked layer group is deposited on the surface of the semiconductor substrate and the inner wall of the trench to complete the fabrication of the core layer structure of the trench capacitor.
[0071] In a specific embodiment, the electrode-dielectric stacked layer group may include a single dielectric layer formed on the surface of the semiconductor substrate and the inner wall of the trench, and a single electrode layer formed on the surface of the single dielectric layer.
[0072] In another specific embodiment, the electrode-dielectric stacked layer group may include a plurality of dielectric layers and a plurality of electrode layers stacked and formed on the surface of the semiconductor substrate and the inner wall of the trench. The plurality of dielectric layers and the plurality of electrode layers are alternately stacked, and adjacent electrode layers are separated by a dielectric layer.
[0073] In the prior art, metal materials such as AlCu and TiPtAu are commonly used as electrode layers. With the advancement of semiconductor technology, doped polysilicon is gradually replacing metal materials due to its low production cost, greater compatibility with silicon, and adjustable resistivity. Therefore, in the present invention, the electrode layer is preferably a polysilicon layer, and the dielectric layer is preferably a SiO2 or SiN layer or a high-k dielectric constant (High-κ) material layer.
[0074] It is understandable that the electrode-dielectric stack can be deposited using existing technology, which will not be elaborated in detail in the present invention.
[0075] As an exemplary illustration, the present invention takes an electrode-dielectric stacked layer group consisting of a single dielectric layer and a single electrode layer as an example to further describe the technical solution of the present invention.
[0076] like Figure 2e As shown, after thermal oxidation repair, a single dielectric layer 31 is first deposited on the surface of the semiconductor substrate 10 and the inner wall of the trench 11, and then a single electrode layer 32 is deposited on the surface of the single dielectric layer 31. The material of the electrode layer 32 is polysilicon.
[0077] The polysilicon may be uniformly deposited on the surface of the single dielectric layer 31 by in-situ doping of polysilicon using LPCVD (Low-Pressure Chemical Vapor Deposition) or PECVD (Plasma-Enhanced Chemical Vapor Deposition) processes in a phosphine and silane gas atmosphere within a temperature range of 500° C. to 600° C.
[0078] After the deposition is completed, there is still a gap in the groove that is connected to the outside, and the maximum width of the gap is W g The deposition thickness of the electrode-dielectric stacking layer group consisting of a single dielectric layer 31 and a single electrode layer 32 is H p1 The deposition thickness of the electrode-dielectric stack in the trench is H p1 The maximum width of the gap in the groove W g The ratio ranges from 0.3 to 1.8.
[0079] In the present invention, a high-temperature annealing step is further included between step S2 and step S3.
[0080] Specifically, after electrode layer 32 is deposited, it is activated by high-temperature annealing to reduce the resistivity of the doped polysilicon and allow it to function as a top electrode. Annealing can be performed using various methods, such as RTP (Rapid Thermal Processing), LPCVD, and APCVD. The annealing temperature ranges from 700°C to 1250°C, and the annealing time ranges from 30 seconds to 1 hour.
[0081] In the above technical solution, during the high temperature annealing process, the grain size of polysilicon first increases, then recrystallizes and expands in volume, thus generating polycrystalline stress, which can easily cause pattern cracks and wafer warping. The applicant has found that when the deposition thickness H of the electrode-dielectric stacked layer group in the trench is limited p1 The maximum width of the gap in the groove W gWhen the ratio ranges from 0.4 to 10.1, the warpage of the manufactured trench capacitor device is within a limited range (the limited range is less than or equal to 200 μm).
[0082] After the annealing is completed, step S3 and step S4 are performed in sequence.
[0083] like Figure 2f As shown, the LPCVD or PECVD process is again used to deposit a layer structure 33 on the electrode layer 32 until the layer structure 33 fills the gap in the trench 11 and closes the trench 11; then the layer structure 33 is deposited again to ensure that the trench 11 is completely closed and the surface of the semiconductor substrate 10 is flattened. During the process of continuing to deposit the layer structure 33, it is necessary to reasonably control the thickness of the layer structure 33 to prevent the stress generated by the layer structure 33 from causing cracks in the pattern and causing wafer warpage. The total deposition thickness of the layer structure 33 is H P4 The thickness of the layer structure 33 deposited in the trench 11 is H p2 The thickness of the layer structure 33 deposited on the surface of the semiconductor substrate 10 is H p3 .
[0084] The applicant found that when the deposition thickness H of the electrode-dielectric stack group in the trench is limited p1 The total deposition thickness H of the layer structure p4 The ratio range is between 0.3 and 1.8; the deposition thickness H of the electrode-dielectric stack in the trench p1 The maximum width of the gap in the groove W g The ratio range is between 0.4 and 10.1; the thickness H of the layer structure deposited on the surface of the semiconductor substrate is p3 The maximum width of the gap in the groove W g When the ratio ranges from 0.6 to 4.9, the warpage of the manufactured trench capacitor device is always within a limited range (the limited range is less than or equal to 200 μm).
[0085] In a specific embodiment, the material of the layer structure 33 can be polysilicon or an insulating layer such as silicon oxide. The maximum width W of the gap in the trench 11 is g The total deposition thickness H of the layer structure 33 is in the range of 50 nm to 400 nm. P4 Greater than or equal to 250nm and less than or equal to 550nm.
[0086] When the material of layer structure 33 is polysilicon, the polysilicon layer can be formed using a high-temperature process in the temperature range of 500°C to 650°C. By directly depositing the polysilicon layer using a high-temperature process and performing in-situ P activation during the deposition of the polysilicon layer, stress relief can be performed during deposition. This can avoid sudden changes in the grain size of the polysilicon layer during the subsequent annealing process, which could generate high stress and cause abnormal problems such as pattern cracks and wafer warpage.
[0087] The present invention also provides a trench capacitor structure, which is manufactured using the above-mentioned trench capacitor-based trench filling method.
[0088] like Figure 2f As shown, the trench capacitor structure of the present invention includes a semiconductor substrate 10 , an electrode-dielectric stacked layer group, and a layer structure 33 .
[0089] A trench 11 is formed on the semiconductor substrate 10. The maximum width of the trench 11 is W t .
[0090] The electrode-dielectric stacking layer group is formed on the surface of the semiconductor substrate 10 and the inner wall of the trench 11. The deposition thickness of the electrode-dielectric stacking layer group in the trench 11 is H p1 The electrode-dielectric stacking layer group does not fill the groove 11 completely, and a gap communicating with the outside is retained in the groove 11. The maximum width of the gap in the groove 11 is W g .
[0091] The layer structure 33 is formed on the electrode-dielectric stacked layer group. The layer structure 33 fills the gap and closes the trench 11. The thickness of the layer structure 33 includes two parts. One part is the thickness of the layer structure deposited in the trench, which is recorded as H. p2 The second is the thickness of the layer structure 33 deposited on the surface of the semiconductor substrate 11, which is recorded as H p3 The total deposited thickness of the layer structure 33 is denoted as H P4 .
[0092] The deposition thickness of the electrode-dielectric stack in the trench is H p1 , the maximum width of the groove W t , the maximum width of the gap in the groove W g The following relationship is satisfied: 2*H p1 =W t -W g The deposition thickness of the electrode-dielectric stack in the trench is H p1 The total deposition thickness H of the layer structure p4 The ratio range is between 0.3 and 1.8; the deposition thickness H of the electrode-dielectric stack in the trench p1 The maximum width of the gap in the groove W gThe ratio range is between 0.4 and 10.1; the thickness H of the layer structure deposited on the surface of the semiconductor substrate is p3 The maximum width of the gap in the groove W g The ratio ranges from 0.6 to 4.9.
[0093] In one embodiment, the maximum width W of the gap in the groove is g The total deposition thickness H of the layer structure is in the range of 50nm-400nm. P4 The thickness of the electrode-dielectric stacked layer group is greater than or equal to 250 nm and less than or equal to 550 nm. The electrode-dielectric stacked layer group includes an electrode layer and a dielectric layer stacked in a stack. The layer structure includes a polysilicon layer or an insulating layer.
[0094] Table 1: Maximum groove width W for the same groove t , the deposition thickness H of different electrode-dielectric stacking layers p1 , the total deposition thickness H of different layer structures p4 , the deposition thickness H of different continuously deposited layer structures on the surface of the semiconductor substrate p3 Under the conditions, the warpage degree of trench capacitor
[0095]
[0096]
[0097] From Table 1, it can be seen that when the deposition thickness H of the electrode-dielectric stacking layer group in the trench is limited p1 The total deposition thickness H of the layer structure p4 The ratio range is between 0.3 and 1.8; the deposition thickness H of the electrode-dielectric stack in the trench p1 The maximum width of the gap in the groove W g The ratio range is between 0.4 and 10.1; the thickness H of the layer structure deposited on the surface of the semiconductor substrate is p3 The maximum width of the gap in the groove W g When the ratio ranges from 0.6 to 4.9, the warping degree of the manufactured trench capacitor is always within a limited range (the limited range is less than or equal to 200 μm).
[0098] Compared with the prior art, the trench filling method and trench capacitor structure based on the present invention can solve abnormal problems such as pattern cracks and wafer warping that occur during the trench filling process by filling the trench in steps.
[0099] The trench filling method and trench capacitor structure based on the present invention limit the thickness relationship between the layer group structure and the layer structure in the trench during the trench filling process, so that abnormal problems such as pattern cracks and wafer warping will not occur after the trench is filled.
[0100] The trench filling method and trench capacitor structure based on the trench capacitor of the present invention improve the overall performance of the device by overfilling. At the same time, the ratio of the thickness of the overfilled layer structure to the thickness of the layer structure in the trench is limited. While improving the device performance, abnormal problems such as pattern cracks and wafer warping will not occur.
[0101] The trench filling method and trench capacitor structure based on the trench capacitor of the present invention directly deposit the polysilicon layer by adopting a high-temperature process, and perform in-situ P activation while depositing the polysilicon layer, and release stress while depositing. This can avoid sudden changes in the grains of the polysilicon layer during the subsequent annealing process, which can avoid generating large stress and causing abnormal problems such as pattern cracks and wafer warping.
[0102] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.
[0103] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.
Claims
1. A trench filling method based on trench capacitor, characterized in that: include: Providing a semiconductor substrate having a trench formed thereon; forming an electrode-dielectric stacking layer group on the surface of the semiconductor substrate and the inner wall of the trench, wherein the electrode-dielectric stacking layer group does not completely fill the trench, and a gap communicating with the outside is retained in the trench; forming a layer structure on the electrode-dielectric stacked layer group, wherein the layer structure fills the gap and closes the groove; The electrode-dielectric stacked layer is deposited in the groove with a thickness H of p1 , the maximum width W of the groove t , the maximum width W of the gap in the groove g The following relationship is satisfied: 2*H p1 =W t -W g .
2. The trench filling method based on trench capacitor according to claim 1, characterized in that: After filling the layer structure until the trench is closed, the layer structure is continuously deposited.
3. The trench filling method based on trench capacitor according to claim 2, characterized in that: The electrode-dielectric stacked layer is deposited in the trench with a thickness H p1 The total deposition thickness of the layer structure H p4 The ratio ranges from 0.3 to 1.8; and / or, The electrode-dielectric stacked layer is deposited in the trench with a thickness H p1 The maximum width W of the gap in the groove g The ratio between the range is between 0.4 and 10.1; and / or, The layer structure is deposited on the surface of the semiconductor substrate to a thickness H p3 The maximum width W of the gap in the groove g The ratio ranges from 0.6 to 4.
9.
4. The trench filling method based on trench capacitor according to claim 2, characterized in that: The total deposited thickness H of the layer structure P4 The deposition thickness H of the layer structure in the trench p2 , the layer structure is deposited on the surface of the semiconductor substrate to a thickness H p3 , the deposition thickness H of the electrode-dielectric stack group p1 , the maximum width W of the groove t , the maximum width W of the gap in the groove g The following relationship is satisfied: 2H p2 =W g ;H P4 =H p2 +H p3 ;H p4 =1 / 2(W t -2*H p1 )+H p3 .
5. The trench filling method based on trench capacitor according to claim 2, characterized in that: The total deposited thickness H of the layer structure P4 Greater than or equal to 250nm and less than or equal to 550nm.
6. The trench filling method based on trench capacitor according to claim 1, characterized in that: The maximum width W of the gap in the groove g The range is 50nm-400nm.
7. The trench filling method based on trench capacitor according to claim 1, characterized in that: After forming the electrode-dielectric stacking layer group, the method further includes: performing high-temperature annealing on the electrode-dielectric stacking layer group; The annealing temperature ranges from 700° C. to 1250° C., and / or the annealing time ranges from 30 seconds to 1 hour.
8. The trench filling method based on trench capacitor according to claim 1, characterized in that: The electrode-dielectric stacked layer group includes an electrode layer and a dielectric layer that are stacked; and the layer structure includes a polysilicon layer or an insulating layer.
9. The trench filling method based on trench capacitor according to claim 8, characterized in that: The layer structure includes a polysilicon layer, and the polysilicon layer is formed by a high temperature process; The temperature range for forming the polysilicon layer is 500° C. to 650° C.
10. The trench filling method based on trench capacitor according to claim 1, characterized in that: A semiconductor substrate is provided, wherein a trench is formed on the semiconductor substrate, specifically comprising: providing a semiconductor substrate, and forming an initial trench on the semiconductor substrate; The surface of the semiconductor substrate and the inner wall of the initial trench are repaired by thermal oxidation.
11. The trench filling method based on trench capacitor according to claim 10, characterized in that: Thermally oxygenating the surface of the semiconductor substrate and the inner wall of the initial trench, comprising: Under high temperature conditions, in a mixed gas environment of hydrogen, oxygen, and HCl, forming a thermal oxide layer on the surface of the semiconductor substrate and the inner wall of the initial trench while removing metal impurities; The thermal oxide layer is removed by a wet method.
12. A trench capacitor structure, characterized in that: include: a semiconductor substrate having a trench formed thereon; an electrode-dielectric stacking layer group formed on the surface of the semiconductor substrate and the inner wall of the trench, wherein the electrode-dielectric stacking layer group does not completely fill the trench, and a gap communicating with the outside is retained in the trench; a layer structure formed on the electrode-dielectric stacked layer group, the layer structure filling the gap and closing the groove; The electrode-dielectric stacking layer is deposited in the groove with a thickness H of p1 , the maximum width W of the groove t , the maximum width W of the gap in the groove g The following relationship is satisfied: 2*H p1 =W t -W g .
13. The trench capacitor structure according to claim 12, wherein: The electrode-dielectric stacked layer is deposited in the trench with a thickness H p1 The total deposition thickness of the layer structure H p4 The ratio ranges from 0.3 to 1.8; and / or, The electrode-dielectric stacked layer is deposited in the trench with a thickness H p1 The maximum width W of the gap in the groove g The ratio between the range is between 0.4 and 10.1; and / or, The maximum width W of the gap in the groove g is in the range of 50 nm to 400 nm; and / or, The total deposited thickness H of the layer structure P4 greater than or equal to 250 nm and less than or equal to 550 nm; and / or, The electrode-dielectric stacked layer group includes an electrode layer and a dielectric layer that are stacked; and the layer structure includes a polysilicon layer or an insulating layer.