Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; the isolation layer is arranged on the substrate; the capacitor structures are arranged on the isolating layer at intervals, and each capacitor structure comprises a first electrode layer, an insulating layer and a second electrode layer which are sequentially stacked from bottom to top; the dielectric layer covers the isolation layer and the capacitor structure, and the dielectric layer is formed through spin coating. According to the scheme, the dielectric layer is formed through spin coating, the dielectric layer has the flat top surface, the CMP technological process is omitted, the technological process can be simplified, the cost can be saved, meanwhile, the performance consistency of different capacitor structures is improved, and then the device performance is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] An integrated passive device (IPD) filter utilizes IPD technology to integrate passive components such as capacitors and inductors onto a single chip. The capacitors in an IPD filter are typically metal-insulator-metal (MIM) capacitors. After the MIM capacitors are fabricated, an oxide layer is typically used as the dielectric layer surrounding them.

[0003] The oxide layer used as a dielectric layer is typically deposited conformally, for example using chemical vapor deposition (CVD) or atomic layer deposition (ALD). The deposited oxide layer's topography is affected by the topography of the structure it covers, resulting in top surface fluctuations. Therefore, after depositing the oxide layer, a chemical mechanical polishing (CMP) process is required to planarize the oxide layer.

[0004] However, since IPD filters generally include multiple MIM capacitors spaced apart, the top surface of the oxide layer fluctuates greatly, which in turn places high demands on the CMP process, resulting in increased costs and process difficulty. At the same time, the CMP process has different grinding rates for different locations on the chip, resulting in inconsistent remaining thicknesses of the oxide layer above different MIM capacitors after the CMP process. As a result, when the oxide layer is etched to form connection holes (which are subsequently filled with conductive material to form conductive plugs to lead out the MIM capacitors), the degree of etching of the MIM capacitors at different locations varies greatly, affecting the performance consistency of the MIM capacitors at different locations.

[0005] Therefore, improvements are needed to at least partially solve the above problems. Summary of the Invention

[0006] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention of this application is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] In order to solve the existing problems, the present application provides a semiconductor device, comprising:

[0008] substrate;

[0009] an isolation layer, disposed on the substrate;

[0010] A plurality of spaced capacitor structures are provided on the isolation layer, wherein the capacitor structures include a first electrode layer, an insulating layer, and a second electrode layer stacked sequentially from bottom to top;

[0011] A dielectric layer covers the isolation layer and the capacitor structure, wherein the dielectric layer is formed by spin coating.

[0012] Exemplarily, the material of the dielectric layer includes an organic dielectric layer, and the material of the organic dielectric layer includes polyimide or benzocyclobutene.

[0013] Exemplarily, a diffusion barrier layer is further included, wherein the diffusion barrier layer covers at least a portion of the capacitor structure, and the dielectric layer covers the diffusion barrier layer.

[0014] Exemplarily, the material of the diffusion barrier layer includes silicon nitride.

[0015] Exemplarily, the capacitor structure further includes a first wiring layer, a second wiring layer, and an etch stop layer, wherein the first wiring layer is located between the isolation layer and the first electrode layer, the second wiring layer is located on the second electrode layer; and the etch stop layer is located on the second wiring layer.

[0016] The semiconductor device further includes a first conductive plug penetrating the dielectric layer and electrically connected to the first electrode layer, and a second conductive plug penetrating the dielectric layer and electrically connected to the second electrode layer.

[0017] Exemplarily, the materials of the first electrode layer, the second electrode layer and the etching stop layer include titanium nitride;

[0018] The material of the first connection layer and the second connection layer includes aluminum;

[0019] The material of the insulating layer includes silicon nitride;

[0020] The isolation layer includes an oxide layer.

[0021] Another aspect of the present application provides a method for manufacturing a semiconductor device, comprising:

[0022] providing a substrate;

[0023] forming an isolation layer on the substrate;

[0024] forming a plurality of capacitor structures spaced apart from each other on the isolation layer, wherein the capacitor structures include a first electrode layer, an insulating layer, and a second electrode layer stacked sequentially from bottom to top;

[0025] A dielectric layer covering the isolation layer and the capacitor structure is formed by spin coating.

[0026] Exemplarily, the material of the dielectric layer includes an organic dielectric layer, and the material of the organic dielectric layer includes polyimide or benzocyclobutene.

[0027] Exemplarily, after forming the capacitor structure and before forming the dielectric layer, the method further includes forming a diffusion barrier layer, wherein the diffusion barrier layer covers at least a portion of the capacitor structure, and the dielectric layer covers the diffusion barrier layer.

[0028] Exemplarily, the capacitor structure further includes a first wiring layer, a second wiring layer, and an etch stop layer, wherein the first wiring layer is located between the isolation layer and the first electrode layer, the second wiring layer is located on the second electrode layer; and the etch stop layer is located on the second wiring layer.

[0029] After forming the dielectric layer, the step of forming a first conductive plug and a second conductive plug is also included, wherein the first conductive plug penetrates the dielectric layer and is electrically connected to the first electrode layer, and the second conductive plug penetrates the dielectric layer and is electrically connected to the second electrode layer.

[0030] In the semiconductor device and manufacturing method of the embodiments of the present application, the dielectric layer is formed by spin coating, and the dielectric layer has a flat top surface, eliminating the CMP process flow, which can simplify the process flow and save costs, while improving the performance consistency of different capacitor structures, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The following drawings of the present application are used as part of the present application for understanding the present application. The drawings show embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

[0032] In the attached figure:

[0033] Figure 1A-1D A cross-sectional schematic diagram of a semiconductor device in the related art is shown;

[0034] Figure 2A-2F A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown;

[0035] Figure 3 A flow chart of a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown.

[0036] Description of reference numerals:

[0037] 101 - aluminum layer, 102 - titanium nitride layer, 103 - silicon nitride layer, 104 - titanium nitride layer, 105 - aluminum layer, 106 - titanium nitride layer, 107 - oxide layer, 108 - first connection hole, 109 - second connection hole;

[0038] 200-substrate, 201-isolation layer, 202-first wiring material layer, 203-first electrode material layer, 204-insulating material layer, 205-second electrode material layer, 206-second wiring material layer, 207-etching barrier material layer, 208-first wiring layer, 209-first electrode layer, 210-insulating layer, 211-second electrode layer, 212-second wiring layer, 213-etching barrier layer, 214-diffusion barrier layer, 215-dielectric layer, 216-first connecting hole, 217-second connecting hole, 218-first conductive plug, 219-second conductive plug. DETAILED DESCRIPTION

[0039] Next, the present application will be described more fully in conjunction with the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0040] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0041] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Embodiments of the application are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the application. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the application.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application relates. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0045] In order to fully understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0046] like Figure 1A As shown, the IPD filter in the related art generally includes multiple spaced MIM capacitors, wherein the MIM capacitor includes an aluminum layer 101, a titanium nitride layer 102, a silicon nitride layer 103, a titanium nitride layer 104, an aluminum layer 105, and a titanium nitride layer 106 stacked in sequence from bottom to top. The titanium nitride layer 102 and the titanium nitride layer 104 serve as the two electrodes of the MIM capacitor, respectively, the silicon nitride layer 103 serves as the insulating medium of the MIM capacitor, the aluminum layer 101 and the aluminum layer 105 serve as the wiring layer, and the titanium nitride layer 106 serves as the etching stopper layer.

[0047] After the MIM capacitor is prepared, Figure 1B As shown in FIG. 1 , an oxide layer 107 is formed to wrap the MIM capacitor, and the oxide layer 107 serves as a dielectric layer. However, since the oxide layer 107 is conformally deposited, the top surface of the oxide layer 107 fluctuates. Multiple spaced-apart MIM capacitors will further increase the fluctuation amplitude of the top surface of the oxide layer 107. Figure 1B As shown, the titanium nitride layer 104 only covers part of the surface of the silicon nitride layer 103, that is, the sizes of the titanium nitride layer 104, the aluminum layer 105 and the titanium nitride layer 106 are smaller than those of the aluminum layer 101, the titanium nitride layer 102 and the silicon nitride layer 103, which will further cause the fluctuation amplitude of the top surface of the oxide layer 107 to become larger.

[0048] like Figure 1C As shown, after depositing the oxide layer 107, a CMP process is used to planarize the oxide layer 107. However, due to the large fluctuations in the top surface of the oxide layer 107, high requirements are placed on the CMP process, which in turn increases the cost and process difficulty. Furthermore, the CMP process has different polishing rates at different locations on the chip (for example, due to the loading effect). As a result, after the CMP process, the remaining thickness of the oxide layer 107 above different MIM capacitors is inconsistent.

[0049] In this way, Figure 1DAs shown, when the oxide layer 107 is etched to form a first connection hole 108 and a second connection hole 109 for respectively leading out the two electrodes of the MIM capacitor, the remaining thickness of the oxide layer 107 above the MIM capacitor is inconsistent, resulting in a large difference in the etching degree of the MIM capacitor at different positions of the etching process. For example, although the titanium nitride layer 106 serves as an etching barrier layer, the thickness of the titanium nitride layer 106 is generally thin. When etching to form the connection hole, it is easy to etch through the titanium nitride layer 106 and expose the aluminum layer 105. Therefore, the area with a thinner remaining thickness of the oxide layer 107 will etch the aluminum layer 105 in the MIM capacitor faster, and the etching amount of the aluminum layer 105 will be greater, resulting in poor performance consistency of the MIM capacitors at different positions, thereby affecting the performance of the semiconductor device.

[0050] In view of the above technical problems, an embodiment of the present application provides a semiconductor device, including:

[0051] substrate;

[0052] an isolation layer, disposed on the substrate;

[0053] A plurality of spaced capacitor structures are provided on the isolation layer, wherein the capacitor structures include a first electrode layer, an insulating layer, and a second electrode layer stacked sequentially from bottom to top;

[0054] The dielectric layer covers the isolation layer and the capacitor structure, wherein the dielectric layer is formed by spin coating.

[0055] In the semiconductor device of the embodiment of the present application, the dielectric layer is formed by spin coating, and the dielectric layer has a flat top surface, which eliminates the CMP process flow, can simplify the process flow and save costs, while improving the performance consistency of different capacitor structures, thereby improving device performance.

[0056] Below, reference Figure 2F The semiconductor device of the present application is described in detail. The semiconductor device can be any suitable device well known to those skilled in the art. In this embodiment, the technical solution of the present invention is explained and illustrated mainly by taking the semiconductor device as an IPD filter as an example.

[0057] like Figure 2F As shown, the semiconductor device of the present application includes: a substrate 200; an isolation layer 201, which is arranged on the substrate 200; a plurality of spaced capacitor structures, which are arranged on the isolation layer 201, and the capacitor structure includes a first electrode layer 209, an insulating layer 210, and a second electrode layer 211 stacked in sequence from bottom to top; a dielectric layer 215, which covers the isolation layer 201 and the capacitor structure, wherein the dielectric layer 215 is formed by spin coating. Exemplarily, the spaced arrangement of the plurality of capacitor structures means that there is a spacing between the capacitor structures, and does not limit the electrical connection method between the plurality of capacitor structures. For example, the plurality of capacitor structures can be connected in parallel or in series.

[0058] In one example, the substrate 200 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, or the substrate 200 may include silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). Although several examples of materials that can form the substrate 200 are described herein, any material that can be used as the substrate 200 falls within the spirit and scope of the present application.

[0059] In one example, the isolation layer 201 plays a role of electrical isolation, and may be an oxide layer (eg, a silicon oxide layer) or any other suitable film layer of a material capable of playing a role of electrical isolation, which is not limited in the present application.

[0060] In one example, the capacitor structure is a MIM capacitor structure, wherein the materials of the first electrode layer 209 and the second electrode layer 211 include but are not limited to conductive materials such as titanium nitride, and the materials of the insulating layer 210 include but are not limited to insulating materials such as silicon nitride.

[0061] In one example, the dielectric layer 215 is formed by spin coating, that is, the dielectric layer 215 is obtained by solidifying the spin-coated solution, so that the dielectric layer 215 has a flat top surface. Compared with the solution of depositing an oxide layer and then performing a CMP process on the oxide layer, the CMP process is omitted, which can simplify the process flow and save costs; at the same time, because the dielectric layer 215 has a flat top surface, the thickness of the dielectric layer 215 above each capacitor structure is equal, and the etching degree for different capacitor structures is the same when the connection holes are subsequently etched to form the connection holes, which improves the performance consistency of different capacitor structures and thereby improves the device performance.

[0062] In one example, the dielectric layer 215 includes an organic dielectric layer, and the material of the organic dielectric layer includes polyimide (PI) or benzocyclobutene (BCB). For example, taking the dielectric layer 215 as an example, the dielectric constants of polyimide and benzocyclobutene are both smaller than the dielectric constant of the oxide layer (the dielectric constant of polyimide is about 3.3, the dielectric constant of benzocyclobutene is about 2.65, and the dielectric constant of the oxide layer is about 4), and the quality factor (Q value) of the capacitor structure is affected by the dielectric constant of the dielectric layer. The smaller the dielectric constant of the dielectric layer, the higher the Q value. Conversely, the larger the dielectric constant of the dielectric layer, the lower the Q value. The dielectric layer 215 is made of polyimide or benzocyclobutene, and has a lower dielectric constant than the dielectric layer made of the oxide layer, thereby improving the Q value of the capacitor structure and thus improving device performance.

[0063] In one example, if Figure 2F As shown, the semiconductor device of the present application further includes a diffusion barrier layer 214, which covers at least a portion of the capacitor structure, and a dielectric layer 215 covering the diffusion barrier layer 214. Exemplarily, the dielectric layer 215 is formed by spin coating. Films that can be formed by spin coating generally have strong hygroscopic properties (for example, polyimide and benzocyclobutene have strong hygroscopic properties). The diffusion barrier layer 214 can effectively prevent liquids such as water vapor absorbed in the dielectric layer 215 from penetrating and diffusing into the capacitor structure, thereby effectively preventing liquids such as water vapor absorbed in the dielectric layer 215 from penetrating and diffusing into the capacitor structure, causing failure of the capacitor structure. Exemplarily, the diffusion barrier layer 214 is conformally deposited.

[0064] In one example, the material of the diffusion barrier layer 214 includes silicon nitride, or the material of the diffusion barrier layer 214 can also be any other suitable insulating material that can prevent the diffusion of water vapor in the dielectric layer 215. Figure 2F As shown, the second electrode layer 211 in the capacitor structure of the present application covers part of the surface of the insulating layer 210, that is, the size of the second electrode layer 211 is smaller than the size of the insulating layer 210 and the first electrode layer 209, and the diffusion barrier layer 214 covers the exposed surface of the insulating layer 210 (that is, the diffusion barrier layer 214 covers the surface of the insulating layer 210 not covered by the second electrode layer 211), which can reduce the edge effect of the capacitor structure. Exemplarily, the material of the diffusion barrier layer 214 is the same as that of the insulating layer 210.

[0065] In one example, if Figure 2F As shown, the capacitor structure further includes a first wiring layer 208, a second wiring layer 212, and an etch stop layer 213, wherein the first wiring layer 208 is located between the isolation layer 201 and the first electrode layer 209, the second wiring layer 212 is located on the second electrode layer 211, and the etch stop layer 213 is located on the second wiring layer 212. Exemplarily, the material of the first wiring layer 208 and the second wiring layer includes, but is not limited to, a conductive material such as aluminum, and the material of the etch stop layer 213 includes, but is not limited to, a conductive material such as titanium nitride. Exemplarily, the etch stop layer 213, the first electrode layer 209, and the second electrode layer 211 have the same material and the same thickness. Exemplarily, the first wiring layer 208, the first electrode layer 209 and the insulating layer 210 have the same size, the second electrode layer 211, the second wiring layer 212 and the etching stop layer 213 have the same size, and the sizes of the second electrode layer 211, the second wiring layer 212 and the etching stop layer 213 are smaller than the sizes of the first wiring layer 208, the first electrode layer 209 and the insulating layer 210.

[0066] In one example, if Figure 2FAs shown, the semiconductor device further includes a first conductive plug 218 that penetrates the dielectric layer 215 and is electrically connected to the first electrode layer 209, and a second conductive plug 219 that penetrates the dielectric layer 215 and is electrically connected to the second electrode layer 211. Exemplarily, the first conductive plug 218 penetrates the dielectric layer 215 above the first electrode layer 209, and the second conductive plug 219 penetrates the dielectric layer 215 above the second electrode layer 211. Exemplarily, when a diffusion barrier layer 214 is formed, the first conductive plug 218 also penetrates the diffusion barrier layer 214 above the first electrode layer 209, and the second conductive plug 219 also penetrates the diffusion barrier layer 214 above the second electrode layer 211.

[0067] In one example, since the thickness of the first electrode layer 209 and the second electrode layer 211 is relatively thin (for example, the thickness of the first electrode layer 209 and the second electrode layer 211 is 630 angstroms), there is a risk of the first electrode layer 209 and the second electrode layer 211 being etched through during the formation of the first conductive plug 218 and the second conductive plug 219. Therefore, a first wiring layer 208 of a conductive material is provided below the first electrode layer 209, and a second wiring layer 212 of a conductive material is provided above the second electrode layer 211 to avoid device failure caused by the etching through of the first electrode layer 209 and the second electrode layer 211; an etching stop layer 213 of a conductive material located on the second wiring layer 212 is used to reduce damage to the second wiring layer 212 during the formation of the first conductive plug 218 and the second conductive plug 219. For example, as Figure 2F As shown, the first conductive plug 218 further penetrates the first electrode layer 209, the second conductive plug 219 further penetrates the etch stop layer 213, and the second conductive plug 219 is electrically connected to the second electrode layer 211 via the second wiring layer 212. By way of example, the thickness of the first wiring layer 208 is 1500 angstroms, the thickness of the second wiring layer 212 is 400 angstroms, and the thickness of the first electrode layer 209, the second electrode layer 211, and the etch stop layer is 630 angstroms. Alternatively, the thickness of each film layer in the capacitor structure may be any other suitable thickness.

[0068] This concludes the introduction to the structure of the semiconductor device according to the embodiment of the present application. The complete semiconductor device may also include other component structures, which will not be detailed here.

[0069] In summary, in the semiconductor device of the embodiment of the present application, the dielectric layer is formed by spin coating, and the dielectric layer has a flat top surface, eliminating the CMP process flow, which can simplify the process flow and save costs, while also improving the performance consistency of different capacitor structures, thereby improving device performance. For example, a diffusion barrier layer is also formed to effectively prevent the capacitor structure from failing due to the penetration and diffusion of liquids such as water vapor absorbed in the dielectric layer 215 into the capacitor structure, and can also reduce the edge effect of the capacitor structure.

[0070] The present application also provides a method for manufacturing a semiconductor device, which is used to manufacture the semiconductor device in the above embodiment. Figure 2A-2F as well as Figure 3 The manufacturing method of the semiconductor device of the present application is described in detail. Figure 2F 1 shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application. Figure 3 The flowchart of the method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown. The semiconductor device can be any suitable device known to those skilled in the art. In this embodiment, the technical solution of the present invention is explained and illustrated mainly by taking the semiconductor device as an IPD filter as an example.

[0071] Illustratively, the method for manufacturing a semiconductor device according to an embodiment of the present application includes the following steps:

[0072] First, execute step S1, as Figure 2A As shown, a substrate 200 is provided.

[0073] In one example, the substrate 200 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, or the substrate 200 may include silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). Although several examples of materials that can form the substrate 200 are described herein, any material that can be used as the substrate 200 falls within the spirit and scope of the present application.

[0074] Then, execute step S2, as Figure 2A As shown, an isolation layer 201 is formed on a substrate 200. For example, the isolation layer 201 may be formed by various deposition methods commonly used in the art, such as chemical vapor deposition or atomic layer deposition.

[0075] In one example, the isolation layer 201 plays a role of electrical isolation, and may be an oxide layer (eg, a silicon oxide layer) or any other suitable film layer of a material capable of playing a role of electrical isolation, which is not limited in the present application.

[0076] Then, execute step S3, as Figure 2B As shown, a plurality of capacitor structures spaced apart are formed on the isolation layer 201 , and the capacitor structures include a first electrode layer 209 , an insulating layer 210 , and a second electrode layer 211 stacked sequentially from bottom to top.

[0077] In one example, the capacitor structure is a MIM capacitor structure, wherein the materials of the first electrode layer 209 and the second electrode layer 211 include but are not limited to conductive materials such as titanium nitride, and the materials of the insulating layer 210 include but are not limited to insulating materials such as silicon nitride.

[0078] In one example, if Figures 2A to 2B As shown, the first electrode layer 209, the insulating layer 210, and the second electrode layer 211 can be formed by the following steps: the first electrode material layer 203, the insulating material layer 204, and the second electrode material layer 205 are sequentially deposited on the isolation layer 201, and the first electrode material layer 203, the insulating material layer 204, and the second electrode material layer 205 are patterned to obtain the first electrode layer 209 and the second electrode layer 211. By way of example, the first electrode material layer 203, the insulating material layer 204, and the second electrode material layer 205 can be formed by various deposition methods commonly used in the art, for example, by chemical vapor deposition or atomic layer deposition.

[0079] Then, execute step S4, as Figure 2D As shown, a dielectric layer 215 covering the isolation layer 201 and the capacitor structure is formed by spin coating.

[0080] In one example, the dielectric layer 215 is formed by spin coating, that is, the dielectric layer 215 is obtained by curing the spin-coated solution, so that the dielectric layer 215 has a flat top surface. Compared with the solution of depositing an oxide layer and then performing a CMP process on the oxide layer, the CMP process is omitted, which can simplify the process flow and save costs; at the same time, because the dielectric layer 215 has a flat top surface, the thickness of the dielectric layer 215 above each capacitor structure is equal, and the etching degree for different capacitor structures is the same when the connection holes are subsequently etched to form the connection holes, which improves the performance consistency of different capacitor structures and thereby improves the device performance.

[0081] In one example, the dielectric layer 215 includes an organic dielectric layer, and the material of the organic dielectric layer includes polyimide (PI) or benzocyclobutene (BCB). For example, taking the dielectric layer 215 as an example, the dielectric constants of polyimide and benzocyclobutene are both smaller than the dielectric constant of the oxide layer (the dielectric constant of polyimide is about 3.3, the dielectric constant of benzocyclobutene is about 2.65, and the dielectric constant of the oxide layer is about 4), and the quality factor (Q value) of the capacitor structure is affected by the dielectric constant of the dielectric layer. The smaller the dielectric constant of the dielectric layer, the higher the Q value. Conversely, the larger the dielectric constant of the dielectric layer, the lower the Q value. The dielectric layer 215 is made of polyimide or benzocyclobutene, and has a lower dielectric constant than the dielectric layer made of the oxide layer, thereby improving the Q value of the capacitor structure and thus improving device performance.

[0082] In one example, if Figure 2C and Figure 2D As shown, after forming the capacitor structure and before forming the dielectric layer 215, the process further includes forming a diffusion barrier layer 214. The diffusion barrier layer 214 covers at least a portion of the capacitor structure, and the dielectric layer 215 covers the diffusion barrier layer 214. Exemplarily, the diffusion barrier layer 214 is conformally deposited, for example, by using a chemical vapor deposition process or an atomic layer deposition process to form the diffusion barrier layer 214. Exemplarily, the deposited diffusion barrier layer 214 covers the entire surface of the capacitor structure.

[0083] In one example, the dielectric layer 215 is formed by spin coating. The hygroscopic properties of the film layer that can be formed by spin coating are generally strong (for example, polyimide and benzocyclobutene have strong hygroscopic properties). The diffusion barrier layer 214 can effectively prevent the water vapor and other liquids absorbed in the dielectric layer 215 from penetrating and diffusing into the capacitor structure, thereby effectively preventing the water vapor and other liquids absorbed in the dielectric layer 215 from penetrating and diffusing into the capacitor structure, causing the capacitor structure to fail.

[0084] In one example, the material of the diffusion barrier layer 214 includes silicon nitride, or the material of the diffusion barrier layer 214 can also be any other suitable insulating material that can prevent the diffusion of water vapor in the dielectric layer 215. For example, the second electrode layer 211 in the capacitor structure of the present application covers part of the surface of the insulating layer 210, that is, the size of the second electrode layer 211 is smaller than the size of the insulating layer 210 and the first electrode layer 209, and the diffusion barrier layer 214 covers the exposed surface of the insulating layer 210 (that is, the diffusion barrier layer 214 covers the surface of the insulating layer 210 not covered by the second electrode layer 211), which can reduce the edge effect of the capacitor structure. For example, the material of the diffusion barrier layer 214 is the same as that of the insulating layer 210.

[0085] In one example, if Figure 2BAs shown, the capacitor structure further includes a first wiring layer 208, a second wiring layer 212, and an etch stop layer 213, wherein the first wiring layer 208 is located between the isolation layer 201 and the first electrode layer 209, the second wiring layer 212 is located on the second electrode layer 211, and the etch stop layer 213 is located on the second wiring layer 212. Exemplarily, the material of the first wiring layer 208 and the second wiring layer includes, but is not limited to, a conductive material such as aluminum, and the material of the etch stop layer 213 includes, but is not limited to, a conductive material such as titanium nitride. Exemplarily, the etch stop layer 213, the first electrode layer 209, and the second electrode layer 211 have the same material and the same thickness.

[0086] In one example, if Figures 2A to 2B As shown, the first wiring layer 208, the second wiring layer 212, and the etch stop layer 213 can be formed by the following steps: depositing the first wiring material layer 202, the second wiring material layer 206, and the etch stop material layer 207; and patterning the first wiring material layer 202, the second wiring material layer 206, and the etch stop material layer 207 to obtain the first wiring layer 208, the second wiring material layer 212, and the etch stop layer 213. By way of example, the first wiring material layer 202, the second wiring material layer 206, and the etch stop material layer 207 can be formed by various deposition methods commonly used in the art, such as chemical vapor deposition or atomic layer deposition.

[0087] In one example, if Figure 2F As shown, after forming the dielectric layer 215, the process also includes forming a first conductive plug 218 and a second conductive plug 219, wherein the first conductive plug 218 penetrates the dielectric layer 215 and is electrically connected to the first electrode layer 209, and the second conductive plug 219 penetrates the dielectric layer 215 and is electrically connected to the second electrode layer 211. Exemplarily, the first conductive plug 218 penetrates the dielectric layer 215 above the first electrode layer 209, and the second conductive plug 219 penetrates the dielectric layer 215 above the second electrode layer 211. Exemplarily, when a diffusion barrier layer 214 is formed, the first conductive plug 218 also penetrates the diffusion barrier layer 214 above the first electrode layer 209, and the second conductive plug 219 also penetrates the diffusion barrier layer 214 above the second electrode layer 211.

[0088] In one example, since the thickness of the first electrode layer 209 and the second electrode layer 211 is relatively thin (for example, the thickness of the first electrode layer 209 and the second electrode layer 211 is 630 angstroms), there is a risk of the first electrode layer 209 and the second electrode layer 211 being etched through during the formation of the first conductive plug 218 and the second conductive plug 219. Therefore, a first connection layer 208 of a conductive material is provided below the first electrode layer 209, and a second connection layer 212 of a conductive material is provided above the second electrode layer 211 to avoid device failure due to etching through the first electrode layer 209 and the second electrode layer 211; the etching stop layer 213 on the second connection layer 212 reduces damage to the second connection layer 212 during the formation of the first conductive plug 218 and the second conductive plug 219. Illustratively, the thickness of the first wiring layer 208 is 1500 angstroms, the thickness of the second wiring layer 212 is 400 angstroms, the thickness of the first electrode layer 209, the second electrode layer 211 and the etching stop layer is 630 angstroms, or the thickness of each film layer in the capacitor structure can also be any other suitable thickness.

[0089] In one example, if Figures 2E to 2F As shown, the first conductive plug 218 and the second conductive plug 219 can be formed by the following steps: etching the dielectric layer 215 to form the first connection hole 216 and the second connection hole 217 respectively; filling the first connection hole 216 and the second connection hole 217 with conductive materials (such as copper, manganese and other conductive materials) to form the first conductive plug 218 and the second conductive plug 219. For example, as Figure 2E and Figure 2F As shown, the first connection hole 216 penetrates the first electrode layer 209 and exposes the first wiring layer 208; the second connection hole 217 penetrates the etch stop layer 213 and exposes the second wiring layer 212, and the second conductive plug 219 is electrically connected to the second electrode layer 211 through the second wiring layer 212. In other embodiments, the bottom of the first connection hole 216 may expose the first electrode layer 209, and the bottom of the second connection hole 217 may expose the etch stop layer 213, and the second conductive plug 219 may be electrically connected to the second electrode layer 211 through the etch stop layer 213 and the second wiring layer 212. By way of example, various etching processes commonly used in the art may be used to etch the dielectric layer 215 to form the first connection hole 216 and the second connection hole 217, respectively, and this application is not limited thereto.

[0090] This completes the description of the key steps of the method for manufacturing the semiconductor device of the present application. The manufacture of a complete semiconductor device may also include other steps, which will not be detailed here one by one. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0091] In summary, the method for manufacturing a semiconductor device according to an embodiment of the present application forms a dielectric layer by spin coating, and the dielectric layer has a flat top surface, eliminating the need for a CMP process, thereby simplifying the process and saving costs, while also improving the performance consistency of different capacitor structures, thereby improving device performance. For example, a diffusion barrier layer is also formed to effectively prevent the capacitor structure from failing due to the penetration and diffusion of liquids such as water vapor absorbed in the dielectric layer 215 into the capacitor structure, and to reduce the edge effect of the capacitor structure.

[0092] Although a number of embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be devised by those skilled in the art, all of which fall within the spirit and scope of the concepts disclosed herein. More particularly, within the scope of the present disclosure, the accompanying drawings, and the appended claims, various modifications and changes may be made to the arrangements and / or components of the subject matter in combination. In addition to modifications and changes to the components and / or arrangements, the use of alternatives will also be readily apparent to those skilled in the art.

Claims

1. A semiconductor device, characterized in that: include: substrate; an isolation layer, disposed on the substrate; A plurality of spaced capacitor structures are provided on the isolation layer, wherein the capacitor structures include a first electrode layer, an insulating layer, and a second electrode layer stacked sequentially from bottom to top; A dielectric layer covers the isolation layer and the capacitor structure, wherein the dielectric layer is formed by spin coating.

2. The semiconductor device according to claim 1, wherein The material of the dielectric layer includes an organic dielectric layer, and the material of the organic dielectric layer includes polyimide or benzocyclobutene.

3. The semiconductor device according to claim 1, wherein It also includes a diffusion barrier layer, wherein the diffusion barrier layer covers at least a portion of the capacitor structure, and the dielectric layer covers the diffusion barrier layer.

4. The semiconductor device according to claim 3, wherein The diffusion barrier layer is made of silicon nitride.

5. The semiconductor device according to claim 1, wherein The capacitor structure further includes a first wiring layer, a second wiring layer and an etching stopper layer, wherein the first wiring layer is located between the isolation layer and the first electrode layer, the second wiring layer is located on the second electrode layer; and the etching stopper layer is located on the second wiring layer; The semiconductor device further includes a first conductive plug penetrating the dielectric layer and electrically connected to the first electrode layer, and a second conductive plug penetrating the dielectric layer and electrically connected to the second electrode layer.

6. The semiconductor device according to claim 5, wherein The materials of the first electrode layer, the second electrode layer and the etching stop layer include titanium nitride; The material of the first connection layer and the second connection layer includes aluminum; The material of the insulating layer includes silicon nitride; The isolation layer includes an oxide layer.

7. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming an isolation layer on the substrate; forming a plurality of capacitor structures spaced apart from each other on the isolation layer, wherein the capacitor structures include a first electrode layer, an insulating layer, and a second electrode layer stacked sequentially from bottom to top; A dielectric layer covering the isolation layer and the capacitor structure is formed by spin coating.

8. The manufacturing method according to claim 7, characterized in that The material of the dielectric layer includes an organic dielectric layer, and the material of the organic dielectric layer includes polyimide or benzocyclobutene.

9. The manufacturing method according to claim 7, characterized in that: After forming the capacitor structure and before forming the dielectric layer, the method further includes forming a diffusion barrier layer, wherein the diffusion barrier layer covers at least a portion of the capacitor structure, and the dielectric layer covers the diffusion barrier layer.

10. The manufacturing method according to claim 7, characterized in that: The capacitor structure further includes a first wiring layer, a second wiring layer and an etching stopper layer, wherein the first wiring layer is located between the isolation layer and the first electrode layer, the second wiring layer is located on the second electrode layer; and the etching stopper layer is located on the second wiring layer; After forming the dielectric layer, the step of forming a first conductive plug and a second conductive plug is also included, wherein the first conductive plug penetrates the dielectric layer and is electrically connected to the first electrode layer, and the second conductive plug penetrates the dielectric layer and is electrically connected to the second electrode layer.

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