GaN-based enhanced HEMT (High Electron Mobility Transistor) device with barrier layer etched in groove and preparation method thereof

Abstract

The invention discloses a barrier layer groove etched GaN-based enhanced HEMT (High Electron Mobility Transistor) device and a preparation method thereof, and relates to the technical field of semiconductor device manufacturing, and the device comprises a substrate, a nucleating layer, a buffer layer, a channel layer, a first barrier layer, an etching barrier layer, a second barrier layer, an ion implantation region, a source and drain electrode, a gate dielectric layer, a gate electrode, a passivation layer and a metal interconnection layer. By introducing the high Al component etching barrier layer and combining the multi-groove structure design, the grid leakage performance, the ohmic contact characteristic and the breakdown voltage capability are remarkably improved. The problems of interface state defects, grid electric leakage, insufficient breakdown voltage and the like in an enhanced GaN-based HEMT device adopting a barrier layer etching method can be effectively solved, and the method has important practical application value.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a GaN-based enhanced HEMT device with barrier layer groove etching and a preparation method thereof. Background Art

[0002] GaN-based high electron mobility transistors (HEMTs) show great promise in 5G communications, power electronics, and high-frequency devices due to their high electron mobility, high-voltage resistance, low loss, and excellent thermal stability. The two-dimensional electron gas (2DEG) formed by their heterojunctions far exceeds the density of traditional materials and exhibits a high saturation velocity, making them suitable for high-frequency, high-power applications. In particular, GaN-based HEMTs primarily come in depletion-mode (normally on, D-mode) and enhancement-mode (normally off, E-mode) structures. Depletion-mode HEMTs are widely studied and applied due to their relatively simple structural design. However, the normally-on switch poses circuit safety and loss issues, making research on normally-off HEMTs of practical significance. Currently, the main methods for achieving enhancement-mode GaN-based HEMTs include recessed gate barrier layer etching, P-GaN layer insertion, and fluorine ion implantation. The barrier layer etching method weakens the polarization effect by etching the barrier layer below the gate, thereby achieving an enhancement-mode device. This method is relatively simple and highly feasible, but it suffers from reliability issues such as high gate leakage, current collapse, and low gate withstand voltage. These issues are related to the lattice mismatch between the barrier layer and the gate dielectric, large interface state defects, and etching precision errors. Therefore, it is necessary to find methods to improve the interface state defects between the barrier layer and the gate dielectric and control the etching precision to improve the gate control performance of enhancement-mode HEMT devices. Summary of the Invention

[0003] The present invention aims to provide a GaN-based enhanced-mode HEMT device with barrier layer recess etching and a preparation method thereof, mainly to solve the performance degradation problem of HEMT devices caused by shallow etching or over-etching of the barrier layer and the interface state defect problem caused by the lattice mismatch between the barrier layer and the gate dielectric.

[0004] To achieve the above object, the technical solution adopted by the present invention is as follows: A GaN-based enhanced-mode HEMT device with barrier layer groove etching comprises a substrate and an epitaxial layer prepared on one side of the substrate, wherein the epitaxial layer comprises a nucleation layer, a buffer layer, a channel layer, a first barrier layer and an etch stop layer stacked in sequence from bottom to top on the substrate, and a second barrier layer prepared on the etch stop layer after selective etching; an ion implantation region extending from the second barrier layer downward to the buffer layer is also prepared on the epitaxial layer, a source and drain are provided at the bottom of the groove of the second barrier layer, and a gate dielectric is deposited on the side of the epitaxial layer away from the substrate. A gate is prepared above the gate groove region of the gate dielectric layer, a passivation layer is prepared above the gate dielectric layer and the gate, openings are formed by sequentially etching the passivation layer and the gate dielectric layer above the source, drain and gate, and metal is deposited in the holes to obtain a metal interconnection layer; wherein, the etch stop layer in the gate groove region is etched into a multi-groove structure due to a uniformly arranged regular-shaped mask, the bottom of the groove is a first barrier layer, and the gate dielectric is filled in the groove structure; a two-dimensional electron gas layer is formed at the interface between the channel layer and the first barrier layer due to a polarization effect.

[0005] Furthermore, in the present invention, the material of the first barrier layer is a III-V compound Al x Ga 1-x N, 0.1≤x≤0.2, thickness is 3~5nm; the etching stop layer material is a III-V compound Al y Ga 1-y N, 0.75≤y≤0.8, thickness is 5~10nm; the material of the second barrier layer 107 is a III-V compound Al z Ga 1-z N, 0.2≤z≤0.3, thickness is 23~25nm.

[0006] The present invention also provides a method for preparing the above device, comprising the following steps: S1, selecting a substrate and forming an epitaxial layer on one side of the substrate by metal organic chemical vapor deposition growth technology; S2, using photolithography mask technology to selectively etch the epitaxial layer to prepare a barrier layer groove; S3, preparing a gate dielectric, a passivation layer and electrodes of the HEMT device on the epitaxial layer etched into the barrier layer groove, thereby completing the preparation of the HEMT device.

[0007] Furthermore, in the present invention, the specific process of step S1 is: S11, providing a substrate and cleaning the substrate; S12, sequentially growing a nucleation layer, a buffer layer, a channel layer, a first barrier layer, and an etch stop layer on the substrate using metal organic chemical vapor deposition; S13, using a lithography and development technique to form a mask on the etch stop layer in the recessed regions of the source and drain electrodes and the gate electrodes, and selectively etching using an inductively coupled plasma etching device to remove the etch stop layer outside the source and drain electrode and gate regions to form an epitaxial wafer; S14, cleaning the epitaxial wafer to remove the photoresist, and then soaking the epitaxial wafer with diluted HCl and ultrapure water in a ratio of 1:10 to remove residual stains after etching, and then passivating the defects after etching by plasma cleaning; S15, using metal organic chemical vapor deposition to continue growing a second barrier layer on the first barrier layer, and the second barrier layer continues to grow after covering the etching stop layer to obtain an epitaxial layer; wherein, after the growth of the second barrier layer is completed, a two-dimensional electron gas layer is formed due to the polarization effect between the channel layer and the first barrier layer and the second barrier layer.

[0008] Furthermore, in the present invention, the substrate is any one of a sapphire substrate, a Si substrate, a GaN substrate, and a SiC substrate.

[0009] Furthermore, in the present invention, the specific process of step S2 is: S21, using a lithography and development technique to define the active area of ​​the HEMT device on the epitaxial layer to form a device isolation mask, and using an ion implantation device to complete the device isolation; S22, cleaning the epitaxial layer after device isolation, forming a mask on the second barrier layer in the recessed regions of the source and drain electrodes and the gate electrodes using a photolithography and development technology, and selectively etching using a plasma etching device to remove the second barrier layer in the recessed regions of the source and drain electrodes and the gate electrodes; S23, cleaning the etched epitaxial layer, forming a mask on the etch barrier layer in the source and drain groove regions and the gate groove region using a uniform photolithography and development technology; etching the etch barrier layer in the source and drain groove regions and the gate groove region using ICP; wherein the etch barrier layer in the gate groove region is etched into a structure having multiple grooves due to the multiple uniformly distributed photoresist masks, and the bottoms of the etch barrier layers in the multiple grooves are the first barrier layer; S24, after etching is completed, the epitaxial layer is cleaned to remove the photoresist, and diluted HCl and ultrapure water are used in a ratio of 1:10 to soak the epitaxial layer to remove the residual stains after etching, and finally plasma cleaning is used to passivate the defects after etching to complete the barrier layer groove etching.

[0010] Furthermore, in the present invention, the specific process of step S3 is: S31, cleaning the epitaxial layer after etching, forming a mask on the groove area of ​​the source and drain electrodes using a photolithography and development technology, performing metal evaporation on the source and drain electrodes using an electron beam evaporation device, and obtaining the source and drain electrodes in ohmic contact with the first barrier layer by high-temperature rapid annealing after metal stripping; S32, depositing a gate dielectric layer on the second barrier layer using a plasma enhanced chemical vapor deposition device, wherein the bottom of the gate dielectric layer in the recessed region of the gate contacts the first barrier layer, and after filling the recessed region of the etch stop layer, further deposition is continued to cover the recessed structure; S33, using a lithography process to form a mask on the gate groove region, and using an electron beam evaporation device to evaporate metal on the gate dielectric in the gate groove region to form a gate; S34, using plasma enhanced chemical vapor deposition to form a passivation layer on the gate dielectric layer, and using photoresist lithography and development technology to form opening masks for the source, drain, and gate electrodes; S35, using a plasma etching device to sequentially etch the passivation layer and the gate dielectric layer in the source and drain regions to form openings; S36: After the hole etching is completed, dilute HCl and ultrapure water in a ratio of 1:10 to soak the epitaxial wafer to remove the residual stains after etching. Use electron beam evaporation equipment to evaporate metal in the hole area to prepare a metal interconnection layer to complete the HEMT device preparation.

[0011] Furthermore, in the present invention, the nucleation layer is AlN material with a thickness of 20~100nm; the buffer layer is a high-resistance GaN material doped with carbon or Al components with a thickness of 500~650nm; and the channel layer is a low-doped GaN material with a thickness of 150~200nm.

[0012] Furthermore, in the present invention, the groove etching shape of the etch stop layer is a plurality of vertical grooves, trapezoidal grooves, and inverted trapezoidal groove structures that are uniformly and regularly arranged.

[0013] Furthermore, in the present invention, the electrode structure of the source and drain is a Ti / Al / Ni / Au metal stacking structure; the corresponding metal thickness is 20 / 130 / 50 / 100nm; the electrode structure of the gate is a Ni / Au metal stacking structure, and the corresponding metal thickness is 50 / 100nm; the electrode metal of the metal interconnection layer is the same as the metal stacking structure of the gate; the gate dielectric is dense Si3N4 with a thickness of 35~50nm.

[0014] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention divides the barrier layer into a first barrier layer and a second barrier layer by inserting an etching barrier layer, which can better control the etching rate of the barrier layer. The high selective etching ability of the etching barrier layer prevents the bottom first barrier layer from being over-etched and causing interface defects, forming a natural ohmic groove that is conducive to ohmic contact, thereby greatly reducing the ohmic contact resistance and improving the output current and high-frequency response capability of the device.

[0015] (2) The present invention avoids the problem of insufficient gate turn-off capability caused by shallow etching of the barrier layer or loss of channel 2DEG caused by over-etching by inserting the etch barrier layer, which is beneficial to the precise etching requirement of the thin barrier layer in the gate region of the enhancement mode device; more importantly, the lattice matching degree between the etch barrier layer and the gate dielectric is lower. Through the design of the etch barrier layer groove, the gate dielectric can better form a lattice buffer with the first barrier layer during the filling process, reducing problems such as interface defects caused by lattice mismatch, and improving the gate control capability and leakage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 1 is a schematic structural diagram of a GaN-based HEMT device provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of a process for preparing an epitaxial layer of a GaN-based HEMT device provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of a barrier layer groove etching process for a GaN-based HEMT device provided by an embodiment of the present invention; Figure 4 This is a schematic diagram of a top view of the structure of a GaN-based HEMT device after epitaxial layer etching provided by an embodiment of the present invention; Figure 5 This is a schematic diagram of a process for preparing an electrode of a GaN-based HEMT device provided by an embodiment of the present invention; Figure 6 This is a schematic structural diagram of another GaN-based HEMT device provided in Comparative Example 1 of the present invention; Figure 7 Schematic diagram of the structure of another GaN-based HEMT device provided in Comparative Example 2 of the present invention; The names corresponding to the reference numerals are: 100. HEMT device; 101. Substrate; 102. Nucleation layer; 103. Buffer layer; 104. Channel layer; 105. First barrier layer; 106. Etch stop layer; 107. Second barrier layer; 108. Two-dimensional electron gas layer; 109. Ion implantation region; 110. Source and drain; 111. Gate dielectric layer; 112. Gate; 113. Passivation layer; 114. Metal interconnect layer. DETAILED DESCRIPTION

[0017] The present invention will be further described below with reference to the accompanying drawings and examples. The embodiments of the present invention include but are not limited to the following examples.

[0018] like Figure 1 As shown, the present invention discloses a GaN-based enhanced HEMT device with barrier layer groove etching and a preparation method thereof. The schematic diagram of the HEMT device structure is shown in FIG. Figure 1 As shown, from bottom to top, there are: substrate 101, nucleation layer 102, buffer layer 103, channel layer 104, first barrier layer 105, etch stop layer 106, second barrier layer 107, ion implantation region 109, source and drain 110, gate dielectric layer 111, gate 112, passivation layer 113, metal interconnect layer 114. A two-dimensional electron gas layer 108 is generated at the interface between the channel layer 104 and the first barrier layer 105 due to the polarization effect. The material of the first barrier layer 105 is a III-V compound Al x Ga 1-x N, 0.1≤x≤0.2, thickness is 3~5nm; the etch stop layer 106 material is a III-V compound Al y Ga 1-y N, 0.75≤y≤0.8, thickness is 5~10nm. The material of the second barrier layer 107 is a III-V compound Al z Ga 1-z N, 0.2≤z≤0.3, thickness is 23~25nm. x Ga 1-x N, 0≤x≤1 materials have different etching rates for the same etching conditions. Generally, the higher the Al content, the slower the etching rate. y Ga 1-y The material with a N value of 0.75≤y≤0.8 serves as the etch barrier layer 106, acting as an etch stop layer. This protects the underlying first barrier layer 105 from overetching and grain boundary defects, and facilitates precise control of the recess etching process. The gate region's etch barrier layer 106 has a uniformly arranged periodic recess structure, with the first barrier layer 105 exposed at the bottom of the recess. The recess is filled with a gate dielectric layer 111, which is thicker than the etch barrier layer 106 and covers the etch barrier layer 106, forming a gate structure recess.

[0019] like Figure 2 FIG. 1 is a schematic diagram of a process for preparing an epitaxial layer of a GaN-based HEMT device 100 by etching a barrier layer groove. The barrier layer is divided into a first barrier layer 105 and a second barrier layer 107 by inserting an etch stop layer 106. The method includes the following steps: Provide a substrate, which can be any one of a sapphire Al2O3 substrate, a Si substrate, a GaN substrate, and a SiC substrate. In this embodiment, Si is used as the substrate; The Si substrate is cleaned and a nucleation layer 102, a buffer layer 103, a channel layer 104, a first barrier layer 105, and an etch stop layer 106 are sequentially grown on the substrate 101 using MOCVD (metal organic chemical vapor deposition). The nucleation layer 102 is made of AlN material with a thickness of 20 to 100 nm. The buffer layer 103 is made of a high-resistance GaN material doped with carbon or Al components with a thickness of 500 to 650 nm. The channel layer 104 is made of a low-doped GaN material with a thickness of 150 to 200 nm. The first barrier layer 105 is made of a III-V compound Al. x Ga 1-x N, 0.1≤x≤0.2, thickness is 3~5nm; the etch stop layer 106 material is a III-V compound Al y Ga 1-y N, 0.75≤y≤0.8, thickness of 5~10nm; using uniform photolithography and development technology to form a mask for the etch barrier layer 106 in the source, drain, and gate groove areas, and using inductively coupled plasma etching equipment ICP to perform selective etching to remove the etch barrier layer 106 outside the source, drain, and gate groove areas; after etching is completed, the epitaxial wafer is cleaned to remove the photoresist, and a solution of 15% dilute HCl and ultrapure water diluted in a ratio of 1:10 is used to soak the epitaxial wafer to remove residual stains after etching, and then the defects after etching are passivated by plasma cleaning.

[0020] After cleaning and etching the epitaxial wafer, MOCVD is used to continue growing the second barrier layer 107 on the substrate; the second barrier layer 107 covers the etching stop layer 106 and then continues to grow to obtain an epitaxial layer, and the second barrier layer 107 is a III-V compound Al z Ga 1-z N, 0.2≤z≤0.3, thickness is 23-25 ​​nm; after the second barrier layer 107 is grown, a two-dimensional electron gas layer 108 is formed due to the polarization effect between the channel layer 104 and the first barrier layer 105 and the second barrier layer 107 .

[0021] like Figure 3 FIG. 1 is a schematic diagram of a GaN-based HEMT device 100 for etching a recessed epitaxial layer by etching a barrier layer. Precise etching of the source / drain recessed region and the gate recessed region is accomplished by selectively etching the barrier layer 106. The fabrication steps include: The epitaxial layer grown on the second barrier layer 107 is subjected to a lithography and development technique to define the active region of the device to form a device isolation mask, and an ion implantation device IMP is used to complete the device isolation; The epitaxial layer after device isolation is cleaned, and a mask is formed on the second barrier layer 107 in the source, drain, and gate groove areas using a uniform photolithography and development technology. Selective etching is performed using ICP to remove the second barrier layer 107 in the source, drain, and gate groove areas. After etching, the epitaxial layer is cleaned to remove the photoresist, and the epitaxial layer is immersed in a solution of 15% diluted HCl and ultrapure water in a ratio of 1:10 to remove residual stains after etching. Finally, plasma cleaning is used to passivate defects after etching.

[0022] The epitaxial layer after etching is cleaned, and a mask is formed on the etch barrier layer 106 in the source, drain and gate groove areas by using a uniform photolithography and development technology. Selective etching is performed using ICP to remove the etch barrier layer 106 in the source, drain and gate groove areas. The etch barrier layer 106 in the source and drain grooves is completely etched. The etch barrier layer 106 in the gate groove area forms an etch barrier layer 106 with multiple grooves due to the uniformly distributed photoresist mask. The bottom of the etch barrier layer 106 in the multiple grooves is the first barrier layer 105. After etching is completed, the epitaxial layer is cleaned to remove the photoresist, and the epitaxial layer is immersed in a solution diluted with 15% dilute HCl and ultrapure water in a ratio of 1:10 to remove residual stains after etching. Finally, plasma cleaning is used to passivate the defects after etching to complete the etching of the barrier layer grooves.

[0023] like Figure 4 FIG. 1 is a schematic top-down view of the structure of the GaN-based HEMT device 100 after epitaxial layer etching according to an embodiment of the present invention. The etch stop layer 106 in the gate recess region is etched into a plurality of evenly spaced recesses using a mask. The bottom of the recesses of the etch stop layer 106 is the first barrier layer 105. In other words, the gate recess region is a region where the etch stop layer 106 at the top of the recess and the first barrier layer 105 at the bottom of the recess are evenly spaced in that order. The recesses of the etch stop layer 106 can have shapes that include not only long strips but also circular columns, square columns, and other structures. The etching of the recesses of the etch stop layer 106 includes not only vertical etching methods but also trapezoidal etching, inverted trapezoidal etching, and other methods.

[0024] like Figure 5 FIG. 1 shows a process for preparing an electrode of a GaN-based HEMT device 100 according to an embodiment of the present invention. The preparation steps include: After etching the epitaxial layer, it is cleaned and a mask is formed in the source and drain groove regions using a photolithography and development technique. Electron beam evaporation equipment (E-beam) is used to evaporate metal for the source and drain electrodes. The electrode structure is a Ti / Al / Ni / Au metal stack. The electrode thickness can be 20 / 130 / 50 / 100 nm. After metal stripping, rapid annealing is performed at 875°C for 30 seconds to achieve ohmic contact between the source and drain electrodes, thereby obtaining source and drain electrodes 110. Due to the presence of the natural grooves in the source and drain electrodes 110, the ohmic contact resistance is greatly reduced, thereby increasing the device drive current. A dense Si3N4 gate dielectric layer 111 with a thickness of 35 to 50 nm is deposited above the device using PECVD (plasma-enhanced chemical vapor deposition). The bottom of the gate dielectric layer 111 in the gate recess region contacts the first barrier layer 105. The recess region is filled with the etch stop layer 106, and then the recess structure is covered by further deposition. Subsequently, a mask is formed in the gate recess region using photoresist, photolithography, and development. A gate 112 is formed in the gate recess region using an E-beam and metal is evaporated using a Ni / Au metal stack structure with an electrode thickness of 50 / 100 nm. The gate 112 forms a Schottky contact with the dense Si3N4 gate dielectric layer 111 in the gate recess, thereby enabling the gate 112 to control the turn-off of the GaN-based HEMT device 100. PECVD is used to deposit Si3N4 with a thickness of 350-500 nm on the device to prepare a passivation layer 113. Photoresist coating, photolithography, and development techniques are used to form opening masks for the source and drain electrodes 110 and the gate electrode 112. In the opening area, ICP is used to sequentially etch the passivation layer 113 and the gate dielectric layer 111 in the source and drain areas to form a through hole. After the opening etching is completed, a dilute HCl concentration of 15% and ultrapure water in a ratio of 1:10 is used to wet the epitaxial layer to remove residual stains after etching. E-beam is used to evaporate metal in the through hole area to prepare a metal interconnection layer 114, completing the preparation of the GaN-based HEMT device 100. The metal interconnection layer 114 has the same metal stacking structure as the gate electrode 112.

[0025] Due to the high Al content y Ga 1-y The N (0.75≤y≤0.8) etch stop layer 106 is inserted between the first barrier layer 105 and the second barrier layer 107. Through the selective etching of different Al components, the over-etching of the first barrier layer 105 is avoided, and the ohmic contact performance of the source and drain is improved. In addition, the etch stop layer 106 in the gate area is uniformly etched into a groove structure. Filling the gate dielectric layer 111 in the groove of the etch stop layer 106 not only increases the contact area between the gate dielectric layer 111 and the etch stop layer 106, but also forms a natural barrier at the boundary of the groove structure, which plays a better role in blocking carrier diffusion, thereby greatly improving the gate leakage problem. The presence of the groove also releases the lattice mismatch stress and avoids the interface state problem caused by the mismatch of the material interface. In addition, since the electric field at the corner of the groove is relatively concentrated, filling the gate dielectric layer 111 in the groove can realize the field plate effect, which is also of practical significance for improving the breakdown voltage of the device.

[0026] Comparative Example 1 As a comparison with the above embodiment, the present invention also provides another GaN-based HEMT device 100, the device structure diagram is shown in FIG. Figure 6As shown; the structural difference between this device and the GaN-based HEMT device 100 of the embodiment is the difference in the groove etching of the etch stop layer 106 in the gate region; the etch stop layer 106 in the gate groove region of the GaN-based HEMT device 100 in this comparative example does not adopt a groove etching structure, that is, it is only necessary to use the photolithography and development technology to form a mask on the etch stop layer 106 in the source and drain regions and then use ICP etching without removing the etch stop layer 106 in the gate groove region. The gate dielectric layer 111 in the gate groove region of the device is deposited on the flat and unetched etch stop layer 106. Since the etch stop layer 106 material is the III-V compound Al y Ga 1-y N, 0.75≤y≤0.8, has a large lattice mismatch problem with the Si3N4 gate dielectric layer 111, so the interface trap states generated by the two will increase the gate leakage problem and reduce the gate's ability to turn off the device.

[0027] Comparative Example 2 As a comparison with the above embodiment, the present invention also provides another GaN-based HEMT device 100, the device structure diagram is shown in FIG. Figure 7 As shown; the epitaxial structure of the device in this comparative example is different from that of the GaN-based HEMT device 100 of the embodiment; in this comparative example, no etching stop layer is inserted into the first barrier layer 105 of the device, that is, the epitaxial growth process sequentially grows a nucleation layer 102, a buffer layer 103, a channel layer 104, and a first barrier layer 105 on the substrate 101, wherein the first barrier layer 105 is a III-V compound Al x Ga 1-x N, 0.1≤x≤0.3, thickness is 28~30nm; after the device isolation is completed, the epitaxial layer uses the uniform photolithography and development technology to form a mask for the first barrier layer 105 in the source, drain and gate regions, and uses ICP to etch to a distance of 3~6nm from the bottom of the first barrier layer 105, then deposits the source and drain metals, and anneals to obtain the source and drain 110; deposits the gate dielectric layer 111 on the device, and finally deposits the gate metal on the gate dielectric layer 111 in the gate groove region to obtain the gate 112; since the Al composition in the first barrier layer 105 is not much different, the precise control capability of ICP selective etching is poor, and over-etching and under-etching of the first barrier layer 105 in the source, drain and gate regions will lead to reduced device performance; in addition, there is a large lattice mismatch problem between the first barrier layer 105 and the Si3N4 gate dielectric layer 111, which is similar to the device in Comparative Example 1, which is not conducive to improving the gate leakage capability and gate control capability.

[0028] Through the above design, the present invention divides the barrier layer into a first barrier layer and a second barrier layer by inserting an etch barrier layer, which can better control the etching rate of the barrier layer. The high selective etching ability of the etch barrier layer prevents the bottom first barrier layer from being over-etched and causing interface defects, forming a natural ohmic groove that is conducive to ohmic contact, thereby greatly reducing the ohmic contact resistance and improving the device output current and high-frequency response capability.

[0029] The above embodiment is only one of the preferred implementation methods of the present invention and should not be used to limit the scope of protection of the present invention. Any changes or modifications that have no substantive meaning made to the main design concept and spirit of the present invention, as long as the technical problems solved are still consistent with the present invention, should be included in the scope of protection of the present invention.

Claims

1. A GaN-based enhanced HEMT device with barrier layer groove etching, comprising a substrate (101) and an epitaxial layer prepared on one side of the substrate (101), characterized in that: The epitaxial layer comprises a nucleation layer (102), a buffer layer (103), a channel layer (104), a first barrier layer (105) and an etching stop layer (106) stacked in sequence from bottom to top on a substrate (101), and a second barrier layer (107) prepared on the etching stop layer (106) after selective etching; an ion implantation region (109) extending downward from the second barrier layer (107) to the buffer layer (103) is also prepared on the epitaxial layer, a source and drain electrode (110) is provided at the bottom of the source and drain electrode groove region of the second barrier layer (107), a gate dielectric layer (111) is deposited on the epitaxial layer away from the substrate (101), and a gate dielectric layer (111) is deposited on the gate dielectric layer. A gate (112) is prepared above the gate groove region of the layer (111), a passivation layer (113) is prepared above the gate dielectric layer (111) and the gate (112), openings are formed by sequentially etching the passivation layer (113) and the gate dielectric layer (111) above the source and drain (110) and the gate (112), and metal is deposited in the holes to obtain a metal interconnection layer (114); wherein the etching barrier layer in the gate groove region is etched into a multi-groove structure, the bottom of the multi-groove structure is a first barrier layer, and the gate dielectric is filled in the groove structure; and a two-dimensional electron gas layer (108) is formed at the interface between the channel layer (104) and the first barrier layer (105) due to a polarization effect.

2. The GaN-based enhancement mode HEMT device with barrier layer groove etching according to claim 1, characterized in that: The material of the first barrier layer (105) is a III-V compound Al x Ga 1-x N, 0.1≤x≤0.2, thickness is 3~5nm; the etching stop layer (106) material is a III-V compound Al y Ga 1-y N, 0.75≤y≤0.8, thickness is 5~10nm; the material of the second barrier layer (107) is a III-V compound Al z Ga 1-z N, 0.2≤z≤0.3, thickness is 23~25nm.

3. A method for preparing a GaN-based enhancement mode HEMT device with barrier layer groove etching, characterized in that: The method for preparing the GaN-based enhancement-mode HEMT device according to claim 2 comprises the following steps: S1, selecting a substrate and forming an epitaxial layer on one side of the substrate by metal organic chemical vapor deposition growth technology; S2, using photolithography mask technology to selectively etch the epitaxial layer to prepare a barrier layer groove; S3, preparing a gate dielectric, a passivation layer and electrodes of the HEMT device on the epitaxial layer etched into the barrier layer groove, thereby completing the preparation of the HEMT device.

4. The method for preparing a GaN-based enhancement mode HEMT device with barrier layer groove etching according to claim 3, characterized in that: The specific process of step S1 is: S11, providing a substrate and cleaning the substrate; S12, using metal organic chemical vapor deposition to sequentially grow a nucleation layer (102), a buffer layer (103), a channel layer (104), a first barrier layer (105), and an etching stop layer (106) on the substrate (101); S13, using a uniform photolithography and development technology to form a mask on the etch barrier layer (106) in the groove area of ​​the source and drain electrodes (110) and the groove area of ​​the gate electrode (112), and using an inductively coupled plasma etching device to perform selective etching to remove the etch barrier layer (106) outside the source and drain electrodes (110) and the gate electrode (112) areas to form an epitaxial wafer; S14, cleaning the epitaxial wafer to remove the photoresist, and then soaking the epitaxial wafer with diluted HCl and ultrapure water in a ratio of 1:10 to remove residual stains after etching, and then passivating the defects after etching by plasma cleaning; S15, using metal organic chemical vapor deposition to continue growing a second barrier layer (107) on the first barrier layer (105), and the second barrier layer (107) continues to grow after covering the etching stop layer (106) to obtain an epitaxial layer; wherein, after the second barrier layer (107) is grown, a two-dimensional electron gas layer (108) is formed due to the polarization effect between the channel layer (104), the first barrier layer (105) and the second barrier layer (107).

5. The method for preparing a GaN-based enhancement mode HEMT device with barrier layer groove etching according to claim 3, characterized in that: The substrate is any one of a sapphire substrate, a Si substrate, a GaN substrate, and a SiC substrate.

6. The method for preparing a GaN-based enhancement mode HEMT device with barrier layer groove etching according to claim 3, characterized in that: The specific process of step S2 is: S21, using a lithography and development technique to define the active area of ​​the HEMT device on the epitaxial layer to form a device isolation mask, and using an ion implantation device to complete the device isolation; S22, cleaning the epitaxial layer after device isolation, using a uniform photolithography and development technology to form a mask on the second barrier layer (107) in the groove area of ​​the source and drain electrodes and the groove area of ​​the gate electrode, and using a plasma etching device to perform selective etching to remove the second barrier layer (107) in the groove area of ​​the source and drain electrodes and the groove area of ​​the gate electrode; S23, cleaning the etched epitaxial layer, forming a mask on the etch barrier layer (106) in the source and drain groove regions and the gate groove region using a uniform photolithography and development technology; etching the etch barrier layer (106) in the source and drain groove regions and the gate groove region using ICP; wherein the gate groove region is etched into a structure having multiple grooves due to multiple uniformly distributed photoresist masks, and the bottom of the etch barrier layer (106) in the multiple grooves is the first barrier layer (105); S24, after etching is completed, the epitaxial layer is cleaned to remove the photoresist, and diluted HCl and ultrapure water are used in a ratio of 1:10 to soak the epitaxial layer to remove the residual stains after etching, and finally plasma cleaning is used to passivate the defects after etching to complete the barrier layer groove etching.

7. The method for preparing a GaN-based enhancement mode HEMT device with barrier layer groove etching according to claim 3, characterized in that: The specific process of step S3 is: S31, cleaning the epitaxial layer after etching, forming a mask on the groove area of ​​the source and drain electrodes using a photolithography and development technology, performing metal evaporation on the source and drain electrodes using an electron beam evaporation device, and obtaining a source and drain electrode (110) in ohmic contact with the first barrier layer (105) by high-temperature rapid annealing after metal stripping; S32, using plasma enhanced chemical vapor deposition equipment to deposit a gate dielectric layer (111) above the second barrier layer (107), wherein the bottom of the gate dielectric layer (111) in the recessed region of the gate contacts the first barrier layer (105), and after filling the recessed region of the etching stop layer (106), further deposition is continued to cover the recessed structure; S33, using a photolithography developer to form a mask on the gate groove area, and using an electron beam evaporation device to evaporate metal on the gate dielectric in the gate groove area to prepare a gate (112); S34, using plasma enhanced chemical vapor deposition to prepare a passivation layer (113) above the gate dielectric layer, and using photoresist lithography and development technology to form opening masks for the source and drain electrodes (110) and the gate electrode (112); S35, using plasma etching equipment to sequentially etch the passivation layer (113) and the gate dielectric layer (111) in the source and drain regions to form openings; S36, after the hole etching is completed, dilute HCl and ultrapure water in a ratio of 1:10 and then soak the epitaxial wafer to remove the residual stains after etching, use electron beam evaporation equipment to evaporate metal in the hole area to prepare a metal interconnection layer (114), and complete the preparation of the HEMT device.

8. The method for preparing a GaN-based enhancement mode HEMT device with barrier layer groove etching according to claim 4, characterized in that: The nucleation layer (102) is made of AlN material with a thickness of 20 to 100 nm; the buffer layer (103) is made of high-resistance GaN material doped with carbon or Al components with a thickness of 500 to 650 nm; and the channel layer (104) is made of low-doped GaN material with a thickness of 150 to 200 nm.

9. The method for preparing a GaN-based enhancement mode HEMT device with barrier layer groove etching according to claim 6, characterized in that: The groove etching shape of the etching stop layer is a plurality of vertical grooves, trapezoidal grooves, and inverted trapezoidal groove structures that are evenly and regularly arranged.

10. The method for preparing a GaN-based enhancement mode HEMT device with barrier layer groove etching according to claim 7, characterized in that: The electrode structure of the source and drain is a Ti / Al / Ni / Au metal stacking structure; the corresponding metal thickness is 20 / 130 / 50 / 100 nm; the electrode structure of the gate is a Ni / Au metal stacking structure, and the corresponding metal thickness is 50 / 100 nm; the electrode metal of the metal interconnection layer (114) is the same as the metal stacking structure of the gate (112); the gate dielectric is dense Si3N4, and the thickness is 35-50 nm.

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