Intelligent super-junction semiconductor structure

Abstract

The invention relates to an intelligent super-junction semiconductor structure, which comprises a main semiconductor and at least one functional semiconductor which are integrally arranged, and is characterized in that the functional semiconductor comprises a functional isolation region and a functional active region arranged in the functional isolation region; the functional active region comprises a plurality of first conductive type functional columns and second conductive type functional columns which are arranged in parallel, and the functional isolation region comprises second conductive type first extension columns arranged at the two ends of the second conductive type functional columns and second conductive type second extension columns arranged at the two sides of the functional active region; according to the invention, the peak electric field is effectively reduced, the stable isolation voltage can be ensured, the electric field curve is smoother, and on the basis that the same isolation voltage is achieved, the isolation voltage is improved, and the isolation performance is improved. The area of the isolation terminal can be effectively reduced, so that the chip area is reduced, and the chip area is saved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an intelligent superjunction semiconductor structure. Background Art

[0002] Semiconductor devices are electronic devices with electrical conductivity between that of good conductors and insulators. They use the special electrical properties of semiconductor materials to perform specific functions. They can be used to generate, control, receive, transform, amplify signals and perform energy conversion. With the rapid development of emerging industries such as new energy, there is an increasing demand for high-power, high-voltage, and high-reliability power semiconductor devices. Among them, superjunction devices, as a new type of power device, are widely used in high-voltage and high-power power electronic equipment due to their advantages of low on-resistance and high breakdown voltage.

[0003] Intelligent superjunction semiconductor devices are based on ordinary superjunction devices and integrate functional semiconductors such as sampling semiconductors, start-up semiconductors, and high-resistance R, or only integrate one of the sampling semiconductor and start-up semiconductor, and the functions of each other are independent and do not affect each other under working conditions; superjunction products are composed of multiple groups of P / N columns alternately connected. In order to ensure that the functional semiconductors are independent of each other, isolation design is required between the functional semiconductors. For isolation design, it is also achieved through the arrangement of P / N columns. When arranging the isolation P / N columns, the isolation voltage between MOS and the withstand voltage of the tube core need to be considered.

[0004] In the current prior art, Figure 1 As shown in the figure, the isolation design of the intelligent super junction semiconductor device is only achieved by designing horizontal P / N columns between the vertical P / N columns. Although this isolation design can meet the voltage withstand requirements of the die, in actual operation, the active areas of the sampling semiconductor and the starting semiconductor will be connected to the main active area of ​​the device after the high-temperature annealing process, resulting in unstable isolation voltage, large fluctuations, and even lower than 50V. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide an intelligent superjunction semiconductor structure to solve the technical problem in the prior art that the isolation voltage is unstable and fluctuates greatly, resulting in a low isolation voltage.

[0006] The present invention provides a smart superjunction semiconductor structure, comprising an integrated main semiconductor and at least one functional semiconductor, wherein the functional semiconductor is arranged within the main semiconductor, and the functional semiconductor comprises a functional isolation region and a functional active region arranged within the functional isolation region; The functional active area includes a plurality of first conductive type functional columns and second conductive type functional columns arranged in parallel, wherein the first conductive type functional columns and the second conductive type functional columns are both extended along a first direction, and the first conductive type functional columns and the second conductive type functional columns are alternately arranged along a second direction; The functional isolation region includes a second conductive type first extension column arranged at both ends of the second conductive type functional column along the first direction and a second conductive type second extension column arranged on both sides of the functional active area. The second conductive type second extension column and the functional active area are arranged along the second direction, and the widths of the second conductive type first extension column and the second conductive type second extension column are both smaller than the width of the second conductive type functional column.

[0007] Optionally, at least two second conductive type first extension columns are provided at each end of the second conductive type functional column, and the second conductive type functional column is connected to one end of the second conductive type first extension column, and adjacent second conductive type first extension columns are separated by the first conductive type functional column.

[0008] Optionally, the width of the second conductive type first extension column and the second conductive type second extension column is set to half the width of the second conductive type functional column.

[0009] Optionally, the second conductive type first extension pillar and the first conductive type functional pillar between two adjacent second conductive type first extension pillars have the same width.

[0010] Optionally, the main semiconductor includes a main terminal area and a main active area arranged in the main terminal area, wherein the main active area has several first conductive type main columns and second conductive type main columns arranged in parallel, the first conductive type main columns and the second conductive type main columns are both extended along the first direction, and the first conductive type main columns and the second conductive type main columns are alternately arranged along the second direction.

[0011] Optionally, the main terminal area includes a second conductive type third extension column arranged at both ends of the second conductive type main column along the first direction and a second conductive type fourth extension column arranged on both sides of the main active area, the second conductive type fourth extension column and the functional active area are arranged along the second direction, and the widths of the second conductive type third extension column and the second conductive type fourth extension column are both smaller than the width of the second conductive type main column.

[0012] Optionally, at least two second conductive type third extension columns are provided at each end of the second conductive type main column, and the second conductive type functional column is connected to one end of the second conductive type first extension column, and adjacent second conductive type third extension columns are separated by the first conductive type main column.

[0013] Optionally, the width of the second conductive type third extension column and the second conductive type fourth extension column are both set to half the width of the second conductive type main column.

[0014] Optionally, the functional semiconductor is configured as a sampling semiconductor and / or a starting semiconductor.

[0015] Optionally, the semiconductor structure is configured as a MOSFET structure or an IGB structure.

[0016] The technical solution of the present invention has the following advantages: The intelligent superjunction semiconductor structure provided by the present invention isolates the functional active area by setting a second conductive type first extension column and a second conductive type second extension column, and has good isolation effect. After the semiconductor structure undergoes a high-temperature annealing process, the independence of the functional active area can still be guaranteed, and the terminal electric field is smoother, which effectively reduces the peak electric field. Therefore, it can be ensured that when the main semiconductor voltage remains unchanged, a stable isolation voltage can be guaranteed, and the design window is increased to more than 200V. In addition, while enhancing the isolation voltage, since the functional isolation area adopts the second conductive type first extension column and the second conductive type second extension column of the same type as the functional active area, the width of the second conductive type first extension column and the second conductive type second extension column is smaller than the second conductive type functional column, and the electric field curve is smoother. On the basis of achieving the same isolation voltage, the isolation terminal area can be effectively reduced, thereby reducing the chip area and saving the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic diagram of the structure of the background technology of the present invention; Figure 2 This is an overall structural diagram of the smart superjunction semiconductor structure of the present invention.

[0019] Description of reference numerals: 1. Main semiconductor; 11. Main active area; 111. First conductive type main column; 112. Second conductive type main column; 12. Main terminal area; 121. Second conductive type third extension column; 122. Second conductive type fourth extension column; 2. Functional semiconductor; 21. Functional active area; 211. First conductive type functional column; 212. Second conductive type functional column; 22. Functional isolation area; 221. Second conductive type first extension column; 222. Second conductive type second extension column. DETAILED DESCRIPTION

[0020] Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, and not all, of the embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the description of the present invention without inventive effort are intended to fall within the scope of protection of the present invention.

[0021] Unless otherwise specified or limited, the terms "disposed," "installed," and "connected" should be interpreted broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; and direct or indirect connections through an intermediary. Those skilled in the art will understand the specific meanings of these terms based on the specific circumstances.

[0022] The directions or positional relationships indicated by terms such as "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inside" and "outside" are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience and simplification of description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, they should not be understood as limiting the present invention.

[0023] The terms "first," "second," "third," etc. are merely used to distinguish between elements of similar nature and do not indicate or imply relative importance or a particular order.

[0024] The terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than the listed elements and may also include additional elements not specifically listed.

[0025] Example The present invention provides an intelligent superjunction semiconductor structure, wherein the semiconductor structure is configured as a MOSFET structure or an IGBT structure. In this embodiment, the MOSFET structure is taken as an example. The MOSFET structure includes an N-type MOSFET structure and a P-type MOSFET structure. For the N-type MOSFET structure, the first conductivity type is N-type and the second conductivity type is P-type; for the P-type MOSFET structure, the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, the N-type MOSFET structure is taken as an example. The direction indicated by the arrow M in the figure is the first direction, and the direction indicated by the arrow N is the second direction.

[0026] Reference Figure 2 As shown, the smart superjunction semiconductor structure includes an integrated main semiconductor 1 and at least one functional semiconductor 2. In this embodiment, two functional semiconductors 2 are provided, and the functional semiconductors 2 are configured as sampling semiconductors and / or start-up semiconductors. Furthermore, in this embodiment, one sampling semiconductor and one start-up semiconductor are provided.

[0027] Specifically, the functional semiconductor 2 is arranged in the main semiconductor 1 and is surrounded by the main semiconductor 1, wherein the functional semiconductor 2 includes a functional isolation region 22 and a functional active region 21 arranged in the functional isolation region 22 and surrounded by the functional isolation region 22, the functional active region 21 includes a plurality of first conductive type functional columns 211 and second conductive type functional columns 212 arranged in parallel, the first conductive type functional columns 211 extending along the first direction, the second conductive type functional columns 212 also extending along the first direction, the plurality of first conductive type functional columns 211 and the plurality of second conductive type functional columns 212 are alternately arranged in sequence along the second direction, so that there is a second conductive type functional column 212 between two adjacent first conductive type functional columns 211, and there is a first conductive type functional column 211 between two adjacent second conductive type functional columns 212; The functional isolation region 22 includes a second conductive type first extension column 221 arranged at both ends of the second conductive type functional column 212 along the first direction and a second conductive type second extension column 222 arranged on both sides of the functional active region 21, wherein the second conductive type first extension column 221 is also extended along the first direction, one end of the second conductive type first extension column 221 is connected to the end of the second conductive type functional column 212, the second conductive type second extension column 222 and the adjacent second conductive type functional column 212 are separated by the first conductive type functional column 211, the second conductive type second extension column 222 and the functional active region 21 are arranged along the second direction, and the width of the second conductive type first extension column 221 and the second conductive type second extension column 222 are both smaller than the width of the second conductive type functional column 212.

[0028] The functional active area 21 is isolated by setting a second conductive type first extension column 221 and a second conductive type second extension column 222, and the isolation effect is good. The semiconductor structure can still ensure the independence of the functional active area 21 after the high-temperature annealing process, and the terminal electric field is smoother, which effectively reduces the peak electric field. Therefore, when the voltage of the main semiconductor 1 remains unchanged, a stable isolation voltage can be guaranteed, and the design window is increased, which can reach more than 200V. In addition, while enhancing the isolation voltage, since the functional isolation area 22 adopts the second conductive type first extension column 221 and the second conductive type second extension column 222 of the same type as the functional active area 21, the width of the second conductive type first extension column 221 and the second conductive type second extension column 222 is smaller than the second conductive type functional column 212, and the electric field curve is smoother. On the basis of achieving the same isolation voltage, the isolation terminal area can be effectively reduced, thereby reducing the chip area and saving the chip area.

[0029] As a specific embodiment, two second conductive type first extension columns 221 are provided at both ends of the second conductive type functional column 212, and the two second conductive type first extension columns 221 at each end of the second conductive type functional column 212 are connected to the second conductive type functional column 212 at one end, so that each end of the second conductive type functional column 212 forms a Y-shaped structure with the two second conductive type first extension columns 221, and a first conductive type functional column 211 is provided between the two adjacent second conductive type first extension columns 221, and is separated by the first conductive type functional column 211.

[0030] Furthermore, the width of the second conductive type first extension column 221 along the second direction is set to half of the width of the second conductive type functional column 212 along the second direction, and the width of the second conductive type second extension column 222 along the second direction is also set to half of the width of the second conductive type functional column 212 along the second direction. The width of the second conductive type first extension column 221 and the first conductive type functional column 211 between two adjacent second conductive type first extension columns 221 are the same.

[0031] By providing two second conductive type first extension columns 221 at both ends of the second conductive type functional column 212, and the widths of the two second conductive type first extension columns 221 are both set to half the width of the second conductive type functional column 212, so that the ratio of the width of the first conductive type functional column 211 to the corresponding second conductive type first extension column 221 between two adjacent second conductive type first extension columns 221 is the same as the ratio of the width of the second conductive type functional column 212 to the adjacent first conductive type functional column 211, avoiding the situation where only one second conductive type first extension column 221 is provided at one end of the second conductive type functional column 212, and the width of the second conductive type first extension column 221 is also set to half the width of the second conductive type functional column 212. The conductive type functional column 212 is half of its width, resulting in the width of the first conductive type functional column 211 between the adjacent second conductive type first extension columns 221 becoming more than twice the second conductive type first extension column 221. In order to ensure charge balance, it is necessary to adjust the ion concentration in the first conductive type functional column 211 here again, which invisibly increases the preparation steps, increases the preparation cost, and increases the preparation time. In this embodiment, each second conductive type functional column 212 is provided with two second conductive type first extension columns 221, which have the same size ratio as the first conductive type functional column 211 and the second conductive type functional column 212 below, and can directly ensure charge balance without further adjusting the ion concentration.

[0032] As a specific implementation method, refer to Figure 2 As shown, the main semiconductor 1 includes an integrated main terminal region 12 and a main active region 11. The main active region 11 is arranged in the main terminal region 12 and is surrounded by the main terminal region 12. The main active region 11 includes a plurality of first conductivity type main pillars 111 and second conductivity type main pillars 112 arranged in parallel. The first conductivity type main pillars 111 extend along a first direction, and the second conductivity type main pillars 112 also extend along the first direction. The plurality of first conductivity type main pillars 111 and second conductivity type main pillars 112 are alternately arranged in sequence along a second direction, so that there is a second conductivity type main pillar 112 between two adjacent conductivity type main pillars, and there is a first conductivity type main pillar 111 between two adjacent second conductivity type main pillars 112. The main terminal area 12 includes a second conductive type third extension column 121 arranged at both ends of the first conductive type main column 111 along the first direction and a second conductive type fourth extension column 122 arranged on both sides of the main active area 11, one end of the second conductive type third extension column 121 is connected to the second conductive type main column 112, the second conductive type fourth extension column 122 and the adjacent second conductive type main column 112 are separated by the first conductive type main column 111, the second conductive type fourth extension column 122 and the main active area 11 are arranged along the second direction, and the width of the second conductive type third extension column 121 and the second conductive type fourth extension column 122 along the second direction are both smaller than the width of the second conductive type main column 112.

[0033] Since the main terminal area 12 adopts the second conductive type third extension column 121 and the second conductive type fourth extension column 122 of the same type as the main active area 11, the width of the second conductive type third extension column 121 and the second conductive type fourth extension column 122 is smaller than the second conductive type functional column 212, and the electric field curve is smoother. On the basis of achieving the same isolation voltage, the isolation terminal area can be effectively reduced, thereby reducing the chip area and further saving the chip area.

[0034] Furthermore, two second conductive type third extension columns 121 are provided at both ends of the second conductive type main column 112, and the two second conductive type third extension columns 121 at each end of the second conductive type main column 112 are connected to the second conductive type main column 112 at one end, so that each end of the second conductive type main column 112 and the two second conductive type third extension columns 121 form a Y-shaped structure, and a first conductive type main column 111 is provided between the two adjacent second conductive type third extension columns 121, and are separated by the first conductive type main column 111.

[0035] Furthermore, the width of the second conductive type third extension column 121 along the second direction is set to half of the width of the second conductive type main column 112 along the second direction, and the width of the second conductive type fourth extension column 122 along the second direction is also set to half of the width of the second conductive type main column 112 along the second direction. The second conductive type third extension column 121 and the first conductive type main column 111 between two adjacent second conductive type third extension columns 121 have the same width.

[0036] By providing two second conductive type third extension columns 121 at both ends of the second conductive type main column 112, and the widths of the two second conductive type third extension columns 121 are both set to half of the second conductive type main column 112, so that the first conductive type main column 111 between two adjacent second conductive type third extension columns 121 also has the same width ratio to the corresponding second conductive type third extension column 121 as the width ratio between the second conductive type main column 112 and the first conductive type main column 111, thereby avoiding the situation where only one second conductive type third extension column 121 is provided at one end of the second conductive type main column 112, and the width of the second conductive type third extension column 121 is also set to half of the width of the second conductive type main column 112. As a result, the width of the first conductive type main column 111 between the adjacent second conductive type third extension columns 121 will become more than twice that of the second conductive type third extension column 121. In order to ensure charge balance, it is necessary to adjust the ion concentration in the first conductive type main column 111 here again, which invisibly increases the preparation steps, increases the preparation cost, and increases the preparation time. In this embodiment, two second conductive type third extension columns 121 are provided at each second conductive type main column 112, which have the same size ratio as the first conductive type main column 111 and the second conductive type main column 112 below, and can directly ensure charge balance without further adjusting the ion concentration, thereby reducing the preparation steps, reducing the preparation cost and time.

[0037] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A smart superjunction semiconductor structure, characterized in that: The invention comprises an integrated main semiconductor and at least one functional semiconductor, wherein the functional semiconductor is arranged in the main semiconductor, and the functional semiconductor comprises a functional isolation region and a functional active region arranged in the functional isolation region; The functional active area includes a plurality of first conductive type functional columns and second conductive type functional columns arranged in parallel, wherein the first conductive type functional columns and the second conductive type functional columns are both extended along a first direction, and the first conductive type functional columns and the second conductive type functional columns are alternately arranged along a second direction; The functional isolation region includes a second conductive type first extension column arranged at both ends of the second conductive type functional column along the first direction and a second conductive type second extension column arranged on both sides of the functional active area. The second conductive type second extension column and the functional active area are arranged along the second direction, and the widths of the second conductive type first extension column and the second conductive type second extension column are both smaller than the width of the second conductive type functional column.

2. The smart superjunction semiconductor structure according to claim 1, wherein: At least two second conductive type first extension columns are provided at each end of the second conductive type functional column, and the second conductive type functional column is connected to one end of the second conductive type first extension column, and adjacent second conductive type first extension columns are separated by the first conductive type functional column.

3. The smart superjunction semiconductor structure according to claim 1, wherein: The width of the second conductive type first extension column and the second conductive type second extension column is set to half the width of the second conductive type functional column.

4. The smart superjunction semiconductor structure according to claim 2, wherein: The second conductive type first extension pillar and the first conductive type functional pillar between two adjacent second conductive type first extension pillars have the same width.

5. The smart superjunction semiconductor structure according to claim 1, wherein: The main semiconductor includes a main terminal area and a main active area arranged in the main terminal area, wherein the main active area has several first conductive type main columns and second conductive type main columns arranged in parallel, the first conductive type main columns and the second conductive type main columns are both extended along the first direction, and the first conductive type main columns and the second conductive type main columns are alternately arranged along the second direction.

6. The smart superjunction semiconductor structure according to claim 5, wherein: The main terminal area includes a second conductive type third extension column arranged at both ends of the second conductive type main column along the first direction and a second conductive type fourth extension column arranged on both sides of the main active area. The second conductive type fourth extension column and the functional active area are arranged along the second direction, and the widths of the second conductive type third extension column and the second conductive type fourth extension column are both smaller than the width of the second conductive type main column.

7. The smart superjunction semiconductor structure according to claim 6, wherein: At least two second conductive type third extension columns are provided at each end of the second conductive type main column, and the second conductive type functional column is connected to one end of the second conductive type first extension column, and adjacent second conductive type third extension columns are separated by the first conductive type main column.

8. The smart superjunction semiconductor structure according to claim 6, wherein: The widths of the second conductive type third extension pillar and the second conductive type fourth extension pillar are both set to half the width of the second conductive type main pillar.

9. The smart superjunction semiconductor structure according to claim 1, wherein: The functional semiconductor is configured as a sampling semiconductor and / or a starting semiconductor.

10. The smart superjunction semiconductor structure according to claim 1, wherein: The semiconductor structure is configured as a MOSFET structure or an IGB structure.

Images